novatek: 14 more SoCs (NT9852x, NT98532/533, NT9832x, NT98332/633) and the loader's MMU hand-off

arch/arm/Kconfig

@@ -824,13 +824,16 @@ config ARCH_K3
 	select FIT
 
 config ARCH_NOVATEK
-	bool "Novatek NA51089 IP camera SoCs"
-	select CPU_V7A
+	bool "Novatek IP camera and NVR SoCs"
+	select CPU_V7A if !ARM64
 	select CREATE_ARCH_SYMLINK
 	help
-	  Novatek's NT98562 and NT98566: one Cortex-A9 with DDR in the
-	  package. The mask ROM starts the vendor loader, which trains the
-	  DDR, loads U-Boot as its device tree describes and starts it.
+	  Novatek's NA51089 cameras (one Cortex-A9) and NA51103 / NA51090
+	  NVRs (Cortex-A53s, AArch64; the SoC selects ARM64). The mask ROM
+	  starts the vendor loader, which trains the DDR, loads U-Boot as
+	  its device tree describes and starts it, on the NVRs through the
+	  board's BL31.
+	  Also the NA51068 DVR/NVR die (NT98321, NT98323), two Cortex-A9s.
 
 config ARCH_OMAP2PLUS
 	bool "TI OMAP2+"

arch/arm/mach-novatek/Kconfig

@@ -4,6 +4,18 @@ choice
 	prompt "Novatek SoC"
 	default TARGET_NT98562
 
+config TARGET_NT98560
+	bool "NT98560"
+	select NVT_NA51089
+	help
+	  NA51089 with external DDR3, 512 MiB on the SDK's board.
+
+config TARGET_NT98561
+	bool "NT98561"
+	select NVT_NA51089
+	help
+	  NA51089 with 64 MiB of DDR2 in the package, as the NT98562.
+
 config TARGET_NT98562
 	bool "NT98562"
 	select NVT_NA51089
@@ -16,18 +28,172 @@ config TARGET_NT98566
 	help
 	  NA51089 with 128 MiB of DDR3 in the package.
 
+config TARGET_NT98520
+	bool "NT98520"
+	select NVT_NA51055
+	help
+	  NA51055 (two Cortex-A9s) with external DDR3, one die, 512 MiB
+	  as the loader is built.
+
+config TARGET_NT98522
+	bool "NT98522"
+	select NVT_NA51055
+	help
+	  NA51055 with 64 MiB of DDR in the package.
+
+config TARGET_NT98523
+	bool "NT98523"
+	select NVT_NA51055
+	help
+	  NA51055 with 128 MiB of DDR in the package.
+
+config TARGET_NT98525
+	bool "NT98525"
+	select NVT_NA51055
+	help
+	  NA51055 with two external DDR3 dies, 512 MiB each on the SDK's
+	  board; U-Boot uses the first.
+
+config TARGET_NT98528
+	bool "NT98528"
+	select NVT_NA51055
+	help
+	  NA51084 (two Cortex-A9s, the NT9852x SDK's other die) with two
+	  external DDR3 dies, 512 MiB each on the SDK's board.
+
+config TARGET_NT98529
+	bool "NT98529"
+	select NVT_NA51055
+	help
+	  NA51084 as the NT98528, its CPU cleared for 1.2 GHz.
+
+config TARGET_NT98532
+	bool "NT98532"
+	select NVT_NS02501
+	help
+	  NS02501 (two Cortex-A32s, AArch32 only) with 256 MiB of DDR, as
+	  the SDK's 532BD NOR board.
+
+config TARGET_NT98533
+	bool "NT98533"
+	select NVT_NS02501
+	help
+	  NS02501 with 256 MiB of DDR in the package (533QD), as the SDK's
+	  533QD boards.
+
+config TARGET_NT98332
+	bool "NT98332 (NA51103)"
+	select NVT_NA51103
+	help
+	  NA51103, the NVR die with two Cortex-A53s, 1 GiB of DDR on the
+	  boards. U-Boot runs in AArch64 at EL2, started by the board's
+	  BL31.
+
+config TARGET_NT98633
+	bool "NT98633 (NA51090)"
+	select NVT_NA51090
+	help
+	  NA51090, the NVR die with four Cortex-A53s, 2 GiB of DDR on the
+	  boards. U-Boot runs in AArch64 at EL2, started by the board's
+	  BL31.
+
+config TARGET_NT98321
+	bool "NT98321"
+	select NVT_NA51068
+	help
+	  NA51068 (DVR/NVR, two Cortex-A9s) with external DDR3, 512 MiB on
+	  the SDK's board, booting from SPI NOR.
+
+config TARGET_NT98323
+	bool "NT98323"
+	select NVT_NA51068
+	help
+	  NA51068 (DVR/NVR, two Cortex-A9s) with external DDR4, 512 MiB on
+	  the SDK's NOR board.
+
 endchoice
 
 config NVT_NA51089
 	bool
 
+config NVT_NA51055
+	bool
+	help
+	  The NT9852x SDK's dies, NA51055 and NA51084: NA51089's blocks at
+	  NA51089's addresses, two Cortex-A9s, their own loader
+	  (board/novatek/na51055/loader). The chip ID tells them apart.
+
+config NVT_NS02501
+	bool
+	help
+	  The NT98532/NT98533 die: NA51089's blocks at NA51089's addresses,
+	  two Cortex-A32s run in AArch32 with a GIC-400 and the generic
+	  timer, its own loader (board/novatek/ns02501/loader).
+
+# The NVR dies: the board's loader warm-resets the A53s into AArch64 and
+# its BL31 (TF-A v2.2) enters U-Boot at EL2 with a fixed SPSR (0x3C9), so
+# U-Boot is an AArch64 one.
+config NVT_NA511XX
+	bool
+	select ARM64
+
+config NVT_NA51103
+	bool
+	select NVT_NA511XX
+
+config NVT_NA51090
+	bool
+	select NVT_NA511XX
+
+config NVT_NA51068
+	bool
+
+config NVT_DDR_SIZE
+	hex
+	default 0x80000000 if TARGET_NT98633
+	default 0x40000000 if TARGET_NT98332
+	default 0x20000000 if TARGET_NT98560 || NVT_NA51068
+	default 0x08000000 if TARGET_NT98566
+	default 0x20000000 if TARGET_NT98520 || TARGET_NT98525
+	default 0x20000000 if TARGET_NT98528 || TARGET_NT98529
+	default 0x08000000 if TARGET_NT98523
+	default 0x10000000 if NVT_NS02501
+	default 0x04000000
+	help
+	  The DDR at 0: the package's, or the board's for a part with
+	  external DDR, as its loader is built. A second DDR die (at
+	  0x40000000 on NA51055 / NA51084) is the media pool's alone. On NA51068
+	  the loader's device tree (/nvt_memory_cfg/dram) says it; this is
+	  the fallback.
+
+config NVT_OSMEM
+	string
+	default "0x57600000" if NVT_NA51090
+	default "0x15e00000" if NVT_NA51103
+	default "160M" if TARGET_NT98321
+	default "192M" if TARGET_NT98323
+	default "256M" if NVT_DDR_SIZE >= 0x20000000
+	default "64M" if TARGET_NT98523
+	default "36M" if NVT_NS02501
+	default "32M"
+	help
+	  What Linux gets of the DDR by default (osmem, mem=); the vendor
+	  media modules get the rest. 32M is what OpenIPC's install guide
+	  sets on the NT98562/566's vendor U-Boot; larger parts give Linux
+	  what their SDK board does (the NT98523's tree keeps its CMA at
+	  48 MiB; the NS02501 boards give Linux 36 MiB), the NVRs what
+	  their firmware sets (Xiongmai's NT98332 NVR 0x15e00000, the
+	  NT98633 NVR's tree 0x57600000).
+
 config SYS_SOC
 	default "novatek"
 
 config SYS_VENDOR
 	default "novatek"
 
 config SYS_BOARD
+	default "na511xx" if NVT_NA511XX
+	default "na51068" if NVT_NA51068
 	default "na51089"
 
 config SYS_CONFIG_NAME

arch/arm/mach-novatek/Makefile

@@ -1,3 +1,8 @@
 # SPDX-License-Identifier: GPL-2.0+
 
+# NA51068 (its own map and timer) has na51068.c; every other die soc.c
+ifdef CONFIG_NVT_NA51068
+obj-y += na51068.o
+else
 obj-y += soc.o
+endif

arch/arm/mach-novatek/include/mach/hardware.h

@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * The memory map of the Novatek die U-Boot is built for: the drivers and
+ * the board code include this rather than a die's own header.
+ */
+
+#ifndef __NVT_HARDWARE_H
+#define __NVT_HARDWARE_H
+
+#if defined(CONFIG_NVT_NA511XX)
+#include <asm/arch/na511xx.h>
+#elif defined(CONFIG_NVT_NA51068)
+#include <asm/arch/na51068.h>
+#else
+#include <asm/arch/na51089.h>
+#endif
+
+#ifndef __ASSEMBLY__
+/* The device tree the loader left (SHMINFO), or NULL */
+const void *nvt_loader_fdt(void);
+#endif
+
+#endif

arch/arm/mach-novatek/include/mach/na51068.h

@@ -0,0 +1,75 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Novatek NA51068 (NT98321, NT98323): memory map, after the NT9832x SDK's
+ * U-Boot 2016.07 (arch-nvt-na51068/IOAddress.h), kernel 4.9.118
+ * (plat-na51068) and board device trees.
+ */
+
+#ifndef __NA51068_H
+#define __NA51068_H
+
+#include <linux/bitops.h>
+
+#define NVT_DDR_BASE		0x00000000
+
+#define NVT_SCU_BASE		0xF9C00000	/* A9 MPCore: SCU, GIC, timers */
+#define NVT_GTIMER_BASE		(NVT_SCU_BASE + 0x200)
+#define NVT_PL310_BASE		0xF9C20000
+#define NVT_SDHCI_BASE		0xFA600000
+#define NVT_FLASH_BASE		0xFA900000	/* Faraday FTSPI020 */
+#define NVT_ETH0_BASE		0xFCC00000
+#define NVT_ETH1_BASE		0xFCD00000
+#define NVT_CG_BASE		0xFE000000	/* clocks, PLLs, resets */
+#define NVT_TOP_BASE		0xFE030000	/* pinmux, chip ID */
+#define NVT_PAD_BASE		0xFE040000
+#define NVT_UART0_BASE		0xFE200000
+#define NVT_GPIO1_BASE		0xFE420000
+#define NVT_GPIO2_BASE		0xFE440000
+#define NVT_WDT_BASE		0xFE8A0000
+
+/* TOP */
+#define NVT_TOP_CHIP_ID		(NVT_TOP_BASE + 0xF0)	/* [31:16] */
+
+/* CG: the CPU's clock, from PLL16, eight times its rate */
+#define NVT_CG_CPU_CKCTRL	(NVT_CG_BASE + 0x100)
+#define NVT_CPU_CK_APLL		BIT(31)		/* else 80 MHz */
+#define NVT_CG_PLL16		(NVT_CG_BASE + 0x107C0)	/* ratio at +0x20/24/28 */
+
+/*
+ * The A9 global timer counts at PLL16's rate, an eighth of the CPU's:
+ * the loader leaves it as it is, the vendor U-Boot enables it.
+ */
+#define NVT_GTIMER_LO		(NVT_GTIMER_BASE + 0x00)
+#define NVT_GTIMER_HI		(NVT_GTIMER_BASE + 0x04)
+#define NVT_GTIMER_CTRL		(NVT_GTIMER_BASE + 0x08)
+
+/* Watchdog: every CTRL write carries the key in [31:16] */
+#define NVT_CG_APB_RSTN		(NVT_CG_BASE + 0x5C)
+#define NVT_CG_WDT_RSTN		BIT(28)
+#define NVT_CG_APB_GATE		(NVT_CG_BASE + 0x78)
+#define NVT_CG_WDT_GATE		BIT(15)
+#define NVT_WDT_CTRL		(NVT_WDT_BASE + 0x00)
+#define NVT_WDT_MANUAL		(NVT_WDT_BASE + 0x0C)
+#define NVT_WDT_KEY		0x5A960000
+#define NVT_WDT_EN		BIT(0)
+
+/*
+ * What the loader leaves in DDR (the /nvt_memory_cfg node of its device
+ * tree, openipc/na51068.dtsi): the device tree at 0x80000, SHMINFO at
+ * 0xA00000, its own code from 0x100000. U-Boot runs where
+ * /nvt_memory_cfg/uboot says: at 0x1E000000, as on every board of the
+ * SDK (all have 512 MiB or more), above Linux's memory and its CMA pools
+ * (0x02000000-0x04800000), below the second core's pen at 0x1FF80000.
+ */
+#define NVT_SHMINFO		(NVT_DDR_BASE + 0x00A00000)
+#define NVT_SHM_LD_NVT		0x00		/* "LD_NVT" */
+#define NVT_SHM_FDT_ADDR	0x2C
+#define NVT_UBOOT_BASE		(NVT_DDR_BASE + 0x1E000000)
+#define NVT_UBOOT_SIZE		0x01F80000
+
+#ifndef __ASSEMBLY__
+/* The loader's device tree, from SHMINFO, or NULL (mach-novatek/na51068.c) */
+const void *nvt_loader_fdt(void);
+#endif
+
+#endif

arch/arm/mach-novatek/include/mach/na51089.h

@@ -1,8 +1,10 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Novatek NA51089 (NT98562, NT98566): memory map, after the vendor
- * U-Boot 2019.04 (arch-nvt-na51089_a32/IOAddress.h) and the SDK's
- * device trees.
+ * Novatek NA51089 (NT98560/561/562/566), and NA51055 / NA51084
+ * (NT98520/522/523/525/528/529) and NS02501 (NT98532/533), which share
+ * its map: after the vendor U-Boots 2019.04 and 2021.10
+ * (arch-nvt-na51089_a32/IOAddress.h, arch-nvt-na51055_a32/IOAddress.h,
+ * arch-nvt-ns02501_a32/IOAddress.h) and the SDKs' device trees.
  */
 
 #ifndef __NA51089_H
@@ -25,15 +27,37 @@
 #define NVT_SDIO1_BASE		0xF0420000
 #define NVT_PL310_BASE		0xFFE00000
 
-/* TOP */
+/*
+ * TOP. NA51055 (NT98520/522/523/525) and NA51084 (NT98528/529), the
+ * NT9852x SDK's two dies, have NA51089's blocks at NA51089's addresses;
+ * the vendor's code tells them apart at run time by this ID.
+ */
 #define NVT_TOP_CHIP_ID		(NVT_TOP_BASE + 0xF0)	/* [31:16] */
 #define NVT_CHIP_NA51089	0x7021
+#define NVT_CHIP_NA51055	0x4821
+#define NVT_CHIP_NA51084	0x5021
+/* NS02501, two Cortex-A32s (AArch32 only): its own targets (NVT_NS02501) */
+#define NVT_CHIP_NS02501	0x5521
+
+#ifndef __ASSEMBLY__
+static inline unsigned int nvt_chip_id(void)
+{
+	return *(volatile unsigned int *)NVT_TOP_CHIP_ID >> 16;
+}
+#endif
 
 /* CG: per-module clock enables and resets (active low) */
 #define NVT_CG_CLKEN0		(NVT_CG_BASE + 0x74)
 #define NVT_CG_RSTN0		(NVT_CG_BASE + 0x84)
 #define NVT_CG_FLASH		BIT(0)
+#ifdef CONFIG_NVT_NS02501
+/* NS02501: the watchdog's clock in CLKEN0, its reset in the word before */
+#define NVT_CG_WDT		BIT(19)
+#define NVT_CG_WDT_RSTN		(NVT_CG_BASE + 0x80)
+#define NVT_CG_WDT_RST		BIT(8)
+#else
 #define NVT_CG_WDT		BIT(17)
+#endif
 
 /*
  * Timer 0 of the twenty in the timer block: the loader leaves it running
@@ -46,15 +70,21 @@
 /* Watchdog: every CTRL write carries the key in [31:16] */
 #define NVT_WDT_CTRL		(NVT_WDT_BASE + 0x00)
 #define NVT_WDT_MANUAL		(NVT_WDT_BASE + 0x0C)
+#define NVT_WDT_DATA		(NVT_WDT_BASE + 0x84)
 #define NVT_WDT_KEY		0x5A960000
 #define NVT_WDT_EN		BIT(0)
 
 /*
  * What the loader leaves in DDR (the /nvt_memory_cfg node of its device
- * tree): the device tree at 0x100000 and the SHMINFO block at 0x200000.
- * U-Boot runs where /nvt_memory_cfg/uboot says.
+ * tree): the device tree at 0x100000 and the SHMINFO block at 0x200000
+ * (0xA00000 in the NS02501 SDK's trees, which openipc/ns02501.dtsi
+ * keeps). U-Boot runs where /nvt_memory_cfg/uboot says.
  */
+#ifdef CONFIG_NVT_NS02501
+#define NVT_SHMINFO		(NVT_DDR_BASE + 0x00A00000)
+#else
 #define NVT_SHMINFO		(NVT_DDR_BASE + 0x00200000)
+#endif
 #define NVT_SHM_LD_NVT		0x00		/* "LD_NVT" */
 #define NVT_SHM_FDT_ADDR	0x2C
 /* /nvt_memory_cfg/uboot: where U-Boot is loaded, and where it stays */