[Feature Request]: Concept for Trace Port Configuration #581

Description

Multicore devices need a different type of trace configuration. New generation devices have Performance Counters and the Cortex-M3 ITM configuration does not longer scale.

This diagram shows various configuration dialogs. Overall they seem to be overwhelming. The block diagram (right button) is the topology of a multicore device).

Initial Tasks:

1. What are the minimum parameters that a Trace Port configuration requires. Initial focus can be limited to just SWO UART mode (however my preference would be to take this wider).

   • Would be Trace Clock and Baudrate sufficient?
   • Can Baudrate be a single 'default' setting so that only Trace Clock is exposed in a UI?
   • Is the configuration of SWO UART mode enough standardized across various devices?
   • Are the proposed csolution.yml settings sufficient

2. Is it feasible to move ITM/DWT (ect.) setup to *.dbgconf? As such features are specific to a processor and a multi-core system has multiple trace components this seems to be an obvious way. However perhaps there are existing scripts that can be reused instead.

Is this request a Security Requirement?

• Yes

Priority

High

Related Issues (Optional)

No response

Additional Notes (Optional)

No response