Repository navigation
Fix narrow signed atomic min/max operand semantics - #12
Merged
Merged
Conversation
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
Narrow ARM64
LDSMAX/LDSMINoperations could store the unsigned comparison result: for example, signed byte max(16, -17) stored -17. The nonparallel TCG fallback reused the result-extension flag to choose operand signedness, although ARM returns the old narrow memory value zero-extended.Keep operand sign extension separate from the original load/store descriptor and returned value. The shared atomic-operation table explicitly marks signed min/max, preserving the parallel helper path and other atomic operations. Direct Unicorn C API regressions cover 64 min/max encodings, six independent operand vectors and four result-register layouts (1,536 executions), including aliases and XZR.
Validation: the original engine failed 384 memory-result checks; the fixed engine passes all 1,536 executions. Complete ARM64, ARM and x86 unit binaries pass, as do NeverD software-backend checks for 168 LSE encodings. No native ARM64 backend execution is claimed by these host tests.
The ARM64 wheel run also exposed an old invalid-jump regression whose one-instruction budget could stop at the jump before the expected target fetch. It now tests that fetch with a bounded timeout instead of depending on translator-specific stop ordering. The corrected regression passes locally.