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feat(intrinsics): admit standard-metadata Ampere-float sparse MMA - #1561
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The Ampere-float sparse admission now carries metadata = standard | ordered. Identity, PTX floor, and the plain 16-bit metadata rule come from that axis. Ordered records keep their ids, ABI i1018..=i1025, and PTX 8.5 spelling. Signed-off-by: YeonwooSung <neos960518@gmail.com>
The same eight Ampere-float shapes now admit metadata = standard, with identity, PTX 7.1, and the 16-bit metadata rule derived from that axis. Ordered records stay on ABI i1018..=i1025. Plain 16-bit metadata documents 0x4, 0x6, 0x8, 0x9, 0xc, 0xd, and 0xe. Evidence is nightly-2026-10-11 llc and CUDA 13.3.33 libNVVM. On an RTX 5090 the eight forms assembled, and the host-GEMM oracle matched all 32 lanes through both the default route and libNVVM cubin materialization. Signed-off-by: YeonwooSung <neos960518@gmail.com>
The oracle covers all eight standard forms. Two-register forms run selectors 0 through 3, and four-register forms run 0 and 1. 16-bit metadata cycles 0x4, 0x6, 0x8, 0x9, 0xc, 0xd, and 0xe. tf32 stays on 0x4 and 0xe. Each lane is compared with a host GEMM. Signed-off-by: YeonwooSung <neos960518@gmail.com>
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Summary
This replaces closed #1355. That PR special-cased one bf16 form. This one adds
metadata = standard | orderedto the Ampere-float sparse family, on the same model as integer sparse MMA. Identity, the PTX floor, and the plain 16-bit metadata rule come from that axis. There is no per-form predicate.The standard shard lists the same eight variants as the ordered shard, in ABI order:
m16n8k8f32 tf32m16n8k16f32 tf32, f32 bf16, f16 f16, f32 f16m16n8k32f32 bf16, f16 f16, f32 f16Ordered records stay on ABI
i1018..=i1025and PTX 8.5. The new records arei1039..=i1046, PTX 7.1,sm_80.kind::f8f6f4is unchanged.Plain 16-bit standard metadata documents the codes the 5090 honors:
0x4,0x6,0x8,0x9,0xc,0xd, and0xe(the six ascending codes plus0x6). The ISA lists twelve. tf32 standard metadata stays on the existing rule, and the oracle only feeds tf320x4and0xe.Evidence
Recorded on an RTX 5090.
7534b0236b9b26c7e6910548038b2285ee1bb5908e4700764dc78a7a1a54b449, rustc6f5da406b56c2db6607202b63daee73aa8c61297. Selected-evidence probe assembled all eight forms forsm_80with CUDA 13.3.33 ptxas (7fdd01a4…). ptxas prints an advisory that.sp::ordered_metadatamay be faster on future architectures. Assembly still succeeds, and the standard spelling is what this family admits.libnvvm.so.4.0.0, SHA-256b6a5db233133fb0ed693f8cb8aeb1d405254ce0ab10364478985292ec98cfcf0, build-id2330c0. nvJitLink SHA-2563ba1e744…. These are the 13.3.33 redistributable binaries, not a hash copied from a sibling record.sparse_mma_standard_float: all eight forms, selectors 0–3 on the 2-register forms and 0–1 on the 4-register forms (24 calls), every lane against a host GEMM.cargo oxide run sparse_mma_standard_float --arch sm_120and the same command with--materialize-cubinboth printedSUCCESS.runtime_validationfor the standard shard isexecutedfrom that run.Test plan
cargo test -p cuda-intrinsics-gen --bin cuda-intrinsics-gencargo run -p cuda-intrinsics-gen -- checkcargo oxide run sparse_mma_standard_float --arch sm_120on an RTX 5090cargo oxide run sparse_mma_standard_float --arch sm_120 --materialize-cubinon an RTX 5090