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MihaiFlorea6/README.md

Hi there, I'm Mihai!👋

I am a Computer Science student at Technical University of Cluj-Napoca, passionate about FPGA design, SoC architecture and low-level embedded systems. My work focuses on developing deterministic real-time hardware, custom communication protocols and hardware-software integration.

Tools

Git, Github, Xilinx Vivado, ArduinoIDE, IntelliJ IDEA, PyCharm, VSCode, KiCad, Streamlit, Pandas.

Languages

C, C++, VHDL, Verilog, Java, Python, Assembly x86.

Projects

  • Autonomous_Obstacle_Avoiding_Robot - C++ driven 2WD platform on Arduino UNO featuring HC-SR04 ultrasonic navigation, deterministic evasion logic and dynamic MP3 audio feedback.
  • ESP32 Smart Mini Hub - IoT automation node featuring FSM control, asynchronous C++ web server and custom KiCad PCB with BJT power stages.
  • Real-Time SoC Alarm System - Verilog security controller for Basys3 with PIN verification, FSM lockout and UART-based Python/Streamlit monitoring.
  • MIPS 5-Stage Pipeline Processor - VHDL implementation of a MIPS32 pipelined architecture (IF, ID, EX, MEM, WB) with dedicated RTL control units.
  • MultiCore Benchmark Studio - Multi-language benchmarking suite evaluating C and Rust concurrency, featuring algorithmic hardware profiling and a live Streamlit telemetry dashboard.

How to reach me: LinkedIn | Email

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  1. Autonomous_Obstacle_Avoiding_Robot Autonomous_Obstacle_Avoiding_Robot Public

    Autonomous Arduino robot featuring ultrasonic obstacle avoidance and dynamic MP3 audio feedback.

    C++

  2. ESP32_Smart_Mini_Hub ESP32_Smart_Mini_Hub Public

    Modular ESP32 automation system with FSM architecture and embedded web server.

    C

  3. RealTime_Alarm_System RealTime_Alarm_System Public

    Verilog Basys3 Alarm System using UART protocol and Python Streamlit real-time software monitoring.

    Verilog

  4. MultiCore_Benchmark_Studio MultiCore_Benchmark_Studio Public

    Multi-language benchmarking suite in C and Rust with a Python telemetry dashboard.

    C

  5. MIPS_5_Stage_Pipeline_Processor MIPS_5_Stage_Pipeline_Processor Public

    MIPS32 5-Stage Pipeline implemented in VHDL

    VHDL