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LinxV5: emit ELF machine 0xE9 #78

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27c2ff9
LinxV5: emit ELF machine 0xE9
Aug 31, 2026
a43a6dd
LinxV5: emit PTO shift and scalar sqrt instructions
Sep 1, 2026
f7b19f6
LinxV5: emit relative matrix tile bindings
Sep 1, 2026
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2 changes: 1 addition & 1 deletion llvm/include/llvm/BinaryFormat/ELF.h
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Expand Up @@ -321,7 +321,7 @@ enum {
EM_CSKY = 252, // C-SKY 32-bit processor
EM_LOONGARCH = 258, // LoongArch
EM_LinxV4 = 260, // LinxV4
EM_LinxV5 = 261, // LinxV5
EM_LinxV5 = 233, // LinxV5 / current LinxISA ELF ABI
};

// Object file classes.
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/LinxV5/LinxV5ISelLowering.cpp
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Expand Up @@ -154,7 +154,7 @@ LinxV5TargetLowering::LinxV5TargetLowering(const TargetMachine &TM,
setOperationAction(ISD::FPOW, FPVTs, Expand);
setOperationAction(ISD::FCOPYSIGN, FPVTs, Expand);
setOperationAction(ISD::FABS, FPVTs, Expand);
setOperationAction(ISD::FSQRT, FPVTs, LibCall);
setOperationAction(ISD::FSQRT, FPVTs, Legal);
setOperationAction(ISD::FEXP, FPVTs, LibCall);
setOperationAction(ISD::FLOG, FPVTs, LibCall);
setOperationAction(ISD::FSIN, FPVTs, LibCall);
Expand Down
55 changes: 42 additions & 13 deletions llvm/lib/Target/LinxV5/LinxV5InstrInfo.td
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Expand Up @@ -270,10 +270,26 @@ class ALUriZ6_Base<bits<3> Func, LinxV5InstOpcode opc, Operand Imm, string opcst
class ALUriZ5_Base<bits<3> Func, LinxV5InstOpcode opc, Operand Imm, string opcstr, LinxV5InstType type> :
LinxV5Inst_E_Z5<type, opc, Func,(outs DstRWithArrow:$DstR), (ins GPRSrc:$SrcL, Imm:$Imm5), opcstr>;

class PTOShiftRR<bits<3> Func, bits<7> OpcodeBits, string opcstr> :
LinxV5Inst<(outs DstRWithArrow:$DstR),
(ins GPRSrc:$SrcL, GPRSrc:$SrcR), opcstr, ""> {
bits<5> SrcR;
bits<5> SrcL;
bits<5> DstR;
let Inst{31-25} = 0;
let Inst{24-20} = SrcR;
let Inst{19-15} = SrcL;
let Inst{14-12} = Func;
let Inst{11-7} = DstR;
let Opcode = OpcodeBits{6-4};
let Inst{3-0} = OpcodeBits{3-0};
let AsmString = opcstr # "\t$SrcL, $SrcR, $DstR";
}

multiclass ALUshift<bits<3> Func, string opcstr, LinxV5InstType type> {
def "" : ALUrrZ5_Base<Func, OPC_Arithmetic_Operation_64, SrcRNONE, opcstr, type>;
def "" : PTOShiftRR<Func, 0b0000101, opcstr>;
def I : ALUriZ6_Base<Func, OPC_Arithmetic_Operation_64_I, uimm6, opcstr#"i", type>;
def W : ALUrrZ5_Base<Func, OPC_Arithmetic_Operation_32, SrcRNONE, opcstr#"w", type>;
def W : PTOShiftRR<Func, 0b0100101, opcstr#"w">;
def IW : ALUriZ5_Base<Func, OPC_Arithmetic_Operation_32_I, uimm5, opcstr#"iw", type>;
}

Expand Down Expand Up @@ -1993,6 +2009,9 @@ def : InstAlias<"B.CATR $Type", (BCATR BAttrType:$Type, 0), 1>;

def : InstAlias<"B.DATR $DataLayout$canon", (BDATR BArgFormat:$DataLayout, Canon:$canon, 31, 3, 0, 0, 0, 0), 1>;
def : InstAlias<"B.DATR\t$srctype, $RMode, $sat", (BDATR 0, 0, BstartDataType:$srctype, 3, 0, RMode:$RMode, Sat:$sat, 0), 1>;
def : InstAlias<"B.DATR\t$srctype, $PadValue, $RMode, $sat",
(BDATR 0, 0, BstartDataType:$srctype, PadValue:$PadValue, 0,
RMode:$RMode, Sat:$sat, 0), 1>;
def : InstAlias<"B.DATR\t$srctype, $RMode", (BDATR 0, 0, BstartDataType:$srctype, 3, 0, RMode:$RMode, 0, 0), 1>;
//def : InstAlias<"B.DATR\t$srctype, $datalayout", (BDATR BArgFormat:$datalayout, 0, BstartDataType:$srctype, 3, 0, 0, 0, 0), 1>;
//def : InstAlias<"B.DATR $DataLayout", (BDATR BArgFormat:$DataLayout, 0, 31, 3, 0, 0, 0, 0), 3>;
Expand Down Expand Up @@ -2684,11 +2703,21 @@ multiclass fPatRR<SDPatternOperator N, string I> {
def : PatRRVT<f16, N, !cast<Instruction>(I # _FH)>;
}

class PatRVT<ValueType VT, SDPatternOperator N, Instruction I> :
Pat<(N VT:$SrcL), (I VT:$SrcL)>;

multiclass fPatR<SDPatternOperator N, string I> {
def : PatRVT<f64, N, !cast<Instruction>(I # _FD)>;
def : PatRVT<f32, N, !cast<Instruction>(I # _FS)>;
def : PatRVT<f16, N, !cast<Instruction>(I # _FH)>;
}

let Predicates = [isScalar, hasFloat, useDAGISel] in {
defm : fPatRR<fadd, "FADD">;
defm : fPatRR<fsub, "FSUB">;
defm : fPatRR<fmul, "FMUL">;
defm : fPatRR<fdiv, "FDIV">;
defm : fPatR<fsqrt, "FSQRT">;
}

class fPatNEG<ValueType VT, Instruction I> :
Expand Down Expand Up @@ -3433,7 +3462,7 @@ class PseudoCUBE_MAMULBAC_Higher_Base_I<string TileOp> :
def PseudoMAMULBAC_Higher_SizeI : PseudoCUBE_MAMULBAC_Higher_Base_I<"MAMULBAC_Higher">;

class PseudoCUBE_MAMULBAC_Base_I<string TileOp> :
PseudoCCallImpl<(outs ACC_TILE_DstWithArrow:$DstTile),
PseudoCCallImpl<(outs TILE_DstWithArrow:$DstTile),
(ins GPRPlusImm:$RegM, PlusImm17:$immM, GPRPlusImm:$RegN, PlusImm17:$immN, GPRPlusImm:$RegK, PlusImm17:$immK, BstartDataType:$DataTypeA, BstartDataType:$DataTypeB,
TileSizeWithBracket:$TileSize, TILE_Src_Reg:$SrcTile0, TILE_Src_Reg:$SrcTile1, TILE_Src_Reg:$SrcTile2)> {
let AsmString = TileOp # "\t<M: $RegM$immM, N: $RegN$immN, K: $RegK$immK, ${DataTypeA}, ${DataTypeB}>" #"\t$SrcTile0, $SrcTile1, $SrcTile2, $DstTile$TileSize";
Expand All @@ -3442,16 +3471,16 @@ class PseudoCUBE_MAMULBAC_Base_I<string TileOp> :
def PseudoMAMULBAC_SizeI : PseudoCUBE_MAMULBAC_Base_I<"TMATMUL.BIAS">;

class PseudoCUBE_MAMULBACC_Base_I<string TileOp> :
PseudoCCallImpl<(outs ACC_TILE_DstWithArrow:$DstTile),
PseudoCCallImpl<(outs TILE_DstWithArrow:$DstTile),
(ins GPRPlusImm:$RegM, PlusImm17:$immM, GPRPlusImm:$RegN, PlusImm17:$immN, GPRPlusImm:$RegK, PlusImm17:$immK, BstartDataType:$DataTypeA, BstartDataType:$DataTypeB,
TileSizeWithBracket:$TileSize, TILE_Src_Reg:$SrcTile0, TILE_Src_Reg:$SrcTile1, ACC_TILE_SRC:$ACC)> {
TileSizeWithBracket:$TileSize, TILE_Src_Reg:$SrcTile0, TILE_Src_Reg:$SrcTile1, TILE_Src_Reg:$ACC)> {
let AsmString = TileOp # "\t<M: $RegM$immM, N: $RegN$immN, K: $RegK$immK, ${DataTypeA}, ${DataTypeB}>" #"\t$SrcTile0, $SrcTile1, $ACC, $DstTile$TileSize";
}

def PseudoMAMULBACC_SizeI : PseudoCUBE_MAMULBACC_Base_I<"TMATMUL.ACC">;

class PseudoCUBE_MAMULBMX_Base_I<string TileOp> :
PseudoCCallImpl<(outs ACC_TILE_DstWithArrow:$DstTile),
PseudoCCallImpl<(outs TILE_DstWithArrow:$DstTile),
(ins GPRPlusImm:$RegM, PlusImm17:$immM, GPRPlusImm:$RegN, PlusImm17:$immN, GPRPlusImm:$RegK, PlusImm17:$immK, BstartDataType:$DataTypeA, BstartDataType:$DataTypeB,
TileSizeWithBracket:$TileSize, TILE_Src_Reg:$SrcTile0, TILE_Src_Reg:$SrcTile1, TILE_Src_Reg:$SrcTile2, TILE_Src_Reg:$SrcTile3)> {
let AsmString = TileOp # "\t<M: $RegM$immM, N: $RegN$immN, K: $RegK$immK, ${DataTypeA}, ${DataTypeB}>" # "\t$SrcTile0, $SrcTile1, $SrcTile2, $SrcTile3, $DstTile$TileSize";
Expand All @@ -3460,7 +3489,7 @@ class PseudoCUBE_MAMULBMX_Base_I<string TileOp> :
def PseudoMAMULBMX_SizeI : PseudoCUBE_MAMULBMX_Base_I<"TMATMULMX">;

class PseudoCUBE_MAMULBMXB_Base_I<string TileOp> :
PseudoCCallImpl<(outs ACC_TILE_DstWithArrow:$DstTile),
PseudoCCallImpl<(outs TILE_DstWithArrow:$DstTile),
(ins GPRPlusImm:$RegM, PlusImm17:$immM, GPRPlusImm:$RegN, PlusImm17:$immN, GPRPlusImm:$RegK, PlusImm17:$immK, BstartDataType:$DataTypeA, BstartDataType:$DataTypeB,
TileSizeWithBracket:$TileSize, TILE_Src_Reg:$SrcTile0, TILE_Src_Reg:$SrcTile1, TILE_Src_Reg:$SrcTile2)> {
let AsmString = TileOp # "\t<M: $RegM$immM, N: $RegN$immN, K: $RegK$immK, ${DataTypeA}, ${DataTypeB}>" # "\t$SrcTile0, $SrcTile1, $SrcTile2, $DstTile$TileSize";
Expand All @@ -3478,7 +3507,7 @@ PseudoCCallImpl<(outs ACC_TILE_DstWithArrow:$DstTile),
def PseudoMAMULBMXAC_Higher_SizeI : PseudoCUBE_MAMULBMXAC_Higher_Base_I<"MAMULBMXAC_Higher">;

class PseudoCUBE_MAMULBMXAC_Base_I<string TileOp> :
PseudoCCallImpl<(outs ACC_TILE_DstWithArrow:$DstTile),
PseudoCCallImpl<(outs TILE_DstWithArrow:$DstTile),
(ins GPRPlusImm:$RegM, PlusImm17:$immM, GPRPlusImm:$RegN, PlusImm17:$immN, GPRPlusImm:$RegK, PlusImm17:$immK, BstartDataType:$DataTypeA, BstartDataType:$DataTypeB,
TileSizeWithBracket:$TileSize, TILE_Src_Reg:$SrcTile0, TILE_Src_Reg:$SrcTile1, TILE_Src_Reg:$SrcTile2, TILE_Src_Reg:$SrcTile3, TILE_Src_Reg:$SrcTile4)> {
let AsmString = TileOp # "\t<M: $RegM$immM, N: $RegN$immN, K: $RegK$immK, ${DataTypeA}, ${DataTypeB}>" # "\t$SrcTile0, $SrcTile1, $SrcTile2, $SrcTile3, $SrcTile4, $DstTile$TileSize";
Expand All @@ -3496,7 +3525,7 @@ class PseudoCUBE_MAMULBMXBAC_Higher_Base_I<string TileOp> :
def PseudoMAMULBMXBAC_Higher_SizeI : PseudoCUBE_MAMULBMXBAC_Higher_Base_I<"MAMULBMXAC_Higher">;

class PseudoCUBE_MAMULBMXBAC_Base_I<string TileOp> :
PseudoCCallImpl<(outs ACC_TILE_DstWithArrow:$DstTile),
PseudoCCallImpl<(outs TILE_DstWithArrow:$DstTile),
(ins GPRPlusImm:$RegM, PlusImm17:$immM, GPRPlusImm:$RegN, PlusImm17:$immN, GPRPlusImm:$RegK, PlusImm17:$immK, BstartDataType:$DataTypeA, BstartDataType:$DataTypeB,
TileSizeWithBracket:$TileSize, TILE_Src_Reg:$SrcTile0, TILE_Src_Reg:$SrcTile1, TILE_Src_Reg:$SrcTile2, TILE_Src_Reg:$SrcTile3)> {
let AsmString = TileOp # "\t<M: $RegM$immM, N: $RegN$immN, K: $RegK$immK, ${DataTypeA}, ${DataTypeB}>" # "\t$SrcTile0, $SrcTile1, $SrcTile2, $SrcTile3, $DstTile$TileSize";
Expand All @@ -3505,18 +3534,18 @@ class PseudoCUBE_MAMULBMXBAC_Base_I<string TileOp> :
def PseudoMAMULBMXBAC_SizeI : PseudoCUBE_MAMULBMXBAC_Base_I<"TMATMULMX.BIAS">;

class PseudoCUBE_MAMULBMXACC_Base_I<string TileOp> :
PseudoCCallImpl<(outs ACC_TILE_DstWithArrow:$DstTile),
PseudoCCallImpl<(outs TILE_DstWithArrow:$DstTile),
(ins GPRPlusImm:$RegM, PlusImm17:$immM, GPRPlusImm:$RegN, PlusImm17:$immN, GPRPlusImm:$RegK, PlusImm17:$immK, BstartDataType:$DataTypeA, BstartDataType:$DataTypeB,
TileSizeWithBracket:$TileSize, TILE_Src_Reg:$SrcTile0, TILE_Src_Reg:$SrcTile1, TILE_Src_Reg:$SrcTile2, TILE_Src_Reg:$SrcTile3, ACC_TILE_SRC:$ACC)> {
TileSizeWithBracket:$TileSize, TILE_Src_Reg:$SrcTile0, TILE_Src_Reg:$SrcTile1, TILE_Src_Reg:$SrcTile2, TILE_Src_Reg:$SrcTile3, TILE_Src_Reg:$ACC)> {
let AsmString = TileOp # "\t<M: $RegM$immM, N: $RegN$immN, K: $RegK$immK, ${DataTypeA}, ${DataTypeB}>" # "\t$SrcTile0, $SrcTile1, $SrcTile2, $SrcTile3, $ACC, $DstTile$TileSize";
}

def PseudoMAMULBMXACC_SizeI : PseudoCUBE_MAMULBMXACC_Base_I<"TMATMULMX.ACC">;

class PseudoCUBE_MAMULBMXBACC_Base_I<string TileOp> :
PseudoCCallImpl<(outs ACC_TILE_DstWithArrow:$DstTile),
PseudoCCallImpl<(outs TILE_DstWithArrow:$DstTile),
(ins GPRPlusImm:$RegM, PlusImm17:$immM, GPRPlusImm:$RegN, PlusImm17:$immN, GPRPlusImm:$RegK, PlusImm17:$immK, BstartDataType:$DataTypeA, BstartDataType:$DataTypeB,
TileSizeWithBracket:$TileSize, TILE_Src_Reg:$SrcTile0, TILE_Src_Reg:$SrcTile1, TILE_Src_Reg:$SrcTile2, ACC_TILE_SRC:$ACC)> {
TileSizeWithBracket:$TileSize, TILE_Src_Reg:$SrcTile0, TILE_Src_Reg:$SrcTile1, TILE_Src_Reg:$SrcTile2, TILE_Src_Reg:$ACC)> {
let AsmString = TileOp # "\t<M: $RegM$immM, N: $RegN$immN, K: $RegK$immK, ${DataTypeA}, ${DataTypeB}>" # "\t$SrcTile0, $SrcTile1, $SrcTile2, $ACC, $DstTile$TileSize";
}

Expand Down
40 changes: 39 additions & 1 deletion llvm/lib/Target/LinxV5/MCTargetDesc/LinxV5TileOpExpand.cpp
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Expand Up @@ -260,7 +260,7 @@ llvm::SmallVector<MCInst> getBATTRFromInst(MCInst Inst,
.addOperand(MCOperand::createImm(0))
.addOperand(MCOperand::createImm(LinxV5Op::Canon::NORMAL_CANON))
.addOperand(MCOperand::createImm(DataTypeB.getImm()))
.addOperand(MCOperand::createImm(LinxV5Op::PadValue::Null))
.addOperand(MCOperand::createImm(LinxV5Op::PadValue::Zero))
.addOperand(MCOperand::createImm(LinxV5Op::CmpMode::EQ))
.addOperand(MCOperand::createImm(LinxV5Op::RMode::RNONE))
.addOperand(MCOperand::createImm(LinxV5Op::Sat::NOSAT))
Expand All @@ -287,6 +287,44 @@ llvm::SmallVector<MCInst> getBIOTFromInst(MCInst Inst, const MCInstrInfo &MII) {
getPseudoCallBIOTBySrcDstNum(McVec, Inst, MII);
return McVec;
}

// Active local Matrix pseudos share one stable operand layout:
// Op0 destination, Op1..6 dimensions, Op7..8 data types,
// Op9 destination SizeCode, Op10..N relative Local sources.
// Bind sources in their encoded order and place the destination only on
// the terminating packet. The source register spellings (T#n/U#n/M#n/N#n)
// are architectural relative-generation selectors, not physical indices.
if (isActiveMatrixPseudo(Inst.getOpcode()) &&
Inst.getOpcode() != LinxV5::PseudoMAMULB_SharedRight_SizeI) {
constexpr unsigned DstOpNo = 0;
constexpr unsigned TileSizeOpNo = 9;
constexpr unsigned FirstSrcOpNo = 10;
assert(Inst.getNumOperands() > FirstSrcOpNo &&
"active Matrix pseudo must carry at least one source");

unsigned SrcOpNo = FirstSrcOpNo;
while (SrcOpNo < Inst.getNumOperands()) {
unsigned Remaining = Inst.getNumOperands() - SrcOpNo;
unsigned ThisCount = std::min(2u, Remaining);
bool IsLast = Remaining <= 2;
unsigned Opcode = ThisCount == 1
? (IsLast ? LinxV5::B_IOT_OneSrc_Dst
: LinxV5::B_IOT_OneSrc_NoDst)
: (IsLast ? LinxV5::B_IOT_TwoSrc_Dst
: LinxV5::B_IOT_TwoSrc_NoDst);
MCInstBuilder Builder(Opcode);
if (IsLast)
Builder.addOperand(Inst.getOperand(DstOpNo));
Builder.addOperand(MCOperand::createImm(0b1111));
if (IsLast)
Builder.addOperand(Inst.getOperand(TileSizeOpNo));
Builder.addOperand(MCOperand::createImm(IsLast ? 1 : 0));
for (unsigned I = 0; I < ThisCount; ++I)
Builder.addOperand(Inst.getOperand(SrcOpNo++));
McVec.push_back(Builder);
}
return McVec;
}
switch (Inst.getOpcode()) {
default:
llvm_unreachable("Can not find BIO From Pseudo Inst!");
Expand Down
25 changes: 22 additions & 3 deletions llvm/test/CodeGen/LinxV5/ISel/Float/fsqrt.ll
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@@ -1,10 +1,29 @@
; RUN: llc < %s --march=linx64v5 -O2 | FileCheck %s --dump-input always -vv --check-prefixes=CHECK,DAG
; RUN: llc < %s --march=linx64v5 -O2 | FileCheck %s --dump-input always -vv --check-prefix=CHECK

declare double @llvm.sqrt.f64(double) nounwind readnone
declare float @llvm.sqrt.f32(float) nounwind readnone
declare half @llvm.sqrt.f16(half) nounwind readnone

; CHECK-LABEL: fsqrt.fd:
; DAG: CALL, sqrt
; CHECK: fsqrt.fd
; CHECK-NOT: CALL
define double @fsqrt.fd(double %a) {
%sqrt = call double @llvm.sqrt.f64(double %a)
ret double %sqrt
}
}

; CHECK-LABEL: fsqrt.fs:
; CHECK: fsqrt.fs
; CHECK-NOT: CALL
define float @fsqrt.fs(float %a) {
%sqrt = call float @llvm.sqrt.f32(float %a)
ret float %sqrt
}

; CHECK-LABEL: fsqrt.fh:
; CHECK: fsqrt.fh
; CHECK-NOT: CALL
define half @fsqrt.fh(half %a) {
%sqrt = call half @llvm.sqrt.f16(half %a)
ret half %sqrt
}
63 changes: 32 additions & 31 deletions llvm/test/MC/LinxV5/CUBE_Mamulb-asm-operands.s
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Expand Up @@ -2,84 +2,85 @@

// imm <Size>
// CHECK: BSTART.CUBE TMATMULMX, FP32
// CHECK: B.DATR FP16, byte0, Null
// CHECK: B.DATR FP16, byte0, Zero
// CHECK: B.DIM zero, 32, ->lb0
// CHECK: B.DIM zero, 24, ->lb1
// CHECK: B.DIM zero, 16, ->lb2
// CHECK: B.IOT [t#1, t#2]
// CHECK: B.IOT [t#3, t#4], last ->acc<64KB>
TMATMULMX <M:32, N:24, K:16, FP32, FP16> T#1, T#2, T#3, T#4, ->ACC<64KB>
// CHECK: B.IOT t#1, t#2, mask=1111
// CHECK: B.IOT t#3, t#4, mask=1111, last, ->u<64KB>
TMATMULMX <M:32, N:24, K:16, FP32, FP16> T#1, T#2, T#3, T#4, ->U<64KB>

// imm <Size>, same datatype
// CHECK: BSTART.CUBE TMATMULMX, FP16
// CHECK-NOT: B.ATTR
// CHECK: B.DIM zero, 32, ->lb0
// CHECK: B.DIM zero, 24, ->lb1
// CHECK: B.DIM zero, 16, ->lb2
// CHECK: B.IOT [t#1, t#3]
// CHECK: B.IOT [t#4], last ->acc<64KB>
TMATMULMX <M:32, N:24, K:16, FP16, FP16> T#1, T#3, T#4, ->ACC<64KB>
// CHECK: B.IOT t#1, t#3, mask=1111
// CHECK: B.IOT t#4, mask=1111, last, ->u<64KB>
TMATMULMX <M:32, N:24, K:16, FP16, FP16> T#1, T#3, T#4, ->U<64KB>

// imm <Size>
// CHECK: BSTART.CUBE TMATMULMX.BIAS, FP32
// CHECK: B.DATR FP16, byte0, Null
// CHECK: B.DATR FP16, byte0, Zero
// CHECK: B.DIM zero, 32, ->lb0
// CHECK: B.DIM zero, 24, ->lb1
// CHECK: B.DIM zero, 16, ->lb2
// CHECK: B.IOT [t#1, t#2]
// CHECK: B.IOT [t#3, t#4]
// CHECK: B.IOT [u#1], last ->acc<64KB>
TMATMULMX.BIAS <M:32, N:24, K:16, FP32, FP16> T#1, T#2, T#3, T#4, U#1 ->ACC<64KB>
// CHECK: B.IOT t#1, t#2, mask=1111
// CHECK: B.IOT t#3, t#4, mask=1111
// CHECK: B.IOT u#1, mask=1111, last, ->u<64KB>
TMATMULMX.BIAS <M:32, N:24, K:16, FP32, FP16> T#1, T#2, T#3, T#4, U#1 ->U<64KB>

// imm <Size>, ACC source
// CHECK: BSTART.CUBE TMATMULMX.ACC, FP32
// CHECK-NOT: B.DATR
// CHECK: B.DIM zero, 32, ->lb0
// CHECK: B.DIM zero, 24, ->lb1
// CHECK: B.DIM zero, 16, ->lb2
// CHECK: B.IOT [t#1, t#2]
// CHECK: B.IOT [t#3, t#4], last ->acc<64KB>
TMATMULMX.ACC <M:32, N:24, K:16, FP32, FP32> T#1, T#2, T#3, T#4, ACC#1 ->ACC<64KB>
// CHECK: B.IOT t#1, t#2, mask=1111
// CHECK: B.IOT t#3, t#4, mask=1111
// CHECK: B.IOT u#1, mask=1111, last, ->u<64KB>
TMATMULMX.ACC <M:32, N:24, K:16, FP32, FP32> T#1, T#2, T#3, T#4, U#1 ->U<64KB>

// imm <Size>
// CHECK: BSTART.CUBE TMATMULMX.BIAS, FP32
// CHECK: B.DATR FP16, byte0, Null
// CHECK: B.DATR FP16, byte0, Zero
// CHECK: B.DIM zero, 32, ->lb0
// CHECK: B.DIM zero, 24, ->lb1
// CHECK: B.DIM zero, 16, ->lb2
// CHECK: B.IOT [t#1, t#3]
// CHECK: B.IOT [t#4, u#1], last ->acc<64KB>
TMATMULMX.BIAS <M:32, N:24, K:16, FP32, FP16> T#1, T#3, T#4, U#1 ->ACC<64KB>
// CHECK: B.IOT t#1, t#3, mask=1111
// CHECK: B.IOT t#4, u#1, mask=1111, last, ->u<64KB>
TMATMULMX.BIAS <M:32, N:24, K:16, FP32, FP16> T#1, T#3, T#4, U#1 ->U<64KB>

// imm <Size>, ACC source
// CHECK: BSTART.CUBE TMATMULMX.ACC, FP32
// CHECK: B.DATR FP16, byte0, Null
// CHECK: B.DATR FP16, byte0, Zero
// CHECK: B.DIM zero, 32, ->lb0
// CHECK: B.DIM zero, 24, ->lb1
// CHECK: B.DIM zero, 16, ->lb2
// CHECK: B.IOT [t#1, t#3]
// CHECK: B.IOT [t#4], last ->acc<64KB>
TMATMULMX.ACC <M:32, N:24, K:16, FP32, FP16> T#1, T#3, T#4, ACC#1 ->ACC<64KB>
// CHECK: B.IOT t#1, t#3, mask=1111
// CHECK: B.IOT t#4, u#1, mask=1111, last, ->u<64KB>
TMATMULMX.ACC <M:32, N:24, K:16, FP32, FP16> T#1, T#3, T#4, U#1 ->U<64KB>

// Reg+imm <Size>
// CHECK: BSTART.CUBE TMATMULMX, FP32
// CHECK: B.DATR FP16, byte0, Null
// CHECK: B.DATR FP16, byte0, Zero
// CHECK: B.DIM a0, 32, ->lb0
// CHECK: B.DIM zero, 24, ->lb1
// CHECK: B.DIM zero, 16, ->lb2
// CHECK: B.IOT [t#1, t#2]
// CHECK: B.IOT [t#3, t#4], last ->acc<64KB>
TMATMULMX <M:R2+32, N:24, K:16, FP32, FP16> T#1, T#2, T#3, T#4, ->ACC<64KB>
// CHECK: B.IOT t#1, t#2, mask=1111
// CHECK: B.IOT t#3, t#4, mask=1111, last, ->u<64KB>
TMATMULMX <M:R2+32, N:24, K:16, FP32, FP16> T#1, T#2, T#3, T#4, ->U<64KB>

// imm <Size>
// CHECK: BSTART.CUBE TMATMULMX, FP32
// CHECK: B.DATR FP16, byte0, Null
// CHECK: B.DATR FP16, byte0, Zero
// CHECK: B.DIM zero, 32, ->lb0
// CHECK: B.DIM zero, 24, ->lb1
// CHECK: B.DIM zero, 16, ->lb2
// CHECK: B.IOT [t#1, t#2]
// CHECK: B.IOT [t#3, t#4], last ->acc<64KB>
TMATMULMX <M:32, N:24, K:16, FP32, FP16> T#1, T#2, T#3, T#4, ->ACC<64KB>
// CHECK: B.IOT t#1, t#2, mask=1111
// CHECK: B.IOT t#3, t#4, mask=1111, last, ->u<64KB>
TMATMULMX <M:32, N:24, K:16, FP32, FP16> T#1, T#2, T#3, T#4, ->U<64KB>

// imm <Size>
// CHECK-NOT: BSTART.CUBE TCVT, FP32
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14 changes: 14 additions & 0 deletions llvm/test/MC/LinxV5/elf-machine.s
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# RUN: llvm-mc -triple=linx64v5 -filetype=obj %s -o %t.o
# RUN: llvm-readobj --file-headers %t.o | FileCheck %s --check-prefix=OBJ
# RUN: ld.lld -e _start %t.o -o %t
# RUN: llvm-readobj --file-headers %t | FileCheck %s --check-prefix=EXEC

# OBJ: Type: Relocatable
# OBJ: Machine: EM_LinxV5 (0xE9)

# EXEC: Type: Executable
# EXEC: Machine: EM_LinxV5 (0xE9)

.globl _start
_start:
c.bstop
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