[PTO 0.58.6][MC] Add single-line TileOp assembly and bundle-aware disassembly to dev-llvm15_56

[zhoubot]

Problem

PTO 0.58.6 defines a canonical single-line TileOp macro-assembly surface over existing physical Block bundles. The dev-llvm15_56 branch has older per-operation pseudos and physical MC decoding, but it does not consume the current 117-operation / 141-form schema or fold complete bundles back into one TileOp line.

Normative input

• PTO-SPEC issue: [ndf]: define PTO 0.58.6 TileOp macro assembly and bundle folding PTO-ISA/pto-spec#261
• PTO-SPEC PR: Define single-line TileOp macro assembly for PTO 0.58.6 PTO-ISA/pto-spec#263
• Reviewed catalog tree: b50ed858d52aa0bf166556b816308f2062f20def
• Catalog: spec/catalog/tile-macro-assembly.json
• Architecture identity: 0.58.6
• Required syntax: exactly one source line per TileOp; newline terminates the instruction; no continuation and no canonical wrapping.

Complete TileOp inventory

Every row below comes from the reviewed PTO-SPEC catalog. Forms are listed exactly as owned by PTO-SPEC.

VEC (31 operations)

TileOp	Canonical one-line forms
TABS	TABS <LB0:ValidCol, LB1:ValidRow?, LB2:Col?, DataType, PadValue?, PEMask>, SrcTile0, ->DstTile<Size>
TADD	TADD <LB0:ValidCol, LB1:ValidRow?, LB2:Col?, DataType, PadValue?, PEMask>, SrcTile0, SrcTile1, ->DstTile<Size>
TADDS	TADDS <LB0:ValidCol, LB1:ValidRow?, LB2:Col?, DataType, PadValue?, PEMask>, SrcTile0, ScalarGPR0?, ->DstTile<Size>
TAND	TAND <LB0:ValidCol, LB1:ValidRow?, LB2:Col?, DataType, PadValue?, PEMask>, SrcTile0, SrcTile1, ->DstTile<Size>
TANDS	TANDS <LB0:ValidCol, LB1:ValidRow?, LB2:Col?, DataType, PadValue?, PEMask>, SrcTile0, ScalarGPR0?, ->DstTile<Size>
TCMP	TCMP <LB0:ValidCol, LB1:ValidRow=1, LB2:Col=ValidCol, DataType, CMode=EQ, PadValue=Null, PEMask>, SrcTile0, SrcTile1, ->PredicateTile<Size> TCMP <LB0:ValidCol, LB1:ValidRow=1, LB2:Col=ValidCol, DataType, CMode=EQ, PadValue=Null, PEMask>, SrcTile0, SrcTile1, ->PredicateCell<Size> TCMP <LB0:ValidCol, LB1:ValidRow=1, LB2:Col=ValidCol, DataType, CMode=EQ, PadValue=Null, SatMode?, PEMask>, SrcTile0, SrcTile1, ->PredicateGPR
TCMPS	TCMPS <LB0:ValidCol, LB1:ValidRow=1, LB2:Col=ValidCol, DataType, CMode=EQ, PadValue=Null, PEMask>, SrcTile0, ScalarGPR0=zero, ->PredicateTile<Size> TCMPS <LB0:ValidCol, LB1:ValidRow=1, LB2:Col=ValidCol, DataType, CMode=EQ, PadValue=Null, PEMask>, SrcTile0, ScalarGPR0=zero, ->PredicateCell<Size> TCMPS <LB0:ValidCol, LB1:ValidRow=1, LB2:Col=ValidCol, DataType, CMode=EQ, PadValue=Null, SatMode?, PEMask>, SrcTile0, ScalarGPR0=zero, ->PredicateGPR
TCVT	TCVT <LB0:ValidCol, LB1:ValidRow?, LB2:Col?, SrcDataType, DstDataType?, RMode?, Sat?, Canonicalize?, Layout?, PadValue?, PEMask>, SrcTile0, ->DstTile<Size>
TEXPANDS	TEXPANDS <LB0:ValidCol, LB1:ValidRow?, LB2:Col?, DataType, Layout?, PadValue?, PEMask>, ScalarGPR0?, ->DstTile<Size>
TFMA	TFMA <LB0:ValidCol, LB1:ValidRow?, LB2:Col?, DataType, PadValue?, PEMask>, SrcTile0, SrcTile1, SrcTile2, ->DstTile<Size>
TMAX	TMAX <LB0:ValidCol, LB1:ValidRow?, LB2:Col?, DataType, PadValue?, PEMask>, SrcTile0, SrcTile1, ->DstTile<Size>
TMAXS	TMAXS <LB0:ValidCol, LB1:ValidRow?, LB2:Col?, DataType, PadValue?, PEMask>, SrcTile0, ScalarGPR0?, ->DstTile<Size>
TMIN	TMIN <LB0:ValidCol, LB1:ValidRow?, LB2:Col?, DataType, PadValue?, PEMask>, SrcTile0, SrcTile1, ->DstTile<Size>
TMINS	TMINS <LB0:ValidCol, LB1:ValidRow?, LB2:Col?, DataType, PadValue?, PEMask>, SrcTile0, ScalarGPR0?, ->DstTile<Size>
TMUL	TMUL <LB0:ValidCol, LB1:ValidRow?, LB2:Col?, DataType, PadValue?, PEMask>, SrcTile0, SrcTile1, ->DstTile<Size>
TMULS	TMULS <LB0:ValidCol, LB1:ValidRow?, LB2:Col?, DataType, PadValue?, PEMask>, SrcTile0, ScalarGPR0?, ->DstTile<Size>
TNEG	TNEG <LB0:ValidCol, LB1:ValidRow?, LB2:Col?, DataType, PadValue?, PEMask>, SrcTile0, ->DstTile<Size>
TNOT	TNOT <LB0:ValidCol, LB1:ValidRow?, LB2:Col?, DataType, PadValue?, PEMask>, SrcTile0, ->DstTile<Size>
TOR	TOR <LB0:ValidCol, LB1:ValidRow?, LB2:Col?, DataType, PadValue?, PEMask>, SrcTile0, SrcTile1, ->DstTile<Size>
TORS	TORS <LB0:ValidCol, LB1:ValidRow?, LB2:Col?, DataType, PadValue?, PEMask>, SrcTile0, ScalarGPR0?, ->DstTile<Size>
TRELU	TRELU <LB0:ValidCol, LB1:ValidRow?, LB2:Col?, DataType, PadValue?, PEMask>, SrcTile0, ->DstTile<Size>
TSEL	TSEL <LB0:ValidCol, LB1:ValidRow=1, LB2:Col=ValidCol, DataType, PadValue=Null, PEMask>, PredicateTile0, SrcTile1, SrcTile2, ->DstTile<Size> TSEL <LB0:ValidCol, LB1:ValidRow=1, LB2:Col=ValidCol, DataType, PadValue=Null, PEMask>, PredicateCell0, SrcTile1, SrcTile2, ->DstTile<Size> TSEL <LB0:ValidCol, LB1:ValidRow=1, LB2:Col=ValidCol, DataType, PadValue=Null, PEMask>, PredicateGPR0, PredicateGPR1{if DataType=U8}, SrcTile1, SrcTile2, ->DstTile<Size>
TSELS	TSELS <LB0:ValidCol, LB1:ValidRow=1, LB2:Col=ValidCol, DataType, PadValue=Null, PEMask>, PredicateTile0, SrcTile1, ScalarFalseGPR=zero, ->DstTile<Size> TSELS <LB0:ValidCol, LB1:ValidRow=1, LB2:Col=ValidCol, DataType, PadValue=Null, PEMask>, PredicateCell0, SrcTile1, ScalarFalseGPR=zero, ->DstTile<Size> TSELS <LB0:ValidCol, LB1:ValidRow=1, LB2:Col=ValidCol, DataType, PadValue=Null, PEMask>, PredicateGPR0, PredicateGPR1{if DataType=U8}, SrcTile1, ScalarFalseGPR=zero, ->DstTile<Size>
TSHL	TSHL <LB0:ValidCol, LB1:ValidRow?, LB2:Col?, DataType, PadValue?, PEMask>, SrcTile0, SrcTile1, ->DstTile<Size>
TSHLS	TSHLS <LB0:ValidCol, LB1:ValidRow?, LB2:Col?, DataType, PadValue?, PEMask>, SrcTile0, ScalarGPR0?, ->DstTile<Size>
TSHR	TSHR <LB0:ValidCol, LB1:ValidRow?, LB2:Col?, DataType, PadValue?, PEMask>, SrcTile0, SrcTile1, ->DstTile<Size>
TSHRS	TSHRS <LB0:ValidCol, LB1:ValidRow?, LB2:Col?, DataType, PadValue?, PEMask>, SrcTile0, ScalarGPR0?, ->DstTile<Size>
TSUB	TSUB <LB0:ValidCol, LB1:ValidRow?, LB2:Col?, DataType, PadValue?, PEMask>, SrcTile0, SrcTile1, ->DstTile<Size>
TSUBS	TSUBS <LB0:ValidCol, LB1:ValidRow?, LB2:Col?, DataType, PadValue?, PEMask>, SrcTile0, ScalarGPR0?, ->DstTile<Size>
TXOR	TXOR <LB0:ValidCol, LB1:ValidRow?, LB2:Col?, DataType, PadValue?, PEMask>, SrcTile0, SrcTile1, ->DstTile<Size>
TXORS	TXORS <LB0:ValidCol, LB1:ValidRow?, LB2:Col?, DataType, PadValue?, PEMask>, SrcTile0, ScalarGPR0?, ->DstTile<Size>

SFU (46 operations)

TileOp	Canonical one-line forms
TCI	TCI <LB0:ValidCol, LB1:ValidRow=1, LB2:Col=ValidCol, DataType, PEMask>, Start=0, Direction=ascending, ->DstTile<Size>
TCOLARGMAX	TCOLARGMAX <LB0:ValidCol, LB1:ValidRow?, LB2:Col?, DataType, Layout?, PadValue?, PEMask>, SrcTile0, ->DstTile<Size>
TCOLARGMIN	TCOLARGMIN <LB0:ValidCol, LB1:ValidRow?, LB2:Col?, DataType, Layout?, PadValue?, PEMask>, SrcTile0, ->DstTile<Size>
TCOLEXPAND	TCOLEXPAND <LB0:ValidCol, LB1:ValidRow?, LB2:Col?, DataType, Layout?, PadValue?, PEMask>, SrcTile0, ->DstTile<Size>
TCOLEXPANDADD	TCOLEXPANDADD <LB0:ValidCol, LB1:ValidRow?, LB2:Col?, DataType, Layout?, PadValue?, PEMask>, SrcTile0, SrcTile1, ->DstTile<Size>
TCOLEXPANDDIV	TCOLEXPANDDIV <LB0:ValidCol, LB1:ValidRow?, LB2:Col?, DataType, Layout?, PadValue?, PEMask>, SrcTile0, SrcTile1, ->DstTile<Size>
TCOLEXPANDEXPDIF	TCOLEXPANDEXPDIF <LB0:ValidCol, LB1:ValidRow?, LB2:Col?, DataType, Layout?, PadValue?, PEMask>, SrcTile0, SrcTile1, ->DstTile<Size>
TCOLEXPANDMAX	TCOLEXPANDMAX <LB0:ValidCol, LB1:ValidRow?, LB2:Col?, DataType, Layout?, PadValue?, PEMask>, SrcTile0, SrcTile1, ->DstTile<Size>
TCOLEXPANDMIN	TCOLEXPANDMIN <LB0:ValidCol, LB1:ValidRow?, LB2:Col?, DataType, Layout?, PadValue?, PEMask>, SrcTile0, SrcTile1, ->DstTile<Size>
TCOLEXPANDMUL	TCOLEXPANDMUL <LB0:ValidCol, LB1:ValidRow?, LB2:Col?, DataType, Layout?, PadValue?, PEMask>, SrcTile0, SrcTile1, ->DstTile<Size>
TCOLEXPANDSUB	TCOLEXPANDSUB <LB0:ValidCol, LB1:ValidRow?, LB2:Col?, DataType, Layout?, PadValue?, PEMask>, SrcTile0, SrcTile1, ->DstTile<Size>
TCOLMAX	TCOLMAX <LB0:ValidCol, LB1:ValidRow?, LB2:Col?, DataType, Layout?, PadValue?, PEMask>, SrcTile0, ->DstTile<Size>
TCOLMIN	TCOLMIN <LB0:ValidCol, LB1:ValidRow?, LB2:Col?, DataType, Layout?, PadValue?, PEMask>, SrcTile0, ->DstTile<Size>
TCOLPROD	TCOLPROD <LB0:ValidCol, LB1:ValidRow?, LB2:Col?, DataType, Layout?, PadValue?, PEMask>, SrcTile0, ->DstTile<Size>
TCOLSUM	TCOLSUM <LB0:ValidCol, LB1:ValidRow?, LB2:Col?, DataType, Layout?, PadValue?, PEMask>, SrcTile0, ->DstTile<Size>
TDIV	TDIV <LB0:ValidCol, LB1:ValidRow?, LB2:Col?, DataType, PadValue?, PEMask>, SrcTile0, SrcTile1, ->DstTile<Size>
TDIVS	TDIVS <LB0:ValidCol, LB1:ValidRow?, LB2:Col?, DataType, PadValue?, PEMask>, SrcTile0, ScalarGPR0?, ->DstTile<Size>
TEXP	TEXP <LB0:ValidCol, LB1:ValidRow?, LB2:Col?, DataType, PadValue?, PEMask>, SrcTile0, ->DstTile<Size>
TGATHER	TGATHER <LB0:ValidCol, LB1:ValidRow?, LB2:Col?, ValueDataType, Layout?, PEMask>, SrcTile0, SrcTile1, ->DstTile<Size>
TGPR2T	TGPR2T <LB0:ValidCol, LB1:ValidRow, U8, PadValueOrByteId?, RMode?, PEMask>, ScalarGPR0, ScalarGPR1, ScalarGPR2, ScalarGPR3, ->DstTile<Size>
TLOG	TLOG <LB0:ValidCol, LB1:ValidRow?, LB2:Col?, DataType, PadValue?, PEMask>, SrcTile0, ->DstTile<Size>
TPACK	TPACK <LB0?, LB1?, LB2?, U32, Layout?, PEMask>, SrcTile0, SrcTile1, ScalarGPR0, ->DstTile<Size>
TPERMUTE	TPERMUTE <LB0?, LB1?, LB2?, DataType, Layout?, PEMask>, SrcTile0, SrcTile1, SrcTile2, ->DstTile<Size>
TRECIP	TRECIP <LB0:ValidCol, LB1:ValidRow?, LB2:Col?, DataType, PadValue?, PEMask>, SrcTile0, ->DstTile<Size>
TREM	TREM <LB0:ValidCol, LB1:ValidRow?, LB2:Col?, DataType, PadValue?, PEMask>, SrcTile0, SrcTile1, ->DstTile<Size>
TREMS	TREMS <LB0:ValidCol, LB1:ValidRow?, LB2:Col?, DataType, PadValue?, PEMask>, SrcTile0, ScalarGPR0?, ->DstTile<Size>
TROWARGMAX	TROWARGMAX <LB0:ValidCol, LB1:ValidRow?, LB2:Col?, DataType, Layout?, PadValue?, PEMask>, SrcTile0, ->DstTile<Size>
TROWARGMIN	TROWARGMIN <LB0:ValidCol, LB1:ValidRow?, LB2:Col?, DataType, Layout?, PadValue?, PEMask>, SrcTile0, ->DstTile<Size>
TROWEXPAND	TROWEXPAND <LB0:ValidCol, LB1:ValidRow?, LB2:Col?, DataType, Layout?, PadValue?, PEMask>, SrcTile0, ->DstTile<Size>
TROWEXPANDADD	TROWEXPANDADD <LB0:ValidCol, LB1:ValidRow?, LB2:Col?, DataType, Layout?, PadValue?, PEMask>, SrcTile0, SrcTile1, ->DstTile<Size>
TROWEXPANDDIV	TROWEXPANDDIV <LB0:ValidCol, LB1:ValidRow?, LB2:Col?, DataType, Layout?, PadValue?, PEMask>, SrcTile0, SrcTile1, ->DstTile<Size>
TROWEXPANDEXPDIF	TROWEXPANDEXPDIF <LB0:ValidCol, LB1:ValidRow?, LB2:Col?, DataType, Layout?, PadValue?, PEMask>, SrcTile0, SrcTile1, ->DstTile<Size>
TROWEXPANDMAX	TROWEXPANDMAX <LB0:ValidCol, LB1:ValidRow?, LB2:Col?, DataType, Layout?, PadValue?, PEMask>, SrcTile0, SrcTile1, ->DstTile<Size>
TROWEXPANDMIN	TROWEXPANDMIN <LB0:ValidCol, LB1:ValidRow?, LB2:Col?, DataType, Layout?, PadValue?, PEMask>, SrcTile0, SrcTile1, ->DstTile<Size>
TROWEXPANDMUL	TROWEXPANDMUL <LB0:ValidCol, LB1:ValidRow?, LB2:Col?, DataType, Layout?, PadValue?, PEMask>, SrcTile0, SrcTile1, ->DstTile<Size>
TROWEXPANDSUB	TROWEXPANDSUB <LB0:ValidCol, LB1:ValidRow?, LB2:Col?, DataType, Layout?, PadValue?, PEMask>, SrcTile0, SrcTile1, ->DstTile<Size>
TROWMAX	TROWMAX <LB0:ValidCol, LB1:ValidRow?, LB2:Col?, DataType, Layout?, PadValue?, PEMask>, SrcTile0, ->DstTile<Size>
TROWMIN	TROWMIN <LB0:ValidCol, LB1:ValidRow?, LB2:Col?, DataType, Layout?, PadValue?, PEMask>, SrcTile0, ->DstTile<Size>
TROWPROD	TROWPROD <LB0:ValidCol, LB1:ValidRow?, LB2:Col?, DataType, Layout?, PadValue?, PEMask>, SrcTile0, ->DstTile<Size>
TROWSUM	TROWSUM <LB0:ValidCol, LB1:ValidRow?, LB2:Col?, DataType, Layout?, PadValue?, PEMask>, SrcTile0, ->DstTile<Size>
TRSQRT	TRSQRT <LB0:ValidCol, LB1:ValidRow?, LB2:Col?, DataType, PadValue?, PEMask>, SrcTile0, ->DstTile<Size>
TSCATTER	TSCATTER <LB0:ValidCol, LB1:ValidRow?, LB2:Col?, ValueDataType, Layout?, PEMask>, SrcTile0, SrcTile1, ->DstTile<Size>
TSHUF	TSHUF <LB0?, LB1?, LB2?, DataType, Layout?, PEMask>, SrcTile0, SrcTile1, ScalarGPR0, ->DstTile<Size>
TSQRT	TSQRT <LB0:ValidCol, LB1:ValidRow?, LB2:Col?, DataType, PadValue?, PEMask>, SrcTile0, ->DstTile<Size>
TTRI	TTRI <LB0:ValidCol, LB1:ValidRow=1, LB2:Col=ValidCol, DataType, PEMask>, Diagonal=0, Orientation=lower, ->DstTile<Size>
TUNPACK	TUNPACK <LB0?, LB1?, LB2?, U32, Layout?, PEMask>, SrcTile0, ScalarGPR0, ->DstTile<Size>

TLSU (28 operations)

TileOp	Canonical one-line forms
GMOV	GMOV <DataType, Layout?, PEMask>, SrcTile0, PeerTid?, ->DstTile<Size>
MGATHER	MGATHER <LB0:ValidCol, LB1:ValidRow?, LB2:Col?, DataType, PadValue?, Layout?, PEMask>, [BaseGPR], RowStrideGPR, SrcTile0, ->DstTile<Size>
MGATHER_ADD	MGATHER_ADD <DataType, PEMask>, [BaseGPR], SrcTile0, SrcTile1, ->DstTile<Size>
MGATHER_AND	MGATHER_AND <DataType, PEMask>, [BaseGPR], SrcTile0, SrcTile1, ->DstTile<Size>
MGATHER_CAS	MGATHER_CAS <DataType, PEMask>, [BaseGPR], RowStrideGPR, SrcTile0, SrcTile1, SrcTile2, ->DstTile<Size>
MGATHER_DEC	MGATHER_DEC <DataType, PEMask>, [BaseGPR], SrcTile0, SrcTile1, ->DstTile<Size>
MGATHER_EXCH	MGATHER_EXCH <DataType, PEMask>, [BaseGPR], SrcTile0, SrcTile1, ->DstTile<Size>
MGATHER_INC	MGATHER_INC <DataType, PEMask>, [BaseGPR], SrcTile0, SrcTile1, ->DstTile<Size>
MGATHER_MASK	MGATHER_MASK <LB0:ValidCol, LB1:ValidRow?, LB2:Col?, DataType, PadValue?, Layout?, PEMask>, [BaseGPR], RowStrideGPR, SrcTile0, PredicateTile1, ->DstTile<Size>
MGATHER_MAX	MGATHER_MAX <DataType, PEMask>, [BaseGPR], SrcTile0, SrcTile1, ->DstTile<Size>
MGATHER_MIN	MGATHER_MIN <DataType, PEMask>, [BaseGPR], SrcTile0, SrcTile1, ->DstTile<Size>
MGATHER_OR	MGATHER_OR <DataType, PEMask>, [BaseGPR], SrcTile0, SrcTile1, ->DstTile<Size>
MGATHER_XOR	MGATHER_XOR <DataType, PEMask>, [BaseGPR], SrcTile0, SrcTile1, ->DstTile<Size>
MSCATTER	MSCATTER <LB0:ValidCol, LB1:ValidRow?, LB2:Col?, DataType, Layout?, PEMask>, [BaseGPR], RowStrideGPR, SrcTile0, SrcTile1
MSCATTER_ADD	MSCATTER_ADD <DataType, PEMask>, [BaseGPR], SrcTile0, SrcTile1
MSCATTER_AND	MSCATTER_AND <DataType, PEMask>, [BaseGPR], SrcTile0, SrcTile1
MSCATTER_DEC	MSCATTER_DEC <DataType, PEMask>, [BaseGPR], SrcTile0, SrcTile1
MSCATTER_INC	MSCATTER_INC <DataType, PEMask>, [BaseGPR], SrcTile0, SrcTile1
MSCATTER_MASK	MSCATTER_MASK <LB0:ValidCol, LB1:ValidRow?, LB2:Col?, DataType, Layout?, PEMask>, [BaseGPR], RowStrideGPR, SrcTile0, SrcTile1, PredicateTile2
MSCATTER_MAX	MSCATTER_MAX <DataType, PEMask>, [BaseGPR], SrcTile0, SrcTile1
MSCATTER_MIN	MSCATTER_MIN <DataType, PEMask>, [BaseGPR], SrcTile0, SrcTile1
MSCATTER_OR	MSCATTER_OR <DataType, PEMask>, [BaseGPR], SrcTile0, SrcTile1
MSCATTER_POPC	MSCATTER_POPC <LB0:ValidCol, DataType, PEMask>, [BaseGPR], SrcTile0
MSCATTER_XOR	MSCATTER_XOR <DataType, PEMask>, [BaseGPR], SrcTile0, SrcTile1
TLOAD	TLOAD <LB0:ValidCol?, LB1:ValidRow?, LB2:Col=ValidCol, DataType, Layout?, PEMask>, [BaseGPR=zero, RowStrideGPR?], ->DstTile<Size> TLOAD.SHARED <LB0:ValidCol?, LB1:ValidRow?, LB2:Col=ValidCol, DataType, Layout?, PEMask>, [BaseGPR=zero, RowStrideGPR?], ->DstShared<Size> TLOAD.CUBE <LB0:ValidCol, LB1:ValidRow, CubeLayout, DTYPE_NONE, PadValue, PEMask>, [BaseGPR=zero, RowStrideGPR?], ->DstTile<Size>
TMOV	TMOV <LB0, LB1?, LB2?, DataType, Layout?, PEMask>, SrcTile0, ->DstTile<Size>
TPREFETCH	TPREFETCH <LB0:ValidCol=1, LB1:ValidRow=1, LB2:Col=ValidCol, DataType, Layout?>, [BaseGPR=zero, RowStrideGPR?]
TSTORE	TSTORE <LB0:ValidCol=SourceDescriptor, LB1:ValidRow=SourceDescriptor, LB2:Col=SourceDescriptor, DataType, Layout?, PEMask>, SrcTile, [BaseGPR=zero, RowStrideGPR?] TSTORE.SHARED <LB0:ValidCol=SourceOr1, LB1:ValidRow=SourceOr1, LB2:Col=SourceOrValidCol, DataType, Layout?, PEMask>, SrcShared, [BaseGPR=zero, RowStrideGPR?] TSTORE.CUBE <LB0:ValidCol, LB1:ValidRow, CubeLayout, DTYPE_NONE, PadValue, PEMask>, SrcTile, [BaseGPR=zero, RowStrideGPR?]

CUBE (12 operations)

TileOp	Canonical one-line forms
TGEMV	TGEMV <LB0:M=1, LB1:N=1, LB2:K=1, AType, BType?, RMode?, Sat?, FPAttrs, PEMask>, SrcVector, SrcMatrix, RowMaxIn{if RowMaxEn&&RowMaxInit}, QuantParamTile{if PreQuantMode=vector}, ReluParamTile{if ReluMode=vector}, QuantParamGPR{if PreQuantMode=scalar}, ReluParamGPR{if ReluMode=scalar}, ->DstTile<Size>, ->RowMaxOut<Size>{if RowMaxEn}, ->GroupMaxOut<Size>{if GroupMaxEn}
TGEMV_ACC	TGEMV_ACC <LB0:M=1, LB1:N=1, LB2:K=1, AType, BType?, RMode?, Sat?, FPAttrs, PEMask>, AccTile, SrcVector, SrcMatrix, RowMaxIn{if RowMaxEn&&RowMaxInit}, QuantParamTile{if PreQuantMode=vector}, ReluParamTile{if ReluMode=vector}, QuantParamGPR{if PreQuantMode=scalar}, ReluParamGPR{if ReluMode=scalar}, ->DstTile<Size>, ->RowMaxOut<Size>{if RowMaxEn}, ->GroupMaxOut<Size>{if GroupMaxEn}
TGEMV_BIAS	TGEMV_BIAS <LB0:M=1, LB1:N=1, LB2:K=1, AType, BType?, RMode?, Sat?, FPAttrs, PEMask>, SrcVector, SrcMatrix, BiasTile, RowMaxIn{if RowMaxEn&&RowMaxInit}, QuantParamTile{if PreQuantMode=vector}, ReluParamTile{if ReluMode=vector}, QuantParamGPR{if PreQuantMode=scalar}, ReluParamGPR{if ReluMode=scalar}, ->DstTile<Size>, ->RowMaxOut<Size>{if RowMaxEn}, ->GroupMaxOut<Size>{if GroupMaxEn}
TGEMV_MX	TGEMV_MX <LB0:M=1, LB1:N=1, LB2:K=1, AType, BType?, RMode?, Sat?, FPAttrs, PEMask>, SrcVector, RowScaleTile{if AType requires MX scale}, SrcMatrix, ColumnScaleTile{if BType requires MX scale}, RowMaxIn{if RowMaxEn&&RowMaxInit}, QuantParamTile{if PreQuantMode=vector}, ReluParamTile{if ReluMode=vector}, QuantParamGPR{if PreQuantMode=scalar}, ReluParamGPR{if ReluMode=scalar}, ->DstTile<Size>, ->RowMaxOut<Size>{if RowMaxEn}, ->GroupMaxOut<Size>{if GroupMaxEn}
TGEMV_MX_ACC	TGEMV_MX_ACC <LB0:M=1, LB1:N=1, LB2:K=1, AType, BType?, RMode?, Sat?, FPAttrs, PEMask>, AccTile, SrcVector, RowScaleTile{if AType requires MX scale}, SrcMatrix, ColumnScaleTile{if BType requires MX scale}, RowMaxIn{if RowMaxEn&&RowMaxInit}, QuantParamTile{if PreQuantMode=vector}, ReluParamTile{if ReluMode=vector}, QuantParamGPR{if PreQuantMode=scalar}, ReluParamGPR{if ReluMode=scalar}, ->DstTile<Size>, ->RowMaxOut<Size>{if RowMaxEn}, ->GroupMaxOut<Size>{if GroupMaxEn}
TGEMV_MX_BIAS	TGEMV_MX_BIAS <LB0:M=1, LB1:N=1, LB2:K=1, AType, BType?, RMode?, Sat?, FPAttrs, PEMask>, SrcVector, RowScaleTile{if AType requires MX scale}, SrcMatrix, ColumnScaleTile{if BType requires MX scale}, BiasTile, RowMaxIn{if RowMaxEn&&RowMaxInit}, QuantParamTile{if PreQuantMode=vector}, ReluParamTile{if ReluMode=vector}, QuantParamGPR{if PreQuantMode=scalar}, ReluParamGPR{if ReluMode=scalar}, ->DstTile<Size>, ->RowMaxOut<Size>{if RowMaxEn}, ->GroupMaxOut<Size>{if GroupMaxEn}
TMATMUL	TMATMUL <LB0:M=1, LB1:N=1, LB2:K=1, AType, BType?, RMode?, Sat?, FPAttrs, PEMask>, SrcTile0, SrcTile1, RowMaxIn{if RowMaxEn&&RowMaxInit}, QuantParamTile{if PreQuantMode=vector}, ReluParamTile{if ReluMode=vector}, QuantParamGPR{if PreQuantMode=scalar}, ReluParamGPR{if ReluMode=scalar}, ->DstTile<Size>, ->RowMaxOut<Size>{if RowMaxEn}, ->GroupMaxOut<Size>{if GroupMaxEn} TMATMUL.SHARED_RIGHT <LB0:M=1, LB1:N=1, LB2:K=1, AType, BType?, RMode?, Sat?, FPAttrs, PEMask{must be 1111}>, LocalLeftGroup, SharedRightGroup, RowMaxIn{if RowMaxEn&&RowMaxInit}, QuantParamTile{if PreQuantMode=vector}, ReluParamTile{if ReluMode=vector}, QuantParamGPR{if PreQuantMode=scalar}, ReluParamGPR{if ReluMode=scalar}, ->DstTile<Size>, ->RowMaxOut<Size>{if RowMaxEn}, ->GroupMaxOut<Size>{if GroupMaxEn} TMATMUL.SHARED_BOTH <LB0:M=1, LB1:N=1, LB2:K=1, AType, BType?, RMode?, Sat?, FPAttrs, PEMask{must be 1111}>, SharedLeftGroup, SharedRightGroup, RowMaxIn{if RowMaxEn&&RowMaxInit}, QuantParamTile{if PreQuantMode=vector}, ReluParamTile{if ReluMode=vector}, QuantParamGPR{if PreQuantMode=scalar}, ReluParamGPR{if ReluMode=scalar}, ->DstTile<Size>, ->RowMaxOut<Size>{if RowMaxEn}, ->GroupMaxOut<Size>{if GroupMaxEn}
TMATMUL_ACC	TMATMUL_ACC <LB0:M=1, LB1:N=1, LB2:K=1, AType, BType?, RMode?, Sat?, FPAttrs, PEMask>, AccTile, SrcTile0, SrcTile1, CScaleTile{if CScaleEn}, RowMaxIn{if RowMaxEn&&RowMaxInit}, QuantParamTile{if PreQuantMode=vector}, ReluParamTile{if ReluMode=vector}, QuantParamGPR{if PreQuantMode=scalar}, ReluParamGPR{if ReluMode=scalar}, ->DstTile<Size>, ->RowMaxOut<Size>{if RowMaxEn}, ->GroupMaxOut<Size>{if GroupMaxEn} TMATMUL_ACC.SHARED_RIGHT <LB0:M=1, LB1:N=1, LB2:K=1, AType, BType?, RMode?, Sat?, FPAttrs, PEMask{must be 1111}>, AccTile, LocalLeftGroup, SharedRightGroup, CScaleTile{if CScaleEn}, RowMaxIn{if RowMaxEn&&RowMaxInit}, QuantParamTile{if PreQuantMode=vector}, ReluParamTile{if ReluMode=vector}, QuantParamGPR{if PreQuantMode=scalar}, ReluParamGPR{if ReluMode=scalar}, ->DstTile<Size>, ->RowMaxOut<Size>{if RowMaxEn}, ->GroupMaxOut<Size>{if GroupMaxEn} TMATMUL_ACC.SHARED_BOTH <LB0:M=1, LB1:N=1, LB2:K=1, AType, BType?, RMode?, Sat?, FPAttrs, PEMask{must be 1111}>, AccTile, SharedLeftGroup, SharedRightGroup, CScaleTile{if CScaleEn}, RowMaxIn{if RowMaxEn&&RowMaxInit}, QuantParamTile{if PreQuantMode=vector}, ReluParamTile{if ReluMode=vector}, QuantParamGPR{if PreQuantMode=scalar}, ReluParamGPR{if ReluMode=scalar}, ->DstTile<Size>, ->RowMaxOut<Size>{if RowMaxEn}, ->GroupMaxOut<Size>{if GroupMaxEn}
TMATMUL_BIAS	TMATMUL_BIAS <LB0:M=1, LB1:N=1, LB2:K=1, AType, BType?, RMode?, Sat?, FPAttrs, PEMask>, SrcTile0, SrcTile1, BiasTile, RowMaxIn{if RowMaxEn&&RowMaxInit}, QuantParamTile{if PreQuantMode=vector}, ReluParamTile{if ReluMode=vector}, QuantParamGPR{if PreQuantMode=scalar}, ReluParamGPR{if ReluMode=scalar}, ->DstTile<Size>, ->RowMaxOut<Size>{if RowMaxEn}, ->GroupMaxOut<Size>{if GroupMaxEn} TMATMUL_BIAS.SHARED_RIGHT <LB0:M=1, LB1:N=1, LB2:K=1, AType, BType?, RMode?, Sat?, FPAttrs, PEMask{must be 1111}>, LocalLeftGroup, SharedRightGroup, BiasTile, RowMaxIn{if RowMaxEn&&RowMaxInit}, QuantParamTile{if PreQuantMode=vector}, ReluParamTile{if ReluMode=vector}, QuantParamGPR{if PreQuantMode=scalar}, ReluParamGPR{if ReluMode=scalar}, ->DstTile<Size>, ->RowMaxOut<Size>{if RowMaxEn}, ->GroupMaxOut<Size>{if GroupMaxEn} TMATMUL_BIAS.SHARED_BOTH <LB0:M=1, LB1:N=1, LB2:K=1, AType, BType?, RMode?, Sat?, FPAttrs, PEMask{must be 1111}>, SharedLeftGroup, SharedRightGroup, BiasTile, RowMaxIn{if RowMaxEn&&RowMaxInit}, QuantParamTile{if PreQuantMode=vector}, ReluParamTile{if ReluMode=vector}, QuantParamGPR{if PreQuantMode=scalar}, ReluParamGPR{if ReluMode=scalar}, ->DstTile<Size>, ->RowMaxOut<Size>{if RowMaxEn}, ->GroupMaxOut<Size>{if GroupMaxEn}
TMATMUL_MX	TMATMUL_MX <LB0:M=1, LB1:N=1, LB2:K=1, AType, BType?, RMode?, Sat?, FPAttrs, PEMask>, SrcTile0, RowScaleTile{if AType requires MX scale}, SrcTile1, ColumnScaleTile{if BType requires MX scale}, RowMaxIn{if RowMaxEn&&RowMaxInit}, QuantParamTile{if PreQuantMode=vector}, ReluParamTile{if ReluMode=vector}, QuantParamGPR{if PreQuantMode=scalar}, ReluParamGPR{if ReluMode=scalar}, ->DstTile<Size>, ->RowMaxOut<Size>{if RowMaxEn}, ->GroupMaxOut<Size>{if GroupMaxEn} TMATMUL_MX.SHARED_RIGHT <LB0:M=1, LB1:N=1, LB2:K=1, AType, BType?, RMode?, Sat?, FPAttrs, PEMask{must be 1111}>, LocalLeftGroup, SharedRightGroup, RowMaxIn{if RowMaxEn&&RowMaxInit}, QuantParamTile{if PreQuantMode=vector}, ReluParamTile{if ReluMode=vector}, QuantParamGPR{if PreQuantMode=scalar}, ReluParamGPR{if ReluMode=scalar}, ->DstTile<Size>, ->RowMaxOut<Size>{if RowMaxEn}, ->GroupMaxOut<Size>{if GroupMaxEn} TMATMUL_MX.SHARED_BOTH <LB0:M=1, LB1:N=1, LB2:K=1, AType, BType?, RMode?, Sat?, FPAttrs, PEMask{must be 1111}>, SharedLeftGroup, SharedRightGroup, RowMaxIn{if RowMaxEn&&RowMaxInit}, QuantParamTile{if PreQuantMode=vector}, ReluParamTile{if ReluMode=vector}, QuantParamGPR{if PreQuantMode=scalar}, ReluParamGPR{if ReluMode=scalar}, ->DstTile<Size>, ->RowMaxOut<Size>{if RowMaxEn}, ->GroupMaxOut<Size>{if GroupMaxEn}
TMATMUL_MX_ACC	TMATMUL_MX_ACC <LB0:M=1, LB1:N=1, LB2:K=1, AType, BType?, RMode?, Sat?, FPAttrs, PEMask>, AccTile, SrcTile0, RowScaleTile{if AType requires MX scale}, SrcTile1, ColumnScaleTile{if BType requires MX scale}, CScaleTile{if CScaleEn}, RowMaxIn{if RowMaxEn&&RowMaxInit}, QuantParamTile{if PreQuantMode=vector}, ReluParamTile{if ReluMode=vector}, QuantParamGPR{if PreQuantMode=scalar}, ReluParamGPR{if ReluMode=scalar}, ->DstTile<Size>, ->RowMaxOut<Size>{if RowMaxEn}, ->GroupMaxOut<Size>{if GroupMaxEn} TMATMUL_MX_ACC.SHARED_RIGHT <LB0:M=1, LB1:N=1, LB2:K=1, AType, BType?, RMode?, Sat?, FPAttrs, PEMask{must be 1111}>, AccTile, LocalLeftGroup, SharedRightGroup, CScaleTile{if CScaleEn}, RowMaxIn{if RowMaxEn&&RowMaxInit}, QuantParamTile{if PreQuantMode=vector}, ReluParamTile{if ReluMode=vector}, QuantParamGPR{if PreQuantMode=scalar}, ReluParamGPR{if ReluMode=scalar}, ->DstTile<Size>, ->RowMaxOut<Size>{if RowMaxEn}, ->GroupMaxOut<Size>{if GroupMaxEn} TMATMUL_MX_ACC.SHARED_BOTH <LB0:M=1, LB1:N=1, LB2:K=1, AType, BType?, RMode?, Sat?, FPAttrs, PEMask{must be 1111}>, AccTile, SharedLeftGroup, SharedRightGroup, CScaleTile{if CScaleEn}, RowMaxIn{if RowMaxEn&&RowMaxInit}, QuantParamTile{if PreQuantMode=vector}, ReluParamTile{if ReluMode=vector}, QuantParamGPR{if PreQuantMode=scalar}, ReluParamGPR{if ReluMode=scalar}, ->DstTile<Size>, ->RowMaxOut<Size>{if RowMaxEn}, ->GroupMaxOut<Size>{if GroupMaxEn}
TMATMUL_MX_BIAS	TMATMUL_MX_BIAS <LB0:M=1, LB1:N=1, LB2:K=1, AType, BType?, RMode?, Sat?, FPAttrs, PEMask>, SrcTile0, RowScaleTile{if AType requires MX scale}, SrcTile1, ColumnScaleTile{if BType requires MX scale}, BiasTile, RowMaxIn{if RowMaxEn&&RowMaxInit}, QuantParamTile{if PreQuantMode=vector}, ReluParamTile{if ReluMode=vector}, QuantParamGPR{if PreQuantMode=scalar}, ReluParamGPR{if ReluMode=scalar}, ->DstTile<Size>, ->RowMaxOut<Size>{if RowMaxEn}, ->GroupMaxOut<Size>{if GroupMaxEn} TMATMUL_MX_BIAS.SHARED_RIGHT <LB0:M=1, LB1:N=1, LB2:K=1, AType, BType?, RMode?, Sat?, FPAttrs, PEMask{must be 1111}>, LocalLeftGroup, SharedRightGroup, BiasTile, RowMaxIn{if RowMaxEn&&RowMaxInit}, QuantParamTile{if PreQuantMode=vector}, ReluParamTile{if ReluMode=vector}, QuantParamGPR{if PreQuantMode=scalar}, ReluParamGPR{if ReluMode=scalar}, ->DstTile<Size>, ->RowMaxOut<Size>{if RowMaxEn}, ->GroupMaxOut<Size>{if GroupMaxEn} TMATMUL_MX_BIAS.SHARED_BOTH <LB0:M=1, LB1:N=1, LB2:K=1, AType, BType?, RMode?, Sat?, FPAttrs, PEMask{must be 1111}>, SharedLeftGroup, SharedRightGroup, BiasTile, RowMaxIn{if RowMaxEn&&RowMaxInit}, QuantParamTile{if PreQuantMode=vector}, ReluParamTile{if ReluMode=vector}, QuantParamGPR{if PreQuantMode=scalar}, ReluParamGPR{if ReluMode=scalar}, ->DstTile<Size>, ->RowMaxOut<Size>{if RowMaxEn}, ->GroupMaxOut<Size>{if GroupMaxEn}

LLVM implementation contract

Generated schema

• Import a compact generated C++ table from the PTO catalog. Do not copy 117 operation definitions into hand-written switches.
• Pin the source catalog digest and architecture identity. Generation must fail on unknown commands, fields, binding kinds, or physical slots.
• Keep the generated table separate from instruction semantics: it maps macro fields to already-supported physical MC instructions.

Assembly

• Intercept a recognized TileOp mnemonic in LinxV5AsmParser before the generic TableGen matcher.
• Parse the whole macro from one source line; reject a newline or continuation before the form is complete.
• Resolve one exact form, apply only schema-owned defaults, then emit header, B.DATR/B.FPATR/B.DIM, B.IOR/B.IOT/B.IOS and a boundary in canonical order.
• Reuse existing physical operand parsers and MC opcodes. Replace the older per-operation pseudo expansion only after parity tests cover the same bytes.
• Reject ambiguous forms, missing physical arguments, illegal carrier kinds, and range modifiers not attached to the mapped physical role.

Disassembly

• Folding cannot be implemented only in LinxV5InstPrinter::printInst, because that API receives one MCInst and cannot safely own subsequent instruction bytes, labels, or annotations.
• Extend LinxV5Disassembler::getInstruction: when decoding an accepted at a BSTART, scan through the exact BSTOP or next-BSTART boundary, validate the complete command sequence, and match it against the generated schema.
• On one exact physical match, return a synthetic TileOp macro MCInst whose reported size covers the complete folded bundle; the printer renders exactly one line.
• On no match, incomplete boundary, illegal sequence, or multiple matches, return the physical BSTART normally. PredicateTile/PredicateCell pairs remain physical unless runtime descriptor state proves a unique carrier.
• Preserve -linxv5-no-aliases as a physical-assembly escape hatch.

Delivery stages

• Generate and validate the compact 117-operation / 141-form C++ schema.
• Add parser infrastructure and representative expansion tests for VEC, SFU, TLSU Local/Shared/CUBE, CUBE Local/Shared, GPR predicate, and range modifiers.
• Close all 141 assembly forms against expected physical bytes.
• Add bundle-aware disassembler folding with explicit BSTOP and next-BSTART boundaries.
• Add fail-closed disassembly cases for ambiguous Tile/Cell carriers, missing boundary, noncanonical command order, unsupported default, and stale mnemonic.
• Run llvm-mc and Clang integrated-assembler coverage on the rebuilt dev-llvm15_56 toolchain.

Acceptance

• Exactly 117 operation identities and 141 forms match the pinned PTO catalog.
• Every accepted macro occupies one source line and round-trips to the same physical bytes.
• Every uniquely foldable physical bundle prints one macro line.
• Ambiguous or noncanonical bundles remain physical assembly.
• Existing physical assembly remains accepted and -linxv5-no-aliases remains available.

[VV0003]

阶段性进展：阶段 1+2 已完成并推送（分支 experiment/latest，commit 7c22e418）。

已交付（对应 issue 的 Delivery stages 1-2 前半）

① Schema 生成与校验

• TileOpSchemaGen/gen_schema.py：从 pinned catalog（b50ed858 tree，digest 181775079d8e）生成紧凑 C++ 表 LinxV5TileOpSchema.inc——117 操作 / 141 form / 1503 field slot / 402 string，生成期对未知命令/字段/绑定类型/slot fail-closed
• LinxV5TileOpSchema.{h,cpp}：查询 API（spelling→form 精确解析、按域枚举 slot）

② 汇编侧：VEC 家族端到端打通

• ParseInstruction 在 TableGen matcher 之前拦截宏拼写；整行单源解析（禁续行），pending-state 存储
• 物理展开从 MatchAndEmitInstruction 执行（MCAsmParser 骨架中唯一安全发射点），按 canonical order 发射 header/B.DATR/B.DIM/B.IOT/B.IOR/BSTOP，复用既有物理 opcode 与编码器
• 属性赋值为值域驱动的位置匹配（可选字段无占位可省略；不可解析 token 按catalog attribute_resolution 规则 closed 拒绝）

实测样例（issue 表格首行 TADD 全形式）：

TADD <32, 16, 32, FP32, Zero, 0b1111>, t#1, t#2, ->t#3<8KB>

展开为 BSTART.TEPL TADD, FP32 + B.DATR ...Zero + 三条 C.B.DIMI + 双源 B.IOT ...last, ->t#3<8KB> + BSTOP，编码字节级正确。scalar 变体（B.IOR 承载标量）、可选维度省略、PEMask、物理汇编共存均已覆盖。

测试

• MC/LinxV5/tileop-macro-vec.s：全形式/最小/scalar/unary + 两个 fail-closed 负例（续行、未知属性）+ 物理形式共存，lit PASS
• MC/LinxV5 套件 35 通过（与基线一致；9 个失败均为预存环境问题如 ld.lld 不在 PATH，非本次引入）

后续（未完成）

• 阶段 2 后半：SFU/TLSU/CUBE 家族的展开器（schema 与拦截基础设施已就绪，按家族补 binding kind 处理）
• 阶段 3：141 form 全量字节 parity 闭合
• 阶段 4-5：LinxV5Disassembler::getInstruction 的 bundle 感知反折叠 + fail-closed 反汇编用例 + clang 集成汇编回归

注：pto-spec llvm#263（catalog 定义）仍为 open PR，本实现锚定其 b50ed858 review 快照；若合入时有改动，生成器重跑即可（表是数据不是语义）。

[VV0003]

阶段 2 完成：全部四大家族（VEC/SFU/TLSU/CUBE）单行宏汇编端到端打通（experiment/latest，commit 3d2f0ce，接前一条评论的 7c22e418）。

本轮新增

SFU（46 操作）：分离记录形式——非终结源记录 + 终结仅目的记录；ValueDataType 别名进 DataType 值域。实测 TROWMAX/TGATHER 全形式正确。

TLSU（28 操作）：

• BSTART.TLSU 直接携带 schema 的 function 码，原子 RMW 全家族（MGATHER/MSCATTER 的 ADD/AND/OR/XOR/INC/DEC/EXCH/MAX/MIN/POPC，码 9..27） 无需 legacy 名字表即可发射
• [BaseGPR, RowStrideGPR] 括号地址 → GM B.IOR，zero（R0）条目按省略槽编码过滤
• 三种记录形态：仅目的（TLOAD/TMOV）、仅源（TSTORE）、仅地址（TPREFETCH）

CUBE（12 操作）：BSTART.CUBE 家族 function 码 + 普通 form 必备的全零 B.FPATR；M/N/K 三维；schema 驱动的条件源槽（RowMaxIn/Quant/Relu）按 optional 省略。实测 TMATMUL <16,32,64,FP32>, t#1, t#2, ->t#3<2KB> 完整 bundle 正确。

schema 增强：FormRecord 增加 header function 码；条件源感知的形状校验（required = schema 非 optional 槽位）。

测试

tileop-macro-families.s（SFU 归约/gather、TLSU load/store/prefetch/RMW、CUBE matmul + 负例）与 tileop-macro-vec.s 均 lit PASS；MC/LinxV5 套件 36 通过（+1 新测试），无回归。

⚠️ 发现的预存分歧（需要单独跟进，不阻塞本工作）

BaseInfo TileOPTMA 枚举与当前 catalog/ASL 的 function 码冲突：枚举把 TMOV_L2S_INSERT/PUBLISH/S2L_BROADCAST/S2L_EXTRACT/SPART 安在 9..14，而当前 ASL 主线这些码是 MGATHER_EXCH/MAX/MIN/ADD/GMOV/INC（已逐一对照 ASL 文件核实）。宏路径直接用 catalog 码不受影响；但 printer 渲染名（如 function 12 打成 TMOV.S2L.EXTRACT）和 LinxV5ISelLowering.cpp:892 起的 Shared TMOV lowering 仍在发旧码——若 ASL 重编号已定稿，Shared TMOV 的编码本身需要协调修复（影响所有 Shared kernel）。建议 ISA/编译器 owner 联合确认后开独立 issue。

剩余（delivery stages 3-5）

• 141 form 全量字节 parity 闭合（四家族代表形式已过，剩余为枚举展开）
• LinxV5Disassembler::getInstruction bundle 感知反折叠 + fail-closed 反汇编用例
• clang 集成汇编（IAs）回归

[VV0003]

阶段 3+4 完成：141 form 全量汇编闭合 + bundle 感知反折叠（experiment/latest，582c00e + dd6aab8，接前两条评论）。

阶段 3（delivery stage 3）：全部 113 个 plain form 汇编闭合

生成器驱动的大宗测试：每个 form 一条代表性宏行（最小必填属性 + 最小必填操作数），覆盖 pinned catalog 全部 141 form。113 个 plain-operand form 全部 0 error 汇编；其余 28 个携带特殊操作数类型（Shared 组、predicate cell/GPR 载体、range modifier）当前 fail-closed。

大宗测试暴露并修复的问题：可选属性延迟绑定（PadValue/CMode/RMode 非匹配 token 转给后续字段，修 34 个 form）、Layout 全家族接受（36 个）、U8/DTYPE_NONE 字面量、CUBE 条件源与多目的记录（形状检查改 required-vs-total 区间；RowMaxOut/GroupMaxOut 各自的 dst-only B.IOT）、TLSU 括号组/独立标量分开计数、TLOAD.CUBE/TSTORE.CUBE 传输选择器（含 legacy TLOAD. 前缀改写与宏拼写的互斥保护）。

阶段 4（delivery stage 4）：反汇编 bundle 折叠

按 issue 合同实现：折叠在 LinxV5Disassembler::getInstruction（不在 printInst）——解码到 tile-op BSTART 时向前扫描到精确 BSTOP/下一 BSTART 边界，校验完整命令序列（header + ≤1 属性命令 + 1..3 C.B.DIMI + ≤8 B.IOT/B_IO + BSTOP），完整 plain-form 形态则 Size 覆盖整个 bundle；非规范/未知/歧义一律回退物理 BSTART。

宏行文本从解码 bundle 重建：schema 匹配拼写、C.B.DIMI imm8（bits[13:6]）、B_IOT_Base 字段布局（SrcTile1[31:26] SrcTile0[25:20] Last[19] TSize[18:15] Func[14:12] DstTile[8:7]）含组合源+目的记录。经地址键侧表（LinxV5TileOpFoldInfo）交给 printer。

-linxv5-no-aliases 物理逃生门：flag 在 disassembler（解码期折叠门）与 printer 间共享，printer 实现 applyTargetSpecificCLOption，llvm-objdump -M linxv5-no-aliases 可用。

Round-trip 验证：TADD <32,16,32,FP32>, t#1, t#2, ->t#3<8KB> → object → 反汇编还原同一宏行（TMATMUL 同）；113 form 的 object 折叠出 33 条完整宏行（含 B_IO 地址记录的 form 部分渲染，完整操作数渲染随 operand-schema walker 后续补全）。

测试

• tileop-macro-fold.s：折叠路径 + -M linxv5-no-aliases 物理路径，lit PASS
• 全套件 lit 37 通过（+3 新测试），无回归

剩余（stage 5 及后续）

• 28 个 special-operand form 的汇编 + 渲染（Shared 组/predicate 载体/range modifier）
• 含 B_IO 地址记录 form 的完整操作数渲染
• fail-closed 反汇编用例补全（歧义 Tile/Cell 载体、缺边界、非规范命令序）
• clang 集成汇编（IAs）回归

[VV0003]

全部交付阶段（1-5）完成。experiment/latest 分支 7 个 commit（7c22e418 → e9a67369），MC/LinxV5 lit 38 通过（+4 新测试），零回归。

交付对照（issue 的 Delivery stages）

阶段	状态	交付物
1. Schema 生成与校验	✅	TileOpSchemaGen/gen_schema.py → LinxV5TileOpSchema.inc（117 op / 141 form / digest 锁定 / 生成期 fail-closed）
2. 解析器基础设施 + 各家族展开	✅	VEC（7c22e418）；SFU/TLSU/CUBE（3d2f0ce）；special 载体（354b554）
3. 全部 form 汇编闭合	✅	141/141：113 plain + 28 special（Shared 组 bare S、predicate tile/cell/GPR、多 form 载体重解析）；生成器驱动大宗测试 0 error
4. bundle 感知反折叠	✅	getInstruction 边界扫描 + 命令序列校验 + schema 匹配（dd6aab8）；round-trip：宏 → ELF → 同一宏行
5. fail-closed 用例 + 回归	✅	缺 BSTOP / 无记录 bundle 保持物理（7368df7）；llvm-mc + clang IAs 回归通过

验收对照（issue 的 Acceptance）

• ✅ 117 操作 / 141 form 与 pinned catalog 匹配（digest 181775079d8e）
• ✅ 每个接受的宏单行、round-trip 同物理字节（TADD/TMATMUL 实测；113 plain form 大宗 ELF 折叠出宏行）
• ✅ 可唯一折叠的物理 bundle 打印一行宏（33 完整宏行/大宗 ELF；B_IO 地址记录的 form 部分渲染）
• ✅ 歧义/非规范 bundle 保持物理（fail-closed 用例：缺边界、无记录）
• ✅ 物理汇编仍接受 + -linxv5-no-aliases 可用（llvm-objdump -M linxv5-no-aliases 实测物理输出）

测试

tileop-macro-vec.s / -families.s / -fold.s / -special.s 四个测试文件，含正负例与逃生门路径；MC/LinxV5 套件 38 通过（基线 35+预存 9 失败为环境项如 ld.lld 不在 PATH，无回归）。clang 集成汇编回归：TileOP 全部核心用例 0 error。

已上报的关联问题

1. BaseInfo TileOPTMA 枚举与 catalog/ASL function 码分歧（9..14 旧 TMOV_L2S 名 vs 现 MGATHER_EXCH/MAX/MIN/ADD/GMOV/INC）——影响 printer 渲染名与 Shared TMOV lowering，需 ISA/编译器 owner 联合裁定（见前面阶段 2 评论）
2. TileOP Support CUDA 10.2 llvm/llvm-project#125（新开）：上游 Minor fix help message git clang-format llvm/llvm-project#124 把 TeplAss.cpp 载体改回 range::assemble（INIT=true），与 Stale comments llvm/llvm-project#115 的 slot 分拆断言矛盾，当前 linx 上该测试 21 处编译失败（与本工作无关，clang IAs 回归时发现）

备注

• pto-spec Fix NameSection::writeBody() to write the number of names that it says it would. llvm/llvm-project#263（catalog 定义）仍为 open PR；实现锚定其 b50ed858 快照，合入后重跑生成器即可
• 分支未推送远程，待 owner 审阅后决定（experiment/latest）

[VV0003]

分支已推送：linxisa/dev-llvm15_56@e9a67369（7 个 commit，7c22e418 → e9a67369，含全部 delivery stages 1-5 + verifyGPR 放宽）。issue #90 实现侧完成，待 review。

[VV0003]

更正：上一条评论所述推送位置有误。dev-llvm15_56 已回退到原顶端 0a141cbd，全部 7 个实验 commit 保存在 linxisa/experiment/latest（e9a67369） 供 review；主分支不受影响。