This project tests the performance of high-radix online addition and multiplication on FPGA. It corresponds to my Master's Thesis for the completion of the MSc Analogue and Digital Integrated Circuit Design program at Imperial College London
This project is academic in nature, and was developed as a means to answer an experimental question. As such it has only been tested using a single software toolchain and hardware stack. It is likely some or all of this code will not function as intended given a different compute environment or settings. The purpose of the repository is to document my implementation, and serve as inspiration for future related projects.
Development was done in Linux
Quartus Prime Lite Edition (20.1.1)
That targeted FPGA was the Intel Cyclone V SoC Development Kit running the Linux image found here (Login: root, Password: root).
- rR_add and rRp_mult contain the tested online arithmetic IP, as well as simulation test benches for verification.
- Adder_Test_Param and mult_test_param are the Quartus projects used to generate the FPGA test benches for data collection
- FPGAFiles/josh contains the python test scripts run on the FPGA, and the collected test data. This mirros the files stored on the Cyclone V SoC.
- run_tests.sh will collect degreadation data on all generated adders and multipliers. It takes about 24 hours to complete
- PLL_Test is a simple Quartus Project to test dynamic reconfiguration of the CycloneV PLL
- mult_csims contains C++ simulations of the online multiplication algorithm
- Reports contains various submitted materials related to this project
Please contact Joshua Laney for questions or suggestions
GNU General Public License v3.0, see license file for terms.