Some of my projects made for the Xilinx Artix 7 FPGA card in ISE 14.7 and Vivado 2020.2 during university. These Projects include: 7_seg controller, 4 bit ALU, ROM access and data processing using a counter and clock divider, Ring counter, Jhonson Counter both using Registers., Up and Down counter.
UPDATE Part2: VGA Manipulation, Screen saver with VGA, UAG, Transmitter/Reciever, Microblaze processor, PWM, ADC, State Machine
Cards I used: Xilinx Artix 7, Xilinx/Logsys Spartan3E Software: ISE 14.7, Vivado 2020.2 Language: Verilog