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Decode #85

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728bd09
chore(decode): testbench link
MatiasYezzi Mar 26, 2026
8a14d40
Create example.sv
Meowcaroni Apr 4, 2026
378851d
fix(decode): AMO_OR funct5
MatiasYezzi Apr 16, 2026
3222d2e
chore(decode): decode tb link
MatiasYezzi Apr 16, 2026
3cc158c
Merge branch 'main' of https://github.com/IEEE-UCF/Gaming-CPU-Project…
MatiasYezzi Apr 16, 2026
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6 changes: 5 additions & 1 deletion rtl/cpu/core/decode.sv
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Original file line number Diff line number Diff line change
@@ -1,6 +1,7 @@
import rv32_pkg::*;

// Decode Module
// EDAplayground testbench: https://edaplayground.com/x/u26L
module decode (

// Clock
Expand Down Expand Up @@ -355,7 +356,7 @@ module decode (
5'b00000: begin amo_op_n = AMO_ADD; end // AMOADD.W
5'b00100: begin amo_op_n = AMO_XOR; end // AMOXOR.W
5'b01100: begin amo_op_n = AMO_AND; end // AMOAND.W
5'b01010: begin amo_op_n = AMO_OR; end // AMOOR.W
5'b01000: begin amo_op_n = AMO_OR; end // AMOOR.W
5'b10000: begin amo_op_n = AMO_MIN; end // AMOMIN.W
5'b10100: begin amo_op_n = AMO_MAX; end // AMOMAX.W
5'b11000: begin amo_op_n = AMO_MINU; end // AMOMINU.W
Expand Down Expand Up @@ -395,7 +396,10 @@ module decode (

endmodule

//------------------------------------------------------------------------------------------------------------------------

// Register File
// EDAplayground testbench: https://edaplayground.com/x/dqch
module register_file (

// Clock
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1 change: 1 addition & 0 deletions sim/sv/example.sv
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Original file line number Diff line number Diff line change
@@ -0,0 +1 @@