Subcircuit files for ICs

library/SubcircuitLibrary/2x1_mux/2x1_mux.cir

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+.title KiCad schematic
+U101 Net-_U101-Pad1_ Net-_U101-Pad2_ Net-_U101-Pad3_ Net-_U101-Pad4_ Net-_U101-Pad5_ Net-_U101-Pad6_ Net-_U101-Pad7_ unconnected-_U101-Pad8_ Net-_U101-Pad9_ Net-_U101-Pad10_ Net-_U101-Pad11_ Net-_U101-Pad12_ Net-_U101-Pad13_ Net-_U101-Pad14_ Net-_U101-Pad15_ unconnected-_U101-Pad16_ PORT
+U102 Net-_U101-Pad15_ Net-_U102-Pad2_ d_inverter
+U103 Net-_U101-Pad1_ Net-_U103-Pad2_ d_inverter
+U104 Net-_U102-Pad2_ Net-_U104-Pad2_ d_buffer
+U105 Net-_U103-Pad2_ Net-_U105-Pad2_ d_inverter
+U106 Net-_U106-Pad1_ Net-_U106-Pad2_ Net-_U101-Pad12_ d_or
+X108 Net-_U101-Pad13_ Net-_U105-Pad2_ Net-_U104-Pad2_ Net-_U106-Pad2_ 3_and
+X107 Net-_U101-Pad14_ Net-_U103-Pad2_ Net-_U104-Pad2_ Net-_U106-Pad1_ 3_and
+X106 Net-_U101-Pad10_ Net-_U105-Pad2_ Net-_U104-Pad2_ Net-_U107-Pad2_ 3_and
+X104 Net-_U101-Pad6_ Net-_U105-Pad2_ Net-_U104-Pad2_ Net-_U108-Pad2_ 3_and
+X105 Net-_U101-Pad11_ Net-_U103-Pad2_ Net-_U104-Pad2_ Net-_U107-Pad1_ 3_and
+U107 Net-_U107-Pad1_ Net-_U107-Pad2_ Net-_U101-Pad9_ d_or
+U108 Net-_U108-Pad1_ Net-_U108-Pad2_ Net-_U101-Pad7_ d_or
+U109 Net-_U109-Pad1_ Net-_U109-Pad2_ Net-_U101-Pad4_ d_or
+X101 Net-_U101-Pad2_ Net-_U103-Pad2_ Net-_U104-Pad2_ Net-_U109-Pad1_ 3_and
+X102 Net-_U101-Pad3_ Net-_U105-Pad2_ Net-_U104-Pad2_ Net-_U109-Pad2_ 3_and
+X103 Net-_U101-Pad5_ Net-_U103-Pad2_ Net-_U104-Pad2_ Net-_U108-Pad1_ 3_and
+.end

library/SubcircuitLibrary/2x1_mux/2x1_mux.cir.out

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+.title kicad schematic
+
+.include 3_and.sub
+* u101 net-_u101-pad1_ net-_u101-pad2_ net-_u101-pad3_ net-_u101-pad4_ net-_u101-pad5_ net-_u101-pad6_ net-_u101-pad7_ unconnected-_u101-pad8_ net-_u101-pad9_ net-_u101-pad10_ net-_u101-pad11_ net-_u101-pad12_ net-_u101-pad13_ net-_u101-pad14_ net-_u101-pad15_ unconnected-_u101-pad16_ port
+* u102 net-_u101-pad15_ net-_u102-pad2_ d_inverter
+* u103 net-_u101-pad1_ net-_u103-pad2_ d_inverter
+* u104 net-_u102-pad2_ net-_u104-pad2_ d_buffer
+* u105 net-_u103-pad2_ net-_u105-pad2_ d_inverter
+* u106 net-_u106-pad1_ net-_u106-pad2_ net-_u101-pad12_ d_or
+x108 net-_u101-pad13_ net-_u105-pad2_ net-_u104-pad2_ net-_u106-pad2_ 3_and
+x107 net-_u101-pad14_ net-_u103-pad2_ net-_u104-pad2_ net-_u106-pad1_ 3_and
+x106 net-_u101-pad10_ net-_u105-pad2_ net-_u104-pad2_ net-_u107-pad2_ 3_and
+x104 net-_u101-pad6_ net-_u105-pad2_ net-_u104-pad2_ net-_u108-pad2_ 3_and
+x105 net-_u101-pad11_ net-_u103-pad2_ net-_u104-pad2_ net-_u107-pad1_ 3_and
+* u107 net-_u107-pad1_ net-_u107-pad2_ net-_u101-pad9_ d_or
+* u108 net-_u108-pad1_ net-_u108-pad2_ net-_u101-pad7_ d_or
+* u109 net-_u109-pad1_ net-_u109-pad2_ net-_u101-pad4_ d_or
+x101 net-_u101-pad2_ net-_u103-pad2_ net-_u104-pad2_ net-_u109-pad1_ 3_and
+x102 net-_u101-pad3_ net-_u105-pad2_ net-_u104-pad2_ net-_u109-pad2_ 3_and
+x103 net-_u101-pad5_ net-_u103-pad2_ net-_u104-pad2_ net-_u108-pad1_ 3_and
+a1 net-_u101-pad15_ net-_u102-pad2_ u102
+a2 net-_u101-pad1_ net-_u103-pad2_ u103
+a3 net-_u102-pad2_ net-_u104-pad2_ u104
+a4 net-_u103-pad2_ net-_u105-pad2_ u105
+a5 [net-_u106-pad1_ net-_u106-pad2_ ] net-_u101-pad12_ u106
+a6 [net-_u107-pad1_ net-_u107-pad2_ ] net-_u101-pad9_ u107
+a7 [net-_u108-pad1_ net-_u108-pad2_ ] net-_u101-pad7_ u108
+a8 [net-_u109-pad1_ net-_u109-pad2_ ] net-_u101-pad4_ u109
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u102 d_inverter(rise_delay=1n fall_delay=0.7n input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u103 d_inverter(rise_delay=1n fall_delay=0.7n input_load=1.0e-12 ) 
+* Schematic Name:                             d_buffer, Ngspice Name: d_buffer
+.model u104 d_buffer(rise_delay=2n fall_delay=2n input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, Ngspice Name: d_inverter
+.model u105 d_inverter(rise_delay=1n fall_delay=0.7n input_load=1.0e-12 ) 
+* Schematic Name:                             d_or, Ngspice Name: d_or
+.model u106 d_or(rise_delay=1.5n fall_delay=1.2n input_load=1.0e-12 ) 
+* Schematic Name:                             d_or, Ngspice Name: d_or
+.model u107 d_or(rise_delay=1.5n fall_delay=1.2n input_load=1.0e-12 ) 
+* Schematic Name:                             d_or, Ngspice Name: d_or
+.model u108 d_or(rise_delay=1.5n fall_delay=1.2n input_load=1.0e-12 ) 
+* Schematic Name:                             d_or, Ngspice Name: d_or
+.model u109 d_or(rise_delay=1.5n fall_delay=1.2n input_load=1.0e-12 ) 
+.tran 0.1e-09 100e-09 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end

library/SubcircuitLibrary/2x1_mux/2x1_mux.kicad_prl

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+      "tracks": 1.0,
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+    "ratsnest_display_mode": 0,
+    "selection_filter": {
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+  "meta": {
+    "filename": "2x1_mux.kicad_prl",
+    "version": 3
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+  "project": {
+    "files": []
+  }
+}