Ryota

README.md

@@ -1 +1 @@
-Lab_4.md
+Easy A*

rtl/control_unit.sv

@@ -0,0 +1,46 @@
+module control_unit #(
+    WIDTH = 32
+) (
+    input logic  [WIDTH-1:0]  ins,
+    input logic               EQ,        //?
+    output logic              pc_src,    // pc branches or not
+    output logic [2:0]        alu_ctrl,  // ALU operation: add, sub, OR
+    output logic              alu_src,   // whether 2nd ALU input is a register data or immediate
+    output logic [1:0]        imm_src,   // type of ins: R, I, S, B
+    output logic              reg_write  // register write enable
+);
+
+logic [6:0]    opcode;
+logic [2:0]    funct3;
+
+assign opcode = ins[6:0];
+assign funct3 = ins[14:12];
+
+//--------     DECODER      --------//
+// Only implementing two basic instructions addi and bne so logic can be very specific and not generalised.
+always_comb
+case (opcode)
+
+    7'd19:  case (funct3) 
+                0: begin    // addi ins
+                    reg_write <= 1;  // storing the resut in register
+                    imm_src <= 0;  
+                    alu_src <= 1  // ALU uses immediate and not rs2
+                    alu_ctrl <= 0 // addition of rs1 + imm
+                    pc_src <= 0;
+                end
+    endcase
+
+    7'd99:  case (funct3)
+                1: begin    // bne ins
+                    reg_write <= 0;
+                    imm_src <= 2;  // type B ins
+                    alu_src <= 0;  // the immediate will be fed into the PC and not used in the ALU
+                    alu_ctrl <= 1; // we are doing a sub to find the difference between instruction addresses
+                    pc_src <= 1;   // pc increments to branch address
+                end
+    endcase
+
+endcase
+
+endmodule 

rtl/instr.mem

@@ -0,0 +1,7 @@
+0f f0 03 13
+00 00 05 13
+00 00 05 93
+00 05 85 13
+00 15 85 93
+fe 65 9c e3
+fe 03 18 e3

rtl/instr_mem.sv

@@ -0,0 +1,20 @@
+module instr_mem #(
+    parameter  ADDRESS_WIDTH = 16,
+               DATA_WIDTH = 32
+)(
+    input logic  [ADDRESS_WIDTH-1:0] addr,
+    output logic [DATA_WIDTH-1:0]    dout
+);
+
+logic [DATA_WIDTH-1:0]  mem_array [2**ADDRESS_WIDTH-1:0];
+
+initial begin
+    $display("Loading Instruction Memory.");
+    $readmemh("instr.mem", mem_array);
+end;
+
+always_ff @(posedge addr)
+
+    dout <= mem_array [addr];
+
+endmodule

rtl/pc/pc_branch.sv

@@ -0,0 +1,11 @@
+module pc_branch #(
+    parameter WIDTH = 32
+) (
+    input  logic [WIDTH-1:0] pc,
+    input  logic [WIDTH-1:0] imm,
+    output logic [WIDTH-1:0] branch_pc
+);
+
+assign branch_pc = pc + imm;
+
+endmodule

rtl/pc/pc_inc.sv

@@ -0,0 +1,10 @@
+module pc_inc #(
+    parameter WIDTH = 32
+) (
+    input  logic [WIDTH-1:0] pc,
+    output logic [WIDTH-1:0] inc_pc
+);
+
+assign inc_pc = pc + 32'b100;
+
+endmodule

rtl/pc/pc_reg.sv

@@ -0,0 +1,17 @@
+module pc_reg #(
+    parameter WIDTH = 32
+) (
+    input  logic             clk,
+    input  logic             rst,
+    input  logic [WIDTH-1:0] pc_in,
+    output logic [WIDTH-1:0] pc_out
+);
+
+always_ff @(posedge clk or posedge rst) begin
+    if (rst)
+        pc_out <= 'b0;
+    else
+        pc_out <= pc_in;
+end
+
+endmodule

rtl/pc/pc_unit.sv

@@ -0,0 +1,46 @@
+module pc_unit #(
+    parameter WIDTH = 32
+) (
+    input  logic             clk,
+    input  logic             rst,
+    input  logic             pc_src,
+    input  logic [WIDTH-1:0] pc_in,
+    input  logic [WIDTH-1:0] immop,
+    output logic [WIDTH-1:0] pc_out
+);
+
+
+logic [WIDTH-1:0] inc_pc;
+logic [WIDTH-1:0] branch_pc;
+logic [WIDTH-1:0] next_pc;
+
+// Increment PC (pc + 4)
+pc_inc #(.WIDTH(WIDTH)) u_inc (
+    .pc(pc_in),
+    .inc_pc(inc_pc)
+);
+
+// Branch PC (pc + imm)
+pc_branch #(.WIDTH(WIDTH)) u_branch (
+    .pc(pc_in),
+    .imm(immop),
+    .branch_pc(branch_pc)
+);
+
+// Next PC multiplexer 
+mux_2 #(.DATA_WIDTH(WIDTH)) u_mux_next_pc (
+    .in0(inc_pc),
+    .in1(branch_pc),
+    .sel(pc_src),
+    .out(next_pc)
+);
+
+// PC register
+pc_reg #(.WIDTH(WIDTH)) u_pc_reg (
+    .clk(clk),
+    .rst(rst),
+    .pc_in(next_pc),
+    .pc_out(pc_out)
+);
+
+endmodule

rtl/reg_file/alu.sv

@@ -0,0 +1,28 @@
+module alu #(
+    parameter DATA_WIDTH 8
+) (
+    input logic [DATA_WIDTH-1:0] aluop1,
+    input logic [DATA_WIDTH-1:0] aluop2,
+    input logic [2:0] aluctrl,
+    output logic [DATA_WIDTH-1:0] aluout,
+    output logic eq
+)
+
+always_comb begin
+    case (aluctrl)
+        0: begin
+            aluout <= aluop1 + aluop2;
+            eq <= 1b'0;
+        end
+        1: begin
+            aluout <= aluop1 - aluop2;
+            eq <= aluout == 1b'0;
+        end
+        default: begin
+            aluout <= 1b'0;
+            eq <= 1b'0;
+        end
+    endcase
+end
+
+endmodule

repo/rtl/mux.sv → rtl/reg_file/mux_2.sv

@@ -1,6 +1,6 @@
-module mux #(
-    DATA_WIDTH = 32
-) (
+module mux_2 #(
+    DATA_WIDTH = 8
+)(
     input   logic [DATA_WIDTH-1:0]  in0,
     input   logic [DATA_WIDTH-1:0]  in1,
     input   logic                   sel,