I'm a systems engineer focused on LLM inference and GPU kernel optimization. I enjoy tracing performance from model graphs down to memory access patterns, then validating improvements on real hardware.
- 🔧 Working on inference performance, CUDA/HIP kernels, quantization, and memory-bound operators
- 🖥️ Daily hardware: AMD Radeon 8060S · gfx1151 (RDNA 3.5) · ROCm 7.1
- 🌱 Exploring vLLM PD disaggregation, speculative decoding, and kernel autotuning
- 📐 Approach: profile → isolate → optimize → verify correctness → benchmark
Added a shared-memory tiled-transpose path to the HIP backend for a non-contiguous F32 workload observed during Qwen3.6-35B-A3B prefill.
- +4% to +12% measured prefill throughput
- Bit-identical output for the copy/reorder operation
- No meaningful decode regression
- 32×32 shared-memory tiling with bank-conflict padding
Interested in practical LLM systems performance, especially optimizations backed by reproducible measurements.