A staff-level engineer across hardware (RTL and FPGA, DSP, signal integrity) and agentic AI. More than 25 years in hardware, and I write the software too.
Portfolio home → · How I check the numbers · Hardware, DSP and signal integrity
Each site is computed and animated by a tested model, and each is checked against something independent of it.
| Track | Sites |
|---|---|
| Foundations: one small model, end to end | Decoder · Training |
| Hardware: the machines underneath, chip to rack | Kernels · Systolic · Accelerators · Racks |
| Inference: serving models at scale | Serving · Architectures · Numerics · Trade-offs |
| Agents: building on models | Harnesses · Protocols · Context · Orchestration · Evals · Security |
| What | Checked against | |
|---|---|---|
| Systolic Arrays Explained | Inside a matrix engine, cycle by cycle | A SystemVerilog array in Verilator: 613 values, 0 mismatches |
| HW Design-Space Agent | A LangGraph agent that explores hardware trade-offs down a fidelity ladder to synthesis | Every number from a recorded run of the agent |
| Signal Integrity | 17 decks, 188 slides, from transmission lines to channel operating margin | 20 cross-checks against published results, largest difference 2.44 % |
| Agent Orchestration Explained | Graphs, multi-agent patterns and durability | Real LangGraph 1.2.14: 39 sessions, checkpoint history equal after every one of 71 operations |
| Transformer Decoder Explained | How one forward pass works, live in the browser | PyTorch, operation by operation, to within 1e-5 |
| LLMs index | 41 sub-hubs listing 275 decks | The deck library behind the sites |
Built with Claude Code as an agentic engineering workflow: I specify the work, set the verification rules and check the numbers; commits made this way carry a Co-Authored-By line. More on the portfolio home.