RTL-to-GDS-II-90nm-Innovus

Full Physical Design flow on a synchronous memory block — Cadence Innovus 21.15, 90nm process. Floorplan to GDSII with timing closure and physical verification.

RTL to GDSII — Synchronous Memory Block | 90nm | Cadence Innovus 21.15

Full Physical Design flow implemented on a synchronous memory block using Cadence Innovus 21.15 on a 90nm process node — from synthesized netlist to fabrication-ready GDSII.

Flow Summary

Stage	Result
Floorplanning	Core area defined, I/O placed, VDD/VSS power ring + stripes
Placement	GigaPlace timing-driven
Clock Tree Synthesis	CCOpt 2-level buffer tree
Post-CTS Optimization	Two-pass optDesign
Routing	NanoRoute
Physical Verification	verify_drc: 0
GDSII Stream-out	final.gds exported — fabrication ready

Final Timing Results (Worst-Case Corner: SS, 0.9V, 125°C)

Metric	Value
WNS	0.927 ns
TNS	0.000 ns
Violating Paths	0
Hold Violations	0

Screenshots

Stage	File
Floorplan	floorplan.png
Placement	placement.png
Clock Tree	cts_debugger.png
Routed Layout	routed_layout.png
Skew Report	skew_report.png
Timing Summary	timing_summary.png
Verification	verification.png
GDSII	final_gds.png

Tools Used

• Cadence Innovus 21.15
• 90nm Process Node
• MMMC Analysis (func_ss / func_ff)
• CCOpt (Clock Tree Synthesis)
• NanoRoute (Routing)
• GigaPlace (Placement)

Key Learnings

Timing is not a single number — it shifts at every stage of the flow. Pre-CTS uses virtual wire delay models. Post-route uses actual extracted RC parasitics. Understanding why WNS changes between stages is what separates someone who ran the tool from someone who learned Physical Design.