feat(simd_soa): iter_i32x16 / iter_i64x8 typed lane iterators on MultiLaneColumn

[AdaWorldAPI]

Adds the signed-integer lane views the gridlake batch SoA needs, unblocking the lance-graph lane-J wiring flagged in that probe's COMMENTARY.

Why

MultiLaneColumn (the gridlake carrier — see examples/onebrc_cascade_probe.rs) exposed only f32x16 / f64x8 / u64x8 / u8x64 lane views. lance-graph's gridlake batch SoA carries i32 min/max and i64 sum columns; #227's onebrc probe only got away without these because it used f32 min/max columns. Without signed integer lanes, a consumer batch SoA can't be viewed through the carrier directly.

Change

• i32x16_from_chunk / i64x8_from_chunk — little-endian decoders mirroring the existing f32x16_from_chunk / u64x8_from_chunk (scalar from_le_bytes loop, lowered to a single register-width load on LE targets; no pointer-cast of the u8-aligned Arc<[u8]>).
• iter_i32x16 / iter_i64x8 methods + len_i32x16 / len_i64x8, routed through crate::simd::{I32x16, I64x8} per the W1a layering rule (never dipping into simd_avx512/simd_neon/scalar directly).
• Parity tests: iter_i32x16_le_round_trip (includes negatives — proves sign-extension survives the LE decode) + iter_i64x8_le_round_trip; extended the empty-count, 3-lane-count, and len asserts.

These are layout-only zero-copy reinterpretations of the backing store (the same category as the existing typed iterators), not new compute kernels — no per-arch AVX/NEON/scalar backend needed beyond the lane types crate::simd already provides.

Verification

• simd_soa module: 13/13 tests pass under the v3 default; library builds clean under --config .cargo/config-native.toml (real AVX-512 backend on an avx512f host) — so the iterators light up the actual 512-bit zmm path, not just the AVX2-halves fallback.
• clippy -D warnings clean; fmt clean.

🤖 Generated with Claude Code

https://claude.ai/code/session_01MLBnPuScZy6w9di2QEjsXM

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Reviewing files that changed from the base of the PR and between de72d15 and ac59b1d.

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• src/simd_soa.rs

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