feat(shader-driver): unbreak with-engine + F32-17D bit-exact qualia tenant (S-series 1+2)

[AdaWorldAPI]

Summary

S-series Steps 1+2: unbreak --features with-engine, then restore bit-exact BusDto round-trip via an F32-17D qualia tenant — the single exactness ground-truth the rest of the SoA migration measures against.

The bug (latent, unmasked)

engine_bridge::dispatch_busdto stored the BusDto headline codebook_index in q[9] and energies in q[0..9], then quantized through QualiaI4_16D::from_f32_17d, which clamp(-1,1) + i4-rounds. So:

• codebook_index 42 → 1, 1234 → 1 (any value ≥ 1 destroyed)
• energy 0.1 → 0.143 (f32 to_bits mismatch)

The "round-trips losslessly through f32" doc was stale — true when qualia was an f32 column, false since D-CSV-5b made it i4. The 3 round-trip tests had been dead-and-red (uncompiled while with-engine was broken on an unimported QUALIA_DIMS). Commit 1 unmasks them; commit 2 fixes them.

Commits

1 — fix: import QUALIA_DIMS — engine_bridge.rs:259 used QUALIA_DIMS but imported only QualiaI4_16D, so --features with-engine failed to compile (the whole dispatch_busdto/unbind_busdto lab surface was dormant). Pure compile fix + two stale =18 comments (the contract is 17; this module's local QUALIA_DIMS is the old padded 18).

2 — feat: F32-17D bit-exact qualia tenant (operator-directed; 3-agent panel LAND):

• BindSpace gains qualia_f32: Box<[QualiaVector]> ([f32;17]/row), #[cfg(with-engine)], singleton only (~278 KB on 4096 rows). MailboxSoA hot path stays i4-only → no +68 B/row × 64k envelope blowup. NOT a D-CSV-5b reversal — it's the second tenant (i4 hot + f32 lab), separately-named (qualia_f32_row/set_qualia_f32) per the iron-rule AP1 guard; production layout byte-unchanged.
• dispatch_busdto writes the f32 tenant alongside the i4 column (i4 stays the hot-path carrier — the ±0.15 i4-tolerance tests are untouched, C7); unbind_busdto reads the f32 tenant (bit-exact). codebook_index rides q[9]-f32 (f32 exact to 2²⁴ ⊇ u16; I-VSA-IDENTITIES register-as-store, no superposition).
• QUALIA_DIMS import gated to with-engine (no default-build unused-import).

Why F32 (not bf16/f16)

Operator's call: one bit-exact anchor for the whole migration. bf16 is integer-exact only to 256, f16 to 2048, and neither is f32-bit-exact — so neither could satisfy the bit-exact tests as the ground-truth. Alternatives deferred.

Tests

• The 3 round-trip tests pass un-ignored and UNMODIFIED (bit-exact assertions are the spec — not weakened to a tolerance).
• Added C8 corner corpus: codebook_index ∈ {0,255,256,1234,4095,65535} round-trips bit-exact (pins the 255/256 nars_f & 0xFF alias boundary + u16 max).
• --features with-engine (singleton): 6/6
• --features with-engine,mailbox-thoughtspace (mailbox arm): 5/5 — headline+energy bit-exact via the f32 tenant; non-headline top_k=0 loss preserved by design (C5/D-DIST-5).
• default lib: 20/20 (cfg field absent — zero hot-path change). fmt clean.

Scope notes

CI's clippy gate (style.yml) scopes to lance-graph-contract/lance-graph/deepnsm — not cognitive-shader-driver or lance-graph-ontology. lance-graph-ontology's 12 pre-existing -D warnings clippy errors (oxrdf/doc-list/to_vec, from #530/#533) are cap-lints-allowed as a dep, not a gate, out of scope. My code introduces no clippy warning.

Next (S3): flip ShaderDriver off the Arc<BindSpace> singleton onto the mailbox set — the F32 tenant is now the bit-exact anchor to diff each step against.

🤖 Generated with Claude Code

https://claude.ai/code/session_01CcpLeEC3XK8Eye53GKBVvi

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Configuration used: Organization UI

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Run ID: 4be92f5a-a66a-4b9a-b9ae-38f26a4ecec1

📥 Commits

Reviewing files that changed from the base of the PR and between e55a8cf and 63d8e15.

📒 Files selected for processing (5)

• .claude/board/AGENT_LOG.md
• .claude/board/EPIPHANIES.md
• crates/cognitive-shader-driver/src/bindspace.rs
• crates/cognitive-shader-driver/src/engine_bridge.rs
• crates/cognitive-shader-driver/tests/busdto_bridge_test.rs

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