gate-sim — Event-Driven Gate-Level Logic Simulator

A small C++17 gate-level logic simulator built around an event-driven simulation core, the same fundamental technique used in RTL/gate-level power and timing tools: instead of re-evaluating the whole circuit every timestep, work only happens when a net actually toggles, and that toggle is what fans out to the gates that read it.

Why this project

Built to demonstrate the concrete building blocks behind gate-level power estimation:

• Event-driven scheduling — a priority_queue of (time, net, value) events drives simulation, not a fixed timestep loop.
• Switching activity tracking — every net records its toggle count, which is the direct input to dynamic power estimation (P ∝ activity × capacitance × V² × f).
• Sequential + combinational logic — AND/OR/NOT/XOR/NAND/NOR gates plus a rising-edge D flip-flop, with signal propagation delay per gate.
• Waveform output — a VCD-format trace so results can be inspected in any standard waveform viewer (e.g. GTKWave).
• STL-driven design — unordered_map, priority_queue, vector used throughout for the netlist graph and event scheduling.

Build

g++ -std=c++17 -O2 -o gate-sim src/main.cpp src/Gate.cpp src/Simulator.cpp

Or with CMake:

mkdir build && cd build
cmake .. -DCMAKE_BUILD_TYPE=Release
make

Run

./gate-sim examples/example.net waveform.vcd

This prints a per-net toggle report and a relative dynamic-power estimate to stdout, and writes waveform.vcd.

Netlist format

INPUT <net>
GATE <name> <AND|OR|NOT|XOR|NAND|NOR> <in1> [in2 ...]
DFF <name> <D> <CLK>
OUTPUT <net>
AT <time> SET <net> <0|1>      # stimulus

See examples/example.net for a worked combinational + sequential example.

Possible extensions

• Parse real gate-level Verilog netlists (subset of structural Verilog) instead of the custom format.
• Per-gate capacitance values (currently uniform) for a more realistic power model.
• Multi-input clock-gating detection.
• Parallelize event processing across independent clock domains.

License

MIT