Whac-A-Mole FPGA Game

A real-time Whac-A-Mole game implemented in SystemVerilog and deployed on an FPGA. The system is driven by finite state machines (FSMs), uses pseudo-random mole generation, and implements deterministic timing for gameplay, scoring, and difficulty scaling.

The design is fully simulatable on Linux using open-source tools and was validated both in simulation and on physical FPGA hardware (DE2-115).

Features

• FSM-based game control and scoring logic
• Pseudo-random mole generation
• Adjustable difficulty levels (timing-based)
• Real-time score display using 7-segment outputs
• Debounced and synchronised mechanical inputs
• Module-level and system-level verification testbenches
• Linux-native simulation using open-source tooling

Hardware Target

• Board: DE2-115 FPGA (Cyclone IV-E)
• Inputs: Toggle switches and push buttons
• Outputs: LEDs (mole indicators), 7-segment displays (score)

The design was synthesised, placed, routed, and validated on real hardware. A short demonstration video is included showing gameplay difficulty selection, and reset behaviour.

Architecture Overview

The project is structured to separate board-specific I/O from reusable game logic. All gameplay functionality is encapsulated in a board-agnostic game module, while top_level acts solely as an FPGA I/O adapter.

Repository Structure

whac-a-mole/
├── rtl/      # Core synthesizable logic
├── tb/       # Module and system-level testbenches
├── sim/      # Simulation scripts and Makefile
└── media/    # Demo GIFs, diagrams, waveform captures 

Core Modules

System block diagram

The system is structured as a set of composable and reusable hardware modules:

• FSM: Controls overall game flow, scoring, and difficulty selection
• Mole: Manages LED activation and hit detection
• Timer: Provides deterministic timing for state transitions
• RNG: Generates pseudo-random mole positions
• Display: Converts binary score values to 7-segment display output
• Debounce and synchroniser modules for mechanical inputs

Game FSM

All gameplay logic is encapsulated in a board-agnostic game module, with top_level acting solely as an FPGA IO adapter.

Simulation & Verification

The design is verified using both module-level and system-level testbenches.

Requirements

• Icarus Verilog
• GTKWave (optional, for waveform viewing)
• Make

Install dependencies on Ubuntu/Debian: sudo apt install -y iverilog verilator gtkwave make

Run simulation

cd sim
make sim
make wave # To view waveforms

Verification includes

• Individual testbenches for each module
• A full system integration test exercising representative gameplay
• Deterministic simulation behaviour suitable for regression workflows

Example waveform: LED register (mole activation)

Project Context

This project was originally developed as part of a university course and later refactored to improve portability, reproducibility, and code clarity. The refactor preserved original functionality while adopting a more industry-aligned workflow, including Linux-based simulation and explicit SystemVerilog typing for improved tool portability.