Background
The top-level system86 module provides signals for accessing all ram and rom chips and if they were external components.
When simulating via a test harness I am able to provide rudimentary placeholder ram and rom implementation that simply defines a large memory region, per instance, at the RTL level. A placeholder module also allow the memory region to be initialised from a file (e.g. ROM image or MAME memory snapshot).
Requirements
I would like to be able to provide a RAM/ROM module that can be wired into the top-level system86 module.
This module will provide a mechanism for mapping a RAM/ROM instance to region in the host hardware's SDRAM. For my purposes this would ideally occur using the AXI4 bus.
There are a least two options
- Provide a single module with multiple signals, covering all the System86 memory chips
- Provide a reusable module that can be instantiated for each memory chip found in the System86.
With regards to 2. it may be possible to make use of the various AXI4 interconnects to allow each module concurrent access to the SDRAM.
For now this simply needs to be functional and only for the limited chips that are required for the System86 progress made so far (program ROMs and tile memory). There is little concern at this point as to the feasibility of this working when managing the throughput required for a fully functional System86 implementation running at fully speed!
Background
The top-level system86 module provides signals for accessing all ram and rom chips and if they were external components.
When simulating via a test harness I am able to provide rudimentary placeholder ram and rom implementation that simply defines a large memory region, per instance, at the RTL level. A placeholder module also allow the memory region to be initialised from a file (e.g. ROM image or MAME memory snapshot).
Requirements
I would like to be able to provide a RAM/ROM module that can be wired into the top-level system86 module.
This module will provide a mechanism for mapping a RAM/ROM instance to region in the host hardware's SDRAM. For my purposes this would ideally occur using the AXI4 bus.
There are a least two options
With regards to 2. it may be possible to make use of the various AXI4 interconnects to allow each module concurrent access to the SDRAM.
For now this simply needs to be functional and only for the limited chips that are required for the System86 progress made so far (program ROMs and tile memory). There is little concern at this point as to the feasibility of this working when managing the throughput required for a fully functional System86 implementation running at fully speed!