From 2db3ba47b8b738d9211ea08d23a4b968c68d809d Mon Sep 17 00:00:00 2001 From: Melvin John Date: Thu, 26 Feb 2026 18:50:18 +0100 Subject: [PATCH 01/18] Multiple ports added --- CMake/add_test.cmake | 7 +- CMake/run_legacy_test.cmake | 2 +- CMake/run_test.cmake | 2 +- build_model/CMakeLists.txt | 10 +- build_model/cv32e40x/verilator_main.cpp | 96 +++++--- build_model/cv32e40x/vproc_top.sv | 300 ++++++++++++++---------- build_model/vector_config.cmake | 2 +- build_tests/CMakeLists.txt | 6 +- 8 files changed, 257 insertions(+), 168 deletions(-) diff --git a/CMake/add_test.cmake b/CMake/add_test.cmake index 8fe8420..f4bcc82 100644 --- a/CMake/add_test.cmake +++ b/CMake/add_test.cmake @@ -30,7 +30,7 @@ macro(add_unit_test TEST_NAME) COMMAND srec_cat ${TEST_NAME}.bin -binary -offset 0x0000 -byte-swap 4 -o ${TEST_NAME}.vmem -vmem COMMAND rm -f prog_${TEST_NAME}.txt COMMAND echo -n "${BUILD_DIR}/vector-tests/${TEST_NAME}.vmem" > prog_${TEST_NAME}.txt - COMMAND ${CMAKE_OBJDUMP} -D ${TEST_NAME}.elf > ${TEST_NAME}_dump.txt + #COMMAND ${CMAKE_OBJDUMP} -D ${TEST_NAME}.elf > ${TEST_NAME}_dump.txt ) execute_process(COMMAND python3 ${SCRIPTS_DIR}/count_test_cases.py ${TEST_SOURCES}/riscv-vector-tests/out/v${VREG_W}x32machine/tests/stage2/${TEST_NAME}.S @@ -45,7 +45,7 @@ macro(add_unit_test TEST_NAME) #Add Test add_test(NAME ${TEST_NAME} - COMMAND ${MODEL_DIR}/verilated_model ${BUILD_DIR}/vector-tests/prog_${TEST_NAME}.txt 32 4194304 ${MEM_LATENCY} 1 ${TEST_NAME} ${VREG_W} ${TEST_CASE_NUM} ${VCD_TRACE_ARGS} + COMMAND ${MODEL_DIR}/verilated_model ${BUILD_DIR}/vector-tests/prog_${TEST_NAME}.txt ${MEM_PORTS} 32 4194304 ${MEM_LATENCY} 1 ${TEST_NAME} ${VREG_W} ${TEST_CASE_NUM} ${VCD_TRACE_ARGS} WORKING_DIRECTORY ${CMAKE_RUNTIME_OUTPUT_DIRECTORY}) message(STATUS "Successfully added ${TEST_NAME}") @@ -142,7 +142,8 @@ macro(add_legacy_test TEST_NAME) COMMAND echo -n "${TEST_BUILD_PATH}/${TEST_NAME}_result.txt " >> prog_${TEST_NAME}.txt COMMAND readelf -s ${folder}-${TEST_NAME}.elf | sed '2,13 s/ //1' | grep vdata_start | cut -d " " -f 6 | tr [=["\n"]=] " " >> prog_${TEST_NAME}.txt COMMAND readelf -s ${folder}-${TEST_NAME}.elf | sed '2,13 s/ //1' | grep vdata_end | cut -d " " -f 6 | tr [=["\n"]=] " " >> prog_${TEST_NAME}.txt - COMMAND ${CMAKE_OBJDUMP} -D ${folder}-${TEST_NAME}.elf > ${TEST_NAME}_dump.txt) + COMMAND ${CMAKE_OBJDUMP} -D ${folder}-${TEST_NAME}.elf > ${TEST_NAME}_dump.txt + ) #If trace option is selected, provide the paths for the .csv and .vcd trace files. Due to argument parsing in verilator_main.cpp, both must be provided diff --git a/CMake/run_legacy_test.cmake b/CMake/run_legacy_test.cmake index 9d18148..f0e663a 100644 --- a/CMake/run_legacy_test.cmake +++ b/CMake/run_legacy_test.cmake @@ -3,7 +3,7 @@ #For reuse, provide the direct path to the files for VERILATED_DIR and BUILD_DIR #Provide the paths for the mem_trace .csv and signal trace .vcd as XXX_TRACE_ARGS to get those outputs. #For test case counting, set argument to 1 for compliance with chipsalliance -execute_process(COMMAND ${VERILATED_DIR}/verilated_model ${BUILD_DIR}/prog_${TEST_NAME}.txt ${MEM_W} 4194304 ${MEM_LATENCY} 1 ${TEST_NAME} ${VREG_W} 1 ${VCD_TRACE_ARGS} +execute_process(COMMAND ${VERILATED_DIR}/verilated_model ${BUILD_DIR}/prog_${TEST_NAME}.txt ${MEM_PORTS} ${MEM_W} 4194304 ${MEM_LATENCY} 1 ${TEST_NAME} ${VREG_W} 1 ${VCD_TRACE_ARGS} RESULT_VARIABLE RETURN_SIM) execute_process(COMMAND diff ${BUILD_DIR}/${TEST_NAME}_result.txt ${BUILD_DIR}/${TEST_NAME}_reference.txt RESULT_VARIABLE RETURN_DIFF) diff --git a/CMake/run_test.cmake b/CMake/run_test.cmake index 51b14d3..c6d7e29 100644 --- a/CMake/run_test.cmake +++ b/CMake/run_test.cmake @@ -2,7 +2,7 @@ #All variables must be passed in from the Add_Tests COMMAND argument #For reuse, provide the direct path to the files for VERILATED_DIR and BUILD_DIR #Provide the paths for the mem_trace .csv and signal trace .vcd as XXX_TRACE_ARGS to get those outputs. -execute_process(COMMAND ${VERILATED_DIR}/verilated_model ${BUILD_DIR}/prog_${TEST_NAME}.txt ${MEM_W} 4194304 ${MEM_LATENCY} 1 ${TEST_NAME} ${VREG_W} ${VCD_TRACE_ARGS} +execute_process(COMMAND ${VERILATED_DIR}/verilated_model ${BUILD_DIR}/prog_${TEST_NAME}.txt ${MEM_PORTS} ${MEM_W} 4194304 ${MEM_LATENCY} 1 ${TEST_NAME} ${VREG_W} ${VCD_TRACE_ARGS} RESULT_VARIABLE RETURN_SIM) if(RETURN_SIM) diff --git a/build_model/CMakeLists.txt b/build_model/CMakeLists.txt index 089c959..841cde2 100644 --- a/build_model/CMakeLists.txt +++ b/build_model/CMakeLists.txt @@ -25,8 +25,8 @@ set(CMAKE_VERBOSE_MAKEFILE ON) set(CMAKE_C_STANDARD 14) set(CMAKE_CXX_STANDARD 14) -option(TRACE "Enable minimal VCD trace outputs" OFF) -option(TRACE_FULL "Enable FULL VCD trace outputs" OFF) #TODO: prevent this option from being cached, force user to always manually enable it +option(TRACE "Enable minimal VCD trace outputs" ON) +option(TRACE_FULL "Enable FULL VCD trace outputs" ON) #TODO: prevent this option from being cached, force user to always manually enable it ######## ## Import RTL configuration from here instead of command line. @@ -40,6 +40,8 @@ message("Selected RISCV_ARCH = ${RISCV_ARCH}") message("Selected VREG_W = ${VREG_W}") set(MEM_W ${VMEM_W}) message("Selected MEM_W = ${MEM_W}") +set(MEM_PORTS ${VMEM_PORTS}) +message("Selected MEM_PORTS = ${MEM_PORTS}") set(MEM_SZ 4194304) @@ -353,7 +355,7 @@ if(TRACE) set(TRACE TRACE) if(TRACE_FULL) - set(TRACE_FLAG ) #no --trace-depth flag defaults to entire model + set(TRACE_FLAG --trace-structs) #no --trace-depth flag defaults to entire model else() set(TRACE_FLAG --trace-depth 2) endif() @@ -398,7 +400,7 @@ if ( ${SCALAR_CORE} STREQUAL "cv32e40x" ) #+define+COREV_ASSERT_OFF #Fixes UVM error with CV32E40X (Needed when not using -DVPROC_SVA) ${TRACE_FLAG} --assert -DVPROC_SVA - -GMEM_W=${MEM_W} -GVMEM_W=${VMEM_W} + -GMEM_W=${MEM_W} -GVMEM_W=${VMEM_W} -GMEM_PORTS=${MEM_PORTS} ${VICUNA_MODE} ${READ_MODE} ${XIF_FLAG} diff --git a/build_model/cv32e40x/verilator_main.cpp b/build_model/cv32e40x/verilator_main.cpp index 373ac9a..6029329 100644 --- a/build_model/cv32e40x/verilator_main.cpp +++ b/build_model/cv32e40x/verilator_main.cpp @@ -20,35 +20,40 @@ int main(int argc, char **argv) { ////////////////////////// //Check validity and parse input arguments ////////////////////////// - if (argc != 9 && argc != 10) { - fprintf(stderr, "ERROR: Correct Usage: %s PROG_PATHS_LIST MEM_W MEM_SZ MEM_LATENCY EXTRA_CYCLES TEST_NAME VREG_W NUM_TEST_CASES [WAVEFORM_FILE]\n", argv[0]); + if (argc != 10 && argc != 11) { + fprintf(stderr, "ERROR: Correct Usage: %s PROG_PATHS_LIST MEM_PORTS MEM_W MEM_SZ MEM_LATENCY EXTRA_CYCLES TEST_NAME VREG_W NUM_TEST_CASES [WAVEFORM_FILE]\n", argv[0]); return 1; } - int mem_w, mem_sz, mem_latency, extra_cycles, num_cases; + int mem_ports, mem_w, mem_sz, mem_latency, extra_cycles, num_cases; { char *endptr; - mem_w = strtol(argv[2], &endptr, 10); + mem_ports = strtol(argv[2], &endptr, 10); + if (mem_ports == 0 || *endptr != 0) { + fprintf(stderr, "ERROR: invalid MEM_PORTS argument\n"); + return 1; + } + mem_w = strtol(argv[3], &endptr, 10); if (mem_w == 0 || *endptr != 0) { fprintf(stderr, "ERROR: invalid MEM_W argument\n"); return 1; } - mem_sz = strtol(argv[3], &endptr, 10); + mem_sz = strtol(argv[4], &endptr, 10); if (mem_sz == 0 || *endptr != 0) { fprintf(stderr, "ERROR: invalid MEM_SZ argument\n"); return 1; } - mem_latency = strtol(argv[4], &endptr, 10); + mem_latency = strtol(argv[5], &endptr, 10); if (*endptr != 0) { fprintf(stderr, "ERROR: invalid MEM_LATENCY argument\n"); return 1; } - extra_cycles = strtol(argv[5], &endptr, 10); + extra_cycles = strtol(argv[6], &endptr, 10); if (*endptr != 0) { fprintf(stderr, "ERROR: invalid EXTRA_CYCLES argument\n"); return 1; } - num_cases = strtol(argv[8], &endptr, 10); + num_cases = strtol(argv[9], &endptr, 10); if (*endptr != 0) { fprintf(stderr, "ERROR: invalid NUM_TEST_CASES argument\n"); return 1; @@ -70,29 +75,35 @@ int main(int argc, char **argv) { ////////////////////////// /*Log File for Scalar Registers*/ - std::string filename=(std::string(argv[6])+std::string("_xreg_commits_verilator.txt")); + std::string filename=(std::string(argv[7])+std::string("_xreg_commits_verilator.txt")); FILE *fxreglog = fopen(filename.c_str(), "w"); /*Log File for Vector Registers. Separate log because actual writes to VREGs might be out of order relative to the Xregs. Should NOT be out of order relative to themselves.*/ - filename=(std::string(argv[6])+std::string("_vreg_commits_verilator.txt")); + filename=(std::string(argv[7])+std::string("_vreg_commits_verilator.txt")); FILE *fvreglog = fopen(filename.c_str(), "w"); /*Log File for Scalar Floating Point Registers*/ - filename=(std::string(argv[6])+std::string("_freg_commits_verilator.txt")); + filename=(std::string(argv[7])+std::string("_freg_commits_verilator.txt")); FILE *ffreglog = fopen(filename.c_str(), "w"); ////////////////////////// //Allocate memory latency buffers ////////////////////////// - - bool *mem_rvalid_queue = (bool *)malloc(sizeof(bool) * mem_latency); - unsigned char **mem_rdata_queue = (unsigned char **)malloc(sizeof(unsigned char *) * mem_latency); //memory data port - bool *mem_err_queue = (bool *)malloc(sizeof(bool) * mem_latency); - - for(int queue_pos = 0; queue_pos < mem_latency; queue_pos++) - { - mem_rdata_queue[queue_pos] = (unsigned char *)malloc(sizeof(unsigned char) * mem_w/8); + bool *mem_rvalid_queue[mem_ports]; + unsigned char **mem_rdata_queue[mem_ports]; + bool *mem_err_queue[mem_ports]; + + for(int i = 0; i < mem_ports; i++){ + mem_rvalid_queue[i] = (bool *)malloc(sizeof(bool) * mem_latency); + mem_rdata_queue[i] = (unsigned char **)malloc(sizeof(unsigned char *) * mem_latency); + mem_err_queue[i] = (bool *)malloc(sizeof(bool) * mem_latency); + + for(int queue_pos = 0; queue_pos < mem_latency; queue_pos++) + { + mem_rdata_queue[i][queue_pos] = (unsigned char *)malloc(sizeof(unsigned char) * mem_w/8); + } } + bool *mem_ivalid_queue = (bool *)malloc(sizeof(bool) * mem_latency); unsigned char **mem_idata_queue = (unsigned char **)malloc(sizeof(unsigned char *) * mem_latency); //memory instruction port @@ -110,11 +121,11 @@ int main(int argc, char **argv) { //Setup vcd trace file ////////////////////////// VerilatedTrace_t *tfp = NULL; - if (argc == 10) { + if (argc == 11) { #ifdef TRACE_VCD tfp = new VerilatedTrace_t; top->trace(tfp, 99); // Trace 99 levels of hierarchy - tfp->open(argv[9]); + tfp->open(argv[10]); #endif } @@ -161,10 +172,12 @@ int main(int argc, char **argv) { ////////////////////////// int i; - for (i = 0; i < mem_latency; i++) { - mem_rvalid_queue[i] = 0; + for(int j = 0; j < mem_ports; j++){ + for (i = 0; i < mem_latency; i++) { + mem_rvalid_queue[j][i] = 0; + } + top->mem_rvalid_i[j] = 0; } - top->mem_rvalid_i = 0; top->mem_irvalid_i = 0; top->clk_i = 0; top->rst_ni = 0; @@ -187,7 +200,7 @@ int main(int argc, char **argv) { char *endptr; - int vreg_w = strtol(argv[7], &endptr, 10); + int vreg_w = strtol(argv[8], &endptr, 10); int cycles_begin_trace = 0; //Traces begin at this cycle count. TODO: expose to the command line int cycles_end_trace = 0; //Traces end at thsi cycle count. TODO: expose to the command line @@ -215,14 +228,15 @@ int main(int argc, char **argv) { ////////////////////////// //Update Memory interfaces ////////////////////////// - - //Update write interface - update_mem_write(top->mem_addr_o, (top->mem_req_o && top->mem_we_o), mem_w, mem_latency, mem_sz, (unsigned char*)&(top->mem_wdata_o), (unsigned char*)&(top->mem_be_o), mem_rvalid_queue, mem); - //Update read interface TODO - STALL IF (top->mem_req_o && !top->mem_we_o). Original Vicuna also did not contain this condition TODO: MEM_REQ_VALID NEEDS TO BE SIGNALLED for writes - update_mem_load(top->mem_addr_o, (top->mem_req_o), mem_w, mem_latency, mem_sz, (unsigned char*)&(top->mem_rdata_i), (bool*)&(top->mem_rvalid_i), (bool*)&(top->mem_err_i), mem_rdata_queue, mem_rvalid_queue, mem_err_queue, mem); - + for(int i = 0; i < mem_ports; i++){ + //Update write interface + update_mem_write(top->mem_addr_o[i], (top->mem_req_o[i] && top->mem_we_o[i]), mem_w, mem_latency, mem_sz, (unsigned char*)&(top->mem_wdata_o[i]), (unsigned char*)&(top->mem_be_o[i]), mem_rvalid_queue[i], mem); + //Update read interface TODO - STALL IF (top->mem_req_o && !top->mem_we_o). Original Vicuna also did not contain this condition TODO: MEM_REQ_VALID NEEDS TO BE SIGNALLED for writes + update_mem_load(top->mem_addr_o[i], (top->mem_req_o[i]), mem_w, mem_latency, mem_sz, (unsigned char*)&(top->mem_rdata_i[i]), (bool*)&(top->mem_rvalid_i[i]), (bool*)&(top->mem_err_i[i]), mem_rdata_queue[i], mem_rvalid_queue[i], mem_err_queue[i], mem); + } + //Update instruction memory interface - update_mem_load(top->mem_iaddr_o, top->mem_ireq_o, 32, mem_latency, mem_sz, (unsigned char*)&(top->mem_irdata_i), (bool*)&(top->mem_irvalid_i), (bool*)&(top->mem_ierr_i), mem_idata_queue, mem_ivalid_queue, mem_ierr_queue, mem); + update_mem_load(top->mem_iaddr_o, top->mem_ireq_o, 32, mem_latency, mem_sz, (unsigned char*)&(top->mem_irdata_i), (bool*)&(top->mem_irvalid_i), (bool*)&(top->mem_ierr_i), mem_idata_queue, mem_ivalid_queue, mem_ierr_queue, mem); top->eval(); @@ -236,7 +250,7 @@ int main(int argc, char **argv) { //Use memory mapped IO at address 0x400 to signal success or failure char w_port; - if (check_memmapio(top->mem_addr_o, (top->mem_req_o && top->mem_we_o), 8, (unsigned char*)&(top->mem_wdata_o), 0x00000400u, &w_port)){ + if (check_memmapio(top->mem_addr_o[0], (top->mem_req_o[0] && top->mem_we_o[0]), 8, (unsigned char*)&(top->mem_wdata_o[0]), 0x00000400u, &w_port)){ if (w_port == 0) { fprintf(stderr, "SUCCESS: TEST PASS - TEST %d - Output Match\n", v_test_failure+v_test_success+2); @@ -323,15 +337,21 @@ int main(int argc, char **argv) { free(dump_path); free(line); free(mem); - free(mem_rvalid_queue); + for(int i = 0; i < mem_ports; i++){ + free(mem_rvalid_queue[i]); + for(int queue_pos = 0; queue_pos < mem_latency; queue_pos++) + { + free(mem_rdata_queue[i][queue_pos]); + } + free(mem_rdata_queue[i]); + free(mem_err_queue[i]); + } + for(int queue_pos = 0; queue_pos < mem_latency; queue_pos++) { - free(mem_rdata_queue[queue_pos]); - free(mem_idata_queue[queue_pos]); + free(mem_idata_queue[queue_pos]); } - free(mem_rdata_queue); free(mem_idata_queue); - free(mem_err_queue); fclose(fprogs); fclose(fxreglog); diff --git a/build_model/cv32e40x/vproc_top.sv b/build_model/cv32e40x/vproc_top.sv index cfa0230..01ea48e 100644 --- a/build_model/cv32e40x/vproc_top.sv +++ b/build_model/cv32e40x/vproc_top.sv @@ -3,23 +3,26 @@ // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -module vproc_top import vproc_pkg::*; #( +module vproc_top import vproc_pkg::*, obi_pkg::*; #( + parameter int unsigned ADDR_W = 32, // memory bus width in bits parameter int unsigned MEM_W = 32, // memory bus width in bits parameter int unsigned VMEM_W = 32, // vector memory interface width in bits + parameter int unsigned MEM_PORTS = 1, + parameter int unsigned PORT_QUEUE_DEPTH = 2, parameter vreg_type VREG_TYPE = VREG_GENERIC, parameter mul_type MUL_TYPE = MUL_GENERIC )( input logic clk_i, input logic rst_ni, - output logic mem_req_o, - output logic [31:0] mem_addr_o, - output logic mem_we_o, - output logic [MEM_W/8-1:0] mem_be_o, - output logic [MEM_W -1:0] mem_wdata_o, - input logic mem_rvalid_i, - input logic mem_err_i, - input logic [MEM_W -1:0] mem_rdata_i, + output logic mem_req_o [MEM_PORTS-1:0], + output logic [31:0] mem_addr_o [MEM_PORTS-1:0], + output logic mem_we_o [MEM_PORTS-1:0], + output logic [MEM_W/8-1:0] mem_be_o [MEM_PORTS-1:0], + output logic [MEM_W -1:0] mem_wdata_o [MEM_PORTS-1:0], + input logic mem_rvalid_i [MEM_PORTS-1:0], + input logic mem_err_i [MEM_PORTS-1:0], + input logic [MEM_W -1:0] mem_rdata_i [MEM_PORTS-1:0], output logic [31:0] pend_vreg_wr_map_o, @@ -87,6 +90,12 @@ module vproc_top import vproc_pkg::*; #( .X_RFW_WIDTH ( X_RFW_WIDTH ), .X_MISA ( X_MISA ) ) vcore_xif (); + + localparam OBI_CFG = obi_default_cfg(ADDR_W, MEM_W, X_ID_WIDTH, ObiMinimalOptionalConfig); + OBI_BUS #( + .OBI_CFG ( OBI_CFG ) + ) vcore_obi_bus [MEM_PORTS-1:0] (); + logic vect_pending_load; logic vect_pending_store; @@ -290,17 +299,17 @@ module vproc_top import vproc_pkg::*; #( // Data read/write for Vector Unit - logic vdata_gnt; - logic vdata_rvalid; - logic vdata_err; - logic [VMEM_W-1:0] vdata_rdata; - logic vdata_req; - logic [31:0] vdata_addr; - logic vdata_we; - logic [VMEM_W/8-1:0] vdata_be; - logic [VMEM_W-1:0] vdata_wdata; - logic [X_ID_WIDTH-1:0] vdata_req_id; - logic [X_ID_WIDTH-1:0] vdata_res_id; + logic vdata_gnt [MEM_PORTS-1:0]; + logic vdata_rvalid [MEM_PORTS-1:0]; + logic vdata_err [MEM_PORTS-1:0]; + logic [VMEM_W-1:0] vdata_rdata [MEM_PORTS-1:0]; + logic vdata_req [MEM_PORTS-1:0]; + logic [31:0] vdata_addr [MEM_PORTS-1:0]; + logic vdata_we [MEM_PORTS-1:0]; + logic [VMEM_W/8-1:0] vdata_be [MEM_PORTS-1:0]; + logic [VMEM_W-1:0] vdata_wdata [MEM_PORTS-1:0]; + logic [X_ID_WIDTH-1:0] vdata_req_id [MEM_PORTS-1:0]; + logic [X_ID_WIDTH-1:0] vdata_res_id [MEM_PORTS-1:0]; // Allow for vector loads/stores to be misaligned with respect to VMEM_W `ifdef FORCE_ALIGNED_READS @@ -319,6 +328,9 @@ module vproc_top import vproc_pkg::*; #( .MUL_TYPE ( MUL_TYPE ), .VLSU_FLAGS ( VLSU_FLAGS ), .BUF_FLAGS ( BUF_FLAGS ), + .OBI_CFG ( OBI_CFG ), + .PORT_QUEUE_DEPTH ( PORT_QUEUE_DEPTH ), + .MEM_PORTS ( MEM_PORTS ), .DONT_CARE_ZERO ( 1'b0 ), .ASYNC_RESET ( 1'b0 ) ) v_core ( @@ -327,9 +339,8 @@ module vproc_top import vproc_pkg::*; #( .xif_issue_if ( vcore_xif ), .xif_commit_if ( vcore_xif ), - .xif_mem_if ( vcore_xif ), - .xif_memres_if ( vcore_xif ), .xif_result_if ( vcore_xif ), + .obi_bus ( vcore_obi_bus ), .pending_load_o ( vect_pending_load ), .pending_store_o ( vect_pending_store ), @@ -361,6 +372,26 @@ module vproc_top import vproc_pkg::*; #( ); + if (USE_XIF_MEM) begin + assign vcore_xif.mem_valid = vcore_obi_bus[0].req; + assign vcore_obi_bus[0].gnt = vcore_xif.mem_ready; + assign vcore_xif.mem_req.id = vcore_obi_bus[0].aid; + assign vcore_xif.mem_req.addr = vcore_obi_bus[0].addr; + assign vcore_xif.mem_req.mode = '0; + assign vcore_xif.mem_req.we = vcore_obi_bus[0].we; + //assign vcore_xif.mem_req.size; //TODO: get size + assign vcore_xif.mem_req.be = vcore_obi_bus[0].be; + assign vcore_xif.mem_req.attr = '0; + assign vcore_xif.mem_req.wdata = vcore_obi_bus[0].wdata; + //assign vcore_xif.mem_req.last; //TODO: get last + assign vcore_xif.mem_req.spec = '0; + assign vcore_obi_bus[0].rvalid = vcore_xif.mem_result_valid; + assign vcore_obi_bus[0].rid = vcore_xif.mem_result.id; + assign vcore_obi_bus[0].rdata = vcore_xif.mem_result.rdata; + assign vcore_obi_bus[0].err = vcore_xif.mem_result.err; + end + + `endif @@ -762,69 +793,75 @@ module vproc_top import vproc_pkg::*; #( assign vdata_wdata = '0; assign vdata_req_id = '0; end else begin - assign vdata_req = vcore_xif.mem_valid; - assign vcore_xif.mem_ready = vdata_gnt; - assign vdata_addr = vcore_xif.mem_req.addr; - assign vdata_we = vcore_xif.mem_req.we; - assign vdata_be = vcore_xif.mem_req.be; - assign vdata_wdata = vcore_xif.mem_req.wdata; - assign vdata_req_id = vcore_xif.mem_req.id; - assign vcore_xif.mem_resp.exc = '0; - assign vcore_xif.mem_resp.exccode = '0; - assign vcore_xif.mem_resp.dbg = '0; - assign vcore_xif.mem_result_valid = vdata_rvalid; - assign vcore_xif.mem_result.id = vdata_res_id; - assign vcore_xif.mem_result.rdata = vdata_rdata; - assign vcore_xif.mem_result.err = vdata_err; - assign vcore_xif.mem_result.dbg = '0; + for(genvar i = 0; i < MEM_PORTS; i++) begin + assign vdata_req[i] = vcore_obi_bus[i].req; + assign vcore_obi_bus[i].gnt = vdata_gnt[i]; + assign vdata_addr[i] = vcore_obi_bus[i].addr; + assign vdata_we[i] = vcore_obi_bus[i].we; + assign vdata_be[i] = vcore_obi_bus[i].be; + assign vdata_wdata[i] = vcore_obi_bus[i].wdata; + assign vdata_req_id[i] = vcore_obi_bus[i].aid; + assign vcore_obi_bus[i].rvalid = vdata_rvalid[i]; + assign vcore_obi_bus[i].rid = vdata_res_id[i]; + assign vcore_obi_bus[i].rdata = vdata_rdata[i]; + assign vcore_obi_bus[i].err = vdata_err[i]; + end end // Data arbiter for main core and vector unit logic sdata_hold; - logic data_req; - logic [31:0] data_addr; - logic data_we; - logic [VMEM_W/8-1:0] data_be; - logic [VMEM_W -1:0] data_wdata; - logic data_gnt; - logic data_rvalid; - logic data_err; - logic [VMEM_W -1:0] data_rdata; - logic sdata_waiting, vdata_waiting; + logic data_req [MEM_PORTS-1:0]; + logic [31:0] data_addr [MEM_PORTS-1:0]; + logic data_we [MEM_PORTS-1:0]; + logic [VMEM_W/8-1:0] data_be [MEM_PORTS-1:0]; + logic [VMEM_W -1:0] data_wdata [MEM_PORTS-1:0]; + logic data_gnt [MEM_PORTS-1:0]; + logic data_rvalid [MEM_PORTS-1:0]; + logic data_err [MEM_PORTS-1:0]; + logic [VMEM_W -1:0] data_rdata [MEM_PORTS-1:0]; + logic sdata_waiting; + logic vdata_waiting [MEM_PORTS-1:0]; logic [31:0] sdata_wait_addr; - logic [X_ID_WIDTH-1:0] vdata_wait_id; - assign sdata_hold = ~USE_XIF_MEM & (vdata_req | vect_pending_store | (vect_pending_load & sdata_we)); + logic [X_ID_WIDTH-1:0] vdata_wait_id [MEM_PORTS-1:0]; + assign sdata_hold = ~USE_XIF_MEM & (vdata_req[0] | vect_pending_store | (vect_pending_load & sdata_we)); always_comb begin - data_req = vdata_req | (sdata_req & ~sdata_hold); - data_addr = sdata_addr; - data_we = sdata_we; + data_req[0] = vdata_req[0] | (sdata_req & ~sdata_hold); + data_addr[0] = sdata_addr; + data_we[0] = sdata_we; `ifdef FORCE_ALIGNED_READS - data_be = {{(VMEM_W-32){1'b0}}, sdata_be} << (sdata_addr[$clog2(VMEM_W/8)-1:0] & {{$clog2(VMEM_W/32){1'b1}}, 2'b00}); - data_wdata = '0; + data_be[0] = {{(VMEM_W-32){1'b0}}, sdata_be} << (sdata_addr[$clog2(VMEM_W/8)-1:0] & {{$clog2(VMEM_W/32){1'b1}}, 2'b00}); + data_wdata[0] = '0; for (int i = 0; i < VMEM_W / 32; i++) begin - data_wdata[32*i +: 32] = sdata_wdata; + data_wdata[0][32*i +: 32] = sdata_wdata; end `else - data_be = {{(VMEM_W-32){1'b0}}, sdata_be}; - data_wdata = {{(VMEM_W-32){1'b0}}, sdata_wdata}; + data_be[0] = {{(VMEM_W-32){1'b0}}, sdata_be}; + data_wdata[0] = {{(VMEM_W-32){1'b0}}, sdata_wdata}; `endif - if (vdata_req) begin - data_addr = vdata_addr; - data_we = vdata_we; - data_be = vdata_be; - data_wdata = vdata_wdata; + if (vdata_req[0]) begin + data_addr[0] = vdata_addr[0]; + data_we[0] = vdata_we[0]; + data_be[0] = vdata_be[0]; + data_wdata[0] = vdata_wdata[0]; + end + for(int i = 1; i < MEM_PORTS; i++) begin + data_req[i] = vdata_req[i]; + data_addr[i] = vdata_addr[i]; + data_we[i] = vdata_we[i]; + data_be[i] = vdata_be[i]; + data_wdata[i] = vdata_wdata[i]; end end - assign sdata_gnt = data_gnt & sdata_req & ~sdata_hold; - assign vdata_gnt = data_gnt & vdata_req; + assign sdata_gnt = data_gnt[0] & sdata_req & ~sdata_hold; + for(genvar i = 0; i < MEM_PORTS; i++) begin + assign vdata_gnt[i] = data_gnt[i] & vdata_req[i]; + end always_ff @(posedge clk_i or negedge rst_ni) begin if (~rst_ni) begin sdata_waiting <= 1'b0; - vdata_waiting <= 1'b0; sdata_wait_addr <= '0; - vdata_wait_id <= '0; end else begin if (sdata_gnt) begin sdata_waiting <= 1'b1; @@ -833,24 +870,43 @@ module vproc_top import vproc_pkg::*; #( else if (sdata_rvalid) begin sdata_waiting <= 1'b0; end - if (vdata_gnt) begin - vdata_waiting <= 1'b1; - vdata_wait_id <= vdata_req_id; - end - else if (vdata_rvalid) begin - vdata_waiting <= 1'b0; - end end end - assign sdata_rvalid = sdata_waiting & data_rvalid; - assign vdata_rvalid = vdata_waiting & data_rvalid; - assign sdata_err = data_err; - assign vdata_err = data_err; + + generate + for (genvar i = 0; i < MEM_PORTS; i++) begin + vproc_queue #( + .WIDTH ( $bits(X_ID_WIDTH) ), + .DEPTH ( PORT_QUEUE_DEPTH ), + .FLOW ( 1'b1 ) + ) v_wait_id_queue ( + .clk_i ( clk_i ), + .async_rst_ni ( 1 ), + .sync_rst_ni ( sync_rst_n ), + .enq_ready_o ( ), + .enq_valid_i ( vdata_gnt[i] ), + .enq_data_i ( vdata_req_id[i] ), + .deq_ready_i ( vdata_rvalid[i] ), + .deq_valid_o ( vdata_waiting[i] ), + .deq_data_o ( vdata_wait_id[i] ), + .flags_any_o ( ), + .flags_all_o ( ) + ); + end + endgenerate + + assign sdata_rvalid = sdata_waiting & data_rvalid[0]; + assign sdata_err = data_err[0]; + + for(genvar i = 0; i < MEM_PORTS; i++) begin + assign vdata_rvalid[i] = vdata_waiting[i] & data_rvalid[i]; + assign vdata_err[i] = data_err[i]; + end `ifdef FORCE_ALIGNED_READS - assign sdata_rdata = data_rdata[(sdata_wait_addr[$clog2(VMEM_W)-1:0] & {3'b000, {($clog2(VMEM_W/8)-2){1'b1}}, 2'b00})*8 +: 32]; + assign sdata_rdata = data_rdata[0][(sdata_wait_addr[$clog2(VMEM_W)-1:0] & {3'b000, {($clog2(VMEM_W/8)-2){1'b1}}, 2'b00})*8 +: 32]; `else - assign sdata_rdata = data_rdata[31:0]; + assign sdata_rdata = data_rdata[0][31:0]; `endif assign vdata_rdata = data_rdata; assign vdata_res_id = vdata_wait_id; @@ -874,28 +930,30 @@ module vproc_top import vproc_pkg::*; #( // Memory Interface signals D-DATA - logic dmem_req; - logic dmem_gnt; - logic [31:0] dmem_addr; - logic dmem_we; - logic [MEM_W/8-1:0] dmem_be; - logic [MEM_W -1:0] dmem_wdata; - logic dmem_rvalid; - logic dmem_wvalid; - logic [MEM_W -1:0] dmem_rdata; - logic dmem_err; + logic dmem_req [MEM_PORTS-1:0]; + logic dmem_gnt [MEM_PORTS-1:0]; + logic [31:0] dmem_addr [MEM_PORTS-1:0]; + logic dmem_we [MEM_PORTS-1:0]; + logic [MEM_W/8-1:0] dmem_be [MEM_PORTS-1:0]; + logic [MEM_W -1:0] dmem_wdata [MEM_PORTS-1:0]; + logic dmem_rvalid [MEM_PORTS-1:0]; + logic dmem_wvalid [MEM_PORTS-1:0]; + logic [MEM_W -1:0] dmem_rdata [MEM_PORTS-1:0]; + logic dmem_err [MEM_PORTS-1:0]; logic d_miss /* verilator public */; logic d_hit /* verilator public */; - assign dmem_req = data_req; - assign dmem_addr = data_addr; - assign dmem_we = data_we && mem_req_o; - assign dmem_be = data_be; - assign dmem_wdata = data_wdata; - assign data_gnt = dmem_gnt; - assign data_rvalid = dmem_rvalid | dmem_wvalid; - assign data_rdata = dmem_rdata; - assign data_err = dmem_err; + for(genvar i = 0; i < MEM_PORTS; i++) begin + assign dmem_req[i] = data_req[i]; + assign dmem_addr[i] = data_addr[i]; + assign dmem_we[i] = data_we[i] && mem_req_o[i]; + assign dmem_be[i] = data_be[i]; + assign dmem_wdata[i] = data_wdata[i]; + assign data_gnt[i] = dmem_gnt[i]; + assign data_rvalid[i] = dmem_rvalid[i] | dmem_wvalid[i]; + assign data_rdata[i] = dmem_rdata[i]; + assign data_err[i] = dmem_err[i]; + end @@ -927,37 +985,43 @@ module vproc_top import vproc_pkg::*; #( // shift register keeping track of the source of mem requests for up to 32 cycles (needed to keep track of reads/writes) - logic req_sources [32]; - logic req_write [32]; // keeping track of whether the request was a write - logic [4:0] req_count; + logic [MEM_PORTS-1:0][31:0] req_sources; + logic [MEM_PORTS-1:0][31:0] req_write; // keeping track of whether the request was a write + logic [MEM_PORTS-1:0][4:0] req_count; always_ff @(posedge clk_i or negedge rst_ni) begin if (~rst_ni) begin - req_count <= '0; + req_count <= '{default: '0}; end else begin - if (mem_rvalid_i) begin - for (int i = 0; i < 31; i++) begin - req_sources [i] <= req_sources [i+1]; - req_write [i] <= req_write [i+1]; + for(int i = 0; i < MEM_PORTS; i++) begin + if (mem_rvalid_i[i]) begin + for (int j = 0; j < 31; j++) begin + req_sources [i][j] <= req_sources [i][j+1]; + req_write [i][j] <= req_write [i][j+1]; + end + if (~dmem_gnt[i]) begin + req_count[i] <= req_count[i] - 1; + end else begin + req_sources [i][req_count[i]-1] <= dmem_gnt[i]; + req_write [i][req_count[i]-1] <= dmem_we[i]; + end end - if (~dmem_gnt) begin - req_count <= req_count - 1; - end else begin - req_sources [req_count-1] <= dmem_gnt; - req_write [req_count-1] <= dmem_we; + else if (dmem_gnt[i]) begin + req_sources [i][req_count] <= dmem_gnt[i]; + req_write [i][req_count] <= dmem_we[i]; + req_count[i] <= req_count[i] + 1; end end - else if (dmem_gnt) begin - req_sources [req_count] <= dmem_gnt; - req_write [req_count] <= dmem_we; - req_count <= req_count + 1; - end end end assign imem_rvalid = mem_irvalid_i; - assign dmem_rvalid = mem_rvalid_i & ~req_write[0]; - assign dmem_wvalid = mem_rvalid_i & req_write[0]; //this could be an issue? + generate + for(genvar i = 0; i < MEM_PORTS; i++) begin + assign dmem_rvalid[i] = mem_rvalid_i[i] & ~req_write[i][0]; + assign dmem_wvalid[i] = mem_rvalid_i[i] & req_write[i][0]; //this could be an issue? + end + endgenerate assign imem_err = mem_ierr_i; assign dmem_err = mem_err_i; diff --git a/build_model/vector_config.cmake b/build_model/vector_config.cmake index ce1e5c6..6500fe6 100644 --- a/build_model/vector_config.cmake +++ b/build_model/vector_config.cmake @@ -8,7 +8,7 @@ set(RISCV_ARCH rv32im_zve32x CACHE STRING "Specify the configuration") #Currently Supported: cv32e40x, cv32a60x set(SCALAR_CORE "cv32e40x") - +set(VMEM_PORTS 4) set(VMEM_W 32) set(VREG_W 128) set(VPROC_PIPELINES "${VMEM_W}:VLSU 32:VELEM,VSLD,VDIV,VALU,VMUL") diff --git a/build_tests/CMakeLists.txt b/build_tests/CMakeLists.txt index cc250ae..f6a555e 100644 --- a/build_tests/CMakeLists.txt +++ b/build_tests/CMakeLists.txt @@ -16,12 +16,12 @@ message(STATUS "CMake Version ${CMAKE_MAJOR_VERSION}.${CMAKE_MINOR_VERSION}.${CM set(MEM_LATENCY 1 CACHE STRING "Memory latency") set(INTEGER 0 CACHE STRING "Variable for ChipsAlliance Tests to build only integer vector tests") -option(TRACE "Enable trace outputs" OFF) +option(TRACE "Enable trace outputs" ON) option(SPIKE "Enable Spike Cosim" OFF) option(PRINT "Enable print statements" OFF) option(LEGACY "Use Legacy unit tests" OFF) -option(BUILD_TEST_SOURCE "Build ChipsAlliance Tests from source. Can skip if already build for chosen configuration" ON) +option(BUILD_TEST_SOURCE "Build ChipsAlliance Tests from source. Can skip if already build for chosen configuration" OFF) ##### @@ -52,6 +52,8 @@ message("Selected VREG_W = ${VREG_W}") message("Selected VMEM_W = ${VMEM_W}") set(MEM_W ${VMEM_W}) message("Selected MEM_W = ${MEM_W}") +set(MEM_PORTS ${VMEM_PORTS}) +message("Selected MEM_PORTS = ${MEM_PORTS}") ##### From 5e899cb35b6477bc158dafff8ecaf01447a2e714 Mon Sep 17 00:00:00 2001 From: Melvin John Date: Tue, 17 Mar 2026 12:14:41 +0100 Subject: [PATCH 02/18] Added files --- build_model/cv32e40x/vproc_top.sv | 81 ++- wavefrom_debug_lsu_extension.gtkw | 1061 +++++++++++++++++++++++++++++ 2 files changed, 1108 insertions(+), 34 deletions(-) create mode 100644 wavefrom_debug_lsu_extension.gtkw diff --git a/build_model/cv32e40x/vproc_top.sv b/build_model/cv32e40x/vproc_top.sv index 01ea48e..19f8536 100644 --- a/build_model/cv32e40x/vproc_top.sv +++ b/build_model/cv32e40x/vproc_top.sv @@ -7,6 +7,7 @@ module vproc_top import vproc_pkg::*, obi_pkg::*; #( parameter int unsigned ADDR_W = 32, // memory bus width in bits parameter int unsigned MEM_W = 32, // memory bus width in bits parameter int unsigned VMEM_W = 32, // vector memory interface width in bits + parameter int unsigned OBI_ID_WIDTH = 8, // vector memory interface width in bits parameter int unsigned MEM_PORTS = 1, parameter int unsigned PORT_QUEUE_DEPTH = 2, parameter vreg_type VREG_TYPE = VREG_GENERIC, @@ -20,9 +21,11 @@ module vproc_top import vproc_pkg::*, obi_pkg::*; #( output logic mem_we_o [MEM_PORTS-1:0], output logic [MEM_W/8-1:0] mem_be_o [MEM_PORTS-1:0], output logic [MEM_W -1:0] mem_wdata_o [MEM_PORTS-1:0], + output logic mem_aid_o [MEM_PORTS-1:0], input logic mem_rvalid_i [MEM_PORTS-1:0], input logic mem_err_i [MEM_PORTS-1:0], input logic [MEM_W -1:0] mem_rdata_i [MEM_PORTS-1:0], + input logic mem_rid_i [MEM_PORTS-1:0], output logic [31:0] pend_vreg_wr_map_o, @@ -91,7 +94,7 @@ module vproc_top import vproc_pkg::*, obi_pkg::*; #( .X_MISA ( X_MISA ) ) vcore_xif (); - localparam OBI_CFG = obi_default_cfg(ADDR_W, MEM_W, X_ID_WIDTH, ObiMinimalOptionalConfig); + localparam OBI_CFG = obi_default_cfg(ADDR_W, MEM_W, OBI_ID_WIDTH, ObiMinimalOptionalConfig); OBI_BUS #( .OBI_CFG ( OBI_CFG ) ) vcore_obi_bus [MEM_PORTS-1:0] (); @@ -308,8 +311,8 @@ module vproc_top import vproc_pkg::*, obi_pkg::*; #( logic vdata_we [MEM_PORTS-1:0]; logic [VMEM_W/8-1:0] vdata_be [MEM_PORTS-1:0]; logic [VMEM_W-1:0] vdata_wdata [MEM_PORTS-1:0]; - logic [X_ID_WIDTH-1:0] vdata_req_id [MEM_PORTS-1:0]; - logic [X_ID_WIDTH-1:0] vdata_res_id [MEM_PORTS-1:0]; + logic [OBI_ID_WIDTH-1:0] vdata_req_id [MEM_PORTS-1:0]; + logic [OBI_ID_WIDTH-1:0] vdata_res_id [MEM_PORTS-1:0]; // Allow for vector loads/stores to be misaligned with respect to VMEM_W `ifdef FORCE_ALIGNED_READS @@ -371,11 +374,11 @@ module vproc_top import vproc_pkg::*, obi_pkg::*; #( .pend_vreg_wr_map_o ( pend_vreg_wr_map_o ) ); - - if (USE_XIF_MEM) begin + // TODO: wire id signal from/to aoptional/roptional field from lsu + if (USE_XIF_MEM) begin assign vcore_xif.mem_valid = vcore_obi_bus[0].req; assign vcore_obi_bus[0].gnt = vcore_xif.mem_ready; - assign vcore_xif.mem_req.id = vcore_obi_bus[0].aid; + //assign vcore_xif.mem_req.id = vcore_obi_bus[0].aid; assign vcore_xif.mem_req.addr = vcore_obi_bus[0].addr; assign vcore_xif.mem_req.mode = '0; assign vcore_xif.mem_req.we = vcore_obi_bus[0].we; @@ -386,7 +389,7 @@ module vproc_top import vproc_pkg::*, obi_pkg::*; #( //assign vcore_xif.mem_req.last; //TODO: get last assign vcore_xif.mem_req.spec = '0; assign vcore_obi_bus[0].rvalid = vcore_xif.mem_result_valid; - assign vcore_obi_bus[0].rid = vcore_xif.mem_result.id; + //assign vcore_obi_bus[0].rid = vcore_xif.mem_result.id; assign vcore_obi_bus[0].rdata = vcore_xif.mem_result.rdata; assign vcore_obi_bus[0].err = vcore_xif.mem_result.err; end @@ -819,15 +822,17 @@ module vproc_top import vproc_pkg::*, obi_pkg::*; #( logic data_rvalid [MEM_PORTS-1:0]; logic data_err [MEM_PORTS-1:0]; logic [VMEM_W -1:0] data_rdata [MEM_PORTS-1:0]; + logic [OBI_ID_WIDTH-1:0] data_req_id [MEM_PORTS-1:0]; + logic [OBI_ID_WIDTH-1:0] data_res_id [MEM_PORTS-1:0]; logic sdata_waiting; - logic vdata_waiting [MEM_PORTS-1:0]; + logic vdata_waiting; logic [31:0] sdata_wait_addr; - logic [X_ID_WIDTH-1:0] vdata_wait_id [MEM_PORTS-1:0]; assign sdata_hold = ~USE_XIF_MEM & (vdata_req[0] | vect_pending_store | (vect_pending_load & sdata_we)); always_comb begin data_req[0] = vdata_req[0] | (sdata_req & ~sdata_hold); data_addr[0] = sdata_addr; data_we[0] = sdata_we; + // TODO: data_req_id[0] = ; for cva core `ifdef FORCE_ALIGNED_READS data_be[0] = {{(VMEM_W-32){1'b0}}, sdata_be} << (sdata_addr[$clog2(VMEM_W/8)-1:0] & {{$clog2(VMEM_W/32){1'b1}}, 2'b00}); @@ -845,6 +850,7 @@ module vproc_top import vproc_pkg::*, obi_pkg::*; #( data_we[0] = vdata_we[0]; data_be[0] = vdata_be[0]; data_wdata[0] = vdata_wdata[0]; + data_req_id[0] = vdata_req_id[0]; end for(int i = 1; i < MEM_PORTS; i++) begin data_req[i] = vdata_req[i]; @@ -852,6 +858,7 @@ module vproc_top import vproc_pkg::*, obi_pkg::*; #( data_we[i] = vdata_we[i]; data_be[i] = vdata_be[i]; data_wdata[i] = vdata_wdata[i]; + data_req_id[i] = vdata_req_id[i]; end end assign sdata_gnt = data_gnt[0] & sdata_req & ~sdata_hold; @@ -873,33 +880,32 @@ module vproc_top import vproc_pkg::*, obi_pkg::*; #( end end - generate - for (genvar i = 0; i < MEM_PORTS; i++) begin - vproc_queue #( - .WIDTH ( $bits(X_ID_WIDTH) ), - .DEPTH ( PORT_QUEUE_DEPTH ), - .FLOW ( 1'b1 ) - ) v_wait_id_queue ( - .clk_i ( clk_i ), - .async_rst_ni ( 1 ), - .sync_rst_ni ( sync_rst_n ), - .enq_ready_o ( ), - .enq_valid_i ( vdata_gnt[i] ), - .enq_data_i ( vdata_req_id[i] ), - .deq_ready_i ( vdata_rvalid[i] ), - .deq_valid_o ( vdata_waiting[i] ), - .deq_data_o ( vdata_wait_id[i] ), - .flags_any_o ( ), - .flags_all_o ( ) - ); - end - endgenerate + vproc_queue #( + .WIDTH ( 1 ), + .DEPTH ( PORT_QUEUE_DEPTH ), + .FLOW ( 1'b1 ) + ) v_wait_id_queue ( + .clk_i ( clk_i ), + .async_rst_ni ( 1 ), + .sync_rst_ni ( sync_rst_n ), + .enq_ready_o ( ), + .enq_valid_i ( vdata_gnt[0] ), + .enq_data_i ( ), + .deq_ready_i ( vdata_rvalid[0] ), + .deq_valid_o ( vdata_waiting ), + .deq_data_o ( ), + .flags_any_o ( ), + .flags_all_o ( ) + ); assign sdata_rvalid = sdata_waiting & data_rvalid[0]; assign sdata_err = data_err[0]; - - for(genvar i = 0; i < MEM_PORTS; i++) begin - assign vdata_rvalid[i] = vdata_waiting[i] & data_rvalid[i]; + + + assign vdata_rvalid[0] = vdata_waiting & data_rvalid[0]; + assign vdata_err[0] = data_err[0]; + for(genvar i = 1; i < MEM_PORTS; i++) begin + assign vdata_rvalid[i] = data_rvalid[i]; assign vdata_err[i] = data_err[i]; end @@ -909,7 +915,7 @@ module vproc_top import vproc_pkg::*, obi_pkg::*; #( assign sdata_rdata = data_rdata[0][31:0]; `endif assign vdata_rdata = data_rdata; - assign vdata_res_id = vdata_wait_id; + assign vdata_res_id = data_res_id; // Memory Interface signals I-DATA logic imem_req; @@ -940,6 +946,8 @@ module vproc_top import vproc_pkg::*, obi_pkg::*; #( logic dmem_wvalid [MEM_PORTS-1:0]; logic [MEM_W -1:0] dmem_rdata [MEM_PORTS-1:0]; logic dmem_err [MEM_PORTS-1:0]; + logic dmem_aid [MEM_PORTS-1:0]; + logic dmem_rid [MEM_PORTS-1:0]; logic d_miss /* verilator public */; logic d_hit /* verilator public */; @@ -953,6 +961,8 @@ module vproc_top import vproc_pkg::*, obi_pkg::*; #( assign data_rvalid[i] = dmem_rvalid[i] | dmem_wvalid[i]; assign data_rdata[i] = dmem_rdata[i]; assign data_err[i] = dmem_err[i]; + assign dmem_aid[i] = data_req_id[i]; + assign data_res_id[i] = dmem_rid[i]; end @@ -1028,6 +1038,9 @@ module vproc_top import vproc_pkg::*, obi_pkg::*; #( assign imem_rdata = mem_irdata_i; assign dmem_rdata = mem_rdata_i; + + assign mem_aid_o = dmem_aid; + assign dmem_rid = mem_rid_i; diff --git a/wavefrom_debug_lsu_extension.gtkw b/wavefrom_debug_lsu_extension.gtkw new file mode 100644 index 0000000..6bc559c --- /dev/null +++ b/wavefrom_debug_lsu_extension.gtkw @@ -0,0 +1,1061 @@ +[*] +[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI +[*] Tue Mar 10 20:21:26 2026 +[*] +[dumpfile] "/home/vboxuser/Desktop/vicuna2_ros_verilator/programs/build/uros_etiss/test_uros_etiss_sig.vcd" +[dumpfile_mtime] "Tue Mar 10 20:21:15 2026" +[dumpfile_size] 174620672 +[savefile] "/home/vboxuser/Desktop/vicuna2_unit_testing/wavefrom_debug_lsu_extension.gtkw" +[timestart] 29396 +[size] 1848 902 +[pos] -1 -1 +*-5.945512 29497 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[treeopen] TOP. +[treeopen] TOP.vproc_top. +[treeopen] TOP.vproc_top.v_core. +[treeopen] TOP.vproc_top.v_core.dec.mode_o. +[treeopen] TOP.vproc_top.v_core.dec_data_q.mode. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.alt_count_next_inc. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.count_next_inc. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.genblk1[0]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.genblk1[0].genblk1. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pipe_in_state_i.mode. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_next.alt_count. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_next.count. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_next.mode. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_q.alt_count. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_q.count. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_q.mode. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.genblk3[0]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_red. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ctrl_i.mode. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_out_ctrl_o. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk4[0]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk6[2]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[0]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[0].genblk1[0]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[1]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[1].genblk1[0]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[2]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[2].genblk1[0]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[3]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[3].genblk1[0]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[4]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[4].genblk1[0]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack_out_ctrl.mode. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.pipe_in_data_i.mode. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.state_init.mode. +[treeopen] TOP.vproc_top.v_core.genblk9[1].pipe. +[treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2. +[treeopen] TOP.vproc_top.v_core.pipe_instr_data.mode. +[treeopen] TOP.vproc_top.v_core.queue_data_d.mode. +[treeopen] TOP.vproc_top.v_core.queue_data_q.mode. +[treeopen] TOP.vproc_top.v_core.queue_pending_wr.mode_i.alu. +[treeopen] TOP.vproc_top.v_core.vregfile. +[treeopen] TOP.vproc_top.v_core.vregfile.genblk1[0]. +[treeopen] TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1. +[treeopen] TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0]. +[treeopen] TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[1]. +[treeopen] TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[2]. +[sst_width] 379 +[signals_width] 646 +[sst_expanded] 1 +[sst_vpaned_height] 259 +@28 +TOP.vproc_top.clk_i +@800200 +-lsu +@200 +-lsu +-input +@28 +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_valid_i +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ready_o +@22 +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.vreg_pend_rd_i[31:0] +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_op1_i[31:0] +[color] 7 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+TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[8][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[9][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[10][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[11][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[12][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[13][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[14][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[15][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[16][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[17][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[18][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[19][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[20][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[21][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[22][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[23][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[24][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[25][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[26][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[27][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[28][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[29][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[30][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[31][127:0] +@1000200 +-RAM +-registers +@800200 +-lsu_extension +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.clk_i +@200 +-scratch_state_q +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_state_q.current_eew[1:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_state_q.fsm_state[2:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_state_q.outstanding_mem_req_cnt[2:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_state_q.pending_load_state_cb[2:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_state_q.pending_store_state_cb[2:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_state_q.store_end_index[0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_state_q.write_index[0] +@200 +-scratch_state_d +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_state_d.fsm_state[2:0] +@200 +-port_state_q +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.port_state_q.portq_elem_cnt[0][0] +@200 +-scratch_memory +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_memory_state_q[0][1:0] +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_memory_q[0].addr[31:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_memory_q[0].data[31:0] +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_memory_q[0].pending_req_cnt[2:0] +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_memory_q[0].wmask[3:0] +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_memory_state_q[1][1:0] +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_memory_q[1].addr[31:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_memory_q[1].data[31:0] +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_memory_q[1].pending_req_cnt[2:0] +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_memory_q[1].wmask[3:0] +@200 +-scratch_pending +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_hit +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_hit_data[31:0] +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_pending +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_pending_data_off[1:0] +#{scratch_pending_index[1:0]} TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_pending_index[0] +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_pending_output[31:0] +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_pending_req_cleared +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_queue_data_out[31:0] +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_queue_pending_data_off_out[1:0] +#{scratch_queue_pending_index_out[1:0]} TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_queue_pending_index_out[0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_queue_pending_out +@200 +-input_queue +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.input_queue.empty +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.input_queue_ready_in +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.input_queue_ready_out +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.input_queue_valid_out +@200 +-output_queue +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.output_queue_ready_in +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.output_queue_ready_out +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.output_queue_valid_out +@200 +-mem_req_queue +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.mem_req_queue_ready_out +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.mem_req_queue_valid_in +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.mem_req_queue_valid_out +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.mem_req_switch +@200 +-port_queue +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.port_queue_rdata_out[0][31:0] +@28 +#{port_queue_write_index_out[0][1:0]} TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.port_queue_write_index_out[0][0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.genblk3[0].port_queue.enq_valid_i +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.genblk3[0].port_write_index_queue.enq_valid_i +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.genblk3[0].port_write_index_queue.enq_ready_o +@200 +-vtop +@28 +TOP.vproc_top.clk_i +TOP.vproc_top.vdata_gnt[0] +TOP.vproc_top.data_rvalid[0] +TOP.vproc_top.vdata_rvalid[0] +@200 +-obi_port_0 +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[0].req +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[0].gnt +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[0].rvalid +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[0].addr[31:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[0].be[3:0] +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[0].we +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[0].err +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[0].rdata[31:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[0].wdata[31:0] +@200 +-obi_port_1 +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[1].req +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[1].gnt +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[1].rvalid +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[1].addr[31:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[1].be[3:0] +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[1].we +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[1].err +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[1].rdata[31:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[1].wdata[31:0] +@200 +-obi_port_2 +-state_req_red_i +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_red_i.res_vaddr[4:0] +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_red_i.res_store +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_red_i.id[3:0] +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_red_i.state_req_valid_q +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_red_i.req_addr_q[31:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_red_i.wdata_buf_q[31:0] +@200 +-state_req_red +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_red.mode.eew[1:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_red.first_cycle +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_red.last_cycle +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_red.req_addr_q[31:0] +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_red.field_counter[2:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_red.field_init_count[2:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_red.suppressed +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_red.mode.store +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_red.wdata_buf_q[31:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_red.wmask_buf_q[3:0] +@200 +-deq_state +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.deq_state.id[3:0] +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.deq_state.first_cycle +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.deq_state.last_cycle +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.deq_state.field_counter[2:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.deq_state.field_init_count[2:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.deq_state.suppressed +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_rdata_valid_d +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.rdata_buf_q[31:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.rdata_buf_d[31:0] +@200 +-general +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_ready +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_stall +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.pending_req_stall +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.mem_exc_q +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.trans_complete_valid +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.trans_complete_valid_o +@1000200 +-lsu_extension +@c00200 +-decoder +@200 +-decoder +@28 +TOP.vproc_top.v_core.dec.instr_valid_i +TOP.vproc_top.v_core.dec.instr_illegal +TOP.vproc_top.v_core.dec.op_illegal +TOP.vproc_top.v_core.dec.vd_invalid +TOP.vproc_top.v_core.dec.vs1_invalid +TOP.vproc_top.v_core.dec.vs2_invalid +TOP.vproc_top.v_core.dec.vtype_invalid +@22 +TOP.vproc_top.v_core.dec.instr_i[31:0] +TOP.vproc_top.v_core.dec.instr_vd[4:0] +TOP.vproc_top.v_core.dec.instr_vs1[4:0] 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+TOP.vproc_top.host_xif.issue_req.rs[2][31:0] +TOP.vproc_top.host_xif.issue_req.instr[31:0] +[pattern_trace] 1 +[pattern_trace] 0 From 997b5241d5aa282573f573d0c9bb2f5c9c335827 Mon Sep 17 00:00:00 2001 From: Melvin John Date: Tue, 17 Mar 2026 12:16:20 +0100 Subject: [PATCH 03/18] Added gtk file --- bli.gtkw | 450 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 450 insertions(+) create mode 100644 bli.gtkw diff --git a/bli.gtkw b/bli.gtkw new file mode 100644 index 0000000..aed8580 --- /dev/null +++ b/bli.gtkw @@ -0,0 +1,450 @@ +[*] +[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI +[*] Mon Mar 16 16:13:10 2026 +[*] +[dumpfile] "/home/vboxuser/Desktop/vicuna2_ros_verilator/programs/build/uros_etiss/test_uros_etiss_sig.vcd" +[dumpfile_mtime] "Mon Mar 16 16:11:10 2026" +[dumpfile_size] 456987779 +[savefile] "/home/vboxuser/Desktop/vicuna2_unit_testing/bli.gtkw" +[timestart] 34367 +[size] 1848 902 +[pos] -1 -1 +*-4.839435 34375 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[treeopen] TOP. +[treeopen] TOP.vproc_top. +[treeopen] TOP.vproc_top.v_core. +[treeopen] TOP.vproc_top.v_core.genblk9[1]. +[treeopen] TOP.vproc_top.v_core.genblk9[1].pipe. +[treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2. +[treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline. +[treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.pack. +[treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.pack.genblk1[0].genblk1. +[treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.pack.genblk1[1]. +[treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.pack.genblk1[1].genblk1. +[treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.pipe_in_state_i.mode. +[treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.pipe_in_state_i.mode.alu. +[treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.state_q.mode. +[treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux. +[treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1]. +[treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1. +[treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit. +[treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1. +[treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu. +[treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.pipe_in_ctrl_i.mode.alu. +[treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.state_ex1_q. +[treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.state_ex1_q.mode. +[treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.state_ex1_q.mode.alu. +[treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[2].genblk1. +[treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[2].genblk1.unit. +[treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[3].genblk1. +[treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[3].genblk1.unit. +[treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[3].genblk1.unit.genblk1. +[treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[5].genblk1. +[treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[5].genblk1.unit. +[treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[5].genblk1.unit.genblk1. +[treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[6]. +[treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[6].genblk1. +[treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[6].genblk1.unit. +[treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[6].genblk1.unit.genblk1. +[treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[6].genblk1.unit.genblk1.elem. +[treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[6].genblk1.unit.genblk1.elem.pipe_in_ctrl_i. +[treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[6].genblk1.unit.genblk1.elem.pipe_in_ctrl_i.mode. +[treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.pipe_in_ctrl_i. +[treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.pipe_in_data_i. +[treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.pipe_in_data_i.mode. +[treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.pipe_in_data_i.mode.alu. +[treeopen] TOP.vproc_top.v_core.vregfile.genblk1[0]. +[treeopen] TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1. +[treeopen] TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0]. +[sst_width] 350 +[signals_width] 513 +[sst_expanded] 1 +[sst_vpaned_height] 238 +@22 +TOP.vproc_top.v_core.genblk9[1].pipe.OP_CNT[31:0] +TOP.vproc_top.v_core.genblk9[1].pipe.RES_CNT[31:0] +TOP.vproc_top.v_core.genblk9[1].pipe.MAX_OP_W[31:0] +TOP.vproc_top.v_core.genblk9[1].pipe.MAX_RES_W[31:0] +@c00200 +-pipeline +@28 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.pipe_in_ready_o +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.pipe_in_valid_i +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.pipe_in_state_i.mode.alu.opx2.cmp[2:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.pipe_in_state_i.mode.alu.opx2.res[2:0] +@22 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.state_q.count.val[7:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.state_q.count.part.low[3:0] +@28 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.state_q.count.part.mul[2:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.state_q.count.part.sign +@22 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.state_q.alt_count.val[7:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.state_q.alt_count.part.low[3:0] +@28 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.state_q.alt_count.part.mul[2:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.state_q.alt_count.part.sign +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.state_q.count_inc[1:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.state_q.alt_count_inc[1:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.state_q.alt_last_cycle +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.state_q.last_cycle +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.state_q.eew[1:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.state_q.emul[1:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.state_q.mode.lsu.alt_count_lsu_use +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.state_q.mode.lsu.alt_eew[1:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.state_q.mode.lsu.alt_emul[1:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.state_q.init_addr +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.state_q.unit[2:0] +@22 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.state_q.vl[6:0] +@28 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.state_q.vl_0 +@22 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.op_load[5:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.op_vaddr[0][4:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.op_vaddr[1][4:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.op_vaddr[2][4:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.op_vaddr[3][4:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.op_vaddr[4][4:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.op_vaddr[5][4:0] +@28 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.res_store +@22 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.vreg_pend_rd_o[31:0] +@1401200 +-pipeline +@c00200 +-Register +@22 +TOP.vproc_top.v_core.vregfile.rd_addr[0][0][4:0] +TOP.vproc_top.v_core.vregfile.rd_addr[1][0][4:0] +TOP.vproc_top.v_core.vregfile.rd_addr[2][0][4:0] +TOP.vproc_top.v_core.vregfile.rd_data[0][0][127:0] +TOP.vproc_top.v_core.vregfile.rd_data[1][0][127:0] +TOP.vproc_top.v_core.vregfile.rd_data[2][0][127:0] +TOP.vproc_top.v_core.vregfile.wr_addr_i[0][4:0] +TOP.vproc_top.v_core.vregfile.wr_be_i[0][15:0] +TOP.vproc_top.v_core.vregfile.wr_data_i[0][127:0] +@28 +TOP.vproc_top.v_core.vregfile.wr_we_i[0] +@1401200 +-Register +@800200 +-alu +@22 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.ALU_OP_W[31:0] +@200 +-input +@28 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.pipe_in_valid_i +@22 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.pipe_in_mask_i[3:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.pipe_in_op1_i[31:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.pipe_in_op2_i[31:0] +@200 +-ctrl_i +@28 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.pipe_in_ctrl_i.vl_0 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.pipe_in_ctrl_i.vl_part[1:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.pipe_in_ctrl_i.vl_part_0 +@200 +-output +@28 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.pipe_out_valid_o +@22 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.pipe_out_mask_o[3:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.pipe_out_res_cmp_o[3:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.pipe_out_res_alu_o[31:0] +@200 +-ctrl_o +@22 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.pipe_out_ctrl_o.res_vaddr[4:0] +@200 +-state_ex1_q +@28 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.state_ex1_q.vl_0 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.state_ex1_q.vl_part[1:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.state_ex1_q.vl_part_0 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.state_ex1_q.mode.alu.opx1.sel[1:0] +@200 +- +@22 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.operand2_9bpb[35:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.operand_mask_q[3:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.sum37[36:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.carry[3:0] +@28 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.state_ex1_subtract +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.pipe_out_ctrl_o.res_store +@22 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.ovflw[3:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.sig_op1[3:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.sig_op2[3:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.sig_res[3:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.operand_mask_tmp_q[3:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.vl_mask[3:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.cmp_d[3:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.cmp_q[3:0] +@28 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.pipe_in_ctrl_i.eew[1:0] +@c00200 +-ex1_q +@28 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.state_ex1_q.alt_count_valid +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.state_ex1_q.count_mul[2:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.state_ex1_q.eew[1:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.state_ex1_q.emul[1:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.state_ex1_q.first_cycle +@22 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.state_ex1_q.id[3:0] +@28 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.state_ex1_q.init_addr +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.state_ex1_q.last_cycle +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.state_ex1_q.last_vl_part +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.state_ex1_q.pend_load +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.state_ex1_q.pend_store +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.state_ex1_q.requires_flush +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.state_ex1_q.res_narrow[1:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.state_ex1_q.res_shift +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.state_ex1_q.res_store +@22 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.state_ex1_q.res_vaddr[4:0] +@28 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.state_ex1_q.unit[2:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.state_ex1_q.vl_0 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.state_ex1_q.vl_part_0 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.state_ex1_q.vxrm[1:0] +@22 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.state_ex1_q.xval[31:0] +@1401200 +-ex1_q +@c00200 +-ex2_q +@28 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.state_ex2_q.alt_count_valid +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.state_ex2_q.count_mul[2:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.state_ex2_q.eew[1:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.state_ex2_q.emul[1:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.state_ex2_q.first_cycle +@22 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.state_ex2_q.id[3:0] +@28 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.state_ex2_q.init_addr +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.state_ex2_q.last_cycle +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.state_ex2_q.last_vl_part +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.state_ex2_q.pend_load +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.state_ex2_q.pend_store +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.state_ex2_q.requires_flush +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.state_ex2_q.res_narrow[1:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.state_ex2_q.res_shift +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.state_ex2_q.res_store +@22 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.state_ex2_q.res_vaddr[4:0] +@28 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.state_ex2_q.unit[2:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.state_ex2_q.vl_0 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.state_ex2_q.vl_part_0 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.state_ex2_q.vxrm[1:0] +@22 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.state_ex2_q.xval[31:0] +@1401200 +-ex2_q +@c00200 +-res_q +@28 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.state_res_q.alt_count_valid +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.state_res_q.count_mul[2:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.state_res_q.eew[1:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.state_res_q.emul[1:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.state_res_q.first_cycle +@22 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.state_res_q.id[3:0] +@28 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.state_res_q.init_addr +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.state_res_q.last_cycle +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.state_res_q.last_vl_part +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.state_res_q.pend_load +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.state_res_q.pend_store +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.state_res_q.requires_flush +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.state_res_q.res_narrow[1:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.state_res_q.res_shift +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.state_res_q.res_store +@22 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.state_res_q.res_vaddr[4:0] +@28 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.state_res_q.unit[2:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.state_res_q.vl_0 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.state_res_q.vl_part_0 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.state_res_q.vxrm[1:0] +@22 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.state_res_q.xval[31:0] +@1401200 +-res_q +@28 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.pipe_in_ctrl_i.mode.alu.cmp +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.pipe_in_ctrl_i.mode.alu.inv_op1 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.pipe_in_ctrl_i.mode.alu.inv_op2 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.pipe_in_ctrl_i.mode.alu.op_mask[1:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.pipe_in_ctrl_i.mode.alu.sat_res +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.pipe_in_ctrl_i.mode.alu.shift_op +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.pipe_in_ctrl_i.mode.alu.sigext +@22 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.pipe_in_ctrl_i.mode.alu.unused[4:0] +@28 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.pipe_in_ctrl_i.mode.alu.opx1.sel[1:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.pipe_in_ctrl_i.mode.alu.opx1.shift[1:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.pipe_in_ctrl_i.mode.alu.opx2.cmp[2:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.pipe_in_ctrl_i.mode.alu.opx2.res[2:0] +@1000200 +-alu +@800200 +-pack +@28 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.pack.RES_MASK[1:0] +@22 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.pack.RES_W[0][31:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.pack.RES_W[1][31:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.pack.VPORT_W[31:0] +@28 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.pack.pipe_in_valid_i +@22 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.pack.pipe_in_res_data_i[0][31:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.pack.pipe_in_res_mask_i[0][31:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.pack.pipe_in_res_data_i[1][31:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.pack.pipe_in_res_mask_i[1][31:0] +@28 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.pack.instr_done_valid_o +@22 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.pack.pipe_in_res_flags_i[1].vreg_idx[4:0] +@28 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.pack.pipe_in_res_flags_i[1].mul_idx[2:0] +@22 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.pack.genblk1[1].genblk1.res_elem[3:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.pack.MSK_MUL[1][31:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.pack.msk_idx[1][6:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.pack.msk_idx_next[1][6:0] +@28 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.pack.pipe_in_res_store_i[1:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.pack.pipe_in_res_valid_i[1:0] +@22 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.pack.pipe_in_vaddr_i[4:0] +@28 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.pack.pipe_in_eew_i[1:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.pack.pipe_in_res_flags_i[1].mul_idx[2:0] +@22 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.pack.genblk1[1].genblk1.res_elem[3:0] +@28 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.pack.pipe_in_res_flags_i[1].first_cycle +@22 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.pack.msk_buffer[0][15:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.pack.msk_buffer_next[0][15:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.pack.msk_buffer[1][15:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.pack.msk_buffer_next[1][15:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.pack.res_buffer[0][127:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.pack.res_buffer_next[0][127:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.pack.res_buffer[1][127:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.pack.res_buffer_next[1][127:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.pack.vreg_wr_addr_o[4:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.pack.vreg_wr_be_o[15:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.pack.vreg_wr_data_o[127:0] +@28 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.pack.vreg_wr_valid_o +@1000200 +-pack +@c00200 +-unpack +@28 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unpack.OP_MASK[5:0] +@22 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unpack.op_buffer[4][127:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unpack.op_buffer_next[4][127:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unpack.op_buffer[5][127:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unpack.op_buffer_next[5][127:0] +@1401200 +-unpack +@c00200 +-elem +@28 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[6].genblk1.unit.genblk1.elem.pipe_in_valid_i +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[6].genblk1.unit.genblk1.elem.pipe_in_mask_i +@22 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[6].genblk1.unit.genblk1.elem.pipe_in_op1_i[31:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[6].genblk1.unit.genblk1.elem.pipe_in_op2_i[31:0] +@28 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[6].genblk1.unit.genblk1.elem.pipe_in_op2_mask_i +@200 +-pipe_in_ctrl_i +@22 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[6].genblk1.unit.genblk1.elem.pipe_in_ctrl_i.mode.elem.op[3:0] +@28 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[6].genblk1.unit.genblk1.elem.pipe_in_ctrl_i.vl_0 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[6].genblk1.unit.genblk1.elem.pipe_in_ctrl_i.vl_part[1:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[6].genblk1.unit.genblk1.elem.pipe_in_ctrl_i.vl_part_0 +@22 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[6].genblk1.unit.genblk1.elem.pipe_out_res_o[31:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[6].genblk1.unit.genblk1.elem.pipe_out_mask_o[3:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[6].genblk1.unit.genblk1.elem.pipe_out_xreg_data_o[31:0] +@28 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[6].genblk1.unit.genblk1.elem.pipe_out_res_valid_o +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[6].genblk1.unit.genblk1.elem.pipe_out_valid_o +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[6].genblk1.unit.genblk1.elem.pipe_out_ctrl_o.res_store +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[6].genblk1.unit.genblk1.elem.state_res_ready +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[6].genblk1.unit.genblk1.elem.state_res_valid_q +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[6].genblk1.unit.genblk1.elem.state_res_valid_d +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[6].genblk1.unit.genblk1.elem.pipe_in_ctrl_i.first_cycle +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[6].genblk1.unit.genblk1.elem.counter_inc +@22 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[6].genblk1.unit.genblk1.elem.counter_q[31:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[6].genblk1.unit.genblk1.elem.counter_d[31:0] +@28 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[6].genblk1.unit.genblk1.elem.mask_q +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[6].genblk1.unit.genblk1.elem.v0msk +@22 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[6].genblk1.unit.genblk1.elem.result_d[31:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[6].genblk1.unit.genblk1.elem.result_q[31:0] +@28 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[6].genblk1.unit.genblk1.elem.result_mask_q +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[6].genblk1.unit.genblk1.elem.result_mask_d +@1401200 +-elem +@800200 +-ram +@22 +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[0][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[1][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[2][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[3][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[4][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[5][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[6][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[7][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[8][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[9][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[10][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[11][127:0] +@23 +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[12][127:0] +@22 +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[13][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[14][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[15][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[16][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[17][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[18][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[19][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[20][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[21][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[22][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[23][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[24][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[25][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[26][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[27][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[28][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[29][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[30][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[31][127:0] +@1000200 +-ram +[pattern_trace] 1 +[pattern_trace] 0 From 49129b3419266dfaa8621c99aa83c2c540038854 Mon Sep 17 00:00:00 2001 From: Melvin John Date: Sun, 22 Mar 2026 19:17:41 +0100 Subject: [PATCH 04/18] Set env variable --- build_model/CMakeLists.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/build_model/CMakeLists.txt b/build_model/CMakeLists.txt index 841cde2..ba406e9 100644 --- a/build_model/CMakeLists.txt +++ b/build_model/CMakeLists.txt @@ -37,6 +37,7 @@ message("Selected SCALAR_CORE = ${SCALAR_CORE}") set(ENV{VPROC_PIPELINES} ${VPROC_PIPELINES}) message("Selected VPROC_PIPELINES = ${VPROC_PIPELINES}") message("Selected RISCV_ARCH = ${RISCV_ARCH}") +set(ENV{VREG_W} ${VREG_W}) message("Selected VREG_W = ${VREG_W}") set(MEM_W ${VMEM_W}) message("Selected MEM_W = ${MEM_W}") From e77e2ace1013506c207526df670703e553c8432a Mon Sep 17 00:00:00 2001 From: Melvin John Date: Wed, 25 Mar 2026 17:55:14 +0100 Subject: [PATCH 05/18] Made MEM_W configurable for unit tests --- CMake/add_test.cmake | 2 +- build_model/CMakeLists.txt | 1 + build_model/cv32e40x/vproc_top.sv | 2 +- build_tests/CMakeLists.txt | 1 + 4 files changed, 4 insertions(+), 2 deletions(-) diff --git a/CMake/add_test.cmake b/CMake/add_test.cmake index f4bcc82..312c125 100644 --- a/CMake/add_test.cmake +++ b/CMake/add_test.cmake @@ -45,7 +45,7 @@ macro(add_unit_test TEST_NAME) #Add Test add_test(NAME ${TEST_NAME} - COMMAND ${MODEL_DIR}/verilated_model ${BUILD_DIR}/vector-tests/prog_${TEST_NAME}.txt ${MEM_PORTS} 32 4194304 ${MEM_LATENCY} 1 ${TEST_NAME} ${VREG_W} ${TEST_CASE_NUM} ${VCD_TRACE_ARGS} + COMMAND ${MODEL_DIR}/verilated_model ${BUILD_DIR}/vector-tests/prog_${TEST_NAME}.txt ${MEM_PORTS} ${MEM_W} 4194304 ${MEM_LATENCY} 1 ${TEST_NAME} ${VREG_W} ${TEST_CASE_NUM} ${VCD_TRACE_ARGS} WORKING_DIRECTORY ${CMAKE_RUNTIME_OUTPUT_DIRECTORY}) message(STATUS "Successfully added ${TEST_NAME}") diff --git a/build_model/CMakeLists.txt b/build_model/CMakeLists.txt index ba406e9..e6c7622 100644 --- a/build_model/CMakeLists.txt +++ b/build_model/CMakeLists.txt @@ -40,6 +40,7 @@ message("Selected RISCV_ARCH = ${RISCV_ARCH}") set(ENV{VREG_W} ${VREG_W}) message("Selected VREG_W = ${VREG_W}") set(MEM_W ${VMEM_W}) +set(ENV{MEM_W} ${VMEM_W}) message("Selected MEM_W = ${MEM_W}") set(MEM_PORTS ${VMEM_PORTS}) message("Selected MEM_PORTS = ${MEM_PORTS}") diff --git a/build_model/cv32e40x/vproc_top.sv b/build_model/cv32e40x/vproc_top.sv index 19f8536..bfb517a 100644 --- a/build_model/cv32e40x/vproc_top.sv +++ b/build_model/cv32e40x/vproc_top.sv @@ -94,7 +94,7 @@ module vproc_top import vproc_pkg::*, obi_pkg::*; #( .X_MISA ( X_MISA ) ) vcore_xif (); - localparam OBI_CFG = obi_default_cfg(ADDR_W, MEM_W, OBI_ID_WIDTH, ObiMinimalOptionalConfig); + localparam OBI_CFG = obi_default_cfg(ADDR_W, VMEM_W, OBI_ID_WIDTH, ObiMinimalOptionalConfig); OBI_BUS #( .OBI_CFG ( OBI_CFG ) ) vcore_obi_bus [MEM_PORTS-1:0] (); diff --git a/build_tests/CMakeLists.txt b/build_tests/CMakeLists.txt index f6a555e..a025975 100644 --- a/build_tests/CMakeLists.txt +++ b/build_tests/CMakeLists.txt @@ -51,6 +51,7 @@ message("Selected RISCV_ARCH = ${RISCV_ARCH}") message("Selected VREG_W = ${VREG_W}") message("Selected VMEM_W = ${VMEM_W}") set(MEM_W ${VMEM_W}) +set(ENV{MEM_W} ${VMEM_W}) message("Selected MEM_W = ${MEM_W}") set(MEM_PORTS ${VMEM_PORTS}) message("Selected MEM_PORTS = ${MEM_PORTS}") From b52395469e874af4cecd35fe818364ab7f2e53e0 Mon Sep 17 00:00:00 2001 From: Melvin John Date: Fri, 10 Apr 2026 10:33:17 +0200 Subject: [PATCH 06/18] Default trace off --- build_model/CMakeLists.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/build_model/CMakeLists.txt b/build_model/CMakeLists.txt index e6c7622..9129bdf 100644 --- a/build_model/CMakeLists.txt +++ b/build_model/CMakeLists.txt @@ -25,8 +25,8 @@ set(CMAKE_VERBOSE_MAKEFILE ON) set(CMAKE_C_STANDARD 14) set(CMAKE_CXX_STANDARD 14) -option(TRACE "Enable minimal VCD trace outputs" ON) -option(TRACE_FULL "Enable FULL VCD trace outputs" ON) #TODO: prevent this option from being cached, force user to always manually enable it +option(TRACE "Enable minimal VCD trace outputs" OFF) +option(TRACE_FULL "Enable FULL VCD trace outputs" OFF) #TODO: prevent this option from being cached, force user to always manually enable it ######## ## Import RTL configuration from here instead of command line. From 4a1a1c798125b48cd156d0ce7e4511a73359ff81 Mon Sep 17 00:00:00 2001 From: Melvin John Date: Fri, 10 Apr 2026 10:33:45 +0200 Subject: [PATCH 07/18] Added waveforms --- bli.gtkw | 167 ++--- debug/wavefrom_debug_lsu_extension.gtkw | 884 ++++++++++++++++++++++++ 2 files changed, 969 insertions(+), 82 deletions(-) create mode 100644 debug/wavefrom_debug_lsu_extension.gtkw diff --git a/bli.gtkw b/bli.gtkw index aed8580..66d24ec 100644 --- a/bli.gtkw +++ b/bli.gtkw @@ -1,15 +1,15 @@ [*] [*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI -[*] Mon Mar 16 16:13:10 2026 +[*] Wed Mar 18 16:26:38 2026 [*] [dumpfile] "/home/vboxuser/Desktop/vicuna2_ros_verilator/programs/build/uros_etiss/test_uros_etiss_sig.vcd" -[dumpfile_mtime] "Mon Mar 16 16:11:10 2026" -[dumpfile_size] 456987779 +[dumpfile_mtime] "Wed Mar 18 16:02:32 2026" +[dumpfile_size] 5218658 [savefile] "/home/vboxuser/Desktop/vicuna2_unit_testing/bli.gtkw" -[timestart] 34367 +[timestart] 410562 [size] 1848 902 [pos] -1 -1 -*-4.839435 34375 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +*-5.839435 410638 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 [treeopen] TOP. [treeopen] TOP.vproc_top. [treeopen] TOP.vproc_top.v_core. @@ -17,18 +17,19 @@ [treeopen] TOP.vproc_top.v_core.genblk9[1].pipe. [treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2. [treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline. -[treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.pack. +[treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.op_count[0]. [treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.pack.genblk1[0].genblk1. [treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.pack.genblk1[1]. [treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.pack.genblk1[1].genblk1. [treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.pipe_in_state_i.mode. [treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.pipe_in_state_i.mode.alu. +[treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.state_q. +[treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.state_q.alt_count. +[treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.state_q.count. [treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.state_q.mode. [treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux. -[treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1]. [treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1. [treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit. -[treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1. [treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu. [treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.pipe_in_ctrl_i.mode.alu. [treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.state_ex1_q. @@ -42,6 +43,7 @@ [treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[5].genblk1. [treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[5].genblk1.unit. [treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[5].genblk1.unit.genblk1. +[treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[5].genblk1.unit.genblk1.sld. [treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[6]. [treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[6].genblk1. [treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[6].genblk1.unit. @@ -50,44 +52,105 @@ [treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[6].genblk1.unit.genblk1.elem.pipe_in_ctrl_i. [treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[6].genblk1.unit.genblk1.elem.pipe_in_ctrl_i.mode. [treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.pipe_in_ctrl_i. +[treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unpack. [treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.pipe_in_data_i. [treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.pipe_in_data_i.mode. [treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.pipe_in_data_i.mode.alu. +[treeopen] TOP.vproc_top.v_core.vregfile. [treeopen] TOP.vproc_top.v_core.vregfile.genblk1[0]. [treeopen] TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1. [treeopen] TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0]. +[treeopen] TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[1]. +[treeopen] TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[2]. [sst_width] 350 -[signals_width] 513 +[signals_width] 368 [sst_expanded] 1 -[sst_vpaned_height] 238 +[sst_vpaned_height] 249 @22 TOP.vproc_top.v_core.genblk9[1].pipe.OP_CNT[31:0] TOP.vproc_top.v_core.genblk9[1].pipe.RES_CNT[31:0] TOP.vproc_top.v_core.genblk9[1].pipe.MAX_OP_W[31:0] TOP.vproc_top.v_core.genblk9[1].pipe.MAX_RES_W[31:0] -@c00200 +@800200 +-decoder +@22 +TOP.vproc_top.v_core.dec.instr_i[31:0] +@28 +TOP.vproc_top.v_core.dec.instr_valid_i +@1000200 +-decoder +@800200 +-pipeline_wrapper +@28 +TOP.vproc_top.v_core.genblk9[1].pipe.unit_alu +TOP.vproc_top.v_core.genblk9[1].pipe.unit_div +TOP.vproc_top.v_core.genblk9[1].pipe.unit_elem +TOP.vproc_top.v_core.genblk9[1].pipe.unit_fpu +TOP.vproc_top.v_core.genblk9[1].pipe.unit_lsu +TOP.vproc_top.v_core.genblk9[1].pipe.unit_mul +@29 +TOP.vproc_top.v_core.genblk9[1].pipe.unit_sld +@1000200 +-pipeline_wrapper +@800200 +-pipeline_instr_state +@28 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.instr_state_i[0][1:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.instr_state_i[1][1:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.instr_state_i[2][1:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.instr_state_i[3][1:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.instr_state_i[4][1:0] +@22 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.state_q.id[3:0] +@28 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.state_valid_q +@22 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.state_next.id[3:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.instr_done_id_o[3:0] +@28 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.instr_done_valid_o +@1000200 +-pipeline_instr_state +@28 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[5].genblk1.unit.genblk1.unit_out_ctrl.alt_last_cycle +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[5].genblk1.unit.pipe_in_ctrl_i.alt_last_cycle +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[5].genblk1.unit.genblk1.sld.pipe_in_ctrl_i.alt_last_cycle +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[5].genblk1.unit.genblk1.sld.state_ex_d.alt_last_cycle +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[5].genblk1.unit.genblk1.sld.state_ex_valid_d +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unpack.pipe_out_valid_o +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unpack.stage_valid_q[4:0] +@22 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unpack.stage_valid_d[4:0] +@28 +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[6].genblk1.unit.pipe_out_ready_i +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[6].genblk1.unit.pipe_in_ready_o +@800200 -pipeline @28 TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.pipe_in_ready_o TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.pipe_in_valid_i -TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.pipe_in_state_i.mode.alu.opx2.cmp[2:0] -TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.pipe_in_state_i.mode.alu.opx2.res[2:0] +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.state_ready +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.state_done +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.state_valid_q +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unpack_valid +@200 +-count @22 TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.state_q.count.val[7:0] -TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.state_q.count.part.low[3:0] @28 TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.state_q.count.part.mul[2:0] -TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.state_q.count.part.sign +@200 +-alt_count @22 TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.state_q.alt_count.val[7:0] -TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.state_q.alt_count.part.low[3:0] @28 TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.state_q.alt_count.part.mul[2:0] -TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.state_q.alt_count.part.sign TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.state_q.count_inc[1:0] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.state_q.alt_count_inc[1:0] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.state_q.alt_last_cycle TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.state_q.last_cycle +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.state_wait_alt_count_q +TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.wait_alt_count_next TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.state_q.eew[1:0] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.state_q.emul[1:0] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.state_q.mode.lsu.alt_count_lsu_use @@ -95,9 +158,6 @@ TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.state_q.mode.lsu.alt_eew[1 TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.state_q.mode.lsu.alt_emul[1:0] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.state_q.init_addr TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.state_q.unit[2:0] -@22 -TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.state_q.vl[6:0] -@28 TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.state_q.vl_0 @22 TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.op_load[5:0] @@ -111,25 +171,20 @@ TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.op_vaddr[5][4:0] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.res_store @22 TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.vreg_pend_rd_o[31:0] -@1401200 +@1000200 -pipeline -@c00200 +@800200 -Register @22 TOP.vproc_top.v_core.vregfile.rd_addr[0][0][4:0] TOP.vproc_top.v_core.vregfile.rd_addr[1][0][4:0] TOP.vproc_top.v_core.vregfile.rd_addr[2][0][4:0] -TOP.vproc_top.v_core.vregfile.rd_data[0][0][127:0] -TOP.vproc_top.v_core.vregfile.rd_data[1][0][127:0] -TOP.vproc_top.v_core.vregfile.rd_data[2][0][127:0] TOP.vproc_top.v_core.vregfile.wr_addr_i[0][4:0] -TOP.vproc_top.v_core.vregfile.wr_be_i[0][15:0] -TOP.vproc_top.v_core.vregfile.wr_data_i[0][127:0] @28 TOP.vproc_top.v_core.vregfile.wr_we_i[0] -@1401200 +@1000200 -Register -@800200 +@c00200 -alu @22 TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.ALU_OP_W[31:0] @@ -295,7 +350,7 @@ TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.pipe_in_ctrl_i.mode.alu.opx1.shift[1:0] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.pipe_in_ctrl_i.mode.alu.opx2.cmp[2:0] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[1].genblk1.unit.genblk1.alu.pipe_in_ctrl_i.mode.alu.opx2.res[2:0] -@1000200 +@1401200 -alu @800200 -pack @@ -321,8 +376,6 @@ TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.pack.pipe_in_res_flags_i[1 @22 TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.pack.genblk1[1].genblk1.res_elem[3:0] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.pack.MSK_MUL[1][31:0] -TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.pack.msk_idx[1][6:0] -TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.pack.msk_idx_next[1][6:0] @28 TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.pack.pipe_in_res_store_i[1:0] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.pack.pipe_in_res_valid_i[1:0] @@ -336,17 +389,7 @@ TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.pack.genblk1[1].genblk1.re @28 TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.pack.pipe_in_res_flags_i[1].first_cycle @22 -TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.pack.msk_buffer[0][15:0] -TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.pack.msk_buffer_next[0][15:0] -TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.pack.msk_buffer[1][15:0] -TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.pack.msk_buffer_next[1][15:0] -TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.pack.res_buffer[0][127:0] -TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.pack.res_buffer_next[0][127:0] -TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.pack.res_buffer[1][127:0] -TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.pack.res_buffer_next[1][127:0] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.pack.vreg_wr_addr_o[4:0] -TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.pack.vreg_wr_be_o[15:0] -TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.pack.vreg_wr_data_o[127:0] @28 TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.pack.vreg_wr_valid_o @1000200 @@ -355,11 +398,6 @@ TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.pack.vreg_wr_valid_o -unpack @28 TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unpack.OP_MASK[5:0] -@22 -TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unpack.op_buffer[4][127:0] -TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unpack.op_buffer_next[4][127:0] -TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unpack.op_buffer[5][127:0] -TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unpack.op_buffer_next[5][127:0] @1401200 -unpack @c00200 @@ -409,41 +447,6 @@ TOP.vproc_top.v_core.genblk9[1].pipe.genblk2.pipeline.unit_mux.genblk1[6].genblk -elem @800200 -ram -@22 -TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[0][127:0] -TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[1][127:0] -TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[2][127:0] -TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[3][127:0] -TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[4][127:0] -TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[5][127:0] -TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[6][127:0] -TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[7][127:0] -TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[8][127:0] -TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[9][127:0] -TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[10][127:0] -TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[11][127:0] -@23 -TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[12][127:0] -@22 -TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[13][127:0] -TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[14][127:0] -TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[15][127:0] -TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[16][127:0] -TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[17][127:0] -TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[18][127:0] -TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[19][127:0] -TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[20][127:0] -TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[21][127:0] -TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[22][127:0] -TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[23][127:0] -TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[24][127:0] -TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[25][127:0] -TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[26][127:0] -TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[27][127:0] -TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[28][127:0] -TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[29][127:0] -TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[30][127:0] -TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[31][127:0] @1000200 -ram [pattern_trace] 1 diff --git a/debug/wavefrom_debug_lsu_extension.gtkw b/debug/wavefrom_debug_lsu_extension.gtkw new file mode 100644 index 0000000..1d793bc --- /dev/null +++ b/debug/wavefrom_debug_lsu_extension.gtkw @@ -0,0 +1,884 @@ +[*] +[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI +[*] Wed Feb 25 22:32:40 2026 +[*] +[dumpfile] "/home/vboxuser/Desktop/vicuna2_unit_testing/debug/working.vcd" +[dumpfile_mtime] "Wed Feb 25 14:38:29 2026" +[dumpfile_size] 74691196 +[savefile] "/home/vboxuser/Desktop/vicuna2_unit_testing/debug/wavefrom_debug_lsu_extension.gtkw" +[timestart] 42057 +[size] 1848 902 +[pos] -1 -1 +*-5.945512 42145 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[treeopen] TOP. +[treeopen] TOP.vproc_top. +[treeopen] TOP.vproc_top.v_core. +[treeopen] TOP.vproc_top.v_core.dec.mode_o. +[treeopen] TOP.vproc_top.v_core.dec_data_q.mode. +[treeopen] TOP.vproc_top.v_core.genblk9[0]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.alt_count_next_inc. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.count_next_inc. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.genblk1[0]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.genblk1[0].genblk1. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pipe_in_state_i.mode. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_next.alt_count. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_next.count. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_next.mode. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_q.alt_count. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_q.count. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_q.mode. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ctrl_i.mode. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_out_ctrl_o. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.xif_mem_if. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk4[0]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk6[2]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[0]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[0].genblk1[0]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[1]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[1].genblk1[0]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[2]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[2].genblk1[0]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[3]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[3].genblk1[0]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[4]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[4].genblk1[0]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack_out_ctrl.mode. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.pipe_in_data_i.mode. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.state_init.mode. +[treeopen] TOP.vproc_top.v_core.genblk9[1].pipe. +[treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2. +[treeopen] TOP.vproc_top.v_core.pipe_instr_data.mode. +[treeopen] TOP.vproc_top.v_core.queue_data_d.mode. +[treeopen] TOP.vproc_top.v_core.queue_data_q.mode. +[treeopen] TOP.vproc_top.v_core.queue_pending_wr.mode_i.alu. +[treeopen] TOP.vproc_top.v_core.vregfile.genblk1[0]. +[treeopen] TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1. +[treeopen] TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0]. +[treeopen] TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[1]. +[sst_width] 379 +[signals_width] 546 +[sst_expanded] 1 +[sst_vpaned_height] 160 +@28 +TOP.vproc_top.clk_i +@800200 +-lsu +@200 +-lsu +-input +@28 +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_valid_i +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ready_o +@22 +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.vreg_pend_rd_i[31:0] +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_op1_i[31:0] +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_op2_i[31:0] +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_mask_i[3:0] +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.vreg_pend_rd_i[31:0] +@200 +-output +@28 +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pending_load_o +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pending_store_o +@22 +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_out_res_o[31:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_out_mask_o[3:0] +@28 +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_out_valid_o +[color] 7 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+TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.pipe_in_res_mask_i[1][31:0] +@28 +[color] 6 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.pipe_in_instr_done_i +[color] 6 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.pipe_in_pend_clr_cnt_i[1:0] +[color] 6 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.pipe_in_pend_clr_i +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.pipe_in_eew_i[1:0] +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.pipe_in_res_valid_i[7:0] +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.pipe_in_res_flags_i[0].elemwise +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.pipe_in_res_flags_i[0].shift +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.pipe_in_res_flags_i[1].elemwise +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.pipe_in_res_flags_i[1].shift +@200 +-output +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.instr_done_id_o[3:0] +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.instr_done_valid_o +@22 +[color] 6 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.vreg_wr_be_o[15:0] +@28 +[color] 6 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.vreg_wr_clr_o +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.vreg_wr_valid_o +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.vreg_wr_be_o[15:0] +[color] 6 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.vreg_wr_addr_o[4:0] +@28 +[color] 6 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.vreg_wr_clr_cnt_o[1:0] +@22 +[color] 6 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.vreg_wr_data_o[127:0] +@28 +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.stage_ready +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.stage_stall +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.stage_valid_q +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.stage_state_q.pend_clr +@22 +[color] 6 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.res_buffer[0][127:0] +[color] 6 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.res_buffer_next[0][127:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.res_buffer[1][127:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.res_buffer_next[1][127:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.msk_buffer[0][15:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.msk_buffer_next[0][15:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.genblk1[0].genblk1.msk_default[3:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.genblk1[0].genblk1.res_default[31:0] +@28 +[color] 6 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.vreg_wr_ready_i +@1401200 +-pack +@c00200 +-unit_wrapper +@200 +-Unit_wrapper +@22 +[color] 1 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.pipe_out_vaddr_o[4:0] +[color] 1 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.unit_out_ctrl.res_vaddr[4:0] +@28 +[color] 1 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.vreg_wr_valid_o +@1401200 +-unit_wrapper +@c00200 +-core +@200 +-core +@28 +TOP.vproc_top.v_core.dec_data_q.mode.cfg.lmul[2:0] +TOP.vproc_top.v_core.instr_state_q[0][1:0] +TOP.vproc_top.v_core.instr_state_q[1][1:0] +TOP.vproc_top.v_core.instr_state_q[2][1:0] +TOP.vproc_top.v_core.instr_state_q[3][1:0] +TOP.vproc_top.v_core.instr_state_q[4][1:0] +TOP.vproc_top.v_core.instr_state_q[5][1:0] +TOP.vproc_top.v_core.instr_state_q[6][1:0] +TOP.vproc_top.v_core.instr_state_q[7][1:0] +TOP.vproc_top.v_core.instr_state_q[8][1:0] +TOP.vproc_top.v_core.instr_state_q[9][1:0] +TOP.vproc_top.v_core.instr_state_q[10][1:0] +TOP.vproc_top.v_core.instr_state_q[11][1:0] +TOP.vproc_top.v_core.instr_state_q[12][1:0] +TOP.vproc_top.v_core.instr_state_q[13][1:0] +TOP.vproc_top.v_core.instr_state_q[14][1:0] +TOP.vproc_top.v_core.instr_state_q[15][1:0] +@22 +TOP.vproc_top.v_core.instr_complete_id[0][3:0] +@28 +TOP.vproc_top.v_core.pipe_instr_valid[1:0] +@22 +TOP.vproc_top.v_core.instr_complete_id[1][3:0] +@28 +TOP.vproc_top.v_core.instr_complete_valid[1:0] +@200 +-queue_data_d +@28 +TOP.vproc_top.v_core.queue_data_d.mode.lsu.nfields[2:0] +@200 +-queue_data_q +@28 +TOP.vproc_top.v_core.queue_data_q.mode.lsu.nfields[2:0] +@1401200 +-core +@c00200 +-unit_mux +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.clk_i +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.unit_queue_enq_ready +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.unit_queue_deq_valid +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.unit_queue_enq_valid +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.unit_queue_deq_unit[2:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.unit_queue_deq_unit_vector[2:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.pipe_out_valid_o +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.pipe_out_ready_i +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.pipe_out_instr_done_o +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.unit_out_instr_done[6:0] +@1401200 +-unit_mux +@22 +TOP.vproc_top.host_xif.issue_req.rs[0][31:0] +TOP.vproc_top.host_xif.issue_req.rs[1][31:0] +TOP.vproc_top.host_xif.issue_req.rs[2][31:0] +TOP.vproc_top.host_xif.issue_req.instr[31:0] +[pattern_trace] 1 +[pattern_trace] 0 +!100000@@ +?"B533 +@23 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.xif_mem_if.mem_req.addr[31:0] +!! From 037354b10a1c3f6f0768a3d38985997e4f3cbd79 Mon Sep 17 00:00:00 2001 From: Melvin John Date: Sat, 11 Apr 2026 17:09:41 +0200 Subject: [PATCH 08/18] Turned flag for aligned reads off --- build_model/cv32e40x/vproc_top.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/build_model/cv32e40x/vproc_top.sv b/build_model/cv32e40x/vproc_top.sv index bfb517a..50debb7 100644 --- a/build_model/cv32e40x/vproc_top.sv +++ b/build_model/cv32e40x/vproc_top.sv @@ -316,7 +316,7 @@ module vproc_top import vproc_pkg::*, obi_pkg::*; #( // Allow for vector loads/stores to be misaligned with respect to VMEM_W `ifdef FORCE_ALIGNED_READS - localparam bit [VLSU_FLAGS_W-1:0] VLSU_FLAGS = (VLSU_FLAGS_W'(1) << VLSU_ALIGNED_UNITSTRIDE); + localparam bit [VLSU_FLAGS_W-1:0] VLSU_FLAGS = (VLSU_FLAGS_W'(0) << VLSU_ALIGNED_UNITSTRIDE); `else localparam bit [VLSU_FLAGS_W-1:0] VLSU_FLAGS = (VLSU_FLAGS_W'(0) << VLSU_ALIGNED_UNITSTRIDE); `endif From 9505aeffd468b91d2b28ef8dcf1e4de8c8ea5968 Mon Sep 17 00:00:00 2001 From: Melvin John Date: Sun, 12 Apr 2026 21:58:25 +0200 Subject: [PATCH 09/18] Added waveform file --- build_model/vector_config.cmake | 2 +- wavefrom_debug_lsu_extension.gtkw | 71 +- wavefrom_debug_lsu_extension_test.gtkw | 1110 ++++++++++++++++++++++++ 3 files changed, 1153 insertions(+), 30 deletions(-) create mode 100644 wavefrom_debug_lsu_extension_test.gtkw diff --git a/build_model/vector_config.cmake b/build_model/vector_config.cmake index 6500fe6..20e44a3 100644 --- a/build_model/vector_config.cmake +++ b/build_model/vector_config.cmake @@ -8,7 +8,7 @@ set(RISCV_ARCH rv32im_zve32x CACHE STRING "Specify the configuration") #Currently Supported: cv32e40x, cv32a60x set(SCALAR_CORE "cv32e40x") -set(VMEM_PORTS 4) +set(VMEM_PORTS 1) set(VMEM_W 32) set(VREG_W 128) set(VPROC_PIPELINES "${VMEM_W}:VLSU 32:VELEM,VSLD,VDIV,VALU,VMUL") diff --git a/wavefrom_debug_lsu_extension.gtkw b/wavefrom_debug_lsu_extension.gtkw index 6bc559c..d17462c 100644 --- a/wavefrom_debug_lsu_extension.gtkw +++ b/wavefrom_debug_lsu_extension.gtkw @@ -1,20 +1,21 @@ [*] [*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI -[*] Tue Mar 10 20:21:26 2026 +[*] Sun Apr 12 16:41:46 2026 [*] -[dumpfile] "/home/vboxuser/Desktop/vicuna2_ros_verilator/programs/build/uros_etiss/test_uros_etiss_sig.vcd" -[dumpfile_mtime] "Tue Mar 10 20:21:15 2026" -[dumpfile_size] 174620672 +[dumpfile] "/home/vboxuser/Desktop/vicuna2_unit_testing/build_tests/build/Testing/last_test_sig.vcd" +[dumpfile_mtime] "Sun Apr 12 16:41:34 2026" +[dumpfile_size] 224004395 [savefile] "/home/vboxuser/Desktop/vicuna2_unit_testing/wavefrom_debug_lsu_extension.gtkw" -[timestart] 29396 +[timestart] 466 [size] 1848 902 [pos] -1 -1 -*-5.945512 29497 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +*-4.945512 530 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 [treeopen] TOP. [treeopen] TOP.vproc_top. [treeopen] TOP.vproc_top.v_core. [treeopen] TOP.vproc_top.v_core.dec.mode_o. [treeopen] TOP.vproc_top.v_core.dec_data_q.mode. +[treeopen] TOP.vproc_top.v_core.genblk9[0]. [treeopen] TOP.vproc_top.v_core.genblk9[0].pipe. [treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2. [treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline. @@ -71,7 +72,7 @@ [sst_width] 379 [signals_width] 646 [sst_expanded] 1 -[sst_vpaned_height] 259 +[sst_vpaned_height] 271 @28 TOP.vproc_top.clk_i @800200 @@ -214,9 +215,7 @@ TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[0][127:0] TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[1][127:0] TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[2][127:0] TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[3][127:0] -@23 TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[4][127:0] -@22 TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[5][127:0] TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[6][127:0] TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[7][127:0] @@ -256,20 +255,18 @@ TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk @28 TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_state_q.current_eew[1:0] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_state_q.fsm_state[2:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_state_q.outstanding_mem_req_cnt[2:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_state_q.pending_load_state_cb[2:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_state_q.pending_store_state_cb[2:0] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_state_q.store_end_index[0] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_state_q.write_index[0] +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_state_q.misalignment_data[31:0] +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_state_q.misalignment_request @200 -scratch_state_d @28 TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_state_d.fsm_state[2:0] @200 -port_state_q -@28 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.port_state_q.portq_elem_cnt[0][0] -@200 -scratch_memory @28 TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_memory_state_q[0][1:0] @@ -290,6 +287,14 @@ TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk @22 TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_memory_q[1].wmask[3:0] @200 +-scratch_memory_d +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_memory_state_d[0][1:0] +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_memory_d[0].data[31:0] +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_memory_d[0].pending_req_cnt[2:0] +@200 -scratch_pending @28 TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_hit @@ -309,6 +314,7 @@ TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_queue_pending_data_off_out[1:0] #{scratch_queue_pending_index_out[1:0]} TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_queue_pending_index_out[0] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_queue_pending_out +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.misalignment_request_out @200 -input_queue @28 @@ -331,6 +337,10 @@ TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.mem_req_switch @200 -port_queue +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.port_queue_ready_out[0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.port_queue_valid_out[0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.port_queue_ready_in[0] @22 TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.port_queue_rdata_out[0][31:0] @28 @@ -342,9 +352,25 @@ TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk -vtop @28 TOP.vproc_top.clk_i +TOP.vproc_top.vdata_req[0] TOP.vproc_top.vdata_gnt[0] TOP.vproc_top.data_rvalid[0] TOP.vproc_top.vdata_rvalid[0] +TOP.vproc_top.mem_req_o[0] +TOP.vproc_top.mem_rvalid_i[0] +@22 +TOP.vproc_top.mem_addr_o[0][31:0] +TOP.vproc_top.mem_be_o[0][3:0] +@28 +TOP.vproc_top.mem_we_o[0] +@22 +TOP.vproc_top.mem_wdata_o[0][31:0] +TOP.vproc_top.mem_rdata_i[0][31:0] +@28 +TOP.vproc_top.sdata_req +TOP.vproc_top.sdata_rvalid +@22 +TOP.vproc_top.sdata_rdata[31:0] @200 -obi_port_0 @28 @@ -362,20 +388,6 @@ TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[0].wdata[31:0] @200 -obi_port_1 -@28 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[1].req -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[1].gnt -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[1].rvalid -@22 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[1].addr[31:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[1].be[3:0] -@28 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[1].we -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[1].err -@22 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[1].rdata[31:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[1].wdata[31:0] -@200 -obi_port_2 -state_req_red_i @22 @@ -415,6 +427,7 @@ TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.deq_state.field_counter[2:0] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.deq_state.field_init_count[2:0] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.deq_state.suppressed +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_rdata_valid_q TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_rdata_valid_d @22 TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.rdata_buf_q[31:0] diff --git a/wavefrom_debug_lsu_extension_test.gtkw b/wavefrom_debug_lsu_extension_test.gtkw new file mode 100644 index 0000000..94620af --- /dev/null +++ b/wavefrom_debug_lsu_extension_test.gtkw @@ -0,0 +1,1110 @@ +[*] +[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI +[*] Sun Apr 12 16:52:47 2026 +[*] +[dumpfile] "/home/vboxuser/Desktop/vicuna2_unit_testing/build_tests/build/Testing/last_test_sig.vcd" +[dumpfile_mtime] "Sun Apr 12 16:41:34 2026" +[dumpfile_size] 224004395 +[savefile] "/home/vboxuser/Desktop/vicuna2_unit_testing/wavefrom_debug_lsu_extension_test.gtkw" +[timestart] 690 +[size] 1848 902 +[pos] -1 -1 +*-4.945512 719 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[treeopen] TOP. +[treeopen] TOP.vproc_top. +[treeopen] TOP.vproc_top.core. +[treeopen] TOP.vproc_top.core.register_file_wrapper_i. +[treeopen] TOP.vproc_top.v_core. +[treeopen] TOP.vproc_top.v_core.dec.mode_o. +[treeopen] TOP.vproc_top.v_core.dec_data_q.mode. +[treeopen] TOP.vproc_top.v_core.genblk9[0]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.alt_count_next_inc. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.count_next_inc. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.genblk1[0]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.genblk1[0].genblk1. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pipe_in_state_i.mode. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_next.alt_count. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_next.count. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_next.mode. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_q.alt_count. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_q.count. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_q.mode. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.genblk3[0]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_red. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ctrl_i.mode. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_out_ctrl_o. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk4[0]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk6[2]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[0]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[0].genblk1[0]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[1]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[1].genblk1[0]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[2]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[2].genblk1[0]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[3]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[3].genblk1[0]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[4]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[4].genblk1[0]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack_out_ctrl.mode. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.pipe_in_data_i.mode. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.state_init.mode. +[treeopen] TOP.vproc_top.v_core.genblk9[1].pipe. +[treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2. +[treeopen] TOP.vproc_top.v_core.pipe_instr_data.mode. +[treeopen] TOP.vproc_top.v_core.queue_data_d.mode. +[treeopen] TOP.vproc_top.v_core.queue_data_q.mode. +[treeopen] TOP.vproc_top.v_core.queue_pending_wr.mode_i.alu. +[treeopen] TOP.vproc_top.v_core.vregfile. +[treeopen] TOP.vproc_top.v_core.vregfile.genblk1[0]. +[treeopen] TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1. +[treeopen] TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0]. +[treeopen] TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[1]. +[treeopen] TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[2]. +[sst_width] 379 +[signals_width] 646 +[sst_expanded] 1 +[sst_vpaned_height] 271 +@28 +TOP.vproc_top.clk_i +@800200 +-lsu +@200 +-lsu +-input +@28 +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_valid_i +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ready_o +@22 +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.vreg_pend_rd_i[31:0] +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_op1_i[31:0] +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_op2_i[31:0] +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_mask_i[3:0] +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.vreg_pend_rd_i[31:0] +@200 +-output +@28 +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pending_load_o +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pending_store_o +@22 +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_out_res_o[31:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_out_mask_o[3:0] +@28 +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_out_valid_o +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_out_pend_clr_o +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_out_ctrl_o.res_store +@200 +-general +@28 +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ctrl_i.mode.lsu.nfields[2:0] +@100000028 +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ctrl_i.mode.lsu.eew[1:0] +@28 +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ctrl_i.mode.lsu.masked +@100000028 +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ctrl_i.mode.lsu.stride[1:0] +@22 +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ctrl_i.xval[31:0] +@28 +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.trans_complete_valid_o +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ctrl_i.init_addr +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ctrl_i.vl_0 +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ctrl_i.mode.lsu.alt_count_lsu_use +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ctrl_i.mode.lsu.alt_eew[1:0] +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ctrl_i.mode.lsu.alt_emul[1:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.VLSU_FLAGS[0] +@200 +-read +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.req_addr_q[0][31:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.req_addr_q[1][31:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.req_addr_q[2][31:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.req_addr_q[3][31:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.req_addr_q[4][31:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.req_addr_q[5][31:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.req_addr_q[6][31:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.req_addr_q[7][31:0] +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.rdata_unit_vl_mask[3:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.rdata_unit_vdmsk[3:0] +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.rdata_stri_vdmsk +@200 +-write +@22 +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.wdata_buf_q[31:0] +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.wmask_buf_q[3:0] +@28 +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.wdata_stri_mask +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.req_suppress +@200 +-state_rdata_q +-pipe_out_ctrl_o +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_out_ctrl_o.res_vaddr[4:0] +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_out_ctrl_o.first_cycle +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_out_ctrl_o.last_cycle +@1000200 +-lsu +@800200 +-registers +@200 +-registers +@22 +[color] 5 +TOP.vproc_top.v_core.csr_vl_o[31:0] +[color] 5 +TOP.vproc_top.v_core.vregfile.rd_addr_i[0][4:0] +[color] 5 +TOP.vproc_top.v_core.vregfile.rd_addr_i[1][4:0] +[color] 5 +TOP.vproc_top.v_core.vregfile.rd_data_o[0][127:0] +[color] 5 +TOP.vproc_top.v_core.vregfile.rd_data_o[1][127:0] +@28 +[color] 5 +TOP.vproc_top.v_core.vregfile.wr_we_i[0] +@22 +[color] 5 +TOP.vproc_top.v_core.vregfile.wr_be_i[0][15:0] +[color] 5 +TOP.vproc_top.v_core.vregfile.wr_addr_i[0][4:0] +[color] 5 +TOP.vproc_top.v_core.vregfile.wr_data_i[0][127:0] +@800200 +-RAM +@200 +-ram +@22 +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[0][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[1][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[2][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[3][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[4][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[5][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[6][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[7][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[8][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[9][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[10][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[11][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[12][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[13][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[14][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[15][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[16][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[17][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[18][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[19][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[20][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[21][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[22][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[23][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[24][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[25][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[26][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[27][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[28][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[29][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[30][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[31][127:0] +@1000200 +-RAM +-registers +@800200 +-lsu_extension +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.clk_i +@200 +-scratch_state_q +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_state_q.current_eew[1:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_state_q.fsm_state[2:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_state_q.store_end_index[0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_state_q.write_index[0] +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_state_q.misalignment_data[31:0] +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_state_q.misalignment_request +@200 +-scratch_state_d +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_state_d.fsm_state[2:0] +@200 +-port_state_q +-scratch_memory +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_memory_state_q[0][1:0] +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_memory_q[0].addr[31:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_memory_q[0].data[31:0] +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_memory_q[0].pending_req_cnt[2:0] +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_memory_q[0].wmask[3:0] +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_memory_state_q[1][1:0] +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_memory_q[1].addr[31:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_memory_q[1].data[31:0] +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_memory_q[1].pending_req_cnt[2:0] +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_memory_q[1].wmask[3:0] +@200 +-scratch_memory_d +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_memory_state_d[0][1:0] +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_memory_d[0].data[31:0] +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_memory_d[0].pending_req_cnt[2:0] +@200 +-scratch_pending +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_hit +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_hit_data[31:0] +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_pending +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_pending_data_off[1:0] +#{scratch_pending_index[1:0]} TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_pending_index[0] +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_pending_output[31:0] +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_pending_req_cleared +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_queue_data_out[31:0] +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_queue_pending_data_off_out[1:0] +#{scratch_queue_pending_index_out[1:0]} TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_queue_pending_index_out[0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_queue_pending_out +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.misalignment_request_out +@200 +-input_queue +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.input_queue.empty +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.input_queue_ready_in +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.input_queue_ready_out +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.input_queue_valid_out +@200 +-output_queue +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.output_queue_ready_in +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.output_queue_ready_out +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.output_queue_valid_out +@200 +-mem_req_queue +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.mem_req_queue_ready_out +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.mem_req_queue_valid_in +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.mem_req_queue_valid_out +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.mem_req_switch +@200 +-port_queue +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.port_queue_ready_out[0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.port_queue_valid_out[0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.port_queue_ready_in[0] +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.port_queue_rdata_out[0][31:0] +@28 +#{port_queue_write_index_out[0][1:0]} TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.port_queue_write_index_out[0][0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.genblk3[0].port_queue.enq_valid_i +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.genblk3[0].port_write_index_queue.enq_valid_i +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.genblk3[0].port_write_index_queue.enq_ready_o +@200 +-vtop +@28 +TOP.vproc_top.clk_i +TOP.vproc_top.vdata_req[0] +TOP.vproc_top.vdata_gnt[0] +TOP.vproc_top.data_rvalid[0] +TOP.vproc_top.vdata_rvalid[0] +TOP.vproc_top.mem_req_o[0] +TOP.vproc_top.mem_rvalid_i[0] +@22 +TOP.vproc_top.mem_addr_o[0][31:0] +TOP.vproc_top.mem_be_o[0][3:0] +@28 +TOP.vproc_top.mem_we_o[0] +@22 +TOP.vproc_top.mem_wdata_o[0][31:0] +TOP.vproc_top.mem_rdata_i[0][31:0] +@28 +TOP.vproc_top.sdata_req +TOP.vproc_top.sdata_rvalid +@22 +TOP.vproc_top.sdata_rdata[31:0] +TOP.vproc_top.core.register_file_wrapper_i.register_file_i.mem[0][31:0] +TOP.vproc_top.core.register_file_wrapper_i.register_file_i.mem[1][31:0] +TOP.vproc_top.core.register_file_wrapper_i.register_file_i.mem[2][31:0] +TOP.vproc_top.core.register_file_wrapper_i.register_file_i.mem[3][31:0] +TOP.vproc_top.core.register_file_wrapper_i.register_file_i.mem[4][31:0] +TOP.vproc_top.core.register_file_wrapper_i.register_file_i.mem[5][31:0] +TOP.vproc_top.core.register_file_wrapper_i.register_file_i.mem[6][31:0] +TOP.vproc_top.core.register_file_wrapper_i.register_file_i.mem[7][31:0] +TOP.vproc_top.core.register_file_wrapper_i.register_file_i.mem[8][31:0] +TOP.vproc_top.core.register_file_wrapper_i.register_file_i.mem[9][31:0] +@23 +TOP.vproc_top.core.register_file_wrapper_i.register_file_i.mem[10][31:0] +@22 +TOP.vproc_top.core.register_file_wrapper_i.register_file_i.mem[11][31:0] +TOP.vproc_top.core.register_file_wrapper_i.register_file_i.mem[12][31:0] +TOP.vproc_top.core.register_file_wrapper_i.register_file_i.mem[13][31:0] +TOP.vproc_top.core.register_file_wrapper_i.register_file_i.mem[14][31:0] +TOP.vproc_top.core.register_file_wrapper_i.register_file_i.mem[15][31:0] +TOP.vproc_top.core.register_file_wrapper_i.register_file_i.mem[16][31:0] +TOP.vproc_top.core.register_file_wrapper_i.register_file_i.mem[17][31:0] +TOP.vproc_top.core.register_file_wrapper_i.register_file_i.mem[18][31:0] +TOP.vproc_top.core.register_file_wrapper_i.register_file_i.mem[19][31:0] +TOP.vproc_top.core.register_file_wrapper_i.register_file_i.mem[20][31:0] +TOP.vproc_top.core.register_file_wrapper_i.register_file_i.mem[21][31:0] +TOP.vproc_top.core.register_file_wrapper_i.register_file_i.mem[22][31:0] +TOP.vproc_top.core.register_file_wrapper_i.register_file_i.mem[23][31:0] +TOP.vproc_top.core.register_file_wrapper_i.register_file_i.mem[24][31:0] +TOP.vproc_top.core.register_file_wrapper_i.register_file_i.mem[25][31:0] +TOP.vproc_top.core.register_file_wrapper_i.register_file_i.mem[26][31:0] +TOP.vproc_top.core.register_file_wrapper_i.register_file_i.mem[27][31:0] +TOP.vproc_top.core.register_file_wrapper_i.register_file_i.mem[28][31:0] +TOP.vproc_top.core.register_file_wrapper_i.register_file_i.mem[29][31:0] +TOP.vproc_top.core.register_file_wrapper_i.register_file_i.mem[30][31:0] +TOP.vproc_top.core.register_file_wrapper_i.register_file_i.mem[31][31:0] +@200 +-obi_port_0 +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[0].req +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[0].gnt +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[0].rvalid +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[0].addr[31:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[0].be[3:0] +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[0].we +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[0].err +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[0].rdata[31:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[0].wdata[31:0] +@200 +-obi_port_1 +-obi_port_2 +-state_req_red_i +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_red_i.res_vaddr[4:0] +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_red_i.res_store +@22 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+@22 +TOP.vproc_top.v_core.instr_complete_id[1][3:0] +@28 +TOP.vproc_top.v_core.instr_complete_valid[1:0] +@200 +-queue_data_d +@28 +TOP.vproc_top.v_core.queue_data_d.mode.lsu.nfields[2:0] +@200 +-queue_data_q +@28 +TOP.vproc_top.v_core.queue_data_q.mode.lsu.nfields[2:0] +@1401200 +-core +@c00200 +-unit_mux +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.clk_i +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.unit_queue_enq_ready +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.unit_queue_deq_valid +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.unit_queue_enq_valid +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.unit_queue_deq_unit[2:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.unit_queue_deq_unit_vector[2:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.pipe_out_valid_o +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.pipe_out_ready_i +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.pipe_out_instr_done_o +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.unit_out_instr_done[6:0] +@1401200 +-unit_mux +@22 +TOP.vproc_top.host_xif.issue_req.rs[0][31:0] +TOP.vproc_top.host_xif.issue_req.rs[1][31:0] +TOP.vproc_top.host_xif.issue_req.rs[2][31:0] +TOP.vproc_top.host_xif.issue_req.instr[31:0] +[pattern_trace] 1 +[pattern_trace] 0 From b63a4a492251b35b15fcce7a4edc11ea16a100b8 Mon Sep 17 00:00:00 2001 From: Melvin John Date: Tue, 14 Apr 2026 22:25:17 +0200 Subject: [PATCH 10/18] Added memory request queue for cv32 since it can ask upto 2 requests --- build_model/cv32e40x/vproc_top.sv | 35 ++++++++++++++++++------------- 1 file changed, 20 insertions(+), 15 deletions(-) diff --git a/build_model/cv32e40x/vproc_top.sv b/build_model/cv32e40x/vproc_top.sv index 50debb7..aec03af 100644 --- a/build_model/cv32e40x/vproc_top.sv +++ b/build_model/cv32e40x/vproc_top.sv @@ -865,20 +865,25 @@ module vproc_top import vproc_pkg::*, obi_pkg::*; #( for(genvar i = 0; i < MEM_PORTS; i++) begin assign vdata_gnt[i] = data_gnt[i] & vdata_req[i]; end - always_ff @(posedge clk_i or negedge rst_ni) begin - if (~rst_ni) begin - sdata_waiting <= 1'b0; - sdata_wait_addr <= '0; - end else begin - if (sdata_gnt) begin - sdata_waiting <= 1'b1; - sdata_wait_addr <= sdata_addr; - end - else if (sdata_rvalid) begin - sdata_waiting <= 1'b0; - end - end - end + + + vproc_queue #( + .WIDTH ( 1 ), + .DEPTH ( 2 ), // cv32 is configured to send out max 2 requests as default + .FLOW ( 1'b1 ) + ) s_wait_id_queue ( + .clk_i ( clk_i ), + .async_rst_ni ( rst_ni ), + .sync_rst_ni ( sync_rst_n ), + .enq_ready_o ( ), + .enq_valid_i ( sdata_gnt ), + .enq_data_i ( sdata_addr ), + .deq_ready_i ( sdata_rvalid ), + .deq_valid_o ( sdata_waiting ), + .deq_data_o ( sdata_wait_addr ), + .flags_any_o ( ), + .flags_all_o ( ) + ); vproc_queue #( .WIDTH ( 1 ), @@ -891,7 +896,7 @@ module vproc_top import vproc_pkg::*, obi_pkg::*; #( .enq_ready_o ( ), .enq_valid_i ( vdata_gnt[0] ), .enq_data_i ( ), - .deq_ready_i ( vdata_rvalid[0] ), + .deq_ready_i ( vdata_rvalid[0] ), .deq_valid_o ( vdata_waiting ), .deq_data_o ( ), .flags_any_o ( ), From 9dd42614a12c6adec6b3ff7fe7781b4b303f1ec8 Mon Sep 17 00:00:00 2001 From: Melvin John Date: Wed, 15 Apr 2026 12:51:03 +0200 Subject: [PATCH 11/18] Deleted unnecessary file --- debug/wavefrom_debug_lsu_extension.gtkw | 884 ------------------------ 1 file changed, 884 deletions(-) delete mode 100644 debug/wavefrom_debug_lsu_extension.gtkw diff --git a/debug/wavefrom_debug_lsu_extension.gtkw b/debug/wavefrom_debug_lsu_extension.gtkw deleted file mode 100644 index 1d793bc..0000000 --- a/debug/wavefrom_debug_lsu_extension.gtkw +++ /dev/null @@ -1,884 +0,0 @@ -[*] -[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI -[*] Wed Feb 25 22:32:40 2026 -[*] -[dumpfile] "/home/vboxuser/Desktop/vicuna2_unit_testing/debug/working.vcd" -[dumpfile_mtime] "Wed Feb 25 14:38:29 2026" -[dumpfile_size] 74691196 -[savefile] "/home/vboxuser/Desktop/vicuna2_unit_testing/debug/wavefrom_debug_lsu_extension.gtkw" -[timestart] 42057 -[size] 1848 902 -[pos] -1 -1 -*-5.945512 42145 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -[treeopen] TOP. -[treeopen] TOP.vproc_top. -[treeopen] TOP.vproc_top.v_core. -[treeopen] TOP.vproc_top.v_core.dec.mode_o. -[treeopen] TOP.vproc_top.v_core.dec_data_q.mode. -[treeopen] TOP.vproc_top.v_core.genblk9[0]. -[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe. -[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2. -[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline. -[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.alt_count_next_inc. -[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.count_next_inc. -[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.genblk1[0]. -[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.genblk1[0].genblk1. -[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pipe_in_state_i.mode. -[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_next.alt_count. -[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_next.count. -[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_next.mode. -[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_q.alt_count. -[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_q.count. -[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_q.mode. -[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux. -[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0]. -[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1. -[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit. -[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1. -[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu. -[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ctrl_i.mode. -[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_out_ctrl_o. -[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.xif_mem_if. -[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack. -[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk4[0]. -[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk6[2]. -[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[0]. -[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[0].genblk1[0]. -[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[1]. -[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[1].genblk1[0]. -[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[2]. -[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[2].genblk1[0]. -[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[3]. -[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[3].genblk1[0]. -[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[4]. -[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[4].genblk1[0]. -[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack_out_ctrl.mode. -[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.pipe_in_data_i.mode. -[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.state_init.mode. -[treeopen] TOP.vproc_top.v_core.genblk9[1].pipe. -[treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2. -[treeopen] TOP.vproc_top.v_core.pipe_instr_data.mode. -[treeopen] TOP.vproc_top.v_core.queue_data_d.mode. -[treeopen] TOP.vproc_top.v_core.queue_data_q.mode. -[treeopen] TOP.vproc_top.v_core.queue_pending_wr.mode_i.alu. -[treeopen] TOP.vproc_top.v_core.vregfile.genblk1[0]. -[treeopen] TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1. -[treeopen] TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0]. -[treeopen] TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[1]. -[sst_width] 379 -[signals_width] 546 -[sst_expanded] 1 -[sst_vpaned_height] 160 -@28 -TOP.vproc_top.clk_i -@800200 --lsu -@200 --lsu --input -@28 -[color] 7 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_valid_i -[color] 7 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ready_o -@22 -[color] 7 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.vreg_pend_rd_i[31:0] -[color] 7 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_op1_i[31:0] -[color] 7 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_op2_i[31:0] -[color] 7 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_mask_i[3:0] -[color] 7 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.vreg_pend_rd_i[31:0] -@200 --output -@28 -[color] 7 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pending_load_o -[color] 7 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pending_store_o -@22 -[color] 7 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_out_res_o[31:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_out_mask_o[3:0] -@28 -[color] 7 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_out_valid_o -[color] 7 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_out_pend_clr_o -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_out_ctrl_o.res_store -@200 --general -@28 -[color] 7 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ctrl_i.mode.lsu.nfields[2:0] -@100000028 -[color] 7 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ctrl_i.mode.lsu.eew[1:0] -@28 -[color] 7 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ctrl_i.mode.lsu.masked -@100000028 -[color] 7 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ctrl_i.mode.lsu.stride[1:0] -@22 -[color] 7 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ctrl_i.xval[31:0] -@28 -[color] 7 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.trans_complete_valid_o -[color] 7 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ctrl_i.init_addr -[color] 7 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ctrl_i.vl_0 -[color] 7 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ctrl_i.mode.lsu.alt_count_lsu_use -[color] 7 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ctrl_i.mode.lsu.alt_eew[1:0] -[color] 7 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ctrl_i.mode.lsu.alt_emul[1:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.VLSU_FLAGS[0] -@200 --read -@22 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.req_addr_q[0][31:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.req_addr_q[1][31:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.req_addr_q[2][31:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.req_addr_q[3][31:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.req_addr_q[4][31:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.req_addr_q[5][31:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.req_addr_q[6][31:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.req_addr_q[7][31:0] -[color] 7 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.rdata_unit_vl_mask[3:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.rdata_unit_vdmsk[3:0] -@28 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.rdata_stri_vdmsk -@200 --write -@22 -[color] 7 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.wdata_buf_q[31:0] -[color] 7 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.wmask_buf_q[3:0] -@28 -[color] 7 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.wdata_stri_mask -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.req_suppress -@200 --state_rdata_q --pipe_out_ctrl_o -@22 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_out_ctrl_o.res_vaddr[4:0] -@28 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_out_ctrl_o.first_cycle -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_out_ctrl_o.last_cycle -@200 --xif_mem -@28 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.xif_mem_if.mem_ready -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.xif_mem_if.mem_valid -@22 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.xif_mem_if.mem_req.addr[31:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.xif_mem_if.mem_req.be[3:0] -@23 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.xif_mem_if.mem_req.wdata[31:0] -@22 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.xif_mem_if.mem_result.rdata[31:0] -@28 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.xif_mem_if.mem_req.we -@1000200 --lsu -@800200 --registers -@200 --registers -@22 -[color] 5 -TOP.vproc_top.v_core.csr_vl_o[31:0] -[color] 5 -TOP.vproc_top.v_core.vregfile.rd_addr_i[0][4:0] -[color] 5 -TOP.vproc_top.v_core.vregfile.rd_addr_i[1][4:0] -[color] 5 -TOP.vproc_top.v_core.vregfile.rd_data_o[0][127:0] -[color] 5 -TOP.vproc_top.v_core.vregfile.rd_data_o[1][127:0] -@28 -[color] 5 -TOP.vproc_top.v_core.vregfile.wr_we_i[0] -@22 -[color] 5 -TOP.vproc_top.v_core.vregfile.wr_be_i[0][15:0] -[color] 5 -TOP.vproc_top.v_core.vregfile.wr_addr_i[0][4:0] -[color] 5 -TOP.vproc_top.v_core.vregfile.wr_data_i[0][127:0] -@1000200 --registers -@c00200 --lsu_extension -@200 --scratch_state_q --scratch_state_d --port_state_q --scratch_pending --input_queue --output_queue --mem_req_queue --port_queue --vtop -@28 -TOP.vproc_top.clk_i -@200 --obi_port --state_req_red_i --state_req_red --deq_state --general -@1401200 --lsu_extension -@c00200 --decoder -@200 --decoder -@28 -TOP.vproc_top.v_core.dec.instr_valid_i -TOP.vproc_top.v_core.dec.instr_illegal -TOP.vproc_top.v_core.dec.op_illegal -TOP.vproc_top.v_core.dec.vd_invalid -TOP.vproc_top.v_core.dec.vs1_invalid -TOP.vproc_top.v_core.dec.vs2_invalid -TOP.vproc_top.v_core.dec.vtype_invalid -@22 -TOP.vproc_top.v_core.dec.instr_i[31:0] -TOP.vproc_top.v_core.dec.instr_vd[4:0] -TOP.vproc_top.v_core.dec.instr_vs1[4:0] -TOP.vproc_top.v_core.dec.instr_vs2[4:0] -TOP.vproc_top.v_core.dec.x_rs1_i[31:0] -TOP.vproc_top.v_core.dec.x_rs2_i[31:0] -@28 -TOP.vproc_top.v_core.dec.valid_o -@800200 --rs1 -@200 --rs1 -@28 -TOP.vproc_top.v_core.dec.rs1_o.xreg -TOP.vproc_top.v_core.dec.rs1_o.vreg -@22 -TOP.vproc_top.v_core.dec.rs1_o.r.vaddr[4:0] -TOP.vproc_top.v_core.dec.rs1_o.r.xval[31:0] -@1000200 --rs1 -@800200 --rs2 -@200 --rs2 -@28 -TOP.vproc_top.v_core.dec.rs2_o.xreg -TOP.vproc_top.v_core.dec.rs2_o.vreg -@22 -TOP.vproc_top.v_core.dec.rs2_o.r.vaddr[4:0] -TOP.vproc_top.v_core.dec.rs2_o.r.xval[31:0] -@1000200 --rs2 -@800200 --rd -@200 --rd -@22 -TOP.vproc_top.v_core.dec.rd_o.addr[4:0] -@28 -TOP.vproc_top.v_core.dec.rd_o.vreg -@1000200 --rd -@28 -TOP.vproc_top.v_core.dec.unit_o[2:0] -TOP.vproc_top.v_core.dec.lmul_i[2:0] -TOP.vproc_top.v_core.dec.mode_o.cfg.vsew[1:0] -TOP.vproc_top.v_core.dec.mode_o.cfg.lmul[2:0] -TOP.vproc_top.v_core.dec.mode_o.lsu.alt_count_lsu_use -TOP.vproc_top.v_core.dec.mode_o.lsu.nfields[2:0] -TOP.vproc_top.v_core.dec.mode_o.lsu.alt_eew[1:0] -TOP.vproc_top.v_core.dec.mode_o.lsu.alt_emul[1:0] -TOP.vproc_top.v_core.dec.mode_o.lsu.eew[1:0] -TOP.vproc_top.v_core.dec.emul_o[1:0] -TOP.vproc_top.v_core.dec.mode_o.lsu.stride[1:0] -@22 -[color] 4 -TOP.vproc_top.v_core.dec.vl_i[6:0] -[color] 4 -TOP.vproc_top.v_core.dec.vl_o[6:0] -@28 -TOP.vproc_top.v_core.dec.vl_override_o -@1401200 --decoder -@c00200 --pending_wr -@28 -TOP.vproc_top.v_core.queue_pending_wr.emul_i[1:0] -TOP.vproc_top.v_core.queue_pending_wr.unit_i[2:0] -TOP.vproc_top.v_core.queue_pending_wr.mode_i.lsu.nfields[2:0] -TOP.vproc_top.v_core.queue_pending_wr.mode_i.lsu.store -@22 -TOP.vproc_top.v_core.queue_pending_wr.pending_wr_o[31:0] -TOP.vproc_top.v_core.queue_pending_wr.rd_i.addr[4:0] -TOP.vproc_top.v_core.queue_pending_wr.pend_vd[31:0] -@1401200 --pending_wr -@c00200 --pipeline_wrapper -@200 --pipeline_wrapper -@22 -TOP.vproc_top.v_core.genblk9[0].pipe.OP0_SRC[31:0] -TOP.vproc_top.v_core.genblk9[0].pipe.OP1_SRC[31:0] -TOP.vproc_top.v_core.genblk9[0].pipe.OP2_SRC[31:0] -TOP.vproc_top.v_core.genblk9[0].pipe.OP0_STAGE[31:0] -TOP.vproc_top.v_core.genblk9[0].pipe.OP1_STAGE[31:0] -TOP.vproc_top.v_core.genblk9[0].pipe.OP2_STAGE[31:0] -TOP.vproc_top.v_core.genblk9[0].pipe.UNPACK_STAGES[31:0] -@28 -[color] 3 -TOP.vproc_top.v_core.genblk9[0].pipe.pipe_in_ready_o -[color] 3 -TOP.vproc_top.v_core.genblk9[0].pipe.pipe_in_valid_i -@22 -[color] 3 -TOP.vproc_top.v_core.genblk9[0].pipe.OP_CNT[31:0] -[color] 3 -TOP.vproc_top.v_core.genblk9[0].pipe.RES_CNT[31:0] -@28 -[color] 3 -TOP.vproc_top.v_core.genblk9[0].pipe.state_init.eew[1:0] -[color] 3 -TOP.vproc_top.v_core.genblk9[0].pipe.state_init.emul[1:0] -[color] 3 -TOP.vproc_top.v_core.genblk9[0].pipe.state_init.mode.cfg.lmul[2:0] -[color] 3 -TOP.vproc_top.v_core.genblk9[0].pipe.state_init.mode.lsu.alt_count_lsu_use -[color] 3 -TOP.vproc_top.v_core.genblk9[0].pipe.state_init.mode.lsu.alt_eew[1:0] -[color] 3 -TOP.vproc_top.v_core.genblk9[0].pipe.state_init.mode.lsu.alt_emul[1:0] -TOP.vproc_top.v_core.genblk9[0].pipe.pipe_in_data_i.mode.lsu.nfields[2:0] -[color] 3 -TOP.vproc_top.v_core.genblk9[0].pipe.state_init.mode.lsu.eew[1:0] -[color] 3 -TOP.vproc_top.v_core.genblk9[0].pipe.state_init.mode.lsu.stride[1:0] -[color] 3 -TOP.vproc_top.v_core.genblk9[0].pipe.state_init.alt_count_inc[1:0] -[color] 3 -TOP.vproc_top.v_core.genblk9[0].pipe.state_init.count_inc[1:0] -@22 -[color] 3 -TOP.vproc_top.v_core.genblk9[0].pipe.state_init.vl[6:0] -@1401200 --pipeline_wrapper -@800200 --pipeline -@200 --pipeline -@28 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.OP_FIELD[2:0] -@22 -[color] 2 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.COUNTER_W[31:0] -[color] 2 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.MAX_OP_W[31:0] -[color] 2 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.COUNTER_OP_W[31:0] -@28 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.OP_ALT_COUNTER[2:0] -[color] 2 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pipe_in_ready_o -[color] 2 -TOP.vproc_top.v_core.genblk9[0].pipe.pipe_in_valid_i -@200 --xval -@22 -[color] 2 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pipe_in_state_i.op_xval[0][31:0] -[color] 2 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pipe_in_state_i.op_xval[1][31:0] -[color] 2 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pipe_in_state_i.op_xval[2][31:0] -[color] 2 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_q.xval[31:0] -@200 --first_cycle -@28 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_q.first_cycle -@200 --last_cycle -@28 -[color] 2 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_q.last_cycle -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.last_cycle_next -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_q.alt_last_cycle -@200 --count -@100000028 -[color] 2 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_q.count_inc[1:0] -@22 -[color] 2 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_q.count.val[7:0] -@28 -[color] 2 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_q.count.part.mul[2:0] -@200 --alt_count -@28 -[color] 2 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_q.alt_count_inc[1:0] -@22 -[color] 2 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_q.alt_count.val[7:0] -@28 -[color] 2 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_q.alt_count.part.mul[2:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.res_store -@200 --count_next -@22 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.count_next_inc.val[7:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.count_next_inc.part.low[3:0] -@28 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.count_next_inc.part.mul[2:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.count_next_inc.part.sign -@200 --alt_count_next -@22 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.alt_count_next_inc.val[7:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.alt_count_next_inc.part.low[3:0] -@28 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.alt_count_next_inc.part.mul[2:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.alt_count_next_inc.part.sign -@200 --field -@28 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_q.field_done -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_q.field_counter[2:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_q.field_init_count[2:0] -@200 --general -@28 -[color] 2 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_done -[color] 2 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_ready -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack_ready -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_valid_q -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_stall -[color] 2 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_q.mode.lsu.alt_count_lsu_use -[color] 2 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.op_flags[0].shift -@100000028 -[color] 2 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_next.eew[1:0] -@28 -[color] 2 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_q.emul[1:0] -[color] 2 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_q.mode.lsu.alt_eew[1:0] -[color] 2 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_q.mode.lsu.alt_emul[1:0] -@22 -[color] 2 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_q.vl[6:0] -@100000028 -[color] 2 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_q.mode.lsu.stride[1:0] -@28 -[color] 2 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_q.mode.lsu.alt_count_lsu_use -[color] 2 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_q.unit[2:0] -[color] 2 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.wait_alt_count_next -[color] 2 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_q.alt_last_cycle -@200 --vreg -@28 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_q.op_flags[0].vreg -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_q.op_flags[1].vreg -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_q.op_flags[2].vreg -@22 -[color] 2 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.op_vaddr[0][4:0] -[color] 2 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.op_vaddr[1][4:0] -[color] 2 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.op_vaddr[2][4:0] -@28 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.res_store -@22 -[color] 2 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack_ctrl.res_vaddr[4:0] -[color] 2 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.op_pend_reads[0][31:0] -[color] 2 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.op_pend_reads[1][31:0] -[color] 2 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.op_pend_reads[2][31:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.op_fields_pend_reads[31:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.op_pend_reads_all[31:0] -[color] 2 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_q.pend_vreg_wr[31:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.vreg_pend_wr_i[31:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.vreg_wr_addr_o[4:0] -@28 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.vreg_wr_valid_o -@22 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.op_load[2:0] -[color] 2 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.vreg_pend_rd_o[31:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack_pend_rd[31:0] -@c00200 --instr_state -@28 -[color] 2 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.instr_state_i[0][1:0] -[color] 2 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.instr_state_i[1][1:0] -[color] 2 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.instr_state_i[2][1:0] -[color] 2 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.instr_state_i[3][1:0] -[color] 2 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.instr_state_i[4][1:0] -[color] 2 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.instr_state_i[5][1:0] -[color] 2 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.instr_state_i[6][1:0] -[color] 2 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.instr_state_i[7][1:0] -[color] 2 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.instr_state_i[8][1:0] -[color] 2 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.instr_state_i[9][1:0] -[color] 2 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.instr_state_i[10][1:0] -[color] 2 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.instr_state_i[11][1:0] -[color] 2 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.instr_state_i[12][1:0] -[color] 2 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.instr_state_i[13][1:0] -[color] 2 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.instr_state_i[14][1:0] -[color] 2 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.instr_state_i[15][1:0] -[color] 2 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_valid_q -@22 -[color] 2 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_q.id[3:0] -@1401200 --instr_state -@1000200 --pipeline -@800200 --unpack -@200 --unpack -@28 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.DONT_CARE_ZERO -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.OP_ALLOW_ELEMWISE[2:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.OP_ALWAYS_ELEMWISE[2:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.OP_MASK[2:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.OP_ALT_COUNTER[2:0] -@22 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.OP_W[0][31:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.OP_W[1][31:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.OP_W[2][31:0] -@28 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.pipe_in_ready_o -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.pipe_in_valid_i -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.pipe_out_ready_i -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.pipe_out_valid_o -@22 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.pipe_in_op_vaddr_i[0][4:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.pipe_in_op_vaddr_i[1][4:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.pipe_in_op_vaddr_i[2][4:0] -@28 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.pipe_in_eew_i[1:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.pipe_in_alt_eew_i[1:0] -@22 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.pipe_out_op_data_o[0][31:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.pipe_out_op_data_o[1][31:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.pipe_out_op_data_o[2][31:0] -@28 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.clk_i -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.pipe_in_op_load_i[2:0] -@22 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.stage_ready[4:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.stage_valid[4:0] -@28 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.stage_valid_any_o -@22 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.stage_valid_q[4:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.stage_valid_d[4:0] -@28 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.stage_state[0].eew[1:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.stage_state[0].eew[1:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.stage_state_q[1].eew[1:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.stage_state_q[2].eew[1:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.stage_state_q[3].eew[1:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.stage_state_q[4].eew[1:0] -@22 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.vreg_buffer_d[0][127:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.vreg_buffer_q[0][127:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.vreg_rd_addr_o[0][4:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.vreg_rd_data_i[0][127:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.vreg_rd_v0_i[127:0] -@28 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.op_load[2:0] -@22 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk5[2].op_default[3:0] -@28 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.clk_i -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.op_addressing[2:0] -@200 --field_op -@22 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.field_buffer[0][127:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.field_buffer[1][127:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.field_buffer[2][127:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.field_buffer[3][127:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.field_buffer[4][127:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.field_buffer[5][127:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.field_buffer[6][127:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.field_buffer_next[0][127:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.field_buffer_next[1][127:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.field_buffer_next[2][127:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.field_buffer_next[3][127:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.field_buffer_next[4][127:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.field_buffer_next[5][127:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.field_buffer_next[6][127:0] -@200 --load_flag_0 -@22 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.op_buffer[0][127:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.op_buffer_next[0][127:0] -@28 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.op_load_eew[0][1:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.op_extract_eew[0][1:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.op_load_flags[0].shift -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.op_load_flags[0].hold -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.op_load_field_counter[0][2:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.op_extract_field_counter[0][2:0] -@200 --load_flag_1 -@22 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.op_buffer[1][127:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.op_buffer_next[1][127:0] -@28 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.op_load_eew[1][1:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.op_extract_eew[1][1:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.op_load_flags[1].field_instr -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.op_load_flags[1].shift -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.op_load_flags[1].hold -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.op_load_field_counter[1][2:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.op_extract_field_counter[1][2:0] -@200 --load_flag_2 -@22 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.op_buffer[2][127:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.op_buffer_next[2][127:0] -@28 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.op_load_eew[2][1:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.op_extract_eew[2][1:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.op_load_flags[2].shift -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.op_load_flags[2].hold -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.op_load_field_counter[2][2:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.op_extract_field_counter[2][2:0] -@22 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk5[0].op_default[31:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk5[1].op_default[31:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.op_data[0][31:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.op_data[1][31:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.op_data[2][31:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.op_vreg_addr[0][4:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.op_vreg_addr[1][4:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.op_vreg_addr[2][4:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.op_vreg_data[0][127:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.op_vreg_data[1][127:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.op_vreg_data[2][127:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.op_xval[0][31:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.op_xval[1][31:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.op_xval[2][31:0] -@1000200 --unpack -@c00200 --pack -@200 --pack -@22 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.RES_MASK[7:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.RES_W[0][31:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.RES_CNT[31:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.RES_ALLOW_ELEMWISE[7:0] -@200 --input -@22 -[color] 6 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.pipe_in_vaddr_i[4:0] -@28 -[color] 7 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.pipe_in_valid_i -@22 -[color] 6 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.pipe_in_res_data_i[0][31:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.pipe_in_res_mask_i[0][31:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.pipe_in_res_data_i[1][31:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.pipe_in_res_mask_i[1][31:0] -@28 -[color] 6 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.pipe_in_instr_done_i -[color] 6 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.pipe_in_pend_clr_cnt_i[1:0] -[color] 6 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.pipe_in_pend_clr_i -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.pipe_in_eew_i[1:0] -@22 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.pipe_in_res_valid_i[7:0] -@28 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.pipe_in_res_flags_i[0].elemwise -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.pipe_in_res_flags_i[0].shift -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.pipe_in_res_flags_i[1].elemwise -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.pipe_in_res_flags_i[1].shift -@200 --output -@22 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.instr_done_id_o[3:0] -@28 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.instr_done_valid_o -@22 -[color] 6 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.vreg_wr_be_o[15:0] -@28 -[color] 6 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.vreg_wr_clr_o -[color] 7 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.vreg_wr_valid_o -@22 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.vreg_wr_be_o[15:0] -[color] 6 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.vreg_wr_addr_o[4:0] -@28 -[color] 6 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.vreg_wr_clr_cnt_o[1:0] -@22 -[color] 6 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.vreg_wr_data_o[127:0] -@28 -[color] 7 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.stage_ready -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.stage_stall -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.stage_valid_q -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.stage_state_q.pend_clr -@22 -[color] 6 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.res_buffer[0][127:0] -[color] 6 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.res_buffer_next[0][127:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.res_buffer[1][127:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.res_buffer_next[1][127:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.msk_buffer[0][15:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.msk_buffer_next[0][15:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.genblk1[0].genblk1.msk_default[3:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.genblk1[0].genblk1.res_default[31:0] -@28 -[color] 6 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.vreg_wr_ready_i -@1401200 --pack -@c00200 --unit_wrapper -@200 --Unit_wrapper -@22 -[color] 1 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.pipe_out_vaddr_o[4:0] -[color] 1 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.unit_out_ctrl.res_vaddr[4:0] -@28 -[color] 1 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.vreg_wr_valid_o -@1401200 --unit_wrapper -@c00200 --core -@200 --core -@28 -TOP.vproc_top.v_core.dec_data_q.mode.cfg.lmul[2:0] -TOP.vproc_top.v_core.instr_state_q[0][1:0] -TOP.vproc_top.v_core.instr_state_q[1][1:0] -TOP.vproc_top.v_core.instr_state_q[2][1:0] -TOP.vproc_top.v_core.instr_state_q[3][1:0] -TOP.vproc_top.v_core.instr_state_q[4][1:0] -TOP.vproc_top.v_core.instr_state_q[5][1:0] -TOP.vproc_top.v_core.instr_state_q[6][1:0] -TOP.vproc_top.v_core.instr_state_q[7][1:0] -TOP.vproc_top.v_core.instr_state_q[8][1:0] -TOP.vproc_top.v_core.instr_state_q[9][1:0] -TOP.vproc_top.v_core.instr_state_q[10][1:0] -TOP.vproc_top.v_core.instr_state_q[11][1:0] -TOP.vproc_top.v_core.instr_state_q[12][1:0] -TOP.vproc_top.v_core.instr_state_q[13][1:0] -TOP.vproc_top.v_core.instr_state_q[14][1:0] -TOP.vproc_top.v_core.instr_state_q[15][1:0] -@22 -TOP.vproc_top.v_core.instr_complete_id[0][3:0] -@28 -TOP.vproc_top.v_core.pipe_instr_valid[1:0] -@22 -TOP.vproc_top.v_core.instr_complete_id[1][3:0] -@28 -TOP.vproc_top.v_core.instr_complete_valid[1:0] -@200 --queue_data_d -@28 -TOP.vproc_top.v_core.queue_data_d.mode.lsu.nfields[2:0] -@200 --queue_data_q -@28 -TOP.vproc_top.v_core.queue_data_q.mode.lsu.nfields[2:0] -@1401200 --core -@c00200 --unit_mux -@28 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.clk_i -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.unit_queue_enq_ready -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.unit_queue_deq_valid -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.unit_queue_enq_valid -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.unit_queue_deq_unit[2:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.unit_queue_deq_unit_vector[2:0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.pipe_out_valid_o -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.pipe_out_ready_i -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.pipe_out_instr_done_o -@22 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.unit_out_instr_done[6:0] -@1401200 --unit_mux -@22 -TOP.vproc_top.host_xif.issue_req.rs[0][31:0] -TOP.vproc_top.host_xif.issue_req.rs[1][31:0] -TOP.vproc_top.host_xif.issue_req.rs[2][31:0] -TOP.vproc_top.host_xif.issue_req.instr[31:0] -[pattern_trace] 1 -[pattern_trace] 0 -!100000@@ -?"B533 -@23 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.xif_mem_if.mem_req.addr[31:0] -!! From 1ced7aebecab02ce660d63b48e2613de3b9720ac Mon Sep 17 00:00:00 2001 From: Melvin John Date: Wed, 15 Apr 2026 17:47:30 +0200 Subject: [PATCH 12/18] Corrected se align --- build_model/CMakeLists.txt | 2 ++ build_model/cv32e40x/vproc_top.sv | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/build_model/CMakeLists.txt b/build_model/CMakeLists.txt index 9129bdf..86f14a6 100644 --- a/build_model/CMakeLists.txt +++ b/build_model/CMakeLists.txt @@ -27,6 +27,8 @@ set(CMAKE_CXX_STANDARD 14) option(TRACE "Enable minimal VCD trace outputs" OFF) option(TRACE_FULL "Enable FULL VCD trace outputs" OFF) #TODO: prevent this option from being cached, force user to always manually enable it +option(OLD_VICUNA "Old vicuna without vl abort" ON) +option(FORCE_ALIGNED_READS "Forces aligned reads for cv32 and vproc" ON) ######## ## Import RTL configuration from here instead of command line. diff --git a/build_model/cv32e40x/vproc_top.sv b/build_model/cv32e40x/vproc_top.sv index aec03af..71690ef 100644 --- a/build_model/cv32e40x/vproc_top.sv +++ b/build_model/cv32e40x/vproc_top.sv @@ -36,7 +36,6 @@ module vproc_top import vproc_pkg::*, obi_pkg::*; #( input logic [32 -1:0] mem_irdata_i ); - if ((MEM_W & (MEM_W - 1)) != 0 || MEM_W < 32) begin $fatal(1, "The memory bus width MEM_W must be at least 32 and a power of two. ", "The current value of %d is invalid.", MEM_W); @@ -835,6 +834,7 @@ module vproc_top import vproc_pkg::*, obi_pkg::*; #( // TODO: data_req_id[0] = ; for cva core `ifdef FORCE_ALIGNED_READS + data_addr[0] = {sdata_addr[31:2], 2'b00}; data_be[0] = {{(VMEM_W-32){1'b0}}, sdata_be} << (sdata_addr[$clog2(VMEM_W/8)-1:0] & {{$clog2(VMEM_W/32){1'b1}}, 2'b00}); data_wdata[0] = '0; for (int i = 0; i < VMEM_W / 32; i++) begin From 54464fb36e5309e350d72e026a1c20dc0782f803 Mon Sep 17 00:00:00 2001 From: Melvin John Date: Wed, 15 Apr 2026 22:38:46 +0200 Subject: [PATCH 13/18] Updated waveforms --- wavefrom_debug.gtkw | 915 ++++++++++++++++++++++++++++++ wavefrom_debug_lsu_extension.gtkw | 14 +- 2 files changed, 923 insertions(+), 6 deletions(-) create mode 100644 wavefrom_debug.gtkw diff --git a/wavefrom_debug.gtkw b/wavefrom_debug.gtkw new file mode 100644 index 0000000..e4f3532 --- /dev/null +++ b/wavefrom_debug.gtkw @@ -0,0 +1,915 @@ +[*] +[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI +[*] Wed Apr 15 16:08:10 2026 +[*] +[dumpfile] "(null)" +[savefile] "/home/vboxuser/Desktop/vicuna2_unit_testing/wavefrom_debug.gtkw" +[timestart] 5243 +[size] 1848 902 +[pos] -1 -1 +*-4.945512 5284 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[treeopen] TOP. +[treeopen] TOP.vproc_top. +[treeopen] TOP.vproc_top.core. +[treeopen] TOP.vproc_top.core.load_store_unit_i. +[treeopen] TOP.vproc_top.core.register_file_wrapper_i. +[treeopen] TOP.vproc_top.host_xif. +[treeopen] TOP.vproc_top.v_core. +[treeopen] TOP.vproc_top.v_core.dec.mode_o. +[treeopen] TOP.vproc_top.v_core.dec_data_q.mode. +[treeopen] TOP.vproc_top.v_core.genblk9[0]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.alt_count_next_inc. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.count_next_inc. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.genblk1[0]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.genblk1[0].genblk1. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pipe_in_state_i. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pipe_in_state_i.mode. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_next.alt_count. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_next.count. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_next.mode. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_q. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_q.alt_count. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_q.count. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_q.mode. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ctrl_i.mode. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_out_ctrl_o. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.state_rdata_q. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.xif_mem_if. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk4[0]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk6[2]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[0]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[0].genblk1[0]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[1]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[1].genblk1[0]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[2]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[2].genblk1[0]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[3]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[3].genblk1[0]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[4]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[4].genblk1[0]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack_out_ctrl.mode. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.pipe_in_data_i.mode. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.state_init.mode. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe_xif. +[treeopen] TOP.vproc_top.v_core.pipe_instr_data.mode. +[treeopen] TOP.vproc_top.v_core.queue_data_d.mode. +[treeopen] TOP.vproc_top.v_core.queue_data_q.mode. +[treeopen] TOP.vproc_top.v_core.queue_pending_wr.mode_i.alu. +[treeopen] TOP.vproc_top.v_core.vregfile. +[treeopen] TOP.vproc_top.v_core.vregfile.genblk1[0]. +[treeopen] TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1. +[treeopen] TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0]. +[treeopen] TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[1]. +[treeopen] TOP.vproc_top.v_core.xif_issue_if. +[sst_width] 379 +[signals_width] 546 +[sst_expanded] 1 +[sst_vpaned_height] 183 +@28 +TOP.vproc_top.clk_i +@800200 +-cv32 +@200 +-cv32 +@28 +TOP.vproc_top.core.data_req_o +TOP.vproc_top.core.data_gnt_i +TOP.vproc_top.core.data_rvalid_i +@22 +TOP.vproc_top.core.data_addr_o[31:0] +@28 +TOP.vproc_top.core.data_we_o +@22 +TOP.vproc_top.core.data_be_o[3:0] +TOP.vproc_top.core.data_rdata_i[31:0] +TOP.vproc_top.core.data_wdata_o[31:0] +TOP.vproc_top.core.register_file_wrapper_i.register_file_i.mem[7][31:0] +TOP.vproc_top.core.register_file_wrapper_i.register_file_i.mem[1][31:0] +TOP.vproc_top.core.register_file_wrapper_i.register_file_i.mem[3][31:0] +TOP.vproc_top.core.register_file_wrapper_i.register_file_i.mem[5][31:0] +TOP.vproc_top.core.register_file_wrapper_i.register_file_i.waddr_i[0][4:0] +@28 +TOP.vproc_top.core.register_file_wrapper_i.register_file_i.we_i[0] +TOP.vproc_top.core.load_store_unit_i.lsu_split_0_o +@22 +TOP.vproc_top.core.load_store_unit_i.trans.addr[31:0] +@28 +TOP.vproc_top.core.load_store_unit_i.valid_0_i +TOP.vproc_top.core.load_store_unit_i.xif_req +TOP.vproc_top.core.load_store_unit_i.split_q +TOP.vproc_top.core.load_store_unit_i.trans.size[1:0] +@1000200 +-cv32 +@800200 +-lsu +@200 +-lsu +-input +@28 +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_valid_i +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ready_o +@22 +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.vreg_pend_rd_i[31:0] +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_op1_i[31:0] +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_op2_i[31:0] +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_mask_i[3:0] +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.vreg_pend_rd_i[31:0] +@200 +-output +@28 +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pending_load_o +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pending_store_o +@22 +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_out_res_o[31:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_out_mask_o[3:0] +@28 +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_out_valid_o +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_out_pend_clr_o +@200 +-general +@28 +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ctrl_i.mode.lsu.nfields[2:0] +@100000028 +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ctrl_i.mode.lsu.eew[1:0] +@28 +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ctrl_i.mode.lsu.masked +@100000028 +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ctrl_i.mode.lsu.stride[1:0] +@22 +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ctrl_i.xval[31:0] +@28 +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.trans_complete_valid_o +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ctrl_i.init_addr +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ctrl_i.vl_0 +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ctrl_i.mode.lsu.alt_count_lsu_use +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ctrl_i.mode.lsu.alt_eew[1:0] +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ctrl_i.mode.lsu.alt_emul[1:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.VLSU_FLAGS[0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.state_req_stall +@200 +-read +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.req_addr_q[0][31:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.req_addr_q[1][31:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.req_addr_q[2][31:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.req_addr_q[3][31:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.req_addr_q[4][31:0] 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+TOP.vproc_top.v_core.instr_state_q[15][1:0] +@22 +TOP.vproc_top.v_core.instr_complete_id[0][3:0] +@28 +TOP.vproc_top.v_core.pipe_instr_valid[1:0] +@22 +TOP.vproc_top.v_core.instr_complete_id[1][3:0] +@28 +TOP.vproc_top.v_core.instr_complete_valid[1:0] +@200 +-queue_data_d +@28 +TOP.vproc_top.v_core.queue_data_d.mode.lsu.nfields[2:0] +@200 +-queue_data_q +@28 +TOP.vproc_top.v_core.queue_data_q.mode.lsu.nfields[2:0] +@1401200 +-core +@c00200 +-unit_mux +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.clk_i +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.unit_queue_enq_ready +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.unit_queue_deq_valid +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.unit_queue_enq_valid +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.unit_queue_deq_unit[2:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.unit_queue_deq_unit_vector[2:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.pipe_out_valid_o +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.pipe_out_ready_i +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.pipe_out_instr_done_o +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.unit_out_instr_done[6:0] +@1401200 +-unit_mux +@22 +TOP.vproc_top.host_xif.issue_req.rs[0][31:0] +TOP.vproc_top.host_xif.issue_req.rs[1][31:0] +TOP.vproc_top.host_xif.issue_req.rs[2][31:0] +TOP.vproc_top.host_xif.issue_req.instr[31:0] +[pattern_trace] 1 +[pattern_trace] 0 +!100000@@ +?"30AC75DC +@23 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.xif_mem_if.mem_req.wdata[31:0] +!! diff --git a/wavefrom_debug_lsu_extension.gtkw b/wavefrom_debug_lsu_extension.gtkw index d17462c..7e8e4e3 100644 --- a/wavefrom_debug_lsu_extension.gtkw +++ b/wavefrom_debug_lsu_extension.gtkw @@ -1,15 +1,15 @@ [*] [*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI -[*] Sun Apr 12 16:41:46 2026 +[*] Wed Apr 15 16:30:49 2026 [*] [dumpfile] "/home/vboxuser/Desktop/vicuna2_unit_testing/build_tests/build/Testing/last_test_sig.vcd" -[dumpfile_mtime] "Sun Apr 12 16:41:34 2026" -[dumpfile_size] 224004395 +[dumpfile_mtime] "Wed Apr 15 16:30:30 2026" +[dumpfile_size] 327078153 [savefile] "/home/vboxuser/Desktop/vicuna2_unit_testing/wavefrom_debug_lsu_extension.gtkw" -[timestart] 466 +[timestart] 697 [size] 1848 902 [pos] -1 -1 -*-4.945512 530 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +*-4.945512 745 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 [treeopen] TOP. [treeopen] TOP.vproc_top. [treeopen] TOP.vproc_top.v_core. @@ -252,8 +252,9 @@ TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[31][127:0] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.clk_i @200 -scratch_state_q -@28 +@29 TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_state_q.current_eew[1:0] +@28 TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_state_q.fsm_state[2:0] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_state_q.store_end_index[0] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_state_q.write_index[0] @@ -269,6 +270,7 @@ TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk -port_state_q -scratch_memory @28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.misalignment_request TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_memory_state_q[0][1:0] @22 TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_memory_q[0].addr[31:0] From a952b52e4754887a41cf96eee6760fec12571899 Mon Sep 17 00:00:00 2001 From: Melvin John Date: Wed, 15 Apr 2026 22:40:40 +0200 Subject: [PATCH 14/18] Added comment --- build_model/cv32e40x/vproc_top.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/build_model/cv32e40x/vproc_top.sv b/build_model/cv32e40x/vproc_top.sv index 71690ef..480265f 100644 --- a/build_model/cv32e40x/vproc_top.sv +++ b/build_model/cv32e40x/vproc_top.sv @@ -314,7 +314,7 @@ module vproc_top import vproc_pkg::*, obi_pkg::*; #( logic [OBI_ID_WIDTH-1:0] vdata_res_id [MEM_PORTS-1:0]; // Allow for vector loads/stores to be misaligned with respect to VMEM_W - `ifdef FORCE_ALIGNED_READS + `ifdef FORCE_ALIGNED_READS // not needed anymore since scratch is aligning already localparam bit [VLSU_FLAGS_W-1:0] VLSU_FLAGS = (VLSU_FLAGS_W'(0) << VLSU_ALIGNED_UNITSTRIDE); `else localparam bit [VLSU_FLAGS_W-1:0] VLSU_FLAGS = (VLSU_FLAGS_W'(0) << VLSU_ALIGNED_UNITSTRIDE); From cce231d2ec68ba392954905cb9b234efb540a37b Mon Sep 17 00:00:00 2001 From: jjones Date: Fri, 10 Apr 2026 16:23:06 +0200 Subject: [PATCH 15/18] Always respond to write request in single cycle --- build_model/cv32e40x/verilator_main.cpp | 6 +++--- build_model/cv32e40x/verilator_support_cv32e40x.cpp | 7 ++++--- build_model/cv32e40x/verilator_support_cv32e40x.h | 2 +- 3 files changed, 8 insertions(+), 7 deletions(-) diff --git a/build_model/cv32e40x/verilator_main.cpp b/build_model/cv32e40x/verilator_main.cpp index 6029329..b63a8ac 100644 --- a/build_model/cv32e40x/verilator_main.cpp +++ b/build_model/cv32e40x/verilator_main.cpp @@ -230,9 +230,9 @@ int main(int argc, char **argv) { ////////////////////////// for(int i = 0; i < mem_ports; i++){ //Update write interface - update_mem_write(top->mem_addr_o[i], (top->mem_req_o[i] && top->mem_we_o[i]), mem_w, mem_latency, mem_sz, (unsigned char*)&(top->mem_wdata_o[i]), (unsigned char*)&(top->mem_be_o[i]), mem_rvalid_queue[i], mem); - //Update read interface TODO - STALL IF (top->mem_req_o && !top->mem_we_o). Original Vicuna also did not contain this condition TODO: MEM_REQ_VALID NEEDS TO BE SIGNALLED for writes - update_mem_load(top->mem_addr_o[i], (top->mem_req_o[i]), mem_w, mem_latency, mem_sz, (unsigned char*)&(top->mem_rdata_i[i]), (bool*)&(top->mem_rvalid_i[i]), (bool*)&(top->mem_err_i[i]), mem_rdata_queue[i], mem_rvalid_queue[i], mem_err_queue[i], mem); + //Update read interface TODO - STALL IF (top->mem_req_o && !top->mem_we_o). Original Vicuna also did not contain this condition TODO: MEM_REQ_VALID NEEDS TO BE SIGNALLED for writes + update_mem_load(top->mem_addr_o[i], (top->mem_req_o[i] && !top->mem_we_o[i]), mem_w, mem_latency, mem_sz, (unsigned char*)&(top->mem_rdata_i[i]), (bool*)&(top->mem_rvalid_i[i]), (bool*)&(top->mem_err_i[i]), mem_rdata_queue[i], mem_rvalid_queue[i], mem_err_queue[i], mem); + update_mem_write(top->mem_addr_o[i], (top->mem_req_o[i] && top->mem_we_o[i]), mem_w, mem_latency, mem_sz, (unsigned char*)&(top->mem_wdata_o[i]), (unsigned char*)&(top->mem_be_o[i]), mem_rvalid_queue[i], mem_err_queue[i], mem); } //Update instruction memory interface diff --git a/build_model/cv32e40x/verilator_support_cv32e40x.cpp b/build_model/cv32e40x/verilator_support_cv32e40x.cpp index 6cc8b6d..1fa5b47 100644 --- a/build_model/cv32e40x/verilator_support_cv32e40x.cpp +++ b/build_model/cv32e40x/verilator_support_cv32e40x.cpp @@ -124,7 +124,7 @@ void update_mem_load(uint32_t address, bool req_valid, uint32_t mem_w, uint32_t queue_data[0][i] |= mem[address+i]; } } - + queue_valid[0] = valid; queue_err[0] = !valid; } @@ -143,7 +143,7 @@ void update_mem_load(uint32_t address, bool req_valid, uint32_t mem_w, uint32_t * * *mem - pointer to memory space */ -void update_mem_write(uint32_t address, bool req_valid, uint32_t mem_w, uint32_t mem_lat, uint32_t mem_size, unsigned char *model_data_o, unsigned char *model_be_o, bool *queue_valid, unsigned char *mem){ +void update_mem_write(uint32_t address, bool req_valid, uint32_t mem_w, uint32_t mem_lat, uint32_t mem_size, unsigned char *model_data_o, unsigned char *model_be_o, bool *queue_valid, bool *queue_err, unsigned char *mem){ if (req_valid) { if (address < mem_size) { @@ -158,7 +158,8 @@ void update_mem_write(uint32_t address, bool req_valid, uint32_t mem_w, uint32_t { fprintf(stderr, "ERROR: WRITE ATTEMPTED OUTSIDE OF VALID ADDRESS SPACE\n"); } - //queue_valid[mem_lat-1] = true; //need to signal valid on store interface for accepted transaction. Can always respond in 1 cycle due to store buffer + queue_valid[mem_lat-1] = true; //need to signal valid on store interface for accepted transaction. Can always respond in 1 cycle due to store buffer + queue_err[mem_lat-1] = false; } } diff --git a/build_model/cv32e40x/verilator_support_cv32e40x.h b/build_model/cv32e40x/verilator_support_cv32e40x.h index 201c6e5..7bc7ffb 100644 --- a/build_model/cv32e40x/verilator_support_cv32e40x.h +++ b/build_model/cv32e40x/verilator_support_cv32e40x.h @@ -127,7 +127,7 @@ void update_mem_load(uint32_t address, bool req_valid, uint32_t mem_w, uint32_t * * *mem - pointer to memory space */ -void update_mem_write(uint32_t address, bool req_valid, uint32_t mem_w, uint32_t mem_lat, uint32_t mem_size, unsigned char *model_data_o, unsigned char *model_be_o, bool *queue_valid, unsigned char *mem); +void update_mem_write(uint32_t address, bool req_valid, uint32_t mem_w, uint32_t mem_lat, uint32_t mem_size, unsigned char *model_data_o, unsigned char *model_be_o, bool *queue_valid, bool *queue_err, unsigned char *mem); /* * Check for a write to memory mapped io. Returns true and copies written data to *data_out if a valid write occurs to the selected address From c4878b18af424ad3d168f6bc661ee00648dd3fe2 Mon Sep 17 00:00:00 2001 From: Melvin John Date: Fri, 17 Apr 2026 00:00:51 +0200 Subject: [PATCH 16/18] Fixed cv32 alignment issue --- build_model/cv32e40x/vproc_top.sv | 6 +- wavefrom_debug_lsu_extension.gtkw | 63 +- wavefrom_debug_lsu_extension_instr.gtkw | 1024 ++++++++++++++++ wavefrom_debug_lsu_extension_revamp.gtkw | 1110 ++++++++++++++++++ wavefrom_debug_lsu_extension_revamp_256.gtkw | 966 +++++++++++++++ 5 files changed, 3149 insertions(+), 20 deletions(-) create mode 100644 wavefrom_debug_lsu_extension_instr.gtkw create mode 100644 wavefrom_debug_lsu_extension_revamp.gtkw create mode 100644 wavefrom_debug_lsu_extension_revamp_256.gtkw diff --git a/build_model/cv32e40x/vproc_top.sv b/build_model/cv32e40x/vproc_top.sv index 480265f..292900c 100644 --- a/build_model/cv32e40x/vproc_top.sv +++ b/build_model/cv32e40x/vproc_top.sv @@ -834,7 +834,7 @@ module vproc_top import vproc_pkg::*, obi_pkg::*; #( // TODO: data_req_id[0] = ; for cva core `ifdef FORCE_ALIGNED_READS - data_addr[0] = {sdata_addr[31:2], 2'b00}; + data_addr[0] = {sdata_addr[31:$clog2(VMEM_W/8)], {$clog2(VMEM_W/8){1'b0}}}; data_be[0] = {{(VMEM_W-32){1'b0}}, sdata_be} << (sdata_addr[$clog2(VMEM_W/8)-1:0] & {{$clog2(VMEM_W/32){1'b1}}, 2'b00}); data_wdata[0] = '0; for (int i = 0; i < VMEM_W / 32; i++) begin @@ -868,7 +868,7 @@ module vproc_top import vproc_pkg::*, obi_pkg::*; #( vproc_queue #( - .WIDTH ( 1 ), + .WIDTH ( $bits(sdata_wait_addr) ), .DEPTH ( 2 ), // cv32 is configured to send out max 2 requests as default .FLOW ( 1'b1 ) ) s_wait_id_queue ( @@ -878,7 +878,7 @@ module vproc_top import vproc_pkg::*, obi_pkg::*; #( .enq_ready_o ( ), .enq_valid_i ( sdata_gnt ), .enq_data_i ( sdata_addr ), - .deq_ready_i ( sdata_rvalid ), + .deq_ready_i ( sdata_rvalid ), .deq_valid_o ( sdata_waiting ), .deq_data_o ( sdata_wait_addr ), .flags_any_o ( ), diff --git a/wavefrom_debug_lsu_extension.gtkw b/wavefrom_debug_lsu_extension.gtkw index 7e8e4e3..bb33d69 100644 --- a/wavefrom_debug_lsu_extension.gtkw +++ b/wavefrom_debug_lsu_extension.gtkw @@ -1,15 +1,15 @@ [*] [*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI -[*] Wed Apr 15 16:30:49 2026 +[*] Wed May 6 22:08:58 2026 [*] -[dumpfile] "/home/vboxuser/Desktop/vicuna2_unit_testing/build_tests/build/Testing/last_test_sig.vcd" -[dumpfile_mtime] "Wed Apr 15 16:30:30 2026" -[dumpfile_size] 327078153 +[dumpfile] "/home/vboxuser/Desktop/vicuna2_unit_testing/debug/vsseg2e8_v0_small.vcd" +[dumpfile_mtime] "Wed May 6 21:27:05 2026" +[dumpfile_size] 57897438 [savefile] "/home/vboxuser/Desktop/vicuna2_unit_testing/wavefrom_debug_lsu_extension.gtkw" -[timestart] 697 +[timestart] 27945 [size] 1848 902 [pos] -1 -1 -*-4.945512 745 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +*-4.945512 28000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 [treeopen] TOP. [treeopen] TOP.vproc_top. [treeopen] TOP.vproc_top.v_core. @@ -41,7 +41,6 @@ [treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_red. [treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ctrl_i.mode. [treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_out_ctrl_o. -[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack. [treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk4[0]. [treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk6[2]. [treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[0]. @@ -72,7 +71,7 @@ [sst_width] 379 [signals_width] 646 [sst_expanded] 1 -[sst_vpaned_height] 271 +[sst_vpaned_height] 237 @28 TOP.vproc_top.clk_i @800200 @@ -162,6 +161,10 @@ TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.rdata_stri_vdmsk @200 -write +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ctrl_i.vl_0 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ctrl_i.vl_part[1:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ctrl_i.vl_part_0 @22 [color] 7 TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.wdata_buf_q[31:0] @@ -252,9 +255,8 @@ TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[31][127:0] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.clk_i @200 -scratch_state_q -@29 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_state_q.current_eew[1:0] @28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_state_q.current_eew[1:0] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_state_q.fsm_state[2:0] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_state_q.store_end_index[0] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_state_q.write_index[0] @@ -339,10 +341,6 @@ TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.mem_req_switch @200 -port_queue -@28 -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.port_queue_ready_out[0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.port_queue_valid_out[0] -TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.port_queue_ready_in[0] @22 TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.port_queue_rdata_out[0][31:0] @28 @@ -390,6 +388,20 @@ TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[0].wdata[31:0] @200 -obi_port_1 +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[1].req +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[1].gnt +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[1].rvalid +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[1].addr[31:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[1].be[3:0] +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[1].we +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[1].err +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[1].rdata[31:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[1].wdata[31:0] +@200 -obi_port_2 -state_req_red_i @22 @@ -434,6 +446,8 @@ TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk @22 TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.rdata_buf_q[31:0] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.rdata_buf_d[31:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.rmask_buf_d[3:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.rmask_buf_q[3:0] @200 -general @28 @@ -745,6 +759,10 @@ TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.op_load[2:0] [color] 2 TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.vreg_pend_rd_o[31:0] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack_pend_rd[31:0] +@200 +-ctrl +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack_ctrl.vl_part_0 @c00200 -instr_state @28 @@ -851,8 +869,9 @@ TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.clk_i TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.op_addressing[2:0] @200 -field_op -@22 +@23 TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.field_buffer_next[0][127:0] +@22 TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.field_buffer_next[1][127:0] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.field_buffer_next[2][127:0] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.field_buffer_next[3][127:0] @@ -913,7 +932,7 @@ TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.op_xval[1][31:0] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.op_xval[2][31:0] @1000200 -unpack -@c00200 +@800200 -pack @200 -pack @@ -995,7 +1014,7 @@ TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.genblk1[0].genblk1.re @28 [color] 6 TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.vreg_wr_ready_i -@1401200 +@1000200 -pack @c00200 -unit_wrapper @@ -1074,3 +1093,13 @@ TOP.vproc_top.host_xif.issue_req.rs[2][31:0] TOP.vproc_top.host_xif.issue_req.instr[31:0] [pattern_trace] 1 [pattern_trace] 0 +!100000@@ +?01 +@29 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_red.mode.store +?00 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_red.suppressed +?"7DA0 +@23 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_red.req_addr_q[31:0] +!! diff --git a/wavefrom_debug_lsu_extension_instr.gtkw b/wavefrom_debug_lsu_extension_instr.gtkw new file mode 100644 index 0000000..bfbb816 --- /dev/null +++ b/wavefrom_debug_lsu_extension_instr.gtkw @@ -0,0 +1,1024 @@ +[*] +[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI +[*] Fri May 15 11:29:57 2026 +[*] +[dumpfile] "/home/vboxuser/Desktop/vicuna2_unit_testing/build_tests/build/Testing/last_test_sig.vcd" +[dumpfile_mtime] "Fri May 15 11:29:44 2026" +[dumpfile_size] 142132414 +[savefile] "/home/vboxuser/Desktop/vicuna2_unit_testing/wavefrom_debug_lsu_extension_instr.gtkw" +[timestart] 1 +[size] 1848 902 +[pos] -1 -1 +*-4.945512 32 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[treeopen] TOP. +[treeopen] TOP.vproc_top. +[treeopen] TOP.vproc_top.v_core. +[treeopen] TOP.vproc_top.v_core.dec.mode_o. +[treeopen] TOP.vproc_top.v_core.dec_data_q.mode. +[treeopen] TOP.vproc_top.v_core.genblk9[0]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.alt_count_next_inc. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.count_next_inc. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.genblk1[0]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.genblk1[0].genblk1. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pipe_in_state_i.mode. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_next.alt_count. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_next.count. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_next.mode. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_q.alt_count. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_q.count. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_q.mode. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.genblk3[0]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_red. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ctrl_i.mode. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_out_ctrl_o. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk4[0]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk6[2]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[0]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[0].genblk1[0]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[1]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[1].genblk1[0]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[2]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[2].genblk1[0]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[3]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[3].genblk1[0]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[4]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[4].genblk1[0]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack_out_ctrl.mode. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.pipe_in_data_i.mode. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.state_init.mode. +[treeopen] TOP.vproc_top.v_core.genblk9[1].pipe. +[treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2. +[treeopen] TOP.vproc_top.v_core.pipe_instr_data.mode. +[treeopen] TOP.vproc_top.v_core.queue_data_d.mode. +[treeopen] TOP.vproc_top.v_core.queue_data_q.mode. +[treeopen] TOP.vproc_top.v_core.queue_pending_wr.mode_i.alu. +[treeopen] TOP.vproc_top.v_core.vregfile. +[treeopen] TOP.vproc_top.v_core.vregfile.genblk1[0]. +[treeopen] TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1. +[treeopen] TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0]. +[treeopen] TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[1]. +[treeopen] TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[2]. +[sst_width] 379 +[signals_width] 646 +[sst_expanded] 1 +[sst_vpaned_height] 237 +@28 +TOP.vproc_top.clk_i +@200 +- +@28 +TOP.vproc_top.imem_req +TOP.vproc_top.imem_gnt +TOP.vproc_top.imem_rvalid +TOP.vproc_top.imem_err +@22 +TOP.vproc_top.imem_addr[31:0] +@23 +TOP.vproc_top.imem_rdata[63:0] +@200 +- +@28 +TOP.vproc_top.instr_req +TOP.vproc_top.instr_gnt +TOP.vproc_top.instr_err +TOP.vproc_top.instr_rvalid +@22 +TOP.vproc_top.instr_addr[31:0] +TOP.vproc_top.instr_wait_addr[31:0] +TOP.vproc_top.instr_rdata[31:0] +@200 +- +@28 +TOP.vproc_top.i_wait_id_queue.enq_ready_o +TOP.vproc_top.i_wait_id_queue.enq_valid_i +TOP.vproc_top.i_wait_id_queue.deq_ready_i +TOP.vproc_top.i_wait_id_queue.deq_valid_o +TOP.vproc_top.i_wait_id_queue.full +TOP.vproc_top.i_wait_id_queue.empty +TOP.vproc_top.i_wait_id_queue.push +TOP.vproc_top.i_wait_id_queue.wr_pos_q[0] +TOP.vproc_top.i_wait_id_queue.wr_pos_d[0] +TOP.vproc_top.i_wait_id_queue.async_rst_ni +TOP.vproc_top.i_wait_id_queue.sync_rst_ni +@800200 +-lsu +@200 +-lsu +-input +@28 +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_valid_i +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ready_o +@22 +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.vreg_pend_rd_i[31:0] +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_op1_i[31:0] +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.vreg_pend_rd_i[31:0] +@200 +-output +@28 +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pending_load_o +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pending_store_o +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_out_valid_o +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_out_pend_clr_o +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_out_ctrl_o.res_store +@200 +-general +@28 +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ctrl_i.mode.lsu.nfields[2:0] +@100000028 +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ctrl_i.mode.lsu.eew[1:0] +@28 +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ctrl_i.mode.lsu.masked +@100000028 +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ctrl_i.mode.lsu.stride[1:0] +@22 +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ctrl_i.xval[31:0] +@28 +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.trans_complete_valid_o +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ctrl_i.init_addr +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ctrl_i.vl_0 +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ctrl_i.mode.lsu.alt_count_lsu_use +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ctrl_i.mode.lsu.alt_eew[1:0] +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ctrl_i.mode.lsu.alt_emul[1:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.VLSU_FLAGS[0] +@200 +-read +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.req_addr_q[0][31:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.req_addr_q[1][31:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.req_addr_q[2][31:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.req_addr_q[3][31:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.req_addr_q[4][31:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.req_addr_q[5][31:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.req_addr_q[6][31:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.req_addr_q[7][31:0] +@28 +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.rdata_stri_vdmsk +@200 +-write +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ctrl_i.vl_0 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ctrl_i.vl_part_0 +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.wdata_stri_mask +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.req_suppress +@200 +-state_rdata_q +-pipe_out_ctrl_o +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_out_ctrl_o.res_vaddr[4:0] +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_out_ctrl_o.first_cycle +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_out_ctrl_o.last_cycle +@1000200 +-lsu +@800200 +-registers +@200 +-registers +@22 +[color] 5 +TOP.vproc_top.v_core.csr_vl_o[31:0] +[color] 5 +TOP.vproc_top.v_core.vregfile.rd_addr_i[0][4:0] +[color] 5 +TOP.vproc_top.v_core.vregfile.rd_addr_i[1][4:0] +[color] 5 +TOP.vproc_top.v_core.vregfile.rd_data_o[0][127:0] +[color] 5 +TOP.vproc_top.v_core.vregfile.rd_data_o[1][127:0] +@28 +[color] 5 +TOP.vproc_top.v_core.vregfile.wr_we_i[0] +@22 +[color] 5 +TOP.vproc_top.v_core.vregfile.wr_be_i[0][15:0] +[color] 5 +TOP.vproc_top.v_core.vregfile.wr_addr_i[0][4:0] +[color] 5 +TOP.vproc_top.v_core.vregfile.wr_data_i[0][127:0] +@800200 +-RAM +@200 +-ram +@22 +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[0][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[1][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[2][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[3][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[4][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[5][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[6][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[7][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[8][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[9][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[10][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[11][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[12][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[13][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[14][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[15][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[16][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[17][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[18][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[19][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[20][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[21][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[22][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[23][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[24][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[25][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[26][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[27][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[28][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[29][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[30][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[31][127:0] +@1000200 +-RAM +-registers +@800200 +-lsu_extension +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.clk_i +@200 +-scratch_state_q +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_state_q.current_eew[1:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_state_q.fsm_state[2:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_state_q.store_end_index[0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_state_q.write_index[0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_state_q.misalignment_request +@200 +-scratch_state_d +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_state_d.fsm_state[2:0] +@200 +-port_state_q +-scratch_memory +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.misalignment_request +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_memory_state_q[0][1:0] +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_memory_q[0].addr[31:0] +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_memory_q[0].pending_req_cnt[2:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_memory_state_q[1][1:0] +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_memory_q[1].addr[31:0] +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_memory_q[1].pending_req_cnt[2:0] +@200 +-scratch_memory_d +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_memory_state_d[0][1:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_memory_d[0].pending_req_cnt[2:0] +@200 +-scratch_pending +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_hit +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_pending +#{scratch_pending_index[1:0]} TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_pending_index[0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_pending_req_cleared +#{scratch_queue_pending_index_out[1:0]} TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_queue_pending_index_out[0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_queue_pending_out +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.misalignment_request_out +@200 +-input_queue +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.input_queue.empty +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.input_queue_ready_in +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.input_queue_ready_out +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.input_queue_valid_out +@200 +-output_queue +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.output_queue_ready_in +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.output_queue_ready_out +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.output_queue_valid_out +@200 +-mem_req_queue +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.mem_req_queue_ready_out +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.mem_req_queue_valid_in +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.mem_req_queue_valid_out +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.mem_req_switch +@200 +-port_queue +@28 +#{port_queue_write_index_out[0][1:0]} TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.port_queue_write_index_out[0][0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.genblk3[0].port_queue.enq_valid_i +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.genblk3[0].port_write_index_queue.enq_valid_i +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.genblk3[0].port_write_index_queue.enq_ready_o +@200 +-vtop +@28 +TOP.vproc_top.clk_i +TOP.vproc_top.vdata_req[0] +TOP.vproc_top.vdata_gnt[0] +TOP.vproc_top.data_rvalid[0] +TOP.vproc_top.vdata_rvalid[0] +TOP.vproc_top.mem_req_o[0] +TOP.vproc_top.mem_rvalid_i[0] +@22 +TOP.vproc_top.mem_addr_o[0][31:0] +@28 +TOP.vproc_top.mem_we_o[0] +TOP.vproc_top.sdata_req +TOP.vproc_top.sdata_rvalid +@22 +TOP.vproc_top.sdata_rdata[31:0] +@200 +-obi_port_0 +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[0].req +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[0].gnt +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[0].rvalid +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[0].addr[31:0] +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[0].we +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[0].err +@200 +-obi_port_1 +-obi_port_2 +-state_req_red_i +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_red_i.res_vaddr[4:0] +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_red_i.res_store +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_red_i.id[3:0] +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_red_i.state_req_valid_q +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_red_i.req_addr_q[31:0] +@200 +-state_req_red +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_red.mode.eew[1:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_red.first_cycle +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_red.last_cycle +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_red.req_addr_q[31:0] +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_red.field_counter[2:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_red.field_init_count[2:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_red.suppressed +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_red.mode.store +@200 +-deq_state +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.deq_state.id[3:0] +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.deq_state.first_cycle +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.deq_state.last_cycle +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.deq_state.field_counter[2:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.deq_state.field_init_count[2:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.deq_state.suppressed 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+TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.unit_queue_enq_valid +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.unit_queue_deq_unit[2:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.unit_queue_deq_unit_vector[2:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.pipe_out_valid_o +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.pipe_out_ready_i +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.pipe_out_instr_done_o +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.unit_out_instr_done[6:0] +@1401200 +-unit_mux +@22 +TOP.vproc_top.host_xif.issue_req.rs[0][31:0] +TOP.vproc_top.host_xif.issue_req.rs[1][31:0] +TOP.vproc_top.host_xif.issue_req.rs[2][31:0] +TOP.vproc_top.host_xif.issue_req.instr[31:0] +[pattern_trace] 1 +[pattern_trace] 0 diff --git a/wavefrom_debug_lsu_extension_revamp.gtkw b/wavefrom_debug_lsu_extension_revamp.gtkw new file mode 100644 index 0000000..f1a81bd --- /dev/null +++ b/wavefrom_debug_lsu_extension_revamp.gtkw @@ -0,0 +1,1110 @@ +[*] +[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI +[*] Thu May 7 10:29:26 2026 +[*] +[dumpfile] "/home/vboxuser/Desktop/vicuna2_unit_testing/build_tests/build/Testing/last_test_sig.vcd" +[dumpfile_mtime] "Thu May 7 10:25:59 2026" +[dumpfile_size] 256824773 +[savefile] "/home/vboxuser/Desktop/vicuna2_unit_testing/wavefrom_debug_lsu_extension_revamp.gtkw" +[timestart] 1121 +[size] 1848 902 +[pos] -1 -1 +*-4.945512 1183 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[treeopen] TOP. +[treeopen] TOP.vproc_top. +[treeopen] TOP.vproc_top.v_core. +[treeopen] TOP.vproc_top.v_core.dec.mode_o. +[treeopen] TOP.vproc_top.v_core.dec_data_q.mode. +[treeopen] TOP.vproc_top.v_core.genblk9[0]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.alt_count_next_inc. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.count_next_inc. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.genblk1[0]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.genblk1[0].genblk1. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pipe_in_state_i.mode. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_next.alt_count. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_next.count. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_next.mode. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_q.alt_count. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_q.count. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_q.mode. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.deq_state. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.genblk3[0]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_red. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ctrl_i.mode. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_out_ctrl_o. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.state_rdata. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk4[0]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk6[2]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[0]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[0].genblk1[0]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[1]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[1].genblk1[0]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[2]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[2].genblk1[0]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[3]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[3].genblk1[0]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[4]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[4].genblk1[0]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack_out_ctrl.mode. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.pipe_in_data_i.mode. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.state_init.mode. +[treeopen] TOP.vproc_top.v_core.genblk9[1].pipe. +[treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2. +[treeopen] TOP.vproc_top.v_core.pipe_instr_data.mode. +[treeopen] TOP.vproc_top.v_core.queue_data_d.mode. +[treeopen] TOP.vproc_top.v_core.queue_data_q.mode. +[treeopen] TOP.vproc_top.v_core.queue_pending_wr.mode_i.alu. +[treeopen] TOP.vproc_top.v_core.vregfile. +[treeopen] TOP.vproc_top.v_core.vregfile.genblk1[0]. +[treeopen] TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1. +[treeopen] TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0]. +[treeopen] TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[1]. +[treeopen] TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[2]. +[sst_width] 379 +[signals_width] 646 +[sst_expanded] 1 +[sst_vpaned_height] 237 +@28 +TOP.vproc_top.clk_i +@800200 +-lsu +@200 +-lsu +-input +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_out_ready_i +[color] 7 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+TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.wdata_buf_q[1][31:0] +@200 +-output +@28 +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pending_load_o +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pending_store_o +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_out_pend_clr_o +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_out_ctrl_o.res_store +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_out_res_o[0][63:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_out_res_o[1][63:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_out_mask_o[0][7:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_out_mask_o[1][7:0] +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_out_valid_o[1:0] +@800022 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.pipe_out_res_valid_o[7:0] +@28 +(0)TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.pipe_out_res_valid_o[7:0] +(1)TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.pipe_out_res_valid_o[7:0] +(2)TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.pipe_out_res_valid_o[7:0] +(3)TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.pipe_out_res_valid_o[7:0] +(4)TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.pipe_out_res_valid_o[7:0] +(5)TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.pipe_out_res_valid_o[7:0] +(6)TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.pipe_out_res_valid_o[7:0] +(7)TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.pipe_out_res_valid_o[7:0] +@1001200 +-group_end +@200 +-general +@28 +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ctrl_i.mode.lsu.nfields[2:0] +@100000028 +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ctrl_i.mode.lsu.eew[1:0] +@28 +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ctrl_i.mode.lsu.masked +@100000028 +[color] 7 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+TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[18][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[19][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[20][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[21][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[22][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[23][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[24][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[25][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[26][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[27][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[28][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[29][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[30][127:0] +TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0].ram[31][127:0] +@1000200 +-RAM +@1401200 +-registers +@800200 +-lsu_extension +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.clk_i +@200 +-scratch_state_q +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_state_q.current_eew[1:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_state_q.fsm_state[2:0] +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_state_q.id[3:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_state_q.misalignment_data[0][31:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_state_q.misalignment_data[1][31:0] +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_state_q.misalignment_request_in[1:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_state_q.misalignment_request_out[1:0] +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_state_q.outstanding_mem_req_cnt[3:0] +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_state_q.store +@200 +-scratch_state_d +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_state_d.fsm_state[2:0] +@200 +-port_state_q +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.port_state_q.portq_elem_cnt[0][1:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.port_state_q.portq_elem_cnt[1][1:0] +@200 +-input_queue +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.input_queue.empty +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.input_queue_ready_in +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.input_queue_ready_out +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.input_queue_valid_out +@200 +-output_queue +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.output_queue_ready_in +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.output_queue_ready_out +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.output_queue_valid_out +@200 +-mem_req_queue +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.mem_req_switch +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.mem_req_queue_ready_in[1:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.mem_req_queue_ready_out[1:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.mem_req_queue_valid_in[1:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.mem_req_queue_valid_out[1:0] +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.mem_req_queue_data_in[0].wdata[31:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.mem_req_queue_data_in[1].wdata[31:0] +@200 +-port_queue +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.port_queue_rdata_out[0][31:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.port_queue_rdata_out[1][31:0] +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.port_queue_valid_out[1:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.port_queue_ready_in[1:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.port_pending_select[0][0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.port_pending_select[1][0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.port_pending_data_off[0][1:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.port_pending_data_off[1][1:0] +@200 +-vtop +@28 +TOP.vproc_top.clk_i +TOP.vproc_top.vdata_req[0] +TOP.vproc_top.vdata_gnt[0] +TOP.vproc_top.data_rvalid[0] +TOP.vproc_top.vdata_rvalid[0] +TOP.vproc_top.mem_req_o[0] +TOP.vproc_top.mem_rvalid_i[0] +@22 +TOP.vproc_top.mem_addr_o[0][31:0] +TOP.vproc_top.mem_be_o[0][3:0] +@28 +TOP.vproc_top.mem_we_o[0] +@22 +TOP.vproc_top.mem_wdata_o[0][31:0] +TOP.vproc_top.mem_rdata_i[0][31:0] +@28 +TOP.vproc_top.sdata_req +TOP.vproc_top.sdata_rvalid +@22 +TOP.vproc_top.sdata_rdata[31:0] +@200 +-obi_port_0 +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[0].req +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[0].gnt +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[0].rvalid +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[0].addr[31:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[0].be[3:0] +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[0].we +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[0].err +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[0].rdata[31:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[0].wdata[31:0] +@200 +-obi_port_1 +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[1].req +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[1].gnt +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[1].rvalid +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[1].addr[31:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[1].be[3:0] +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[1].we +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[1].err +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[1].rdata[31:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[1].wdata[31:0] +@200 +-obi_port_2 +-state_req_red_i +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_red_i.res_vaddr[4:0] +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_red_i.res_store +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_red_i.id[3:0] +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_red_i.state_req_valid_q +@200 +-state_req_red +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_red.req_addr_q[0][31:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_red.req_addr_q[1][31:0] +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_red.mem_req_valid[1:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_red.mode.eew[1:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_red.first_cycle +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_red.last_cycle +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_red.field_init_count[2:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_red.mode.store +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_red.wdata_buf_q[0][31:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_red.wdata_buf_q[1][31:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_red.wmask_buf_q[0][3:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_red.wmask_buf_q[1][3:0] +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_red.suppressed[1:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.misalignment_request[1:0] +@200 +-output_signals +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.clk_i +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.all_ports_finished +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.deq_state_end_of_field +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.misalignment_request_out[1:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.misalignment_request_out_any +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.misalignment_request_finished +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.rdata_buf_d[0][31:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.rdata_buf_d[1][31:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.rdata_buf_q[0][31:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.rdata_buf_q[1][31:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.rmask_buf_d[0][3:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.rmask_buf_d[1][3:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.rmask_buf_q[0][3:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.rmask_buf_q[1][3:0] +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.port_queue_pending_select_out[0][0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.port_queue_pending_select_out[1][0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.port_queue_pending_data_off[0][1:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.port_queue_pending_data_off[1][1:0] +@200 +-deq_state +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.deq_state.id[3:0] +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.deq_state.first_cycle +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.deq_state.last_cycle +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.deq_state.field_init_count[2:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_rdata_valid_q +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_rdata_valid_d +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.deq_state.mem_req_valid[1:0] +@200 +-general +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_ready +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_stall +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.pending_req_stall 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+TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.unit_out_ready[6:0] +@1000200 +-unit_mux +@22 +TOP.vproc_top.host_xif.issue_req.rs[0][31:0] +TOP.vproc_top.host_xif.issue_req.rs[1][31:0] +TOP.vproc_top.host_xif.issue_req.rs[2][31:0] +TOP.vproc_top.host_xif.issue_req.instr[31:0] +[pattern_trace] 1 +[pattern_trace] 0 +!100000@@ +?"20D90 +@23 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_red.req_addr_q[0][31:0] +!! diff --git a/wavefrom_debug_lsu_extension_revamp_256.gtkw b/wavefrom_debug_lsu_extension_revamp_256.gtkw new file mode 100644 index 0000000..38f9131 --- /dev/null +++ b/wavefrom_debug_lsu_extension_revamp_256.gtkw @@ -0,0 +1,966 @@ +[*] +[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI +[*] Thu May 7 20:06:32 2026 +[*] +[dumpfile] "/home/vboxuser/Desktop/vicuna2_unit_testing/build_tests/build/Testing/last_test_sig.vcd" +[dumpfile_mtime] "Thu May 7 14:05:43 2026" +[dumpfile_size] 447294111 +[savefile] "/home/vboxuser/Desktop/vicuna2_unit_testing/wavefrom_debug_lsu_extension_revamp_256.gtkw" +[timestart] 10705 +[size] 1848 902 +[pos] -1 -1 +*-4.945512 10762 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[treeopen] TOP. +[treeopen] TOP.vproc_top. +[treeopen] TOP.vproc_top.v_core. +[treeopen] TOP.vproc_top.v_core.dec.mode_o. +[treeopen] TOP.vproc_top.v_core.dec_data_q.mode. +[treeopen] TOP.vproc_top.v_core.genblk9[0]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.alt_count_next_inc. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.count_next_inc. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.genblk1[0]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.genblk1[0].genblk1. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pipe_in_state_i.mode. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_next.alt_count. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_next.count. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_next.mode. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_q.alt_count. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_q.count. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.state_q.mode. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.deq_state. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.genblk3[0]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_red. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ctrl_i.mode. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_out_ctrl_o. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.state_rdata. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk4[0]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk6[2]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[0]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[0].genblk1[0]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[1]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[1].genblk1[0]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[2]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[2].genblk1[0]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[3]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[3].genblk1[0]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[4]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack.genblk7[4].genblk1[0]. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unpack_out_ctrl.mode. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.pipe_in_data_i.mode. +[treeopen] TOP.vproc_top.v_core.genblk9[0].pipe.state_init.mode. +[treeopen] TOP.vproc_top.v_core.genblk9[1].pipe. +[treeopen] TOP.vproc_top.v_core.genblk9[1].pipe.genblk2. +[treeopen] TOP.vproc_top.v_core.pipe_instr_data.mode. +[treeopen] TOP.vproc_top.v_core.queue_data_d.mode. +[treeopen] TOP.vproc_top.v_core.queue_data_q.mode. +[treeopen] TOP.vproc_top.v_core.queue_pending_wr.mode_i.alu. +[treeopen] TOP.vproc_top.v_core.vregfile. +[treeopen] TOP.vproc_top.v_core.vregfile.genblk1[0]. +[treeopen] TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1. +[treeopen] TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[0]. +[treeopen] TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[1]. +[treeopen] TOP.vproc_top.v_core.vregfile.genblk1[0].genblk1.genblk1[2]. +[sst_width] 379 +[signals_width] 646 +[sst_expanded] 1 +[sst_vpaned_height] 237 +@28 +TOP.vproc_top.clk_i +@800200 +-lsu +@200 +-lsu +-input +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_out_ready_i +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_valid_i +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ready_o +@22 +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.vreg_pend_rd_i[31:0] +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.vreg_pend_rd_i[31:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.wdata_buf_q[0][31:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.wdata_buf_q[1][31:0] +@200 +-output +@28 +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pending_load_o +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pending_store_o +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_out_pend_clr_o +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_out_ctrl_o.res_store +@800022 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.pipe_out_res_valid_o[7:0] +@28 +(0)TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.pipe_out_res_valid_o[7:0] +(1)TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.pipe_out_res_valid_o[7:0] +(2)TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.pipe_out_res_valid_o[7:0] +(3)TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.pipe_out_res_valid_o[7:0] +(4)TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.pipe_out_res_valid_o[7:0] +(5)TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.pipe_out_res_valid_o[7:0] +(6)TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.pipe_out_res_valid_o[7:0] +(7)TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.pipe_out_res_valid_o[7:0] +@1001200 +-group_end +@200 +-general +@28 +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ctrl_i.mode.lsu.nfields[2:0] +@100000028 +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ctrl_i.mode.lsu.eew[1:0] +@28 +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ctrl_i.mode.lsu.masked +@100000028 +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ctrl_i.mode.lsu.stride[1:0] +@22 +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ctrl_i.xval[31:0] +@28 +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.trans_complete_valid_o +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ctrl_i.init_addr +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ctrl_i.vl_0 +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ctrl_i.mode.lsu.alt_count_lsu_use +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ctrl_i.mode.lsu.alt_eew[1:0] +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ctrl_i.mode.lsu.alt_emul[1:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.VLSU_FLAGS[0] +@200 +-read +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.rdata_buf[0][31:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.rdata_buf[1][31:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.rdata_unit_vdmsk[0][3:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.rdata_unit_vdmsk[1][3:0] +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.state_rdata.mem_req_vl_part[0][1:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.state_rdata.mem_req_vl_part[1][1:0] +@200 +-addr +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.req_addr_q[0][31:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.req_addr_q[1][31:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.req_addr_q[2][31:0] +@23 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.req_addr_q[3][31:0] +@200 +-write +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ctrl_i.mem_req_vl_part[0][1:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ctrl_i.mem_req_vl_part[1][1:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ctrl_i.mem_req_vl_part[2][1:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ctrl_i.mem_req_vl_part[3][1:0] +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ctrl_i.mem_req_vl_part_0[3:0] +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ctrl_i.vl_part[3:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ctrl_i.vl_part_0 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_in_ctrl_i.mode.lsu.masked +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.wdata_buf_q[0][31:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.wdata_buf_q[1][31:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.wmask_buf_q[0][3:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.wmask_buf_q[1][3:0] +@200 +-state_rdata_q +-pipe_out_ctrl_o +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_out_ctrl_o.res_vaddr[4:0] +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_out_ctrl_o.first_cycle +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.pipe_out_ctrl_o.last_cycle +@1000200 +-lsu +@c00200 +-registers +@200 +-registers +@22 +[color] 5 +TOP.vproc_top.v_core.csr_vl_o[31:0] +[color] 5 +TOP.vproc_top.v_core.vregfile.rd_addr_i[0][4:0] +[color] 5 +TOP.vproc_top.v_core.vregfile.rd_addr_i[1][4:0] +@28 +[color] 5 +TOP.vproc_top.v_core.vregfile.wr_we_i[0] +@22 +[color] 5 +TOP.vproc_top.v_core.vregfile.wr_addr_i[0][4:0] +@800200 +-RAM +@200 +-ram +@1000200 +-RAM +@1401200 +-registers +@800200 +-lsu_extension +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.clk_i +@200 +-scratch_state_q +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_state_q.current_eew[1:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_state_q.fsm_state[2:0] +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_state_q.id[3:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_state_q.misalignment_data[0][31:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_state_q.misalignment_data[1][31:0] +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_state_q.store +@200 +-scratch_state_d +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.scratch_state_d.fsm_state[2:0] +@200 +-port_state_q +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.port_state_q.portq_elem_cnt[0][1:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.port_state_q.portq_elem_cnt[1][1:0] +@200 +-input_queue +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.input_queue.empty +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.input_queue_ready_in +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.input_queue_ready_out +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.input_queue_valid_out +@200 +-output_queue +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.output_queue_ready_in +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.output_queue_ready_out +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.output_queue_valid_out +@200 +-mem_req_queue +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.mem_req_switch +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.mem_req_queue_data_in[0].wdata[31:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.mem_req_queue_data_in[1].wdata[31:0] +@200 +-port_queue +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.port_queue_rdata_out[0][31:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.port_queue_rdata_out[1][31:0] +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.port_pending_data_off[0][1:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.port_pending_data_off[1][1:0] +@200 +-vtop +@28 +TOP.vproc_top.clk_i +TOP.vproc_top.vdata_req[0] +TOP.vproc_top.vdata_gnt[0] +TOP.vproc_top.data_rvalid[0] +TOP.vproc_top.vdata_rvalid[0] +TOP.vproc_top.mem_req_o[0] +TOP.vproc_top.mem_rvalid_i[0] +@22 +TOP.vproc_top.mem_addr_o[0][31:0] +TOP.vproc_top.mem_be_o[0][3:0] +@28 +TOP.vproc_top.mem_we_o[0] +@22 +TOP.vproc_top.mem_wdata_o[0][31:0] +TOP.vproc_top.mem_rdata_i[0][31:0] +@28 +TOP.vproc_top.sdata_req +TOP.vproc_top.sdata_rvalid +@22 +TOP.vproc_top.sdata_rdata[31:0] +@200 +-obi_port_0 +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[0].req +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[0].gnt +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[0].rvalid +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[0].addr[31:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[0].be[3:0] +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[0].we +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[0].err +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[0].rdata[31:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[0].wdata[31:0] +@200 +-obi_port_1 +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[1].req +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[1].gnt +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[1].rvalid +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[1].addr[31:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[1].be[3:0] +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[1].we +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[1].err +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[1].rdata[31:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[1].wdata[31:0] +@200 +-obi_port_2 +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[2].req +@200 +-obi_port_3 +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.obi_bus[3].req +@200 +-state_req_red_i +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_red_i.res_vaddr[4:0] +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_red_i.res_store +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_red_i.id[3:0] +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_red_i.state_req_valid_q +@200 +-state_req_red +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_red.mem_req_valid[3:0] +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_red.req_addr_q[0][31:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_red.req_addr_q[1][31:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_red.req_addr_q[2][31:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_red.req_addr_q[3][31:0] +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_red.mode.eew[1:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_red.first_cycle +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_red.last_cycle +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_red.field_init_count[2:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_red.mode.store +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_red.wdata_buf_q[0][31:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_red.wdata_buf_q[1][31:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_red.wmask_buf_q[0][3:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_red.wmask_buf_q[1][3:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_red.suppressed[3:0] +@200 +-output_signals +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.clk_i +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.all_ports_finished +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.deq_state_end_of_field +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.misalignment_request_out_any +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.misalignment_request_finished +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.rdata_buf_d[0][31:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.rdata_buf_d[1][31:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.rdata_buf_q[0][31:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.rdata_buf_q[1][31:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.rmask_buf_d[0][3:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.rmask_buf_d[1][3:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.rmask_buf_q[0][3:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.rmask_buf_q[1][3:0] +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.port_queue_pending_data_off[0][1:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.port_queue_pending_data_off[1][1:0] +@200 +-deq_state +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.deq_state.id[3:0] +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.deq_state.first_cycle +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.deq_state.last_cycle +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.deq_state.field_init_count[2:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_rdata_valid_q +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_rdata_valid_d +@200 +-general +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_ready +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.state_req_stall +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.pending_req_stall +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.mem_exc_q +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.trans_complete_valid +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.lsu.lsu_extension.trans_complete_valid_o +@1000200 +-lsu_extension +@c00200 +-decoder +@200 +-decoder +@28 +TOP.vproc_top.v_core.dec.instr_valid_i +TOP.vproc_top.v_core.dec.instr_illegal +TOP.vproc_top.v_core.dec.op_illegal +TOP.vproc_top.v_core.dec.vd_invalid +TOP.vproc_top.v_core.dec.vs1_invalid +TOP.vproc_top.v_core.dec.vs2_invalid +TOP.vproc_top.v_core.dec.vtype_invalid +@22 +TOP.vproc_top.v_core.dec.instr_i[31:0] +TOP.vproc_top.v_core.dec.instr_vd[4:0] +TOP.vproc_top.v_core.dec.instr_vs1[4:0] +TOP.vproc_top.v_core.dec.instr_vs2[4:0] +TOP.vproc_top.v_core.dec.x_rs1_i[31:0] +TOP.vproc_top.v_core.dec.x_rs2_i[31:0] +@28 +TOP.vproc_top.v_core.dec.valid_o +@800200 +-rs1 +@200 +-rs1 +@28 +TOP.vproc_top.v_core.dec.rs1_o.xreg +TOP.vproc_top.v_core.dec.rs1_o.vreg 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+TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.RES_W[0][31:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.RES_CNT[31:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.RES_ALLOW_ELEMWISE[7:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.MEM_W[31:0] +@200 +-input +@22 +[color] 6 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.pipe_in_vaddr_i[4:0] +@28 +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.pipe_in_valid_i +[color] 6 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.pipe_in_instr_done_i +[color] 6 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.pipe_in_pend_clr_cnt_i[1:0] +[color] 6 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.pipe_in_pend_clr_i +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.pipe_in_eew_i[1:0] +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.pipe_in_res_valid_i[7:0] +@800200 +-res_data_i[0] +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.pipe_in_res_flags_i[0].elemwise +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.pipe_in_res_flags_i[0].field_instr +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.pipe_in_res_flags_i[0].lsu_instr +@1000200 +-res_data_i[0] +@200 +-output +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.pipe_in_ready_o +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.instr_done_id_o[3:0] +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.instr_done_valid_o +[color] 6 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.vreg_wr_clr_o +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.vreg_wr_valid_o +@22 +[color] 6 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.vreg_wr_addr_o[4:0] +@28 +[color] 6 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.vreg_wr_clr_cnt_o[1:0] +[color] 7 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.stage_ready +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.stage_stall +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.stage_valid_q +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.stage_state_q.pend_clr +[color] 6 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.vreg_wr_ready_i +@1000200 +-pack +@c00200 +-unit_wrapper +@200 +-Unit_wrapper +@22 +[color] 1 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.pipe_out_vaddr_o[4:0] +[color] 1 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.genblk1[0].genblk1.unit.genblk1.unit_out_ctrl.res_vaddr[4:0] +@28 +[color] 1 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.pack.vreg_wr_valid_o +@1401200 +-unit_wrapper +@800200 +-core +@200 +-core +@28 +TOP.vproc_top.v_core.queue_push +TOP.vproc_top.v_core.dec_valid +TOP.vproc_top.v_core.dec_buf_valid_q +TOP.vproc_top.v_core.dec_buf_valid_d +TOP.vproc_top.v_core.dec_data_q.mode.cfg.lmul[2:0] +TOP.vproc_top.v_core.instr_state_q[0][1:0] +TOP.vproc_top.v_core.instr_state_q[1][1:0] +TOP.vproc_top.v_core.instr_state_q[2][1:0] +TOP.vproc_top.v_core.instr_state_q[3][1:0] +TOP.vproc_top.v_core.instr_state_q[4][1:0] +TOP.vproc_top.v_core.instr_state_q[5][1:0] +TOP.vproc_top.v_core.instr_state_q[6][1:0] +TOP.vproc_top.v_core.instr_state_q[7][1:0] +TOP.vproc_top.v_core.instr_state_q[8][1:0] +TOP.vproc_top.v_core.instr_state_q[9][1:0] +TOP.vproc_top.v_core.instr_state_q[10][1:0] +TOP.vproc_top.v_core.instr_state_q[11][1:0] +TOP.vproc_top.v_core.instr_state_q[12][1:0] +TOP.vproc_top.v_core.instr_state_q[13][1:0] +TOP.vproc_top.v_core.instr_state_q[14][1:0] +TOP.vproc_top.v_core.instr_state_q[15][1:0] +@22 +TOP.vproc_top.v_core.instr_complete_id[0][3:0] +@28 +TOP.vproc_top.v_core.pipe_instr_valid[1:0] +@22 +TOP.vproc_top.v_core.instr_complete_id[1][3:0] +@28 +TOP.vproc_top.v_core.instr_complete_valid[1:0] +@200 +-queue_data_d +@28 +TOP.vproc_top.v_core.queue_data_d.mode.lsu.nfields[2:0] +@200 +-queue_data_q +@28 +TOP.vproc_top.v_core.queue_data_q.mode.lsu.nfields[2:0] +@1000200 +-core +@800200 +-unit_mux +@28 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.clk_i +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.unit_queue_enq_ready +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.unit_queue_deq_valid +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.unit_queue_enq_valid +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.unit_queue_deq_unit[2:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.unit_queue_deq_unit_vector[2:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.pipe_out_valid_o +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.pipe_out_ready_i +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.pipe_out_instr_done_o +@22 +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.unit_out_instr_done[6:0] +TOP.vproc_top.v_core.genblk9[0].pipe.genblk2.pipeline.unit_mux.unit_out_ready[6:0] +@1000200 +-unit_mux +@22 +TOP.vproc_top.host_xif.issue_req.rs[0][31:0] +TOP.vproc_top.host_xif.issue_req.rs[1][31:0] +TOP.vproc_top.host_xif.issue_req.rs[2][31:0] +TOP.vproc_top.host_xif.issue_req.instr[31:0] +[pattern_trace] 1 +[pattern_trace] 0 From 9e5a99dfd0938015ceb209cf0190e654d05afb8f Mon Sep 17 00:00:00 2001 From: Melvin John Date: Fri, 15 May 2026 14:00:15 +0200 Subject: [PATCH 17/18] Added alignment for instruction port --- build_model/cv32e40x/verilator_main.cpp | 4 +-- build_model/cv32e40x/vproc_top.sv | 42 ++++++++++++++++++++----- 2 files changed, 36 insertions(+), 10 deletions(-) diff --git a/build_model/cv32e40x/verilator_main.cpp b/build_model/cv32e40x/verilator_main.cpp index b63a8ac..ebeb1c3 100644 --- a/build_model/cv32e40x/verilator_main.cpp +++ b/build_model/cv32e40x/verilator_main.cpp @@ -111,7 +111,7 @@ int main(int argc, char **argv) { //even though known instruction interface width of 32 bits, malloc like this for compatability with memory management helper functions for(int queue_pos = 0; queue_pos < mem_latency; queue_pos++) { - mem_idata_queue[queue_pos] = (unsigned char *)malloc(sizeof(unsigned char) * 32/8); + mem_idata_queue[queue_pos] = (unsigned char *)malloc(sizeof(unsigned char) * mem_w/8); } Vvproc_top *top = new Vvproc_top; @@ -236,7 +236,7 @@ int main(int argc, char **argv) { } //Update instruction memory interface - update_mem_load(top->mem_iaddr_o, top->mem_ireq_o, 32, mem_latency, mem_sz, (unsigned char*)&(top->mem_irdata_i), (bool*)&(top->mem_irvalid_i), (bool*)&(top->mem_ierr_i), mem_idata_queue, mem_ivalid_queue, mem_ierr_queue, mem); + update_mem_load(top->mem_iaddr_o, top->mem_ireq_o, mem_w, mem_latency, mem_sz, (unsigned char*)&(top->mem_irdata_i), (bool*)&(top->mem_irvalid_i), (bool*)&(top->mem_ierr_i), mem_idata_queue, mem_ivalid_queue, mem_ierr_queue, mem); top->eval(); diff --git a/build_model/cv32e40x/vproc_top.sv b/build_model/cv32e40x/vproc_top.sv index 292900c..7ae357a 100644 --- a/build_model/cv32e40x/vproc_top.sv +++ b/build_model/cv32e40x/vproc_top.sv @@ -33,7 +33,7 @@ module vproc_top import vproc_pkg::*, obi_pkg::*; #( output logic [31:0] mem_iaddr_o, input logic mem_irvalid_i, input logic mem_ierr_i, - input logic [32 -1:0] mem_irdata_i + input logic [MEM_W-1:0] mem_irdata_i ); if ((MEM_W & (MEM_W - 1)) != 0 || MEM_W < 32) begin @@ -866,6 +866,23 @@ module vproc_top import vproc_pkg::*, obi_pkg::*; #( assign vdata_gnt[i] = data_gnt[i] & vdata_req[i]; end + vproc_queue #( + .WIDTH ( $bits(instr_wait_addr) ), + .DEPTH ( 2 ), // cv32 is configured to send out max 2 requests as default + .FLOW ( 1'b1 ) + ) i_wait_id_queue ( + .clk_i ( clk_i ), + .async_rst_ni ( rst_ni ), + .sync_rst_ni ( 1'b1 ), // sync_rst_n + .enq_ready_o ( ), + .enq_valid_i ( imem_gnt ), + .enq_data_i ( instr_addr ), + .deq_ready_i ( imem_rvalid ), + .deq_valid_o ( ), + .deq_data_o ( instr_wait_addr ), + .flags_any_o ( ), + .flags_all_o ( ) + ); vproc_queue #( .WIDTH ( $bits(sdata_wait_addr) ), @@ -931,13 +948,22 @@ module vproc_top import vproc_pkg::*, obi_pkg::*; #( logic imem_err; logic i_miss /* verilator public */; logic i_hit /* verilator public */; - - assign imem_req = instr_req; - assign imem_addr = instr_addr; - assign instr_gnt = imem_gnt; - assign instr_rvalid = imem_rvalid; - assign instr_rdata = imem_rdata[31:0]; - assign instr_err = imem_err; + logic [31:0] instr_wait_addr; + + always_comb begin + imem_req = instr_req; + instr_gnt = imem_gnt; + instr_rvalid = imem_rvalid; + instr_err = imem_err; + + `ifdef FORCE_ALIGNED_READS + imem_addr = {instr_addr[31:$clog2(VMEM_W/8)], {$clog2(VMEM_W/8){1'b0}}}; + instr_rdata = imem_rdata[(instr_wait_addr[$clog2(VMEM_W)-1:0] & {3'b000, {($clog2(VMEM_W/8)-2){1'b1}}, 2'b00})*8 +: 32]; + `else + imem_addr = instr_addr; + instr_rdata = imem_rdata[31:0]; + `endif + end // Memory Interface signals D-DATA From e7c398df142d528c47067fd19427a8fef43c86b5 Mon Sep 17 00:00:00 2001 From: Melvin John Date: Fri, 22 May 2026 15:16:47 +0200 Subject: [PATCH 18/18] Added config file --- .gitignore | 2 +- build_model/vector_config.cmake | 5 ++++- build_model/vector_config.cmake_old | 16 ++++++++++++++++ 3 files changed, 21 insertions(+), 2 deletions(-) create mode 100644 build_model/vector_config.cmake_old diff --git a/.gitignore b/.gitignore index 9854a46..0df213c 100644 --- a/.gitignore +++ b/.gitignore @@ -1,4 +1,4 @@ toolchain/* - +debug/* build_model/build/* build_tests/build/* diff --git a/build_model/vector_config.cmake b/build_model/vector_config.cmake index 20e44a3..37c9017 100644 --- a/build_model/vector_config.cmake +++ b/build_model/vector_config.cmake @@ -11,5 +11,8 @@ set(SCALAR_CORE "cv32e40x") set(VMEM_PORTS 1) set(VMEM_W 32) set(VREG_W 128) -set(VPROC_PIPELINES "${VMEM_W}:VLSU 32:VELEM,VSLD,VDIV,VALU,VMUL") + +math(EXPR VMEM_TOTAL_W "${VMEM_PORTS} * ${VMEM_W}") + +set(VPROC_PIPELINES "${VMEM_TOTAL_W}:VLSU 32:VELEM,VSLD,VDIV,VALU,VMUL") diff --git a/build_model/vector_config.cmake_old b/build_model/vector_config.cmake_old new file mode 100644 index 0000000..f90f374 --- /dev/null +++ b/build_model/vector_config.cmake_old @@ -0,0 +1,16 @@ +### +# Set configurations of the system here. This is imported into CMAKE +### + +#Currently Supported: rv32im, rv32im_zve32x, rv32imf, rv32imf_zhf, rv32imf_zve32x, rv32imf_zve32f +set(RISCV_ARCH rv32im_zve32x CACHE STRING "Specify the configuration") + +#Currently Supported: cv32e40x, cv32a60x +set(SCALAR_CORE "cv32e40x") + +set(VMEM_PORTS 1) +set(VMEM_W 32) +set(VREG_W 128) + +set(VPROC_PIPELINES "${VMEM_W}:VLSU 32:VELEM,VSLD,VDIV,VALU,VMUL") +