Currently the padding is set solely based on the architecture assumptions:
|
// Add trailing padding for certain architectures. |
|
// |
|
// - ARM: make sure the entire TBF is a power of 2 to make configuring the |
|
// MPU easy. |
|
// - RISC_V: make sure the entire TBF is a multiple of 4 to meet TBF |
|
// alignment requirements. |
|
// - x86: use 4k padding to match page size. |
|
let trailing_padding = match elf_file.ehdr.e_machine { |
|
elf::abi::EM_ARM => Some(TrailingPadding::TotalSizePowerOfTwo), |
|
elf::abi::EM_RISCV => Some(TrailingPadding::TotalSizeMultiple(4)), |
|
elf::abi::EM_386 => Some(TrailingPadding::TotalSizeMultiple(4096)), |
|
_ => None, |
|
}; |
However these assumptions are not always correct. For instance, in case of RISC-V, the MPU (PMP) might have greater alignment requirements (see tock/tock#4417). This can be kind of worked around by adding something like
.dummy : {
. = ALIGN(4096); /* For 4096 granularity */
} > FLASH
but it also breaks as elf2tbf adds at least 4 bytes for relocation data to the total size.
Currently the padding is set solely based on the architecture assumptions:
elf2tab/src/convert.rs
Lines 192 to 204 in 06b05fd
However these assumptions are not always correct. For instance, in case of RISC-V, the MPU (PMP) might have greater alignment requirements (see tock/tock#4417). This can be kind of worked around by adding something like
but it also breaks as
elf2tbfadds at least 4 bytes for relocation data to the total size.