main.v

`timescale 1ns / 1ps
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// Company: 
// Engineer: 
// 
// Create Date: 08/27/2025 09:12:29 PM
// Design Name: 
// Module Name: main
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module main(
    input SW0,
    input SW1,
    input SW3,
    input SW4,
    input BTNU,
    input BTND,
    input clk,
    output LED0,
    output LED1,
    output LED2,
    output LED3,
    output LED15
    );
    
    // set up registers for blinking LED 
    reg [31:0] counter;
    reg LED15_REG;
    
    // set LEDs to turn on @ required conditions
    assign LED0 =  (SW0 && SW1) ? 1 : 0;
    assign LED1 = (SW3 || SW4) ? 1 : 0;
    assign LED2 = (BTNU ^ BTND) ? 1 : 0;
    assign LED3 = ~(BTNU ^ BTND) ? 1 : 0;
    assign LED15 = LED15_REG;
    
    always @(posedge clk)
    begin
        // magic numbers represent middle & end of duty cycle
        if(counter == 32'b00000101111101011110000011111111) // if counted 100,000,000 positive edges
        begin
            LED15_REG <= 0; // reset LED
            counter <= 0; // reset counter
        end
        else if(counter == 32'b00000010111110101111000010000000) // if counted 50,000,000 positive edges
        begin
            LED15_REG <= 1; // set LED
            counter <= counter + 1; // increment counter
        end
        else
            counter <= counter + 1; // increment counter
        
    end
    
endmodule