diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index cbda1b41d..1a897579a 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -1,16 +1,18 @@ # hvisor Github Actions CI # wheatfox +# +# GitHub: format + license checks only. name: CI on: - push: - branches: - - main - - dev - pull_request: - branches: - - main - - dev + # push: + # branches: + # - main + # - dev + # pull_request: + # branches: + # - main + # - dev workflow_dispatch: env: MODE: debug @@ -29,253 +31,11 @@ jobs: - name: Install Dependencies run: | sudo apt-get update - sudo apt-get install -y qemu-system-aarch64 qemu-system-riscv64 gdb-multiarch llvm-dev libclang-dev wget + sudo apt-get install -y qemu-system-aarch64 qemu-system-riscv64 gdb-multiarch llvm-dev libclang-dev wget python3-venv cargo install --version 0.3.0 --locked cargo-binutils - name: Format Check run: make fmt-test - # this job uses `cargo test` semantics to run unit test exclusively in QEMU - unittest: - name: unittest - runs-on: ubuntu-latest - strategy: - fail-fast: false # continue to run all jobs even if some fail - matrix: - include: - # aarch64 - - arch: aarch64 - board: "qemu-gicv3" - rustc_target: aarch64-unknown-none - - arch: aarch64 - board: "qemu-gicv2" - rustc_target: aarch64-unknown-none - - arch: riscv64 - board: "qemu-plic" - rustc_target: riscv64gc-unknown-none-elf - - arch: riscv64 - board: "qemu-aia" - rustc_target: riscv64gc-unknown-none-elf - steps: - - name: Checkout Repository - uses: actions/checkout@v4 - - name: Install Rust Toolchain - uses: dtolnay/rust-toolchain@stable - with: - targets: ${{ matrix.rustc_target }} - components: rust-src - - name: Setup QEMU from Source - if: matrix.arch == 'riscv64' - uses: ./.github/actions/setup-qemu - with: - qemu-version: "10.1.0" - install-path: "/opt/qemu" - - name: Install Dependencies - run: | - sudo apt-get update - if [ "${{ matrix.arch }}" = "riscv64" ]; then - sudo apt-get install -y gdb-multiarch llvm-dev libclang-dev wget - else - sudo apt-get install -y qemu-system-aarch64 gdb-multiarch llvm-dev libclang-dev wget - fi - cargo install --version 0.3.0 --locked cargo-binutils - - name: Set up environment variables - run: | - echo "ARCH=${{ matrix.arch }}" >> $GITHUB_ENV - echo "BOARD=${{ matrix.board }}" >> $GITHUB_ENV - - name: Unit Test - run: make test - - # this job is for compilation test, it will make sure all aarch64, riscv64, loongarch64 can be compiled successfully - # there is no actual running in this job - build: - name: build - runs-on: ${{ matrix.runs-on }} - strategy: - fail-fast: false - matrix: - include: - # aarch64 - - arch: aarch64 - board: "qemu-gicv3" - rustc_target: aarch64-unknown-none - runs-on: ubuntu-latest - - arch: aarch64 - board: "qemu-gicv2" - rustc_target: aarch64-unknown-none - runs-on: ubuntu-latest - - arch: aarch64 - board: "zcu102" - rustc_target: aarch64-unknown-none - runs-on: ubuntu-latest - - arch: aarch64 - board: "imx8mp" - rustc_target: aarch64-unknown-none - runs-on: ubuntu-latest - - arch: aarch64 - board: "rk3568" - rustc_target: aarch64-unknown-none - runs-on: ubuntu-latest - - arch: aarch64 - board: "rk3588" - rustc_target: aarch64-unknown-none - runs-on: ubuntu-latest - - arch: aarch64 - board: "ok6254-c" - rustc_target: aarch64-unknown-none - runs-on: ubuntu-latest - - arch: aarch64 - board: "phytium-pi" - rustc_target: aarch64-unknown-none - runs-on: ubuntu-latest - - arch: aarch64 - board: "sysoul_x3300" - rustc_target: aarch64-unknown-none - runs-on: ubuntu-latest - # riscv64 - - arch: riscv64 - board: "qemu-aia" - rustc_target: riscv64gc-unknown-none-elf - runs-on: ubuntu-latest - - arch: riscv64 - board: "qemu-plic" - rustc_target: riscv64gc-unknown-none-elf - runs-on: ubuntu-latest - - arch: riscv64 - board: "hifive-premier-p550" - rustc_target: riscv64gc-unknown-none-elf - runs-on: ubuntu-latest - - arch: riscv64 - board: "megrez" - rustc_target: riscv64gc-unknown-none-elf - runs-on: ubuntu-latest - - arch: riscv64 - board: "ur-dp1000" - rustc_target: riscv64gc-unknown-none-elf - runs-on: ubuntu-latest - # loongarch64 - - arch: loongarch64 - board: "ls3a5000" - rustc_target: loongarch64-unknown-none - runs-on: ubuntu-latest - - arch: loongarch64 - board: "ls3a6000" - rustc_target: loongarch64-unknown-none - runs-on: ubuntu-latest - # x86_64 - - arch: x86_64 - board: "qemu" - rustc_target: x86_64-unknown-none - runs-on: ubuntu-latest - - arch: x86_64 - board: "nuc14mnk" - rustc_target: x86_64-unknown-none - runs-on: ubuntu-latest - - arch: x86_64 - board: "ecx-2300f-peg" - rustc_target: x86_64-unknown-none - runs-on: ubuntu-latest - steps: - - name: Checkout Repository - uses: actions/checkout@v4 - - name: Install Rust Toolchain - uses: dtolnay/rust-toolchain@stable - with: - targets: ${{ matrix.rustc_target }} - components: rust-src - - name: Install Dependencies - run: | - sudo apt-get update - sudo apt-get install -y wget - cargo install --version 0.3.0 --locked cargo-binutils - wget -q https://github.com/sunhaiyong1978/CLFS-for-LoongArch/releases/download/8.0/loongarch64-clfs-8.0-cross-tools-gcc-full.tar.xz - tar -xf loongarch64-clfs-8.0-cross-tools-gcc-full.tar.xz - echo "$GITHUB_WORKSPACE/cross-tools/bin" >> $GITHUB_PATH - - name: Set up environment variables - run: | - echo "ARCH=${{ matrix.arch }}" >> $GITHUB_ENV - echo "BOARD=${{ matrix.board }}" >> $GITHUB_ENV - - name: Build - run: make - - # this job is for booting root and nonroot inside qemu for system test - systemtest: - # if: false # we need to update corresponding scripts for the new board abstraction - name: systemtest - runs-on: ${{ matrix.runs-on }} - strategy: - fail-fast: false - matrix: - include: - # aarch64 - - arch: aarch64 - rustc_target: aarch64-unknown-none - board: "qemu-gicv3" - runs-on: ubuntu-22.04 - qemu_version: "9.0.2" - # riscv64 - - arch: riscv64 - rustc_target: riscv64gc-unknown-none-elf - board: "qemu-plic" - runs-on: ubuntu-22.04 - qemu_version: "9.0.2" - # x86_64 - - arch: x86_64 - rustc_target: x86_64-unknown-none - board: "qemu" - runs-on: ["self-hosted", "X64"] - qemu_version: "9.2.3" - # Because other features need to be customized scripts - steps: - - name: Checkout Repository - uses: actions/checkout@v4 - - name: Install Rust Toolchain - uses: dtolnay/rust-toolchain@stable - with: - targets: ${{ matrix.rustc_target }} - components: rust-src - - - name: Setup QEMU from Source - if: matrix.arch != 'x86_64' - uses: ./.github/actions/setup-qemu - with: - qemu-version: ${{ matrix.qemu_version }} - install-path: '/opt/qemu' - - - name: Setup ARM aarch64-none-linux-gnu - if: matrix.arch == 'aarch64' - uses: ./.github/actions/setup-aarch64-none-linux-gnu - with: - version: '10.3-2021.07' - install-path: '/opt/aarch64-none-linux-gnu' - - - name: Setup RISCV riscv64-unknown-linux-gnu - if: matrix.arch == 'riscv64' - uses: ./.github/actions/setup-riscv64-unknown-linux-gnu - with: - version: '13.2.0' - install-path: '/opt/riscv64-unknown-linux-gnu' - - - name: Install Dependencies - run: | - sudo apt-get update - sudo apt-get install -y qemu-system-aarch64 qemu-system-riscv64 gdb-multiarch llvm-dev libclang-dev wget expect device-tree-compiler p7zip-full gcc-aarch64-linux-gnu gcc-riscv64-linux-gnu - cargo install --version 0.3.0 --locked cargo-binutils - - - name: x86_64 Dependencies - if: matrix.arch == 'x86_64' - run: | - sudo apt-get install -y qemu-system-x86-64 grub-common xorriso grub-efi-amd64 mtools ovmf - sudo chmod 777 /dev/kvm - sed -i 's/ecam_base:.*,/ecam_base: 0xb0000000,/' ./platform/x86_64/qemu/board.rs - - - name: Set up environment variables - run: | - echo "ARCH=${{ matrix.arch }}" >> $GITHUB_ENV - echo "BOARD=${{ matrix.board }}" >> $GITHUB_ENV - - name: Run System Test - run: | - make stest - license-checker: name: license-checker runs-on: ubuntu-latest @@ -284,5 +44,5 @@ jobs: uses: actions/checkout@v4 - name: License Check run: | - set -x - ./tools/license_checker.sh \ No newline at end of file + set -x + ./tools/license_checker.sh diff --git a/.gitignore b/.gitignore index 224a95737..245fbf3f1 100644 --- a/.gitignore +++ b/.gitignore @@ -7,6 +7,7 @@ /platform/*/*/image/kernel/* /platform/*/*/image/virtdisk/* /platform/*/*/image/bootloader/out +/platform/*/*/image/mb2_bootloader/out /platform/*/*/image/iso/boot/kernel/* /platform/*/*/image/iso/boot/hvisor /tools/hvisor @@ -32,8 +33,15 @@ flash.img* .vscode/settings.json compile.sh src/platform/__board.rs -.config +.config* .cursorrules .vscode/extensions.json # systemtest -rootfs1.zip* \ No newline at end of file +rootfs1.zip* +jenkins/__pycache__ +jenkins/logs/ +logs/ +jenkins-cli.jar +tools/kconfig/.venv/ +tools/kconfig/__pycache__/ +kernel_build/ diff --git a/CHANGELOG.md b/CHANGELOG.md index c3b5d3a9b..45d0be5c2 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -2,7 +2,34 @@ > ⚠️ Please update this file for any changes to the hvisor project along with your name and GitHub profile link under the CURRENT section. -## CURRENT - v0.5 +## CURRENT - v0.6 + +- [feature] **PCIe/virtio**: Add emulated virtio PCI device support. ([PR #287](https://github.com/syswonder/hvisor/pull/287), [ZZJJWarth](https://github.com/ZZJJWarth)) +- [ci] Update CI workflow, add license / format checks, restore manual workflow triggers, and update CI terminal output. ([PR #302](https://github.com/syswonder/hvisor/pull/302), [PR #306](https://github.com/syswonder/hvisor/pull/306), [PR #360](https://github.com/syswonder/hvisor/pull/360), [Xingyu Chen](https://github.com/dallasxy)) +- [feature] **aarch64**: Extend VCPU state handling. ([PR #303](https://github.com/syswonder/hvisor/pull/303), [Jingyu Liu](https://github.com/liulog)) +- [feature] **riscv64**: Add virtual **RISC-V IOMMU** support. ([PR #307](https://github.com/syswonder/hvisor/pull/307), [Jingyu Liu](https://github.com/liulog)) +- [bugfix] Detect and diagnose hvisor memory region overlap with the root zone, and add overlap checks between MMIO passthrough and MMIO intercept handler regions. ([PR #311](https://github.com/syswonder/hvisor/pull/311), [PR #384](https://github.com/syswonder/hvisor/pull/384), [Inquisitor-201](https://github.com/Inquisitor-201), [Solicey](https://github.com/Solicey)) +- [bugfix] **aarch64**: Use `dc civac` instead of `dc ivac` in `invalidate_dcache_range`. ([PR #312](https://github.com/syswonder/hvisor/pull/312), [Inquisitor-201](https://github.com/Inquisitor-201)) +- [refactor] Remove redundant frame allocator wrappers, fix alignment parameter semantics, and fix `alloc_contiguous` alignment. ([PR #316](https://github.com/syswonder/hvisor/pull/316), [PR #359](https://github.com/syswonder/hvisor/pull/359), [Nehckl](https://github.com/Inquisitor-201), [Jingyu Liu](https://github.com/liulog)) +- [refactor] Migrate platform options from Cargo features to **Kconfig**. ([PR #319](https://github.com/syswonder/hvisor/pull/319), [Xingyu Chen](https://github.com/dallasxy)) +- [feature] **PCIe**: Add **DWC MSI** injection and **SR-IOV** support (VF enumeration, capability handler, ARI). ([PR #321](https://github.com/syswonder/hvisor/pull/321), [PR #358](https://github.com/syswonder/hvisor/pull/358), [Zhongkai Xu](https://github.com/ZhongkaiXu)) +- [feature] **aarch64**: Support **OpenHarmony** on dayu200 platform. ([PR #357](https://github.com/syswonder/hvisor/pull/357), [Stone749990226](https://github.com/Stone749990226)) +- [feature] **x86_64**: Boot **Asterinas** as zone1 via Multiboot2, with virtio-console support, x2APIC timer virtualization, IOAPIC fixes, and dedicated Jenkins CI. ([PR #362](https://github.com/syswonder/hvisor/pull/362), [PR #376](https://github.com/syswonder/hvisor/pull/376), [yyda](https://github.com/yydawx)) +- [config] Complete PCI fields in zone examples. ([PR #363](https://github.com/syswonder/hvisor/pull/363), [Jaxtonmax](https://github.com/Jaxtonmax)) +- [feature] **riscv64**: Add **RVA23** ISA features for QEMU platforms. ([PR #364](https://github.com/syswonder/hvisor/pull/364), [Jingyu Liu](https://github.com/liulog)) +- [platform] **aarch64**: Add support for **Jetson Orin** with UEFI memory map virtualization. ([PR #366](https://github.com/syswonder/hvisor/pull/366), [Ren HangQi](https://github.com/ForeverYolo)) +- [feature] **x86_64**: Add a hypercall to query the ECAM base. ([PR #377](https://github.com/syswonder/hvisor/pull/377), [yyda](https://github.com/yydawx)) +- [platform] **riscv64**: Add initial support for **Spacemit k3-com260**. ([PR #378](https://github.com/syswonder/hvisor/pull/378), [Jingyu Liu](https://github.com/liulog)) +- [feature] **rk3588 (sysoul_x3300)**: Add Linux NPU / GPU / display zone configurations via SCMI. ([PR #379](https://github.com/syswonder/hvisor/pull/379), [agicy](https://github.com/agicy)) +- [feature] **loongarch64**: Make SMP IPI and Virtio IRQ delivery stateful, track guest-to-physical CPU mappings, and fix Virtio consuming too much CPU. ([PR #380](https://github.com/syswonder/hvisor/pull/380), [Xinhao Li](https://github.com/li041), [Stl_](https://github.com/weifenjihe)) +- [ci] **aarch64**: Add hardware CI for rk3568 and phytium-pi. ([PR #381](https://github.com/syswonder/hvisor/pull/381), [Xingyu Chen](https://github.com/dallasxy)) +- [bugfix] **loongarch64**: Preserve firmware PCI bridge bus numbers. ([PR #386](https://github.com/syswonder/hvisor/pull/386), [Stl_](https://github.com/weifenjihe)) +- [infra] Support older Python environments in Kconfig tooling and fix the LoongArch release build. ([Xinhao Li](https://github.com/li041), [Stl_](https://github.com/weifenjihe)) +- [bugfix] **aarch64**: Refine early boot assembly. ([Nehckl](https://github.com/Inquisitor-201)) + +## History Release + +## hvisor - v0.5 - [platform] **aarch64**: Add support for **sysoul_x3300**. ([agicy](https://github.com/agicy)) - [feature] **aarch64**: Add dual-zone Linux / Android deployment. ([agicy](https://github.com/agicy)) @@ -24,8 +51,6 @@ - [ci] Add CI / CD support for **x86_64**. ([Tianhong Liu](https://github.com/Solicey)) - [ci] Add performance benchmarking scripts for QEMU platforms. ([Xinhao Li](https://github.com/li041)) -## History Release - ## hvisor - v0.4 - [platform] **x86**: Add support for ECX-2300F-PEG. ([Tianhong Liu](https://github.com/Solicey)) @@ -53,7 +78,7 @@ - [platform] **aarch64**: Improve QEMU GICv2/GICv3 configurations and add zone1-linux support. ([agicy](https://github.com/agicy)) - [platform] **loongarch64**: Add support for Loongson 3A5 / 3A6 platforms and improve clock and trap handling. ([wheatfox](https://github.com/enkerewpo)) - [feature] Add **aarch32** support. ([Guowei Li](https://github.com/KouweiLee)) -- [feature] **riscv64** enhancements: g-stage dynamic detection, eic770x_soc, and syscrg emulation. ([Jingyu Liu](https://github.com/liulog)) +- [feature] **riscv64** enhancements: g-stage dynamic detection, hypervisor_v0_6 (EIC770x SoC), and syscrg emulation. ([Jingyu Liu](https://github.com/liulog)) - [infra] Unify UART / MPIDR mapping, centralize IOMMU configuration, remove redundant arch feature flags, and tidy Cargo/zone/hypercall code. ([Nehckl](https://github.com/Inquisitor-201), [Ren HangQi](https://github.com/ForeverYolo)) - [infra/tool] **aarch64**: Optimized the structure of GIC parameters ([Ren HangQi](https://github.com/ForeverYolo)) - [ci/misc] Update dependencies, add ccache support, and improve build/tooling workflows. ([Jingyu Liu](https://github.com/liulog)) diff --git a/Cargo.lock b/Cargo.lock index 98b19c05c..9644e03a3 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -159,7 +159,7 @@ dependencies = [ [[package]] name = "hvisor" -version = "0.1.0" +version = "0.6.0" dependencies = [ "aarch64-cpu", "acpi", diff --git a/Cargo.toml b/Cargo.toml index 89b4cd1fc..381e11771 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -1,6 +1,6 @@ [package] name = "hvisor" -version = "0.1.0" +version = "0.6.0" edition = "2021" # See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html @@ -47,62 +47,6 @@ acpi = "=5.2.0" uguid = "=2.2.0" uefi-raw = "=0.9.0" -[features] -############# general ############## -iommu = [] # supported by: aarch64, riscv64 -pci = [] # supported by: aarch64, riscv64,loongarch64 -share_s2pt = ["iommu"] -print_timestamp = [] # print timestamp when logging - -############# IOMMU ############## -riscv_iommu = ["iommu"] -arm_smmu = ["iommu"] -intel_vtd = ["iommu"] - -############# PCIe access mechanism ############## -ecam_pcie = [] # Standard ECAM mechanism (default for most platforms) -dwc_pcie = [] # DesignWare PCIe Core mechanism (CFG0/CFG1, used by RK3568) -loongarch64_pcie = [] # LoongArch PCIe mechanism (used by LoongArch platforms) -no_pcie_bar_realloc = [] - -############# aarch64 ############## -# irqchip driver -gicv2 = [] -gicv3 = [] - -# uart driver -pl011 = [] -xuartps = [] -imx_uart = [] -uart_16550 = [] -sifive_ccache = [] -eic7700_sysreg = [] -uart16550a = [] - -############## riscv64 ############# -# irqchip driver -plic = [] -dp1000_plic = [] -aia = [] -aclint = [] -# extensions -sstc = [] -# platform specific -eic770x_soc = [] - -########### loongarch64 ############ -# irqchip driver -loongson_7a2000 = [] -# uart driver -loongson_uart = [] -# cpu (not used for now) -loongson_3a5000 = [] -loongson_3a6000 = [] - -############# x86_64 ############### -graphics = [] -split_screen = [] - [profile.dev] # panic = "abort" # avoid cargo test failure, this is a bug of cargo debug = 2 diff --git a/Jenkinsfile b/Jenkinsfile new file mode 100644 index 000000000..9215383d8 --- /dev/null +++ b/Jenkinsfile @@ -0,0 +1,495 @@ +/** ARCH/BOARD come from matrix BID (arch/board); ci.yaml must not duplicate them. */ +def parseBid(String bid) { + def parts = (bid ?: '').split('/', 2) + if (parts.size() != 2 || !parts[0] || !parts[1]) { + error("invalid BID: ${bid}") + } + return [arch: parts[0], board: parts[1]] +} + +/** Optional platform_board in ci.yaml maps BID board to make/platform board. */ +def platformBoard(String bid, String configuredBoard = '') { + return configuredBoard ?: parseBid(bid).board +} + +def parseCiBuildArgs(cfg) { + def buildArgs = [:] + if (!cfg?.build_args) { + return buildArgs + } + cfg.build_args.each { item -> + if (item instanceof Map) { + item.each { k, v -> + buildArgs[k.toString()] = v.toString() + } + } else { + def parts = item.toString().split('=', 2) + if (parts.size() == 2) { + buildArgs[parts[0]] = parts[1] + } + } + } + return buildArgs +} + +def matrixCellDir() { + def bid = env.BID ?: '' + return "${env.WORKSPACE}/.matrix/${bid.replace('/', '__')}" +} + +/** Isolated workspace for top-level CI jobs (linter, license-checker, …). */ +def jenkinsJobDir(String name) { + return "${env.WORKSPACE}/.jenkins/${name}" +} + +/** Copy repo into an isolated dir; excludes other Jenkins sandboxes from the source tree. */ +def syncWorkspaceTo(String destDir) { + sh """ + mkdir -p '${destDir}' + rsync -a --delete \\ + --exclude '.jenkins/' \\ + --exclude '.matrix/' \\ + --exclude '.jenkins-matrix/' \\ + '${env.WORKSPACE}/' '${destDir}/' + """ +} + +def loadCiYaml() { + def data = readYaml file: 'jenkins/ci.yaml' + def bids = data?.bids + if (!(bids instanceof List)) { + error("jenkins/ci.yaml: 'bids' must be a list") + } + return data +} + +def getBidConfig(ci, String bid) { + return (ci.bids ?: []).find { entry -> + return (entry?.bid ?: '').toString().trim() == bid + } +} + +def normalizeToolArch(String arch) { + def raw = (arch ?: '').toString().trim() + def mapping = [ + 'aarch64' : 'arm64', + 'arm64' : 'arm64', + 'riscv64' : 'riscv', + 'riscv' : 'riscv', + 'loongarch64': 'loongarch', + 'loongarch' : 'loongarch', + ] + return mapping.get(raw, raw) +} + +/** GitHub Check name for this matrix cell */ +def matrixCheckName() { + return (env.BID ?: '').toString() +} + +/** Marker file: only finish checks that published IN_PROGRESS. */ +def githubCheckStartedMarker(String checkName) { + def safe = checkName.replace('/', '__').replaceAll(/[^A-Za-z0-9_.-]/, '_') + return "${env.WORKSPACE}/.jenkins/check-started/${safe}" +} + +def markGithubCheckStarted(String checkName) { + def marker = githubCheckStartedMarker(checkName) + sh "mkdir -p '${env.WORKSPACE}/.jenkins/check-started' && : > '${marker}'" +} + +def isGithubCheckStarted(String checkName) { + return fileExists(githubCheckStartedMarker(checkName)) +} + +def publishGithubCheckInProgress(String checkName) { + publishChecks( + name: checkName, + title: checkName, + summary: 'In progress', + status: 'IN_PROGRESS', + conclusion: 'NONE', + detailsURL: "${env.RUN_DISPLAY_URL ?: env.BUILD_URL}", + ) + markGithubCheckStarted(checkName) +} + +def publishGithubCheckCompleted(String checkName, String conclusion) { + def summaries = [ + 'SUCCESS' : 'Passed', + 'FAILURE' : 'Failed', + 'CANCELLED': 'Cancelled', + ] + publishChecks( + name: checkName, + title: checkName, + summary: summaries.get(conclusion, conclusion), + status: 'COMPLETED', + conclusion: conclusion, + detailsURL: "${env.RUN_DISPLAY_URL ?: env.BUILD_URL}", + ) +} + +def publishMatrixCheckInProgress() { + publishGithubCheckInProgress(matrixCheckName()) +} + +def publishMatrixCheckCompleted(String conclusion) { + publishGithubCheckCompleted(matrixCheckName(), conclusion) +} + +def finishGithubCheck(String checkName, String buildResult) { + if (!isGithubCheckStarted(checkName)) { + echo "Skip GitHub check completion for '${checkName}' (in-progress was never published)" + return + } + def conclusion = [ + 'SUCCESS' : 'SUCCESS', + 'FAILURE' : 'FAILURE', + 'UNSTABLE': 'FAILURE', + 'ABORTED' : 'CANCELLED', + 'NOT_BUILT': 'CANCELLED', + ].get(buildResult ?: '', 'FAILURE') + publishGithubCheckCompleted(checkName, conclusion) +} + +def hasCiTests() { + return getBidConfig(loadCiYaml(), env.BID) != null +} + +def toolchainPathShell() { + return "export PATH=${env.CARGO_HOME}/bin:${env.TOOLCHAIN_PATHS}:\$PATH" +} + +def qemuPathShell() { + return "export PATH=${env.QEMU_PATH}:\$PATH" +} + +/** Kconfig: symlink agent venv + make defconfig. Keep in sync with Makefile kconfig_python path. */ +def kconfigSetupShell(String arch, String board) { + return """ + ${toolchainPathShell()} + chmod +x tools/kconfig/host_config.sh tools/kconfig/save_defconfig.sh 2>/dev/null || true + if [ ! -x tools/kconfig/.venv/bin/python ]; then + if [ ! -x ${env.KCONFIG_VENV}/bin/python ]; then + echo "ERROR: CI kconfig venv missing: ${env.KCONFIG_VENV}/bin/python" >&2 + exit 1 + fi + mkdir -p tools/kconfig + ln -sfn ${env.KCONFIG_VENV} tools/kconfig/.venv + fi + make defconfig ARCH=${arch} BOARD=${board} BID= + """ +} + +pipeline { + agent any + + options { + timestamps() + } + + post { + always { + echo "=== DEBUG: Branch ${env.BRANCH_NAME} ===" + echo "=== DEBUG: Commit ${env.GIT_COMMIT} ===" + deleteDir() + } + } + + environment { + HVISOR_TOOL_URL = 'https://github.com/syswonder/hvisor-tool.git' + HVISOR_TOOL_PATH = 'hvisor-tool' + RUST_HOME = '/usr/local/rustup' + CARGO_HOME = '/usr/local/cargo' + QEMU_PATH = '/home/light/DEMO/qemu-10.1.0/build' + TEST_IMG_BASE = '/home/light/DEMO/syswonder/test_img' + KCONFIG_VENV = "/home/light/DEMO/syswonder/test_img/venv" + RISCV_TOOLCHAIN_PATH = '/home/light/DEMO/toolchain/riscv64-glibc-ubuntu-24.04-gcc' + AARCH64_TOOLCHAIN_PATH = '/home/light/DEMO/toolchain/gcc-arm-10.3-2021.07-x86_64-aarch64-none-linux-gnu' + LOONGARCH64_TOOLCHAIN_PATH = '/home/light/DEMO/toolchain/loongarch_cross_tools' + // All toolchain bins on PATH; same for every matrix cell (no per-arch selection). + TOOLCHAIN_PATHS = "${env.RISCV_TOOLCHAIN_PATH}/bin:${env.AARCH64_TOOLCHAIN_PATH}/bin:${env.LOONGARCH64_TOOLCHAIN_PATH}/bin" + TFTP_DIR = '/home/light/tftp' + PYTHONDONTWRITEBYTECODE = '1' + } + + stages { + stage('Linter') { + steps { + script { + publishGithubCheckInProgress('linter') + def cellWs = jenkinsJobDir('linter') + syncWorkspaceTo(cellWs) + dir(cellWs) { + sh kconfigSetupShell('aarch64', 'qemu-gicv3') + ''' + cargo fmt --all -- --check + ''' + } + } + } + post { + always { + script { finishGithubCheck('linter', currentBuild.currentResult) } + } + } + } + + stage('License checker') { + steps { + script { + publishGithubCheckInProgress('license-checker') + def cellWs = jenkinsJobDir('license-checker') + syncWorkspaceTo(cellWs) + dir(cellWs) { + sh """ + chmod +x tools/license_checker.sh + ./tools/license_checker.sh + """ + } + } + } + post { + always { + script { finishGithubCheck('license-checker', currentBuild.currentResult) } + } + } + } + + stage('Multi-Platform Matrix') { + matrix { + axes { + axis { + name 'BID' + values( + 'aarch64/imx8mp', + 'aarch64/jeston-orin', + 'aarch64/ok6254-c', + 'aarch64/phytium-pi', + 'aarch64/qemu-gicv2', + 'aarch64/qemu-gicv3', + 'aarch64/rk3568', + 'aarch64/rk3588', + 'aarch64/sysoul_x3300', + 'aarch64/zcu102', + 'loongarch64/ls3a5000', + 'loongarch64/ls3a6000', + 'riscv64/hifive-premier-p550', + 'riscv64/megrez', + 'riscv64/qemu-aia', + 'riscv64/qemu-plic', + 'riscv64/ur-dp1000', + 'x86_64/ecx-2300f-peg', + 'x86_64/nuc14mnk', + 'x86_64/qemu', + 'x86_64/qemu_asterinas', + ) + } + } + + stages { + stage('Prepare cell') { + steps { + script { + publishMatrixCheckInProgress() + syncWorkspaceTo(matrixCellDir()) + } + } + } + + stage('Compile') { + steps { + dir(matrixCellDir()) { + script { + def bid = parseBid(env.BID) + def arch = bid.arch + // BID may name a test variant (qemu_asterinas); platform_board selects the actual make/platform board (qemu). + def bidCfg = getBidConfig(loadCiYaml(), env.BID) + def board = platformBoard(env.BID, bidCfg?.platform_board?.toString() ?: '') + echo "Compile hvisor [BID=${env.BID}, ARCH=${arch}, BOARD=${board}]" + sh kconfigSetupShell(arch, board) + if (arch != 'x86_64') { + sh """ + ${toolchainPathShell()} + make dtb ARCH=${arch} BOARD=${board} BID= + """ + } + sh """ + ${toolchainPathShell()} + make all ARCH=${arch} BOARD=${board} MODE=release BID= + """ + } + } + } + } + + stage('Build hvisor-tool') { + when { + expression { return hasCiTests() } + } + steps { + dir(matrixCellDir()) { + script { + def bidCfg = getBidConfig(loadCiYaml(), env.BID) + def buildArgs = parseCiBuildArgs(bidCfg) + def bidTool = parseBid(env.BID) + def tarch = normalizeToolArch(buildArgs.TARCH ?: bidTool.arch) + def kdir = buildArgs.KDIR + if (!kdir) { + error("jenkins/ci.yaml BID=${env.BID}: build_args must include KDIR") + } + + echo "Build hvisor-tool [BID=${env.BID}, TARCH=${tarch}, KDIR=${kdir}]" + if (!fileExists(env.HVISOR_TOOL_PATH)) { + sh "mkdir -p ${env.HVISOR_TOOL_PATH}" + } + dir(env.HVISOR_TOOL_PATH) { + checkout([ + $class: 'GitSCM', + branches: [[name: '*/main']], + extensions: [[$class: 'CloneOption', depth: 1, noTags: true]], + userRemoteConfigs: [[url: env.HVISOR_TOOL_URL]] + ]) + } + sh """ + export PATH=${env.TOOLCHAIN_PATHS}:\$PATH + make -C ${env.HVISOR_TOOL_PATH} all ARCH=${tarch} KDIR=${kdir} + """ + } + } + } + } + + stage('Prepare test') { + when { + expression { return hasCiTests() } + } + steps { + dir(matrixCellDir()) { + script { + def bidCfg = getBidConfig(loadCiYaml(), env.BID) + def buildArgs = parseCiBuildArgs(bidCfg) + def bidParsed = parseBid(env.BID) + def arch = bidParsed.arch + // Keep the server artifact BID separate from the real platform board used by make and prepare.sh. + def board = platformBoard(env.BID, bidCfg?.platform_board?.toString() ?: '') + def kdir = (buildArgs.KDIR ?: '').toString() + def testsCfg = bidCfg.tests ?: [:] + def artifactDir = testsCfg.artifact_dir ?: bidParsed.board + def mode = (testsCfg.mode ?: '').toString().trim() + if (!kdir || !mode) { + error("jenkins/ci.yaml BID=${env.BID}: tests.mode and build_args KDIR are required") + } + + if (mode == 'qemu') { + def prepareScript = "jenkins/prepare.sh" + def externalFile = "${env.TEST_IMG_BASE}/${arch}/${artifactDir}" + def configure = "./platform/${arch}/${board}/" + echo "Prepare rootfs [BID=${env.BID}]" + sh """ + cp -r ${externalFile}/* ${configure} + if [ "${artifactDir}" != "${board}" ]; then + mkdir -p "${configure}/image/kernel" "${configure}/image/virtdisk" + cp "${env.TEST_IMG_BASE}/${arch}/${board}/image/kernel/setup.bin" "${configure}/image/kernel/setup.bin" + cp "${env.TEST_IMG_BASE}/${arch}/${board}/image/kernel/vmlinux.bin" "${configure}/image/kernel/vmlinux.bin" + cp "${env.TEST_IMG_BASE}/${arch}/${board}/image/virtdisk/rootfs1.img" "${configure}/image/virtdisk/rootfs1.img" + fi + chmod +x "${prepareScript}" + sudo -E env \\ + ARCH="${arch}" \\ + BOARD="${board}" \\ + KDIR="${kdir}" \\ + WORKSPACE_ROOT="\$(pwd)" \\ + HVISOR_TOOL_PATH="${env.HVISOR_TOOL_PATH}" \\ + "${prepareScript}" + """ + } else if (mode == 'board') { + def tftpDir = (testsCfg.tftp_dir ?: env.TFTP_DIR).toString() + def zone0Dtbs = testsCfg.zone0_dtbs ?: [] + if (testsCfg.zone0_dtb) { + zone0Dtbs = [testsCfg.zone0_dtb] + } + def zone0Image = (testsCfg.zone0_image ?: "${kdir}/arch/arm64/boot/Image").toString() + echo "Deploy TFTP artifacts [BID=${env.BID}, TFTP_DIR=${tftpDir}]" + sh """ + export TERM=\${TERM:-xterm} + ${toolchainPathShell()} + tftp_staging="\$(pwd)/.tftp-staging" + rm -rf "\${tftp_staging}" + make cp ARCH=${arch} BOARD=${board} MODE=release TFTP_DIR="\${tftp_staging}" + test -f "\${tftp_staging}/hvisor.bin" + sudo mkdir -p "${tftpDir}" + sudo find "${tftpDir}" -mindepth 1 -maxdepth 1 -type f -delete + sudo cp "\${tftp_staging}/hvisor.bin" "${tftpDir}/" + test -f "${tftpDir}/hvisor.bin" || { + echo "error: hvisor.bin missing in ${tftpDir}" >&2 + exit 1 + } + """ + zone0Dtbs.each { dtb -> + sh """ + test -f "${dtb}" + sudo cp "${dtb}" "${tftpDir}/" + """ + } + sh """ + test -f "${zone0Image}" || { + echo "error: zone0 kernel Image not found: ${zone0Image}" >&2 + exit 1 + } + sudo cp "${zone0Image}" "${tftpDir}/Image" + test -f "${tftpDir}/Image" || { + echo "error: Image missing in ${tftpDir}" >&2 + exit 1 + } + sudo chmod -R a+rX "${tftpDir}" + ls -la "${tftpDir}" + """ + } else { + error("jenkins/ci.yaml BID=${env.BID}: unsupported tests.mode='${mode}'") + } + } + } + } + } + + stage('Run test cases') { + when { + expression { return hasCiTests() } + } + steps { + dir(matrixCellDir()) { + script { + def bidCfg = getBidConfig(loadCiYaml(), env.BID) + def mode = (bidCfg.tests?.mode ?: '').toString().trim() + echo "Run tests via ci_runner [BID=${env.BID}, mode=${mode}]" + if (mode == 'board') { + sh """ + export TERM=\${TERM:-xterm} + sudo -E python3 jenkins/ci_runner.py \ + --bid "${env.BID}" + """ + } else { + sh """ + export TERM=\${TERM:-xterm} + ${toolchainPathShell()} + ${qemuPathShell()} + python3 jenkins/ci_runner.py \ + --bid "${env.BID}" + """ + } + } + } + } + } + } + + post { + always { + script { finishGithubCheck(matrixCheckName(), currentBuild.currentResult) } + } + } + } + } + } +} diff --git a/Makefile b/Makefile index 6cb472514..ecc2247f4 100644 --- a/Makefile +++ b/Makefile @@ -4,7 +4,6 @@ STATS ?= off PORT ?= 2333 MODE ?= release BOARD ?= qemu-gicv3 -FEATURES= BID ?= ptest ?= @@ -23,15 +22,6 @@ else BOARD := $(shell echo $(BID) | cut -d'/' -f2) endif -# if user add FEATURES in environment, we use it -# else we use the default FEATURES in platform/$(ARCH)/$(BOARD)/cargo/features -ifeq ($(FEATURES),) - FEATURES := $(shell ./tools/read_features.sh $(ARCH) $(BOARD) || echo ERROR) - ifeq ($(FEATURES),ERROR) - $(error ERROR: Read FEATURES failed. Please check if ARCH="$(ARCH)" and BOARD="$(BOARD)" are correct.) - endif -endif - ifeq ($(ARCH),aarch64) RUSTC_TARGET := aarch64-unknown-none GDB_ARCH := aarch64 @@ -56,7 +46,6 @@ export ARCH export BOARD export BID export RUSTC_TARGET -export FEATURES # Build paths build_path := target/$(RUSTC_TARGET)/$(MODE) @@ -69,7 +58,6 @@ systemtest_tdownload := $(test_dir)/systemtest/tdownload_all.sh # Build arguments build_args := -build_args += --features "$(FEATURES)" build_args += --target $(RUSTC_TARGET) build_args += -Z build-std=core,alloc build_args += -Z build-std-features=compiler-builtins-mem @@ -86,16 +74,58 @@ COLOR_BLUE := $(shell tput setaf 4) COLOR_BOLD := $(shell tput bold) COLOR_RESET := $(shell tput sgr0) +# Defconfig / menuconfig: see tools/kconfig/kconfig_cli.py +kconfig_python := tools/kconfig/.venv/bin/python + # Targets -.PHONY: all elf disa run gdb monitor clean tools rootfs vscode -all: clean_check gen_cargo_config vscode $(hvisor_bin) +.PHONY: all elf disa run gdb monitor clean tools rootfs vscode ci-run defconfig menuconfig savedefconfig ensure_config clean_check kconfig_venv link_board check-hv-mem-overlap +kconfig_venv: + @if [ ! -x $(kconfig_python) ]; then \ + echo "$(COLOR_YELLOW)Creating tools/kconfig/.venv (kconfiglib)...$(COLOR_RESET)"; \ + ./tools/kconfig/bootstrap_venv.sh; \ + fi + +ensure_config: + @CONFIG_ARCH=; CONFIG_BOARD=; \ + if [ -f .config ]; then \ + CONFIG_ARCH=$$(grep '^# ARCH=' .config 2>/dev/null | head -1 | sed 's/^# ARCH=//'); \ + [ -n "$$CONFIG_ARCH" ] || CONFIG_ARCH=$$(grep '^ARCH=' .config | head -1 | cut -d'=' -f2); \ + CONFIG_BOARD=$$(grep '^# BOARD=' .config 2>/dev/null | head -1 | sed 's/^# BOARD=//'); \ + [ -n "$$CONFIG_BOARD" ] || CONFIG_BOARD=$$(grep '^BOARD=' .config | head -1 | cut -d'=' -f2); \ + fi; \ + if [ ! -f .config ]; then \ + echo "$(COLOR_YELLOW)No .config; running defconfig for $(ARCH)/$(BOARD)$(COLOR_RESET)"; \ + $(MAKE) --no-print-directory defconfig; \ + elif [ "$$CONFIG_ARCH" != "$(ARCH)" ] || [ "$$CONFIG_BOARD" != "$(BOARD)" ]; then \ + echo "$(COLOR_YELLOW)$(COLOR_BOLD)ARCH or BOARD changed (OLD: $$CONFIG_ARCH/$$CONFIG_BOARD, NEW: $(ARCH)/$(BOARD)), cleaning and reloading defconfig...$(COLOR_RESET)"; \ + ./tools/clean.sh; \ + $(MAKE) --no-print-directory defconfig; \ + fi + +clean_check: ensure_config + +link_board: + @mkdir -p src/platform + @ln -sfn ../../platform/$(ARCH)/$(BOARD)/board.rs src/platform/__board.rs + +defconfig: kconfig_venv + @$(kconfig_python) tools/kconfig/kconfig_cli.py defconfig + @$(MAKE) --no-print-directory link_board + +menuconfig: kconfig_venv + @$(kconfig_python) tools/kconfig/kconfig_cli.py menuconfig + +savedefconfig: + @./tools/kconfig/save_defconfig.sh "$(ARCH)" "$(BOARD)" + +all: ensure_config gen_cargo_config vscode $(hvisor_bin) check-hv-mem-overlap @printf "\n" @printf "$(COLOR_GREEN)$(COLOR_BOLD)hvisor build summary:$(COLOR_RESET)\n" @printf "%-10s %s\n" "ARCH =" "$(COLOR_BOLD)$(ARCH)$(COLOR_RESET)" @printf "%-10s %s\n" "BOARD =" "$(COLOR_BOLD)$(BOARD)$(COLOR_RESET)" @printf "%-10s %s\n" "BID =" "$(COLOR_BOLD)$(BID)$(COLOR_RESET)" @printf "%-10s %s\n" "LOG =" "$(COLOR_BOLD)$(LOG)$(COLOR_RESET)" - @printf "%-10s %s\n" "FEATURES =" "$(COLOR_BOLD)$(FEATURES)$(COLOR_RESET)" + @printf "%-10s %s\n" "DEFCONFIG =" "$(COLOR_BOLD)platform/$(ARCH)/$(BOARD)/kconfig/defconfig$(COLOR_RESET)" @printf "%-10s %s\n" "RUSTC_TARGET =" "$(COLOR_BOLD)$(RUSTC_TARGET)$(COLOR_RESET)" @printf "%-10s %s\n" "BUILD_PATH =" "$(COLOR_BOLD)$(build_path)$(COLOR_RESET)" @printf "%-10s %s\n" "HVISON_BIN_SIZE =" "$(COLOR_BOLD)$(shell du -h $(hvisor_bin) | cut -f1)$(COLOR_RESET)" @@ -109,29 +139,26 @@ all: clean_check gen_cargo_config vscode $(hvisor_bin) @printf "\n" @printf "$(COLOR_GREEN)$(COLOR_BOLD)hvisor build success!$(COLOR_RESET)\n" -clean_check: -# if .config not exist, then everything is fine -# else we read .config and parse ARCH and BOARD, if they are different, we clean the build - @if [ -f ".config" ]; then \ - CONFIG_ARCH=$$(cat .config | grep "ARCH" | cut -d'=' -f2); \ - CONFIG_BOARD=$$(cat .config | grep "BOARD" | cut -d'=' -f2); \ - if [ "$$CONFIG_ARCH" != "$(ARCH)" ] || [ "$$CONFIG_BOARD" != "$(BOARD)" ]; then \ - echo "$(COLOR_YELLOW)$(COLOR_BOLD)ARCH or BOARD changed(OLD: $$CONFIG_ARCH/$$CONFIG_BOARD, NEW: $(ARCH)/$(BOARD)), cleaning...$(COLOR_RESET)"; \ - ./tools/clean.sh; \ - fi; \ - fi - gen_cargo_config: @printf "$(COLOR_GREEN)$(COLOR_BOLD)generating .cargo/config.toml...$(COLOR_RESET)\n" - ./tools/gen_cargo_config.sh + @chmod +x tools/kconfig/host_config.sh 2>/dev/null || true + ./tools/kconfig/host_config.sh cargo @printf "$(COLOR_GREEN)$(COLOR_BOLD)generating .cargo/config.toml success!$(COLOR_RESET)\n" +check-hv-mem-overlap: $(hvisor_bin) platform/$(ARCH)/$(BOARD)/board.rs + @printf "$(COLOR_GREEN)$(COLOR_BOLD)checking hvisor memory vs root zone regions...$(COLOR_RESET)\n" + @python3 tools/check_hv_mem_overlap.py $(hvisor_elf) platform/$(ARCH)/$(BOARD)/board.rs && \ + printf "$(COLOR_GREEN)$(COLOR_BOLD)check passed!$(COLOR_RESET)\n" || \ + (printf "$(COLOR_RED)$(COLOR_BOLD)OVERLAP DETECTED! See details above.$(COLOR_RESET)\n" && \ + false) + vscode: @printf "$(COLOR_GREEN)$(COLOR_BOLD)generating .vscode/settings.json...$(COLOR_RESET)\n" - ./tools/gen_vscode_settings.sh + @chmod +x tools/kconfig/host_config.sh 2>/dev/null || true + ./tools/kconfig/host_config.sh vscode @printf "$(COLOR_GREEN)$(COLOR_BOLD)generating .vscode/settings.json success!$(COLOR_RESET)\n" -elf: +elf: ensure_config gen_cargo_config cargo build $(build_args) disa: @@ -141,6 +168,10 @@ disa: run: all $(QEMU) $(QEMU_ARGS) +ci-run: all + @mkdir -p "$(CURDIR)/.qemu" + $(MAKE) run QEMU_ARGS+='$(subst -nographic,-display none,$(filter-out -s -S -serial mon:stdio,$(QEMU_ARGS))) -monitor none -chardev socket,id=char0,path=$(CURDIR)/.qemu/qemu.sock,server=on,wait=off -serial chardev:char0' + gdb: all $(QEMU) $(QEMU_ARGS) -s -S @@ -156,22 +187,21 @@ monitor: jlink-server: JLinkGDBServer -select USB -if JTAG -device Cortex-A53 -port 1234 -cp: - cp $(hvisor_bin) ~/tftp +TFTP_DIR ?= ~/tftp + +cp: $(hvisor_bin) + mkdir -p $(TFTP_DIR) + cp $(hvisor_bin) $(TFTP_DIR)/ test-pre: download-test-img chmod +x platform/$(ARCH)/$(BOARD)/test/runner.sh @echo "added execute permission to test runner.sh for board $(BOARD)" -fmt-test: all - cargo fmt --all -- --check - @echo "cargo fmt check passed!" - fmt: all cargo fmt --all @echo "your code has been formatted" -clippy: +clippy: ensure_config gen_cargo_config cargo clippy $(build_args) flash-img: @@ -187,10 +217,10 @@ download-test-img: else echo "\nflash.img found\n"; \ fi -test: clean test-pre gen_cargo_config +test: clean test-pre ensure_config gen_cargo_config cargo test $(build_args) -vv -stest: clean test-pre gen_cargo_config +stest: clean test-pre ensure_config gen_cargo_config ./platform/$(ARCH)/$(BOARD)/test/systemtest/tcompiledtb.sh ./platform/$(ARCH)/$(BOARD)/test/systemtest/tdownload_all.sh ./platform/$(ARCH)/$(BOARD)/test/systemtest/trootfs_deploy.sh @@ -199,7 +229,7 @@ stest: clean test-pre gen_cargo_config # Performance benchmark: data collection only, does not affect pass/fail. # Calls systemtest scripts for DTS, then perftest/tdownload_all.sh when present # (fallback to systemtest/tdownload_all.sh), and perftest/trootfs_deploy.sh. -perf: clean test-pre gen_cargo_config +perf: clean test-pre ensure_config gen_cargo_config ./platform/$(ARCH)/$(BOARD)/test/systemtest/tcompiledtb.sh @if [ -x "$(perftest_tdownload)" ]; then \ $(perftest_tdownload); \ @@ -211,7 +241,7 @@ perf: clean test-pre gen_cargo_config # Prepare perf image only: reuse existing rootfs img when present, download # missing assets, deploy benchmark scripts/tools into image, and print path. -perf-prepare-img: clean test-pre gen_cargo_config +perf-prepare-img: clean test-pre ensure_config gen_cargo_config ./platform/$(ARCH)/$(BOARD)/test/systemtest/tcompiledtb.sh @if [ -x "$(perftest_tdownload)" ]; then \ $(perftest_tdownload); \ diff --git a/README-zh.md b/README-zh.md index f22d5a154..959dc020b 100644 --- a/README-zh.md +++ b/README-zh.md @@ -66,6 +66,7 @@ hvisor 是一个用 Rust 实现的 Type-1 裸机虚拟机监控器，采用分 - [x] Rockchip RK3568 - [x] Forlinx OK6254-C - [x] Phytium Pi +- [x] Jetson Orin ### riscv64 @@ -73,6 +74,7 @@ hvisor 是一个用 Rust 实现的 Type-1 裸机虚拟机监控器，采用分 - [x] Milk-V Megrez - [x] Sifive Hifive Premier P550 - [x] dp-1000 +- [x] Spacemit k3-com260 - [ ] FPGA 香山（昆明湖）on S2C Prodigy S7-19PS-2 ### loongarch64 @@ -93,7 +95,8 @@ hvisor 是一个用 Rust 实现的 Type-1 裸机虚拟机监控器，采用分 - [x] Zephyr AArch32 - [x] RT-Thread - [x] Android -- [ ] OpenHarmony +- [x] OpenHarmony +- [x] Asterinas ## 开始使用 @@ -105,22 +108,25 @@ hvisor 是一个用 Rust 实现的 Type-1 裸机虚拟机监控器，采用分 - [更新日志](./CHANGELOG.md) - 支持 USB zoneU 直通 - 支持 PCIe 总线虚拟化 +- 支持 Android +- 支持 OpenHarmony +- 支持 Jetson Orin +- 支持 IOMMU 虚拟化（Intel VT-d / RISC-V 虚拟 IOMMU） +- 支持时钟控制器虚拟化（virtio-scmi Clock 协议，ARM） +- 支持 NPU zoneU 直通（sysoul_x3300-scmi） ### 计划中 -- 支持 OpenHarmony - 支持 ARMv9 - 支持 GICv4 - 支持缓存着色 -- 支持 SR-IOV -- 支持 NPU zoneU 直通 - 支持 Nvidia GPU zoneU 直通 +- 支持 ARM SMMU 虚拟化 +- 支持 x86_64 时钟控制器虚拟化 +- 支持 SR-IOV - Web Management tool - 设备树配置工具 -- 支持 Nvidia Orin - 支持 Nvidia Thor - 支持 Raspberry Pi 5 -- 支持 IOMMU 虚拟化 -- 支持 时钟控制器 虚拟化 - 支持 pinctrl 虚拟化 - 支持无 zone0 启动 zoneU / zoneR diff --git a/README.md b/README.md index 57e964d7d..b82eb1edd 100644 --- a/README.md +++ b/README.md @@ -65,6 +65,7 @@ hvisor is a Type-1 bare-metal virtual machine monitor implemented in Rust, featu - [x] Rockchip RK3568 - [x] Forlinx OK6254-C - [x] Phytium Pi +- [x] Jetson Orin ### riscv64 @@ -72,6 +73,7 @@ hvisor is a Type-1 bare-metal virtual machine monitor implemented in Rust, featu - [x] Milk-V Megrez - [x] Sifive Hifive Premier P550 - [x] dp-1000 +- [x] Spacemit k3-com260 - [ ] FPGA XiangShan(KunMingHu) on S2C Prodigy S7-19PS-2 ### loongarch64 @@ -92,7 +94,8 @@ hvisor is a Type-1 bare-metal virtual machine monitor implemented in Rust, featu - [x] Zephyr AArch32 - [x] RT-Thread - [x] Android -- [ ] OpenHarmony +- [x] OpenHarmony +- [x] Asterinas ## Getting Started @@ -103,22 +106,25 @@ Please refer to the hvisor documentation for quick start guides, build and run i - [CHANGELOG](./CHANGELOG.md) - Support for USB zoneU passthrough - Support for PCIe bus virtualization +- Support for Android +- Support for OpenHarmony +- Support for Jetson Orin +- Support for IOMMU virtualization (Intel VT-d / RISC-V virtual IOMMU) +- Support for Clock Controller virtualization (virtio-scmi Clock protocol, ARM) +- Support for NPU zoneU passthrough (sysoul_x3300-scmi) ### Planned -- Support for OpenHarmony - Support for ARMv9 - Support for GICv4 - Support for Cache Coloring -- Support for SR-IOV -- Support for NPU zoneU passthrough - Support for Nvidia GPU zoneU passthrough +- Support for ARM SMMU virtualization +- Support for Clock Controller virtualization on x86_64 +- Support for SR-IOV - Web Management tool - Device Tree configuration tool -- Support for Nvidia Orin - Support for Nvidia Thor - Support for Raspberry Pi 5 -- Support for IOMMU virtualization -- Support for Clock Controller virtualization - Support for pinctrl virtualization - Support for booting zoneU / zoneR without zone0 diff --git a/build.rs b/build.rs index 9fdedbbf7..9de7058df 100644 --- a/build.rs +++ b/build.rs @@ -14,6 +14,7 @@ // Authors: // Yulong Han // +use std::collections::{HashMap, HashSet}; use std::io::Write; use std::{env, fs, path::Path}; @@ -29,58 +30,116 @@ fn log(output: &str) { writeln!(file, "{}", output).expect("Failed to write to log file"); } -// .config -// ARCH=... -// BOARD=... struct BuildEnv { arch: String, board: String, bid: String, - features: String, } +// parse ARCH, BOARD and BID from .config fn parse_build_env(file_path: &str) -> BuildEnv { let file = fs::read_to_string(file_path).expect("Failed to read .config file"); let mut arch = String::new(); let mut board = String::new(); let mut bid = String::new(); - let mut features = String::new(); for line in file.lines() { - let parts: Vec<&str> = line.split('=').collect(); - if parts.len() != 2 { + let t = line.trim(); + if let Some(v) = t.strip_prefix("# ARCH=") { + arch = v.to_string(); + continue; + } + if let Some(v) = t.strip_prefix("# BOARD=") { + board = v.to_string(); + continue; + } + if let Some(v) = t.strip_prefix("# BID=") { + bid = v.to_string(); + continue; + } + if t.starts_with('#') { continue; } - match parts[0] { - "ARCH" => arch = parts[1].to_string(), - "BOARD" => board = parts[1].to_string(), - "BID" => bid = parts[1].to_string(), - "FEATURES" => features = parts[1].to_string(), + let Some((k, v)) = t.split_once('=') else { + continue; + }; + match k { + "ARCH" if arch.is_empty() => arch = v.to_string(), + "BOARD" if board.is_empty() => board = v.to_string(), + "BID" if bid.is_empty() => bid = v.to_string(), _ => {} } } - BuildEnv { - arch, - board, - bid, - features, + BuildEnv { arch, board, bid } +} + +fn load_cfg_map(root: &Path) -> HashMap { + let path = root.join("kconfig/cfg_map.toml"); + let raw = fs::read_to_string(&path).unwrap_or_else(|_| panic!("missing {}", path.display())); + let mut m = HashMap::new(); + let mut in_symbols = false; + for line in raw.lines() { + let t = line.trim(); + if t.is_empty() || t.starts_with('#') { + continue; + } + if t == "[symbols]" { + in_symbols = true; + continue; + } + if t.starts_with('[') { + in_symbols = false; + continue; + } + if !in_symbols { + continue; + } + let Some((k, v)) = t.split_once('=') else { + continue; + }; + let k = k.trim().trim_matches('"'); + let v = v.trim().trim_matches('"'); + m.insert(k.to_string(), v.to_string()); + } + if m.is_empty() { + panic!("cfg_map.toml: no entries under [symbols]"); } + m +} + +// parse enabled config keys from .config +fn parse_enabled_config_keys(config_text: &str) -> HashSet { + let mut out = HashSet::new(); + for line in config_text.lines() { + let line = line.trim(); + if line.is_empty() || line.starts_with('#') { + continue; + } + let Some((key, val)) = line.split_once('=') else { + continue; + }; + let val = val.trim(); + if val != "y" && val != "m" { + continue; + } + if key.starts_with("CONFIG_") { + out.insert(key.to_string()); + } + } + out } fn main() { - // cleanup the log file let log_path = Path::new(BUILD_LOG_FILE); if log_path.exists() { fs::remove_file(log_path).expect("Failed to remove log file"); } let project_toml_root = env::var("CARGO_MANIFEST_DIR").unwrap(); - // read the .config file at the project root - let config_path = format!("{}/.config", project_toml_root); - let mut build_env = parse_build_env(&config_path); + let root = Path::new(&project_toml_root); + let config_path = root.join(".config"); + let mut build_env = parse_build_env(config_path.to_str().unwrap()); if !build_env.bid.is_empty() { - // BID=$ARCH/$BOARD, parse it - // update the build_env with the parsed values let parts: Vec<&str> = build_env.bid.split('/').collect(); if parts.len() != 2 { log(&format!("Invalid BID format: {}", build_env.bid)); @@ -91,35 +150,45 @@ fn main() { } build_env.arch = parts[0].to_string(); build_env.board = parts[1].to_string(); - } else { - log(&format!( - "BID environment variable not found, using ARCH and BOARD" - )); - if build_env.arch.is_empty() || build_env.board.is_empty() { - log(&format!("ARCH or BOARD environment variable not found")); - panic!( - "ARCH or BOARD environment variable not found, please check the log file({}) for more details", - BUILD_LOG_FILE - ); - } + } else if build_env.arch.is_empty() || build_env.board.is_empty() { + log("ARCH or BOARD missing in .config"); + panic!( + "ARCH or BOARD missing in .config (run: make defconfig), see {}", + BUILD_LOG_FILE + ); } let arch = build_env.arch; let board = build_env.board; let bid = build_env.bid; - let features = build_env.features; let pwd = env::current_dir().unwrap(); log(&format!("Current directory: {}", pwd.display())); + let cfg_map = load_cfg_map(root); + let config_text = fs::read_to_string(&config_path).expect("read .config"); + let enabled = parse_enabled_config_keys(&config_text); + + for rust_cfg in cfg_map.values().collect::>() { + println!("cargo:rustc-check-cfg=cfg({rust_cfg})"); + } + + for k in &enabled { + if let Some(rust_cfg) = cfg_map.get(k) { + println!("cargo:rustc-cfg={rust_cfg}"); + } else if k.starts_with("CONFIG_") { + log(&format!("warning: unknown config key in .config: {k}")); + } + } + let target_path_str = format!("{}/src/platform/__board.rs", pwd.display()); let target_path = Path::new(&target_path_str); let source_path_str = format!("{}/platform/{}/{}/board.rs", pwd.display(), arch, board); let source_path = Path::new(&source_path_str); log(&format!( - "Building for ARCH={} BOARD={}, BID={}, FEATURES={}", - arch, board, bid, features + "Building for ARCH={arch} BOARD={board}, BID={bid}, enabled_cfgs={}", + enabled.len() )); log(&format!( @@ -129,24 +198,40 @@ fn main() { )); if !source_path.exists() { - log(&format!("Invalid board.rs path: {}, make sure the ARCH and BOARD environment variables are set correctly", source_path_str)); - panic!( - "Invalid board.rs, please check the log file({}) for more details", - BUILD_LOG_FILE - ); + log(&format!("Invalid board.rs path: {source_path_str}")); + panic!("Invalid board.rs, please check the log file({BUILD_LOG_FILE}) for more details"); } - // soft link the board.rs to __board.rs if target_path.exists() { fs::remove_file(target_path).expect("Failed to remove existing __board.rs"); } std::os::unix::fs::symlink(source_path, target_path).expect("Failed to create symlink"); - log(&format!("Linking successful")); + log("Linking successful"); println!("cargo:rerun-if-env-changed=ARCH"); println!("cargo:rerun-if-env-changed=BOARD"); println!("cargo:rerun-if-env-changed=BID"); - println!("cargo:rerun-if-env-changed=FEATURES"); - println!("cargo:rerun-if-changed={}", source_path_str); - println!("cargo:rerun-if-changed={}", target_path_str); + println!("cargo:rerun-if-changed={}", config_path.display()); + println!( + "cargo:rerun-if-changed={}", + root.join("kconfig/cfg_map.toml").display() + ); + println!( + "cargo:rerun-if-changed={}", + root.join("kconfig/Kconfig").display() + ); + println!( + "cargo:rerun-if-changed={}", + root.join("tools/kconfig/kconfig_cli.py").display() + ); + println!( + "cargo:rerun-if-changed={}", + root.join("platform") + .join(&arch) + .join(&board) + .join("kconfig/defconfig") + .display() + ); + println!("cargo:rerun-if-changed={source_path_str}"); + println!("cargo:rerun-if-changed={target_path_str}"); } diff --git a/jenkins/board_flow.py b/jenkins/board_flow.py new file mode 100644 index 000000000..ea13c154a --- /dev/null +++ b/jenkins/board_flow.py @@ -0,0 +1,809 @@ +#!/usr/bin/env python3 +"""Board CI flow helpers (zone0, login, network_and_trans, zone1).""" + +from __future__ import annotations + +import os +import re +import shlex +import subprocess +import time +import uuid +from collections.abc import Callable +from pathlib import Path +from typing import Any + +from terminal import Terminal, TerminalCommandError, TerminalTimeoutError + +ZONE0_READY_PATTERN = r"root@[^\r\n]*#\s?|(?:\r?\n)#\s*(?:\r?\n|$)" +ZONE1_INNER_PROMPT_TIMEOUT = 60.0 +ZONE1_PTS_PATTERN = r"/dev/pts/\d+" +GUNZIP_ARTIFACTS = {"hvisor.gz": "hvisor"} +SPLIT_PART_RE = re.compile(r"^(.+)\.part\.[a-z]{2}$") +BOARD_PUBKEY_LINE = re.compile(r"^ssh-(?:ed25519|rsa)\s+\S+") +BOARD_CMD_MARKER_RE = re.compile(r"__HV_M_(?P[a-f0-9]{4}):(?P\d+)") +MAX_BOARD_CMD_LEN = 128 +LOGIN_TOOLS_DEFAULT = [ + "ping", + "ssh", + "scp", + "gzip", + "gunzip", + "cat", + "ip", + "test", + "wc", + "mkdir", + "timeout", +] + + +def logs_dir(cfg: dict[str, Any]) -> Path: + path = Path(cfg["workspace"]) / "logs" + path.mkdir(parents=True, exist_ok=True) + return path + + +def release_logs_ownership(cfg: dict[str, Any]) -> None: + """Return logs/ to the invoking user when ci_runner ran under sudo.""" + if os.geteuid() != 0: + return + sudo_uid = os.environ.get("SUDO_UID") + sudo_gid = os.environ.get("SUDO_GID") + if not sudo_uid or not sudo_gid: + return + uid, gid = int(sudo_uid), int(sudo_gid) + path = Path(cfg["workspace"]) / "logs" + if not path.is_dir(): + return + for root, dirs, files in os.walk(path, topdown=False): + for name in files: + os.chown(os.path.join(root, name), uid, gid) + for name in dirs: + os.chown(os.path.join(root, name), uid, gid) + os.chown(path, uid, gid) + + +def save_case_log(cfg: dict[str, Any], name: str, content: str) -> None: + path = logs_dir(cfg) / name + path.write_text(content, encoding="utf-8") + print(f"[board_flow] saved {path}", flush=True) + + +def retry_step( + name: str, + fn: Callable[[], None], + retries: int = 2, + delay: float = 3.0, + *, + on_retry: Callable[[], None] | None = None, +) -> None: + last_exc: Exception | None = None + for attempt in range(retries + 1): + if attempt > 0: + print(f"[board_flow] retry {name} ({attempt}/{retries})", flush=True) + if on_retry is not None: + on_retry() + time.sleep(delay) + try: + fn() + return + except (TerminalTimeoutError, TerminalCommandError) as exc: + last_exc = exc + assert last_exc is not None + raise last_exc + + +def shell_pattern(cfg: dict[str, Any]) -> str: + custom = str(cfg.get("zone0_ready_pattern", "")).strip() + return custom or ZONE0_READY_PATTERN + + +def board_wait_shell(term: Terminal, cfg: dict[str, Any], timeout: float = 30.0) -> None: + # Send Enter so the shell prints a fresh prompt in new collector output. + # wait_pattern only searches from the current offset onward. + term.send("") + if not term.wait_pattern(shell_pattern(cfg), timeout=timeout): + raise TerminalTimeoutError("timed out waiting for shell prompt") + + +def board_run( + term: Terminal, + command: str, + *, + timeout: float = 30.0, +) -> tuple[int, str]: + """Run a short shell command; completion is detected via wait_pattern on a marker.""" + if len(command) > MAX_BOARD_CMD_LEN: + raise ValueError( + f"board command too long ({len(command)} > {MAX_BOARD_CMD_LEN}): {command!r}" + ) + run_id = uuid.uuid4().hex[:4] + marker_needle = rf"__HV_M_{run_id}:\d+" + offset = term.offset() + term.send(f"{command}; echo __HV_M_{run_id}:$?") + + deadline = time.monotonic() + timeout + while time.monotonic() < deadline: + remaining = deadline - time.monotonic() + if remaining <= 0: + break + if term.wait_pattern(marker_needle, timeout=min(0.2, remaining), from_offset=offset): + chunk = term.tail_since(offset) + matches = [m for m in BOARD_CMD_MARKER_RE.finditer(chunk) if m.group("run_id") == run_id] + if matches: + match = matches[-1] + rc = int(match.group("rc")) + return rc, chunk[: match.start()] + + raise TerminalTimeoutError( + f"timed out waiting for board command marker __HV_M_{run_id}", + partial_output=term.tail_since(offset), + ) + + +def board_run_check( + term: Terminal, + command: str, + *, + timeout: float = 30.0, +) -> str: + rc, output = board_run(term, command, timeout=timeout) + if rc != 0: + raise TerminalCommandError(f"command failed with rc={rc}: {command}\n{output.strip()}") + return output + + +def board_run_retry( + term: Terminal, + command: str, + timeout: float, + *, + retries: int = 1, + check_exit: bool = False, +) -> tuple[int, str]: + last_exc: TerminalTimeoutError | None = None + for attempt in range(retries + 1): + if attempt > 0: + time.sleep(3.0) + try: + rc, output = board_run(term, command, timeout=timeout) + if check_exit and rc != 0: + raise TerminalCommandError( + f"command failed with rc={rc}: {command}\n{output.strip()}" + ) + return rc, output + except TerminalTimeoutError as exc: + last_exc = exc + assert last_exc is not None + raise last_exc + + +def board_power(cfg: dict[str, Any], action: str) -> None: + power_port = str(cfg.get("power_serial", "")).strip() + if not power_port: + print(f"[power] skip {action}: power_serial is empty", flush=True) + return + script = cfg["workspace"] / "jenkins" / "board_power.sh" + if not script.is_file(): + raise SystemExit(f"board power script not found: {script}") + channel = str(cfg.get("power_channel", 4)) + print(f"[power] {action} port={power_port} channel={channel}", flush=True) + subprocess.run( + ["bash", str(script), action, power_port, channel], + check=True, + cwd=cfg["workspace"], + ) + + +def board_power_cycle(cfg: dict[str, Any]) -> None: + board_power(cfg, "cycle") + + +def board_power_off(cfg: dict[str, Any]) -> None: + board_power(cfg, "off") + + +def close_board_terminal(cfg: dict[str, Any]) -> None: + term = cfg.get("_board_term") + if term is not None: + term.close() + cfg["_board_term"] = None + + +def get_board_terminal(cfg: dict[str, Any]) -> Terminal | None: + return cfg.get("_board_term") + + +def zone0_ready_pattern(cfg: dict[str, Any]) -> str: + return shell_pattern(cfg) + + +def uboot_commands(cfg: dict[str, Any]) -> list[str]: + raw = cfg.get("uboot_cmds") + if isinstance(raw, list): + cmds = [str(item).strip() for item in raw if str(item).strip()] + if cmds: + return cmds + cmd = str(cfg.get("uboot_cmd", "")).strip() + return [cmd] if cmd else [] + + +def board_wait_uboot_prompt( + term: Terminal, + pattern: str, + timeout: float, + *, + autoboot_window: float = 0.0, +) -> None: + if autoboot_window > 0: + deadline = time.monotonic() + autoboot_window + while time.monotonic() < deadline: + remaining = deadline - time.monotonic() + if remaining <= 0: + break + if term.wait_pattern(pattern, timeout=min(0.2, remaining)): + return + term.send(" ") + else: + term.send("") + term.send("") + if not term.wait_pattern(pattern, timeout=timeout): + raise TerminalTimeoutError(f"timed out waiting for U-Boot prompt (pattern={pattern!r})") + + +def send_board_uboot_commands(cfg: dict[str, Any], term: Terminal) -> None: + cmds = uboot_commands(cfg) + if not cmds: + return + uboot_ready = str(cfg.get("uboot_ready_pattern", "")).strip() or r"=>" + initial_timeout = float(cfg.get("uboot_prompt_timeout", 60.0)) + step_timeout = float(cfg.get("uboot_step_timeout", 0.0)) + if step_timeout <= 0: + step_timeout = max(initial_timeout, 60.0) + autoboot_window = float(cfg.get("uboot_autoboot_window", 0.0)) + board_wait_uboot_prompt( + term, + uboot_ready, + timeout=initial_timeout, + autoboot_window=autoboot_window, + ) + for index, cmd in enumerate(cmds): + term.send(cmd) + if index < len(cmds) - 1: + board_wait_uboot_prompt(term, uboot_ready, timeout=step_timeout) + + +def boot_board_zone0(cfg: dict[str, Any], term: Terminal) -> None: + board_power_cycle(cfg) + send_board_uboot_commands(cfg, term) + timeout = float(cfg.get("zone0_shell_timeout", 180.0)) + if not term.wait_pattern(zone0_ready_pattern(cfg), timeout=timeout): + raise TerminalTimeoutError("timed out waiting for zone0 shell prompt") + + +def board_login_user(term: Terminal, cfg: dict[str, Any]) -> str: + _, out = board_run(term, "id -un", timeout=15.0) + for line in out.splitlines(): + candidate = line.strip() + if candidate and re.fullmatch(r"[\w.-]+", candidate): + return candidate + raise TerminalCommandError(f"failed to detect board login user: {out.strip()!r}") + + +def prepare_board_shell(cfg: dict[str, Any], term: Terminal) -> None: + if cfg.get("_board_shell_ready"): + return + user = board_login_user(term, cfg) + cfg["board_is_root"] = user == "root" + board_run(term, "export HOME=$(cd ~ && pwd)", timeout=15.0) + cfg["_board_shell_ready"] = True + print(f"[board] shell ready: user={user}", flush=True) + + +def check_login_tools(cfg: dict[str, Any], term: Terminal) -> None: + tools = cfg.get("login_tools") or LOGIN_TOOLS_DEFAULT + missing: list[str] = [] + for tool in tools: + name = str(tool) + rc, _ = board_run( + term, + f"command -v {shlex.quote(name)} >/dev/null", + timeout=15.0, + ) + if rc != 0: + missing.append(name) + if missing: + print(f"[login] WARNING: missing required tools: {missing}", flush=True) + raise SystemExit(1) + print(f"[login] all required tools available ({len(tools)})", flush=True) + + +def netmask_prefix(netmask: str) -> int: + try: + return sum(bin(int(part)).count("1") for part in netmask.split(".")) + except (ValueError, AttributeError): + return 24 + + +def board_ssh_host(cfg: dict[str, Any]) -> str: + return f"{cfg['host_user']}@{cfg['host_ip']}" + + +def board_path(work_dir: str, *parts: str) -> str: + rel = "/".join(parts) + if work_dir == "~": + return f"~/{rel}" if rel else "~" + return f"{work_dir}/{rel}" if rel else work_dir + + +def ping_success(output: str) -> bool: + if re.search(r"0%\s*(?:packet\s*)?loss\b", output, re.I): + return True + if re.search(r"0%\s*包丢失", output): + return True + match = re.search(r"(\d+)\s*packets?\s*received", output, re.I) + if match and int(match.group(1)) > 0: + return True + match = re.search(r"已接收\s*(\d+)\s*个包", output) + return bool(match and int(match.group(1)) > 0) + + +def board_pubkey_from_output(output: str) -> str | None: + for line in output.splitlines(): + candidate = line.strip() + if BOARD_PUBKEY_LINE.match(candidate): + return candidate + return None + + +def export_board_ssh_env(cfg: dict[str, Any], term: Terminal) -> None: + if cfg.get("_board_ssh_env"): + return + connect = int(cfg.get("ssh_connect_timeout", 60)) + board_run(term, f"export CI_SSH_HOST={shlex.quote(board_ssh_host(cfg))}", timeout=15.0) + board_run(term, 'export CI_SSH_OPTS="-o BatchMode=yes"', timeout=15.0) + board_run(term, f'export CI_SSH_OPTS="$CI_SSH_OPTS -o ConnectTimeout={connect}"', timeout=15.0) + board_run( + term, + 'export CI_SSH_OPTS="$CI_SSH_OPTS -o StrictHostKeyChecking=no"', + timeout=15.0, + ) + cfg["_board_ssh_env"] = True + + +def setup_board_interface(cfg: dict[str, Any], term: Terminal) -> None: + board_ip = str(cfg.get("board_ip", "")).strip() + board_iface = str(cfg.get("board_iface", "")).strip() + if not board_ip or not board_iface: + return + netmask = str(cfg.get("board_netmask", "255.255.255.0")).strip() or "255.255.255.0" + prefix = netmask_prefix(netmask) + board_run(term, f"ip addr flush dev {board_iface} 2>/dev/null || true", timeout=15.0) + board_run(term, f"ip addr add {board_ip}/{prefix} dev {board_iface}", timeout=30.0) + board_run(term, f"ip link set {board_iface} down", timeout=15.0) + board_run(term, f"ip link set {board_iface} up", timeout=15.0) + link_wait = float(cfg.get("link_wait", 0.0)) + if link_wait > 0: + print(f"[network] waiting {link_wait}s for link", flush=True) + time.sleep(link_wait) + board_wait_shell(term, cfg, timeout=10.0) + + +def ping_host(cfg: dict[str, Any], term: Terminal) -> None: + host_ip = cfg["host_ip"] + ping_count = int(cfg.get("ping_count", 3)) + ping_retries = int(cfg.get("ping_retries", 1)) + ping_output = "" + for attempt in range(ping_retries): + if attempt > 0: + retry_wait = float(cfg.get("link_wait", 5.0)) or 5.0 + print(f"[network] ping retry {attempt + 1}/{ping_retries}", flush=True) + time.sleep(retry_wait) + board_run( + term, + f"ping -c {ping_count} -W 5 {host_ip} >/tmp/ci_ping.log 2>&1", + timeout=30.0 + ping_count * 5.0, + ) + _, ping_output = board_run(term, "cat /tmp/ci_ping.log", timeout=15.0) + if ping_success(ping_output): + break + save_case_log(cfg, "deploy_ping.log", f"=== ping {host_ip} ===\n{ping_output}\n") + if not ping_success(ping_output): + raise TerminalCommandError(f"ping {host_ip} failed") + print(f"[network] ping {host_ip} ok", flush=True) + + +def probe_board_ssh(cfg: dict[str, Any], term: Terminal) -> None: + export_board_ssh_env(cfg, term) + host_user = cfg["host_user"] + host_ip = cfg["host_ip"] + connect_timeout = int(cfg.get("ssh_connect_timeout", 60)) + board_limit = connect_timeout + 15 + probe_rc, probe_out = board_run( + term, + f"timeout {board_limit} ssh $CI_SSH_OPTS $CI_SSH_HOST true /dev/null || true", + timeout=15.0, + ) + if not board_pubkey_from_output(pub_out): + _, pub_out2 = board_run(term, "cat ~/.ssh/id_rsa.pub 2>/dev/null || true", timeout=15.0) + pub_out = pub_out + pub_out2 + pubkey = board_pubkey_from_output(pub_out) + if not pubkey: + raise TerminalCommandError( + f"ssh probe to {host_user}@{host_ip} failed and board public key not found\n" + f"{probe_out.strip()}" + ) + auth_keys = f"/home/{host_user}/.ssh/authorized_keys" + raise TerminalCommandError( + f"ssh probe to {host_user}@{host_ip} failed; add board public key to " + f"{auth_keys} on the CI host:\n{pubkey}" + ) + + +def setup_board_network(cfg: dict[str, Any], term: Terminal) -> None: + setup_board_interface(cfg, term) + ping_host(cfg, term) + probe_board_ssh(cfg, term) + + +def resolve_staging_dir(raw: str, arch: str, board: str) -> str: + base = (raw or "/home/light/ci_deploy").rstrip("/") + suffix = f"{arch}__{board.replace('/', '__')}" + if base.endswith(suffix): + return base + return f"{base}/{suffix}" + + +def stage_board_files(cfg: dict[str, Any]) -> None: + script = cfg["workspace"] / "jenkins" / "board_stage.sh" + if not script.is_file(): + raise SystemExit(f"board stage script not found: {script}") + env = os.environ.copy() + env["ARCH"] = cfg["arch"] + env["BOARD"] = cfg["board"] + env["WORKSPACE_ROOT"] = str(cfg["workspace"]) + env["HVISOR_TOOL_PATH"] = cfg["hvisor_tool_path"] + env["STAGING_DIR"] = cfg["staging_dir"] + if cfg.get("zone1_dtb"): + zone1_dtb = Path(cfg["zone1_dtb"]) + if not zone1_dtb.is_absolute(): + zone1_dtb = cfg["workspace"] / zone1_dtb + env["ZONE1_DTB"] = str(zone1_dtb.resolve()) + subprocess.run(["bash", str(script)], check=True, cwd=cfg["workspace"], env=env) + + +def staging_alias(cfg: dict[str, Any]) -> str: + alias = Path("/tmp/s") / cfg["board"].replace("/", "_") + target = Path(cfg["staging_dir"]) + alias.parent.mkdir(parents=True, exist_ok=True) + if alias.is_symlink() or alias.exists(): + alias.unlink() + alias.symlink_to(target, target_is_directory=True) + return str(alias) + + +def parse_staging(staging_path: Path) -> tuple[list[str], dict[str, list[str]], list[str]]: + regular: list[str] = [] + split_groups: dict[str, list[str]] = {} + for entry in staging_path.iterdir(): + if not entry.is_file(): + continue + name = entry.name + match = SPLIT_PART_RE.match(name) + if match: + split_groups.setdefault(match.group(1), []).append(name) + continue + regular.append(name) + for base in split_groups: + split_groups[base] = sorted(split_groups[base]) + parts = [part for names in split_groups.values() for part in names] + pull_files = sorted(regular + parts, key=lambda n: staging_path.joinpath(n).stat().st_size) + return regular, split_groups, pull_files + + +def file_pull_timeout(file_size: int, remaining: float) -> float: + needed = max(90.0, file_size / 8192.0 + 45.0) + return min(remaining, needed) + + +def ensure_scp_tmp(cfg: dict[str, Any], term: Terminal) -> None: + board_run(term, f"mkdir -p {cfg['scp_tmp_dir']}", timeout=15.0) + + +def scp_one_to_tmp( + cfg: dict[str, Any], + term: Terminal, + name: str, + file_size: int, + file_timeout: float, + all_logs: list[str], +) -> None: + tmp = cfg["scp_tmp_dir"] + tmp_file = cfg["scp_tmp_file"] + scp_limit = max(60, int(file_timeout) - 5) + scp_cmd = ( + f"timeout {scp_limit} scp -q $CI_SSH_OPTS $CI_SSH_HOST:$CI_D/{name} " + f"$CI_F /dev/null" + ) + dest_in_tmp = f"{tmp}/{name}" + try: + rc, out = board_run_retry(term, scp_cmd, file_timeout, retries=0) + if rc != 0: + raise TerminalCommandError(f"board scp failed for {name!r}: {out.strip()}") + rc, out = board_run_retry(term, f"cp {tmp_file} {dest_in_tmp}", 30.0, retries=0) + if rc != 0: + raise TerminalCommandError(f"board tmp install failed for {name!r}: {out.strip()}") + except TerminalTimeoutError: + check_tmp = f"test $(wc -c < {tmp_file}) -eq {file_size}" + rc, out = board_run_retry(term, check_tmp, 30.0, retries=0) + if rc != 0: + all_logs.append(f"=== scp_{name} timeout ===\n{out}\n") + raise + rc, out = board_run_retry(term, f"cp {tmp_file} {dest_in_tmp}", 30.0, retries=0) + if rc != 0: + raise TerminalCommandError(f"board tmp install failed for {name!r}: {out.strip()}") + print(f"[trans] scp recovered after timeout: {name}", flush=True) + all_logs.append(f"=== scp_{name} ok ===\n") + + +def assemble_split_in_tmp( + cfg: dict[str, Any], + term: Terminal, + staging_path: Path, + base: str, + parts: list[str], + all_logs: list[str], +) -> None: + tmp = cfg["scp_tmp_dir"] + expected_size = sum(staging_path.joinpath(part).stat().st_size for part in parts) + out_path = f"{tmp}/{base}" + print(f"[trans] assemble {base} from {len(parts)} part(s) in tmp", flush=True) + board_run_check(term, f"cp {tmp}/{parts[0]} {out_path}", timeout=60.0) + for part in parts[1:]: + board_run_check(term, f"cat {tmp}/{part} >> {out_path}", timeout=60.0) + board_run_check(term, f"test $(wc -c < {out_path}) -eq {expected_size}", timeout=30.0) + for part in parts: + board_run(term, f"rm -f {tmp}/{part}", timeout=15.0) + all_logs.append(f"=== assemble {base} ===\n") + + +def gunzip_in_tmp(cfg: dict[str, Any], term: Terminal, gz_name: str, all_logs: list[str]) -> None: + raw_name = GUNZIP_ARTIFACTS[gz_name] + raw_path = Path(cfg["hvisor_tool_path"]) / "output" / raw_name + raw_size = raw_path.stat().st_size + tmp = cfg["scp_tmp_dir"] + print(f"[trans] gunzip in tmp: {gz_name} -> {raw_name}", flush=True) + board_run_check(term, f"gunzip -f {tmp}/{gz_name}", timeout=120.0) + board_run_check(term, f"test $(wc -c < {tmp}/{raw_name}) -eq {raw_size}", timeout=30.0) + all_logs.append(f"=== gunzip {raw_name} ===\n") + + +def install_tmp_to_workdir(cfg: dict[str, Any], term: Terminal, names: list[str]) -> None: + work_dir = cfg["zone1_work_dir"] + tmp = cfg["scp_tmp_dir"] + board_run(term, f"mkdir -p {work_dir}", timeout=15.0) + for name in names: + board_run_check(term, f"cp {tmp}/{name} {board_path(work_dir, name)}", timeout=60.0) + for script in ("boot_zone1.sh", "hvisor", "check_serial.sh"): + board_run(term, f"chmod +x {board_path(work_dir, script)} 2>/dev/null || true", timeout=15.0) + print(f"[trans] installed {len(names)} file(s) to {work_dir}", flush=True) + + +def pull_to_tmp_and_install(cfg: dict[str, Any], term: Terminal) -> None: + stage_board_files(cfg) + staging_path = Path(cfg["staging_dir"]) + if not staging_path.is_dir(): + raise TerminalCommandError(f"staging dir not found: {staging_path}") + staging_dir = staging_alias(cfg) + ensure_scp_tmp(cfg, term) + export_board_ssh_env(cfg, term) + board_run(term, f"export CI_D={shlex.quote(staging_dir)}", timeout=15.0) + board_run(term, f"export CI_T={shlex.quote(cfg['scp_tmp_dir'])}", timeout=15.0) + board_run(term, f"export CI_F={shlex.quote(cfg['scp_tmp_file'])}", timeout=15.0) + regular_files, split_groups, pull_files = parse_staging(staging_path) + if not pull_files: + raise TerminalCommandError(f"no staged files in {staging_path}") + pull_timeout = float(cfg.get("pull_timeout", 600.0)) + deadline = time.monotonic() + pull_timeout + all_logs: list[str] = [] + tmp = cfg["scp_tmp_dir"] + stale = sorted(set(pull_files) | set(split_groups) | set(GUNZIP_ARTIFACTS.values())) + for name in stale: + board_run(term, f"rm -f {tmp}/{name}", timeout=15.0) + print(f"[trans] pulling {len(pull_files)} file(s) to {tmp}", flush=True) + for index, name in enumerate(pull_files, start=1): + if index > 1: + time.sleep(3.0) + remaining = deadline - time.monotonic() + if remaining <= 0: + raise TerminalTimeoutError("pull timed out before completing scp") + file_size = staging_path.joinpath(name).stat().st_size + file_timeout = file_pull_timeout(file_size, remaining) + print(f"[trans] scp ({index}/{len(pull_files)}): {name}", flush=True) + scp_one_to_tmp(cfg, term, name, file_size, file_timeout, all_logs) + for base, parts in sorted(split_groups.items()): + assemble_split_in_tmp(cfg, term, staging_path, base, parts, all_logs) + for gz_name in GUNZIP_ARTIFACTS: + if gz_name in regular_files or gz_name in split_groups: + gunzip_in_tmp(cfg, term, gz_name, all_logs) + install_names = sorted(set(regular_files) | set(split_groups)) + for gz, raw in GUNZIP_ARTIFACTS.items(): + if gz in install_names: + install_names.remove(gz) + install_names.append(raw) + install_tmp_to_workdir(cfg, term, install_names) + save_case_log(cfg, "deploy_scp.log", "".join(all_logs)) + + +def strip_board_markers(text: str) -> str: + return BOARD_CMD_MARKER_RE.sub("", text) + + +def parse_boot_script_lines(content: str) -> list[str]: + content = strip_board_markers(content) + lines: list[str] = [] + for raw in content.splitlines(): + line = raw.strip() + if not line or line.startswith("#"): + continue + if line.startswith("#!/"): + continue + if "__HV_M_" in line or "; echo " in line: + continue + lines.append(line) + return lines + + +def board_zone_list_shows_running( + term: Terminal, + zone_name: str = "linux2", +) -> None: + # hvisor-tool returns zone count (non-zero) from zone list; validate output instead. + _, out = board_run(term, "./hvisor zone list", timeout=15.0) + if zone_name not in out or "running" not in out: + raise TerminalCommandError( + f"zone list missing running {zone_name!r}:\n{out.strip()}" + ) + + +def boot_line_command(work_dir: str, line: str) -> str: + stripped = line.rstrip() + if stripped.startswith("cd "): + inner = stripped + else: + inner = f"cd {work_dir} && {stripped}" + if stripped.endswith("&"): + return f"( {inner} )" + return inner + + +def line_timeout(line: str) -> float: + if "&" in line or "nohup" in line: + return 30.0 + return 120.0 + + +def find_zone1_pts(term: Terminal, timeout: float = 60.0) -> int: + """Return the newest virtio-console pts number (poll ls until it appears).""" + deadline = time.monotonic() + timeout + last_output = "" + while time.monotonic() < deadline: + _, pts_output = board_run(term, "ls -1 /dev/pts/[0-9]*", timeout=15.0) + last_output = pts_output + pts_numbers = sorted(int(m) for m in re.findall(r"/dev/pts/(\d+)", pts_output)) + if pts_numbers: + return pts_numbers[-1] + time.sleep(1.0) + raise TerminalCommandError( + f"timed out waiting for zone1 pts device (last ls output: {last_output.strip()!r})" + ) + + +def run_boot_script_lines(cfg: dict[str, Any], term: Terminal) -> None: + work_dir = cfg["zone1_work_dir"] + boot_script = "boot_zone1.sh" + _, content = board_run(term, f"cat {board_path(work_dir, boot_script)}", timeout=30.0) + lines = parse_boot_script_lines(content) + if not lines: + raise TerminalCommandError(f"no executable lines in {boot_script}") + print(f"[zone1] running {len(lines)} line(s) from {boot_script}", flush=True) + for index, line in enumerate(lines, start=1): + cmd = boot_line_command(work_dir, line) + if len(cmd) > MAX_BOARD_CMD_LEN: + raise TerminalCommandError( + f"boot line {index} too long ({len(cmd)} > {MAX_BOARD_CMD_LEN}): {line!r}" + ) + try: + board_run_check(term, cmd, timeout=line_timeout(line)) + except TerminalCommandError as exc: + raise TerminalCommandError(f"boot line {index} failed: {line}\n{exc}") from exc + + +def boot_board_zone0_with_retry(cfg: dict[str, Any], term: Terminal) -> None: + retry_step( + "zone0_boot", + lambda: boot_board_zone0(cfg, term), + retries=int(cfg.get("retry_zone0", 2)), + ) + + +def board_login(cfg: dict[str, Any], term: Terminal) -> int: + prepare_board_shell(cfg, term) + check_login_tools(cfg, term) + return 0 + + +def board_network_and_trans(cfg: dict[str, Any], term: Terminal) -> int: + def run_trans() -> None: + setup_board_network(cfg, term) + pull_to_tmp_and_install(cfg, term) + + def on_network_retry() -> None: + term.send("\x03") + time.sleep(1.0) + board_wait_shell(term, cfg, timeout=30.0) + + retry_step( + "network_and_trans", + run_trans, + retries=int(cfg.get("retry_network", 2)), + on_retry=on_network_retry, + ) + return 0 + + +def board_zone1_stop(cfg: dict[str, Any], term: Terminal) -> None: + """Stop zone1 before a retry (hvisor-tool: zone shutdown -id ).""" + work_dir = cfg["zone1_work_dir"] + zone_id = int(cfg.get("zone1_id", 1)) + board_run(term, f"cd {work_dir}", timeout=15.0) + rc, out = board_run(term, f"./hvisor zone shutdown -id {zone_id}", timeout=60.0) + if rc != 0: + print( + f"[zone1] shutdown rc={rc} (zone may not be running): {out.strip()}", + flush=True, + ) + board_wait_shell(term, cfg, timeout=30.0) + + +def board_zone1_start(cfg: dict[str, Any], term: Terminal) -> int: + work_dir = cfg["zone1_work_dir"] + inner_log = "/tmp/zone1_inner.log" + + def run_zone1() -> None: + board_run(term, f"cd {work_dir}", timeout=15.0) + board_run(term, "ls", timeout=15.0) + run_boot_script_lines(cfg, term) + board_zone_list_shows_running( + term, str(cfg.get("zone1_name", "linux2")) + ) + max_pts = find_zone1_pts(term) + board_run(term, f"cd {work_dir}", timeout=15.0) + check_rc, _ = board_run( + term, + f"./check_serial.sh /dev/pts/{max_pts} {inner_log} {int(ZONE1_INNER_PROMPT_TIMEOUT)}", + timeout=ZONE1_INNER_PROMPT_TIMEOUT + 30.0, + ) + if check_rc != 0: + raise TerminalCommandError("check_serial.sh failed (no console prompt)") + _, inner_output = board_run(term, f"tail -c 131072 {inner_log}", timeout=30.0) + if inner_output: + save_case_log(cfg, "zone1_inner_serial.log", inner_output) + + retry_step( + "zone1_start", + run_zone1, + retries=int(cfg.get("retry_zone1", 1)), + on_retry=lambda: board_zone1_stop(cfg, term), + ) + print("zone1_started successfully", flush=True) + return 0 diff --git a/jenkins/board_power.sh b/jenkins/board_power.sh new file mode 100755 index 000000000..150e3c097 --- /dev/null +++ b/jenkins/board_power.sh @@ -0,0 +1,76 @@ +#!/bin/sh +# Relay power control for board CI (socat hex frames). +# Usage: board_power.sh off|on|cycle [channel] +# cycle: off, wait 3s, on + +set -eu + +action=${1:?action required (off|on|cycle)} +port=${2:?serial port required, e.g. /dev/ttyUSB1} +channel=${3:-4} +lock_file=${RELAY_LOCK_FILE:-/var/lock/hvisor-relay.lock} +lock_timeout=${RELAY_LOCK_TIMEOUT:-300} + +case "${channel}" in + 1|2|3|4) ;; + *) + echo "invalid relay channel: ${channel}" >&2 + exit 1 + ;; +esac + +socat_serial_addr() { + # by-path device names contain ':'; socat treats them as option separators. + case "$port" in + *:*) + escaped=$(printf '%s' "$port" | sed 's/:/\\:/g') + printf 'GOPEN:%s,b9600,raw,echo=0' "$escaped" + ;; + *) + printf '%s,b9600,raw,echo=0' "$port" + ;; + esac +} + +send_frame() { + state=$1 + checksum=$((0xA0 + channel + state)) + printf '[power] send port=%s channel=%s state=%s frame=A0%02X%02X%02X\n' \ + "$port" "$channel" "$state" "$channel" "$state" "$checksum" + frame=$(printf '\\%03o\\%03o\\%03o\\%03o' 160 "$channel" "$state" "$checksum") + addr=$(socat_serial_addr) + if [ "$(id -u)" -eq 0 ]; then + printf '%b' "$frame" | socat - "$addr" >/dev/null + else + printf '%b' "$frame" | sudo socat - "$addr" >/dev/null + fi +} + +command -v flock >/dev/null 2>&1 || { + echo "error: flock is required for relay serial locking" >&2 + exit 1 +} + +exec 9>"${lock_file}" +flock -w "${lock_timeout}" 9 || { + echo "error: timed out waiting for relay lock: ${lock_file}" >&2 + exit 1 +} + +case "$action" in + off) + send_frame 0 + ;; + on) + send_frame 1 + ;; + cycle) + send_frame 0 + sleep 3 + send_frame 1 + ;; + *) + echo "usage: $0 off|on|cycle [channel]" >&2 + exit 1 + ;; +esac diff --git a/jenkins/board_stage.sh b/jenkins/board_stage.sh new file mode 100755 index 000000000..8880f738f --- /dev/null +++ b/jenkins/board_stage.sh @@ -0,0 +1,101 @@ +#!/bin/sh +# Stage zone1 deploy artifacts on the CI host; the board pulls them via scp. +# Zone0 boot artifacts (hvisor.bin, Image, dtbs) belong in tftp_dir, not here. + +set -eux + +ARCH=${ARCH:?ARCH is required} +BOARD=${BOARD:?BOARD is required} +WORKSPACE_ROOT=${WORKSPACE_ROOT:-$(pwd)} +HVISOR_TOOL_PATH=${HVISOR_TOOL_PATH:-${WORKSPACE_ROOT}/hvisor-tool} +STAGING_DIR=${STAGING_DIR:-/home/light/ci_deploy} + +case "${HVISOR_TOOL_PATH}" in + /*) ;; + *) HVISOR_TOOL_PATH="${WORKSPACE_ROOT}/${HVISOR_TOOL_PATH}" ;; +esac + +PLATFORM_DIR="${WORKSPACE_ROOT}/platform/${ARCH}/${BOARD}" +CONFIGS_DIR="${PLATFORM_DIR}/configs" +IMAGE_DIR="${PLATFORM_DIR}/image" +SCRIPTS_DIR="${PLATFORM_DIR}/scripts" +ZONE1_BOOT_SCRIPT="${SCRIPTS_DIR}/boot_zone1.sh" +CHECK_SERIAL_SCRIPT="${WORKSPACE_ROOT}/jenkins/check_serial.sh" + +if [ -z "${ZONE1_DTB:-}" ]; then + for candidate in \ + "${IMAGE_DIR}/dts/zone1-linux.dtb" \ + "${IMAGE_DIR}/dts/linux2.dtb"; do + if [ -f "${candidate}" ]; then + ZONE1_DTB="${candidate}" + break + fi + done + ZONE1_DTB=${ZONE1_DTB:-${IMAGE_DIR}/dts/zone1-linux.dtb} +fi + +echo "ARCH: ${ARCH}" +echo "BOARD: ${BOARD}" +echo "HVISOR_TOOL_PATH: ${HVISOR_TOOL_PATH}" +echo "STAGING_DIR: ${STAGING_DIR}" + +if [ ! -f "${HVISOR_TOOL_PATH}/output/hvisor" ]; then + echo "error: hvisor tool binary not found: ${HVISOR_TOOL_PATH}/output/hvisor" + exit 1 +fi +if [ ! -f "${HVISOR_TOOL_PATH}/output/hvisor.ko" ]; then + echo "error: hvisor.ko not found: ${HVISOR_TOOL_PATH}/output/hvisor.ko" + exit 1 +fi +if [ ! -f "${ZONE1_BOOT_SCRIPT}" ]; then + echo "error: zone1 start script not found: ${ZONE1_BOOT_SCRIPT}" + exit 1 +fi + +if [ ! -f "${ZONE1_DTB}" ] && [ -d "${IMAGE_DIR}/dts" ]; then + echo "zone1 dtb is missing, building from ${IMAGE_DIR}/dts" + make -C "${IMAGE_DIR}/dts" all || true +fi + +rm -rf "${STAGING_DIR}" +mkdir -p "${STAGING_DIR}" + +cp "${HVISOR_TOOL_PATH}/output/hvisor.ko" "${STAGING_DIR}/" +gzip -c "${HVISOR_TOOL_PATH}/output/hvisor" > "${STAGING_DIR}/hvisor.gz" +cp "${CONFIGS_DIR}/"* "${STAGING_DIR}/" +cp "${ZONE1_BOOT_SCRIPT}" "${STAGING_DIR}/" + +if [ -f "${ZONE1_DTB}" ]; then + cp "${ZONE1_DTB}" "${STAGING_DIR}/" +else + echo "warning: zone1 dtb unavailable, skip copying ${ZONE1_DTB}" +fi + +if [ -f "${CHECK_SERIAL_SCRIPT}" ]; then + cp "${CHECK_SERIAL_SCRIPT}" "${STAGING_DIR}/" +fi + +chmod -R a+rX "${STAGING_DIR}" +chmod +x "${STAGING_DIR}/boot_zone1.sh" + +if [ "$(id -u)" -eq 0 ] && id light >/dev/null 2>&1; then + chown -R light:light "${STAGING_DIR}" +fi + +DEPLOY_SPLIT_CHUNK_BYTES=${DEPLOY_SPLIT_CHUNK_BYTES:-524288} +for staged_file in "${STAGING_DIR}"/*; do + [ -f "${staged_file}" ] || continue + staged_name=$(basename "${staged_file}") + case "${staged_name}" in + *.part.*) continue ;; + esac + size=$(stat -c%s "${staged_file}") + if [ "${size}" -gt "${DEPLOY_SPLIT_CHUNK_BYTES}" ]; then + split -b "${DEPLOY_SPLIT_CHUNK_BYTES}" "${staged_file}" "${STAGING_DIR}/${staged_name}.part." + rm -f "${staged_file}" + echo "split ${staged_name}: ${size} bytes into ${DEPLOY_SPLIT_CHUNK_BYTES}-byte chunks" + fi +done + +echo "board staging completed: ${STAGING_DIR}" +ls -la "${STAGING_DIR}" diff --git a/jenkins/check_serial.sh b/jenkins/check_serial.sh new file mode 100755 index 000000000..fb2cd6316 --- /dev/null +++ b/jenkins/check_serial.sh @@ -0,0 +1,50 @@ +#!/bin/sh +# Non-interactive virtio-console check for inner zone (/dev/pts/x). +# Usage: check_serial.sh [timeout_sec] [command...] + +set -eu + +pts_dev=${1:?pts device required} +log_file=${2:?log file required} +shift 2 + +prompt_timeout=60 +if [ $# -gt 0 ] && [ "$1" -eq "$1" ] 2>/dev/null; then + prompt_timeout=$1 + shift +fi + +: > "$log_file" + +read_pts() { + timeout "${1:-2}" cat "$pts_dev" 2>/dev/null >> "$log_file" || true +} + +has_console_ready() { + tr -d '\r' < "$log_file" | sed 's/\x1b\[[0-9;?]*[ -\/]*[@-~]//g' \ + | grep -qE 'root@[^[:space:]]*[#$][[:space:]]*$|^[[:space:]]*#[[:space:]]*$|login:[[:space:]]*$' +} + +deadline=$(( $(date +%s) + prompt_timeout )) +while [ "$(date +%s)" -lt "$deadline" ]; do + printf '\r\n' > "$pts_dev" 2>/dev/null || true + read_pts 2 + if has_console_ready; then + break + fi + sleep 0.2 +done + +if ! has_console_ready; then + echo "check_serial: timed out after ${prompt_timeout}s waiting for console prompt on $pts_dev" \ + >> "$log_file" + exit 1 +fi + +if [ $# -gt 0 ]; then + printf '%s\r\n' "$@" + sleep 1 + read_pts 10 +fi + +exit 0 diff --git a/jenkins/ci.yaml b/jenkins/ci.yaml new file mode 100644 index 000000000..9542f239a --- /dev/null +++ b/jenkins/ci.yaml @@ -0,0 +1,115 @@ +bids: + - bid: riscv64/qemu-plic + build_args: + - KDIR=/home/light/DEMO/linux/linux-6.10 + tests: + mode: qemu + cases: + - zone0_start + - zone1_start + + - bid: aarch64/qemu-gicv3 + build_args: + - KDIR=/home/light/DEMO/linux/linux-5.4 + tests: + mode: qemu + uboot_cmd: bootm 0x40400000 - 0x40000000 + cases: + - zone0_start + - zone1_start + + - bid: aarch64/rk3568 + build_args: + - KDIR=/home/light/DEMO/sdk/rk356x-up4-2c/kernel + tests: + mode: board + serial: /dev/serial/by-path/pci-0000:00:14.0-usb-0:9:1.0-port0 + power_serial: /dev/serial/by-path/pci-0000:00:14.0-usb-0:10:1.0-port0 + power_channel: 4 + baudrate: 1500000 + tftp_dir: /home/light/tftp/rk3568 + zone0_dtbs: + - platform/aarch64/rk3568/image/dts/rk3568_limit_zone0.dtb + zone0_image: /home/light/DEMO/sdk/rk356x-up4-2c/kernel/arch/arm64/boot/Image + uboot_ready_pattern: '=>' + zone0_ready_pattern: 'root@linux:[^\r\n]*#\s?' + zone0_shell_timeout: 180 + uboot_step_timeout: 90 + uboot_cmds: + - pci enum; setenv serverip 192.168.1.181; setenv ipaddr 192.168.1.240; setenv loadaddr 0x60800000; setenv fdt_addr 0xa0000000; setenv zone0_kernel_addr 0x00280000 + - tftp ${loadaddr} ${serverip}:rk3568/hvisor.bin + - tftp ${fdt_addr} ${serverip}:rk3568/rk3568_limit_zone0.dtb + - tftp ${zone0_kernel_addr} ${serverip}:rk3568/Image + - bootm ${loadaddr} - ${fdt_addr} + deploy: + board_ip: 192.168.1.240 + board_iface: eth0 + link_wait: 3 + host_ip: 192.168.1.181 + host_user: light + zone1_dtb: platform/aarch64/rk3568/image/dts/rk3568_limit_zone1.dtb + cases: + - zone0_start + - login + - network_and_trans + - zone1_start + + - bid: aarch64/phytium-pi + build_args: + - KDIR=/home/light/DEMO/linux/kernel-5.10 + tests: + mode: board + serial: /dev/serial/by-path/pci-0000:00:14.0-usb-0:7:1.0-port0 + power_serial: /dev/serial/by-path/pci-0000:00:14.0-usb-0:10:1.0-port0 + power_channel: 3 + baudrate: 115200 + tftp_dir: /home/light/tftp/phytium-pi + zone0_dtbs: + - platform/aarch64/phytium-pi/image/dts/linux1.dtb + - platform/aarch64/phytium-pi/image/dts/phytium-pi-board-v2.dtb + zone0_image: /home/light/DEMO/phytium-pi-external/Image + uboot_ready_pattern: 'Phytium-Pi#' + zone0_ready_pattern: 'root@[^\r\n]*:\/#\s?|(?:\r?\n)#\s*(?:\r?\n|$)' + zone0_shell_timeout: 300 + uboot_step_timeout: 600 + uboot_autoboot_window: 15 + uboot_cmds: + - setenv serverip 192.168.1.181; setenv ipaddr 192.168.1.179; setenv loadaddr 0x90100000; setenv fdt_addr 0x90000000; setenv zone0_kernel_addr 0xa0400000; setenv zone0_fdt_addr 0xa0000000 + - tftp ${loadaddr} ${serverip}:phytium-pi/hvisor.bin + - tftp ${fdt_addr} ${serverip}:phytium-pi/phytium-pi-board-v2.dtb + - tftp ${zone0_kernel_addr} ${serverip}:phytium-pi/Image + - tftp ${zone0_fdt_addr} ${serverip}:phytium-pi/linux1.dtb + - bootm ${loadaddr} - ${fdt_addr} + deploy: + board_ip: 192.168.1.179 + board_iface: eth0 + link_wait: 8 + ping_retries: 3 + host_ip: 192.168.1.181 + host_user: light + pull_timeout: 900 + cases: + - zone0_start + - login + - network_and_trans + - zone1_start + + - bid: x86_64/qemu + build_args: + - KDIR=/home/light/DEMO/linux/linux-5.19 + tests: + mode: qemu + cases: + - zone0_start + - zone1_start + + - bid: x86_64/qemu_asterinas + platform_board: qemu + build_args: + - KDIR=/home/light/DEMO/linux/linux-5.19 + tests: + mode: qemu + artifact_dir: qemu_asterinas + cases: + - zone0_start + - asterinas_zone1_regression diff --git a/jenkins/ci_config.py b/jenkins/ci_config.py new file mode 100755 index 000000000..fe20d81fd --- /dev/null +++ b/jenkins/ci_config.py @@ -0,0 +1,102 @@ +#!/usr/bin/env python3 +"""Read jenkins/ci.yaml for BID and test metadata.""" + +from __future__ import annotations + +import argparse +import json +from pathlib import Path +from typing import Any + +import yaml + + +ROOT = Path(__file__).resolve().parent.parent +CI_YAML = ROOT / "jenkins" / "ci.yaml" + + +def parse_bid(bid: str) -> tuple[str, str]: + parts = bid.strip().split("/", 1) + if len(parts) != 2 or not parts[0].strip() or not parts[1].strip(): + raise ValueError(f"invalid BID: {bid!r}") + return parts[0].strip(), parts[1].strip() + + +def normalize_build_args(raw: list[Any] | None) -> dict[str, str]: + result: dict[str, str] = {} + for item in raw or []: + if isinstance(item, dict): + for key, val in item.items(): + result[str(key)] = str(val) + continue + parts = str(item).split("=", 1) + if len(parts) == 2: + result[parts[0]] = parts[1] + return result + + +def load_ci() -> dict[str, Any]: + if not CI_YAML.exists(): + raise RuntimeError(f"missing ci config: {CI_YAML}") + with CI_YAML.open("r", encoding="utf-8") as fh: + data = yaml.safe_load(fh) or {} + bids = data.get("bids") + if not isinstance(bids, list): + raise RuntimeError("ci.yaml: 'bids' must be a list") + return data + + +def list_bids(data: dict[str, Any]) -> list[str]: + out: list[str] = [] + for item in data.get("bids", []): + bid = str((item or {}).get("bid", "")).strip() + if bid: + out.append(bid) + return out + + +def get_bid_entry(data: dict[str, Any], bid: str) -> dict[str, Any]: + for item in data.get("bids", []): + entry = item or {} + if str(entry.get("bid", "")).strip() == bid: + build_args = normalize_build_args(entry.get("build_args")) + tests = entry.get("tests") or {} + mode = str(tests.get("mode", "")).strip() + cases = tests.get("cases") or [] + if not isinstance(cases, list): + raise RuntimeError(f"{bid}: tests.cases must be a list") + return { + "bid": bid, + "platform_board": str(entry.get("platform_board") or "").strip(), + "build_args": build_args, + "mode": mode, + "cases": [str(x) for x in cases if str(x).strip()], + "tests": tests, + } + raise RuntimeError(f"bid not found in ci.yaml: {bid}") + + +def parse_args() -> argparse.Namespace: + parser = argparse.ArgumentParser(description="Read jenkins/ci.yaml") + sub = parser.add_subparsers(dest="command", required=True) + + sub.add_parser("list-bids", help="List all BID entries") + get_parser = sub.add_parser("get-bid", help="Get one BID config") + get_parser.add_argument("--bid", required=True) + return parser.parse_args() + + +def main() -> int: + args = parse_args() + data = load_ci() + if args.command == "list-bids": + print(json.dumps({"bids": list_bids(data)})) + return 0 + if args.command == "get-bid": + print(json.dumps(get_bid_entry(data, args.bid))) + return 0 + raise RuntimeError(f"unknown command: {args.command}") + + +if __name__ == "__main__": + raise SystemExit(main()) diff --git a/jenkins/ci_runner.py b/jenkins/ci_runner.py new file mode 100755 index 000000000..877e179de --- /dev/null +++ b/jenkins/ci_runner.py @@ -0,0 +1,478 @@ +#!/usr/bin/env python3 +from __future__ import annotations + +import argparse +import os +import re +import socket +import signal +import subprocess +import time +from pathlib import Path +from typing import Any, Callable + +from board_flow import ( + board_login, + board_network_and_trans, + board_power_off, + board_zone1_start, + boot_board_zone0_with_retry, + close_board_terminal, + get_board_terminal, + logs_dir, + release_logs_ownership, +) +from ci_config import get_bid_entry, load_ci, parse_bid +from terminal import Terminal, TerminalCommandError, TerminalTimeoutError + + +CaseFunc = Callable[[dict[str, Any], Terminal | None], int] + + +def platform_board(board: str, configured: str = "") -> str: + return configured.strip() or board + + +def wait_qemu_socket(path: str, timeout: float = 30.0) -> None: + deadline = time.monotonic() + timeout + while time.monotonic() < deadline: + if Path(path).exists(): + try: + sock = socket.socket(socket.AF_UNIX, socket.SOCK_STREAM) + sock.settimeout(0.5) + sock.connect(path) + sock.close() + return + except OSError: + pass + time.sleep(0.2) + raise SystemExit(f"qemu socket not ready: {path}") + + +def terminate_managed_process(cfg: dict[str, Any]) -> None: + proc = cfg.get("_managed_proc") + if proc is None or proc.poll() is not None: + return + try: + os.killpg(proc.pid, signal.SIGTERM) + except ProcessLookupError: + return + try: + proc.wait(timeout=5.0) + except subprocess.TimeoutExpired: + try: + os.killpg(proc.pid, signal.SIGKILL) + except ProcessLookupError: + pass + + +def zone_list_shows_running(output: str, zone_name: str = "linux2") -> None: + """hvisor-tool zone list returns zone count as exit code; validate output instead.""" + if zone_name not in output or "running" not in output: + raise TerminalCommandError( + f"zone list missing running {zone_name!r}:\n{output.strip()}" + ) + + +def run_and_print_quiet( + term: Terminal, + command: str, + quiet_seconds: float = 1.0, + max_duration: float = 30.0, + check_exit: bool = True, +) -> tuple[str, int]: + output, rc = term.run_until_quiet_with_status( + command, + quiet_seconds=quiet_seconds, + max_duration=max_duration, + ) + if output: + print(output, end="", flush=True) + if check_exit and rc != 0: + raise TerminalCommandError(f"command failed with rc={rc}: {command}") + return output, rc + + +def run_and_print_quiet_raw( + term: Terminal, + command: str, + quiet_seconds: float = 1.0, + max_duration: float = 30.0, +) -> str: + output = term.send_until_quiet( + command, + quiet_seconds=quiet_seconds, + max_duration=max_duration, + ) + if output: + print(output, end="", flush=True) + return output + + +def read_and_print_until_quiet( + term: Terminal, + quiet_seconds: float = 3.0, + max_duration: float = 120.0, +) -> str: + output = term.read_until_quiet( + quiet_seconds=quiet_seconds, + max_duration=max_duration, + ) + if output: + print(output, end="", flush=True) + return output + + +def run_and_print_send_only( + term: Terminal, + command: str, + read_duration: float = 0.5, +) -> str: + output = term.send_and_drain(command, read_duration=read_duration) + if output: + print(output, end="", flush=True) + return output + + +def resolve_staging_dir(raw: str, arch: str, board: str) -> str: + base = (raw or "/home/light/ci_deploy").rstrip("/") + suffix = f"{arch}__{board.replace('/', '__')}" + if base.endswith(suffix): + return base + return f"{base}/{suffix}" + + +def zone0_start(cfg: dict[str, Any], term: Terminal | None) -> int: + print("————————————————\ncase: zone0_start\n————————————————\n", flush=True) + if cfg["mode"] == "qemu": + cmd = ["make", f"ARCH={cfg['arch']}", f"BOARD={cfg['board']}", "MODE=release", "ci-run"] + env = os.environ.copy() + env["BID"] = "" + proc = subprocess.Popen(cmd, cwd=cfg["workspace"], start_new_session=True, env=env) + cfg["_managed_proc"] = proc + wait_qemu_socket(cfg["socket_path"], timeout=30.0) + with build_terminal(cfg) as qemu_term: + bid = cfg["bid"] + if bid == "aarch64/qemu-gicv3": + _ = read_and_print_until_quiet( + qemu_term, + quiet_seconds=3.0, + max_duration=10.0, + ) + uboot = str(cfg.get("uboot_cmd", "")).strip() + if uboot: + qemu_term.send(uboot) + else: + qemu_term.send("bootm 0x40400000 - 0x40000000") + if bid in ("x86_64/qemu", "x86_64/qemu_asterinas"): + time.sleep(10.0) + _ = read_and_print_until_quiet( + qemu_term, + quiet_seconds=5, + max_duration=180.0, + ) + return 0 + if cfg["mode"] == "board": + log_path = logs_dir(cfg) / "zone0_console.log" + log_path.write_text("", encoding="utf-8") + board_term = build_terminal(cfg, log_path) + board_term.open() + cfg["_board_term"] = board_term + boot_board_zone0_with_retry(cfg, board_term) + return 0 + return 0 + + +def login(cfg: dict[str, Any], term: Terminal | None) -> int: + print("————————————————\ncase: login\n————————————————\n", flush=True) + if cfg["mode"] != "board": + print("[login] skipped (not board mode)", flush=True) + return 0 + if term is None: + raise SystemExit("terminal backend is required") + return board_login(cfg, term) + + +def network_and_trans(cfg: dict[str, Any], term: Terminal | None) -> int: + print("————————————————\ncase: network_and_trans\n————————————————\n", flush=True) + if cfg["mode"] != "board": + print("[network_and_trans] skipped (not board mode)", flush=True) + return 0 + if term is None: + raise SystemExit("terminal backend is required") + return board_network_and_trans(cfg, term) + + +def zone1_start(cfg: dict[str, Any], term: Terminal | None) -> int: + print("————————————————\ncase: zone1_start\n————————————————\n", flush=True) + if cfg["mode"] == "board": + if term is None: + raise SystemExit("terminal backend is required") + return board_zone1_start(cfg, term) + if term is None: + raise SystemExit("terminal backend is required") + _, _ = run_and_print_quiet(term, "cd /root", quiet_seconds=1.0, max_duration=15.0) + _, _ = run_and_print_quiet( + term, + "./boot_zone1.sh", + quiet_seconds=15, + max_duration=120.0, + check_exit=False, + ) + zone_list_out, _ = run_and_print_quiet( + term, + "./hvisor zone list", + quiet_seconds=1.0, + max_duration=15.0, + check_exit=False, + ) + zone_list_shows_running(zone_list_out, str(cfg.get("zone1_name", "linux2"))) + if cfg["arch"] != "x86_64": + _ = run_and_print_quiet_raw(term, "script /dev/null", quiet_seconds=1.0, max_duration=15.0) + pts_output, _ = run_and_print_quiet(term, "ls -1 /dev/pts/[0-9]*", quiet_seconds=1.0, max_duration=15.0) + pts_numbers = sorted(int(match) for match in re.findall(r"/dev/pts/(\d+)", pts_output)) + if not pts_numbers: + raise TerminalCommandError("failed to find numeric pts from 'ls -1 /dev/pts/[0-9]*'") + max_pts = pts_numbers[-1] + _ = run_and_print_send_only(term, f"screen /dev/pts/{max_pts}", read_duration=20.0) + _ = run_and_print_send_only(term, "\n", read_duration=2.0) + print("zone1_started successfully", flush=True) + return 0 + + +def asterinas_zone1_regression(cfg: dict[str, Any], term: Terminal | None) -> int: + print("————————————————\ncase: asterinas_zone1_regression\n————————————————\n", flush=True) + if term is None: + raise SystemExit("terminal backend is required") + + _, _ = run_and_print_quiet(term, "cd /root", quiet_seconds=1.0, max_duration=15.0) + _, _ = run_and_print_quiet( + term, + "cat boot_zone1_asterinas.sh", + quiet_seconds=1.0, + max_duration=15.0, + ) + _, _ = run_and_print_quiet( + term, + "bash boot_zone1_asterinas.sh", + quiet_seconds=15, + max_duration=45.0, + ) + zone_list_out, _ = run_and_print_quiet( + term, + "./hvisor zone list", + quiet_seconds=1.0, + max_duration=15.0, + check_exit=False, + ) + zone_list_shows_running(zone_list_out, "asterinas") + + pts_output, _ = run_and_print_quiet( + term, + "ls -1 /dev/pts/[0-9]*", + quiet_seconds=1.0, + max_duration=15.0, + ) + pts_numbers = sorted(int(match) for match in re.findall(r"/dev/pts/(\d+)", pts_output)) + if not pts_numbers: + raise TerminalCommandError("failed to find numeric pts from 'ls -1 /dev/pts/[0-9]*'") + max_pts = pts_numbers[-1] + + _ = run_and_print_send_only(term, f"screen /dev/pts/{max_pts}", read_duration=20.0) + _ = read_and_print_until_quiet(term, quiet_seconds=3.0, max_duration=30.0) + + regression_marker = "__HV_REGRESSION_RC_" + term.send_one_by_one(f"/test/run_regression_test.sh; echo {regression_marker}$?") + output = "" + deadline = time.monotonic() + 900.0 + while time.monotonic() < deadline: + chunk = term.read_for(duration=2.0) + if not chunk: + continue + output += chunk + print(chunk, end="", flush=True) + + rc_match = re.search(re.escape(regression_marker) + r"(\d+)", output) + if rc_match is not None and rc_match.group(1) != "0": + raise TerminalCommandError( + f"Asterinas regression exited with rc={rc_match.group(1)}" + ) + if rc_match is not None and "All regression tests passed" in output: + break + if "All regression tests passed" not in output: + raise TerminalCommandError("Asterinas regression completion marker not found") + + # Ctrl-A d detaches from GNU screen; Ctrl-A Ctrl-A d is not a detach. + term.backend.write(b"\x01d") + time.sleep(1.0) + term.backend.write(b"\r") + detach_output = read_and_print_until_quiet(term, quiet_seconds=2.0, max_duration=10.0) + if "root@zone0" not in detach_output: + raise TerminalCommandError("failed to return to zone0 after screen detach") + print("asterinas_zone1_regression_passed", flush=True) + return 0 + + +CASE_HANDLERS: dict[str, CaseFunc] = { + "zone0_start": zone0_start, + "login": login, + "network_and_trans": network_and_trans, + "zone1_start": zone1_start, + "asterinas_zone1_regression": asterinas_zone1_regression, +} + + +def parse_args() -> argparse.Namespace: + parser = argparse.ArgumentParser(description="Run BID test cases from jenkins/ci.yaml") + parser.add_argument("--bid", required=True, help="BID key in jenkins/ci.yaml") + return parser.parse_args() + + +def load_runtime_config(args: argparse.Namespace) -> dict[str, Any]: + ci = load_ci() + bid_entry = get_bid_entry(ci, args.bid) + tests = bid_entry["tests"] + deploy = tests.get("deploy") or {} + if not isinstance(deploy, dict): + deploy = {} + + try: + arch, bid_board = parse_bid(args.bid) + except ValueError as exc: + raise SystemExit(str(exc)) from exc + board = platform_board(bid_board, bid_entry.get("platform_board", "")) + mode = bid_entry.get("mode", "").strip() + cases = bid_entry.get("cases", []) + if not mode: + raise SystemExit(f"incomplete config for bid '{args.bid}': tests.mode is required") + if not cases: + raise SystemExit(f"no test cases configured for bid '{args.bid}'") + + cell_root = Path.cwd() + hvisor_tool_path = os.environ.get("HVISOR_TOOL_PATH", "").strip() + if not hvisor_tool_path: + hvisor_tool_path = str((cell_root / "hvisor-tool").resolve()) + elif not Path(hvisor_tool_path).is_absolute(): + hvisor_tool_path = str((cell_root / hvisor_tool_path).resolve()) + + scp_tmp_dir = str(deploy.get("scp_tmp_dir", "/tmp/ci_pull")).strip() or "/tmp/ci_pull" + uboot_step = float(tests.get("uboot_step_timeout", 0.0)) + uboot_prompt = float(tests.get("uboot_prompt_timeout", 60.0)) + if uboot_step <= 0: + uboot_step = max(uboot_prompt, 60.0) + + return { + "bid": args.bid, + "arch": arch, + "board": board, + "mode": mode, + "cases": cases, + "workspace": cell_root, + "hvisor_tool_path": hvisor_tool_path, + "socket_path": str((cell_root / ".qemu" / "qemu.sock").resolve()), + "serial_port": str(tests.get("serial", "/dev/null")), + "power_serial": str(tests.get("power_serial", "")).strip(), + "power_channel": int(tests.get("power_channel", 4)), + "baudrate": int(tests.get("baudrate", 1500000)), + "uboot_cmd": str(tests.get("uboot_cmd", "")).strip(), + "uboot_cmds": tests.get("uboot_cmds") or [], + "uboot_ready_pattern": str(tests.get("uboot_ready_pattern", "")).strip(), + "uboot_prompt_timeout": uboot_prompt, + "uboot_step_timeout": uboot_step, + "uboot_autoboot_window": float(tests.get("uboot_autoboot_window", 0.0)), + "zone0_ready_pattern": str(tests.get("zone0_ready_pattern", "")).strip(), + "zone0_shell_timeout": float(tests.get("zone0_shell_timeout", 180.0)), + "board_ip": str(deploy.get("board_ip", "")).strip(), + "board_iface": str(deploy.get("board_iface", "eth0")).strip(), + "board_netmask": str(deploy.get("board_netmask", "255.255.255.0")).strip(), + "host_ip": str(deploy.get("host_ip", "")).strip(), + "host_user": str(deploy.get("host_user", "light")).strip(), + "link_wait": float(deploy.get("link_wait", 0.0)), + "ping_retries": int(deploy.get("ping_retries", 1)), + "ping_count": int(deploy.get("ping_count", 3)), + "ssh_connect_timeout": int(deploy.get("ssh_connect_timeout", 60)), + "pull_timeout": float(deploy.get("pull_timeout", 600.0)), + "staging_dir": resolve_staging_dir( + str(deploy.get("staging_dir", "/home/light/ci_deploy")), + arch, + board, + ), + "zone1_work_dir": str(deploy.get("zone1_work_dir", "/root")).strip() or "/root", + "zone1_dtb": str(deploy.get("zone1_dtb", "")).strip(), + "scp_tmp_dir": scp_tmp_dir, + "scp_tmp_file": f"{scp_tmp_dir}/f", + "retry_zone0": 2, + "retry_network": 2, + "retry_zone1": 1, + } + + +def build_terminal(cfg: dict[str, Any], log_path: Path | None = None) -> Terminal: + if cfg["mode"] == "qemu": + return Terminal.from_qemu_socket(path=cfg["socket_path"], log_path=log_path) + return Terminal.from_serial( + port=cfg["serial_port"], + baudrate=cfg["baudrate"], + log_path=log_path, + ) + + +def main() -> int: + args = parse_args() + cfg = load_runtime_config(args) + try: + for case_name in cfg["cases"]: + case_fn = CASE_HANDLERS.get(case_name) + if case_fn is None: + available = ", ".join(sorted(CASE_HANDLERS.keys())) + raise SystemExit(f"unknown case '{case_name}', available: {available}") + + if case_name == "zone0_start": + try: + rc = case_fn(cfg, None) + except (TerminalTimeoutError, TerminalCommandError) as exc: + print(f"[ci_runner] failed in case '{case_name}': {exc}", flush=True) + return 1 + if rc != 0: + return rc + time.sleep(5.0) + continue + + term = get_board_terminal(cfg) if cfg["mode"] == "board" else None + if term is None and cfg["mode"] == "board": + log_path = logs_dir(cfg) / "board_console.log" + log_path.write_text("", encoding="utf-8") + term = build_terminal(cfg, log_path) + term.open() + cfg["_board_term"] = term + + if cfg["mode"] == "qemu": + with build_terminal(cfg) as qemu_term: + try: + rc = case_fn(cfg, qemu_term) + except (TerminalTimeoutError, TerminalCommandError) as exc: + print(f"[ci_runner] failed in case '{case_name}': {exc}", flush=True) + return 1 + if rc != 0: + return rc + else: + assert term is not None + try: + rc = case_fn(cfg, term) + except (TerminalTimeoutError, TerminalCommandError) as exc: + print(f"[ci_runner] failed in case '{case_name}': {exc}", flush=True) + return 1 + if rc != 0: + return rc + time.sleep(5.0) + return 0 + finally: + release_logs_ownership(cfg) + close_board_terminal(cfg) + terminate_managed_process(cfg) + if cfg.get("mode") == "board": + board_power_off(cfg) + + +if __name__ == "__main__": + raise SystemExit(main()) diff --git a/jenkins/discover_platforms.py b/jenkins/discover_platforms.py new file mode 100644 index 000000000..3642a7d8b --- /dev/null +++ b/jenkins/discover_platforms.py @@ -0,0 +1,59 @@ +#!/usr/bin/env python3 +"""Discover platform ARCH/BOARD pairs from platform/*/*.""" + +from __future__ import annotations + +import argparse +import json +from pathlib import Path + + +ROOT = Path(__file__).resolve().parent.parent +PLATFORM_DIR = ROOT / "platform" + + +def discover() -> list[dict[str, str]]: + items: list[dict[str, str]] = [] + if not PLATFORM_DIR.exists(): + return items + + for arch_dir in sorted(PLATFORM_DIR.iterdir()): + if not arch_dir.is_dir(): + continue + for board_dir in sorted(arch_dir.iterdir()): + if not board_dir.is_dir(): + continue + items.append( + { + "arch": arch_dir.name, + "board": board_dir.name, + "bid": f"{arch_dir.name}/{board_dir.name}", + } + ) + return items + + +def parse_args() -> argparse.Namespace: + parser = argparse.ArgumentParser(description="Discover platform ARCH/BOARD pairs") + parser.add_argument( + "--format", + choices=["json", "lines"], + default="json", + help="Output format", + ) + return parser.parse_args() + + +def main() -> int: + args = parse_args() + items = discover() + if args.format == "lines": + for item in items: + print(item["bid"]) + return 0 + print(json.dumps(items)) + return 0 + + +if __name__ == "__main__": + raise SystemExit(main()) diff --git a/jenkins/prepare.sh b/jenkins/prepare.sh new file mode 100644 index 000000000..747bb626e --- /dev/null +++ b/jenkins/prepare.sh @@ -0,0 +1,158 @@ +#!/bin/sh + +set -eux + +ARCH=${ARCH:?ARCH is required} +BOARD=${BOARD:?BOARD is required} +KDIR=${KDIR:?KDIR is required} +WORKSPACE_ROOT=${WORKSPACE_ROOT:-$(pwd)} +HVISOR_TOOL_PATH=${HVISOR_TOOL_PATH:-${WORKSPACE_ROOT}/hvisor-tool} + +case "${HVISOR_TOOL_PATH}" in + /*) ;; + *) HVISOR_TOOL_PATH="${WORKSPACE_ROOT}/${HVISOR_TOOL_PATH}" ;; +esac + +PLATFORM_DIR="${WORKSPACE_ROOT}/platform/${ARCH}/${BOARD}" +CONFIGS_DIR="${PLATFORM_DIR}/configs" +IMAGE_DIR="${PLATFORM_DIR}/image" +SCRIPTS_DIR="${PLATFORM_DIR}/scripts" +VIRTDISK_DIR="${IMAGE_DIR}/virtdisk" + +ROOTFS_DIR="${VIRTDISK_DIR}/rootfs" +ROOTFS_IMG="" +ZONE1_DTB="${IMAGE_DIR}/dts/zone1-linux.dtb" +ZONE1_DTS_DIR="${IMAGE_DIR}/dts" +ZONE1_BOOT_SCRIPT="${SCRIPTS_DIR}/boot_zone1.sh" +ZONE1_ASTERINAS_BOOT_SCRIPT="${SCRIPTS_DIR}/boot_zone1_asterinas.sh" +KERNEL_IMAGE="" + +# Asterinas CI artifacts follow the qemu_asterinas layout: +# image/kernel/aster-kernel-osdk-bin +# image/virtdisk/initramfs.cpio.gz +# ASTERINAS_KERNEL/ASTERINAS_INITRAMFS override these for local validation. +ASTERINAS_KERNEL_DEFAULT="${IMAGE_DIR}/kernel/aster-kernel-osdk-bin" +ASTERINAS_INITRAMFS_DEFAULT="${VIRTDISK_DIR}/initramfs.cpio.gz" +ZONE1_DISK_SIZE_MB="${ZONE1_DISK_SIZE_MB:-512}" + +case "${ARCH}" in + x86_64) + KERNEL_IMAGE="${KDIR}/arch/x86/boot/setup.bin ${KDIR}/arch/x86/boot/vmlinux.bin" + ;; + aarch64) + KERNEL_IMAGE="${KDIR}/arch/arm64/boot/Image" + ;; + riscv64) + KERNEL_IMAGE="${KDIR}/arch/riscv/boot/Image" + ;; + *) + echo "error: unsupported ARCH for kernel image selection: ${ARCH}" + exit 1 + ;; +esac + +if [ "${ARCH}" = "x86_64" ]; then + JUMP=${IMAGE_DIR}/bootloader/out/boot.bin +fi + +mkdir -p "${ROOTFS_DIR}" + +if [ -f "${VIRTDISK_DIR}/rootfs1.ext4" ]; then + ROOTFS_IMG="${VIRTDISK_DIR}/rootfs1.ext4" +elif [ -f "${VIRTDISK_DIR}/rootfs1.img" ]; then + ROOTFS_IMG="${VIRTDISK_DIR}/rootfs1.img" +fi + +if [ -z "${ROOTFS_IMG}" ]; then + echo "error: rootfs image not found: ${VIRTDISK_DIR}/rootfs1.ext4 or ${VIRTDISK_DIR}/rootfs1.img" + exit 1 +fi + +if [ ! -f "${ROOTFS_IMG}" ]; then + echo "error: rootfs image not found: ${ROOTFS_IMG}" + exit 1 +fi + +if mountpoint -q "${ROOTFS_DIR}"; then + umount "${ROOTFS_DIR}" +fi + +mount -t ext4 "${ROOTFS_IMG}" "${ROOTFS_DIR}" +trap 'umount "${ROOTFS_DIR}"' EXIT + +echo "ARCH: ${ARCH}" +echo "BOARD: ${BOARD}" +echo "KDIR: ${KDIR}" +echo "HVISOR_TOOL_PATH: ${HVISOR_TOOL_PATH}" + +cp "${HVISOR_TOOL_PATH}/output/hvisor" "${HVISOR_TOOL_PATH}/output/hvisor.ko" "${ROOTFS_DIR}/root/" +cp "${CONFIGS_DIR}/"* "${ROOTFS_DIR}/root/" + +for kernel_image in ${KERNEL_IMAGE}; do + cp "${kernel_image}" "${ROOTFS_DIR}/root/" +done + +if [ "${ARCH}" = "x86_64" ]; then + cp "${JUMP}" "${ROOTFS_DIR}/root/" +fi + +if [ -n "${ASTERINAS_KERNEL:-}" ] || [ -f "${ASTERINAS_KERNEL_DEFAULT}" ] || + [ -n "${ASTERINAS_INITRAMFS:-}" ] || [ -f "${ASTERINAS_INITRAMFS_DEFAULT}" ]; then + ASTERINAS_KERNEL="${ASTERINAS_KERNEL:-${ASTERINAS_KERNEL_DEFAULT}}" + ASTERINAS_INITRAMFS="${ASTERINAS_INITRAMFS:-${ASTERINAS_INITRAMFS_DEFAULT}}" + if [ ! -f "${ASTERINAS_KERNEL}" ]; then + echo "error: Asterinas kernel not found: ${ASTERINAS_KERNEL}" + exit 1 + fi + if [ ! -f "${ASTERINAS_INITRAMFS}" ]; then + echo "error: Asterinas initramfs not found: ${ASTERINAS_INITRAMFS}" + exit 1 + fi + cp "${ASTERINAS_KERNEL}" "${ROOTFS_DIR}/root/aster-kernel-osdk-bin" + cp "${ASTERINAS_INITRAMFS}" "${ROOTFS_DIR}/root/initramfs.cpio.gz" + + MB2_BOOT="${IMAGE_DIR}/mb2_bootloader/out/mb2_boot.bin" + if [ -f "${MB2_BOOT}" ]; then + cp "${MB2_BOOT}" "${ROOTFS_DIR}/root/" + else + echo "error: Multiboot2 bootloader not found: ${MB2_BOOT}" + exit 1 + fi + + ZONE1_DISK="${ROOTFS_DIR}/zone1_disk.img" + rm -f "${ZONE1_DISK}" + truncate -s "${ZONE1_DISK_SIZE_MB}M" "${ZONE1_DISK}" + mkfs.ext2 -F -b 4096 "${ZONE1_DISK}" +fi + +if [ "${ARCH}" != "x86_64" ]; then + if [ ! -f "${ZONE1_DTB}" ]; then + if [ -d "${ZONE1_DTS_DIR}" ]; then + echo "zone1 dtb is missing, building it from ${ZONE1_DTS_DIR}" + make -C "${ZONE1_DTS_DIR}" all || true + else + echo "warning: dts directory not found: ${ZONE1_DTS_DIR}" + fi + fi + + if [ -f "${ZONE1_DTB}" ]; then + cp "${ZONE1_DTB}" "${ROOTFS_DIR}/root/" + else + echo "warning: zone1 dtb is unavailable, skip copying ${ZONE1_DTB}" + fi +fi + +cp "${ZONE1_BOOT_SCRIPT}" "${ROOTFS_DIR}/root/" +if [ -f "${ZONE1_ASTERINAS_BOOT_SCRIPT}" ]; then + cp "${ZONE1_ASTERINAS_BOOT_SCRIPT}" "${ROOTFS_DIR}/root/" +fi + +if [ -f "${ROOTFS_DIR}/root/boot_zone1.sh" ]; then + chmod +x "${ROOTFS_DIR}/root/boot_zone1.sh" +fi +if [ -f "${ROOTFS_DIR}/root/boot_zone1_asterinas.sh" ]; then + chmod +x "${ROOTFS_DIR}/root/boot_zone1_asterinas.sh" +fi +if [ -f "${ROOTFS_DIR}/root/screen_zone1.sh" ]; then + chmod +x "${ROOTFS_DIR}/root/screen_zone1.sh" +fi diff --git a/jenkins/sync_bid_matrix.py b/jenkins/sync_bid_matrix.py new file mode 100644 index 000000000..ef6c8c84f --- /dev/null +++ b/jenkins/sync_bid_matrix.py @@ -0,0 +1,136 @@ +#!/usr/bin/env python3 +"""Sync BID matrix values in Jenkinsfile from platform directory.""" + +from __future__ import annotations + +import argparse +import sys +from pathlib import Path + + +def collect_bids(platform_dir: Path) -> list[str]: + if not platform_dir.is_dir(): + raise FileNotFoundError(f"platform dir not found: {platform_dir}") + + bids: list[str] = [] + for arch_dir in sorted(p for p in platform_dir.iterdir() if p.is_dir()): + for board_dir in sorted(p for p in arch_dir.iterdir() if p.is_dir()): + bids.append(f"{arch_dir.name}/{board_dir.name}") + return bids + + +def find_bid_values_block(lines: list[str]) -> tuple[int, int, str]: + """Return (start_idx, end_idx, values_indent). end_idx points to ')' line.""" + bid_line_idx = None + for i, line in enumerate(lines): + if "name 'BID'" in line: + bid_line_idx = i + break + if bid_line_idx is None: + raise ValueError("cannot find `name 'BID'` in Jenkinsfile") + + values_idx = None + values_indent = "" + for i in range(bid_line_idx + 1, len(lines)): + stripped = lines[i].strip() + if not stripped: + continue + if stripped.startswith("values("): + values_idx = i + values_indent = lines[i][: len(lines[i]) - len(lines[i].lstrip(" "))] + break + raise ValueError("cannot find `values(` right after `name 'BID'`") + if values_idx is None: + raise ValueError("cannot find `values(` in BID axis") + + end_idx = None + for i in range(values_idx + 1, len(lines)): + if lines[i].strip() == ")": + end_idx = i + break + if end_idx is None: + raise ValueError("cannot find closing `)` for BID values block") + + return values_idx, end_idx, values_indent + + +def build_value_lines(bids: list[str], values_indent: str) -> list[str]: + item_indent = values_indent + " " + return [f"{item_indent}'{bid}',\n" for bid in bids] + + +def sync_jenkinsfile(jenkinsfile: Path, bids: list[str], write: bool) -> bool: + original = jenkinsfile.read_text(encoding="utf-8") + lines = original.splitlines(keepends=True) + + values_idx, end_idx, values_indent = find_bid_values_block(lines) + new_lines = build_value_lines(bids, values_indent) + + updated_lines = lines[: values_idx + 1] + new_lines + lines[end_idx:] + updated = "".join(updated_lines) + changed = updated != original + + if changed and write: + jenkinsfile.write_text(updated, encoding="utf-8") + return changed + + +def parse_args() -> argparse.Namespace: + repo_root = Path(__file__).resolve().parents[1] + parser = argparse.ArgumentParser( + description="Sync Jenkinsfile BID matrix from platform directories." + ) + parser.add_argument( + "--platform-dir", + type=Path, + default=repo_root / "platform", + help="Path to platform root directory (default: %(default)s)", + ) + parser.add_argument( + "--jenkinsfile", + type=Path, + default=repo_root / "Jenkinsfile", + help="Path to Jenkinsfile (default: %(default)s)", + ) + parser.add_argument( + "--update", + action="store_true", + help="Update Jenkinsfile. Without this flag, only check diff.", + ) + parser.add_argument( + "--check", + action="store_true", + help="Exit with code 1 when Jenkinsfile is out of sync.", + ) + parser.add_argument( + "--list", + action="store_true", + help="Print all discovered BID values and exit.", + ) + return parser.parse_args() + + +def main() -> int: + args = parse_args() + bids = collect_bids(args.platform_dir) + if args.list: + print("\n".join(bids)) + return 0 + + changed = sync_jenkinsfile(args.jenkinsfile, bids, write=args.update) + + if changed: + if args.update: + print(f"updated {args.jenkinsfile} with {len(bids)} bids") + else: + print(f"{args.jenkinsfile} is out of sync ({len(bids)} bids expected)") + else: + print(f"{args.jenkinsfile} is up to date ({len(bids)} bids)") + + if args.check and changed: + return 1 + return 0 + + +if __name__ == "__main__": + sys.exit(main()) diff --git a/jenkins/terminal.py b/jenkins/terminal.py new file mode 100644 index 000000000..eb4035345 --- /dev/null +++ b/jenkins/terminal.py @@ -0,0 +1,581 @@ +#!/usr/bin/env python3 +"""Unified terminal helpers for QEMU UNIX socket and physical serial ports.""" + +from __future__ import annotations + +import os +import queue +import re +import select +import socket +import threading +import time +import uuid +from abc import ABC, abstractmethod +from dataclasses import dataclass +from pathlib import Path + +import serial + + +MARKER_ID_LEN = 4 +HV_M_MARKER_RE = re.compile(rf"__HV_M_(?P[a-f0-9]{{{MARKER_ID_LEN}}}):(?P\d+)") + + +def new_marker_id() -> str: + return uuid.uuid4().hex[:MARKER_ID_LEN] + + +class TerminalTimeoutError(TimeoutError): + """Raised when terminal command wait times out.""" + + def __init__(self, message: str, *, partial_output: str = "") -> None: + super().__init__(message) + self.partial_output = partial_output + + +class TerminalCommandError(RuntimeError): + """Raised when a terminal command exits with non-zero status.""" + + +class TerminalBackend(ABC): + """Backend abstraction for terminal IO.""" + + @abstractmethod + def open(self) -> None: + pass + + @abstractmethod + def close(self) -> None: + pass + + @abstractmethod + def read(self, max_bytes: int = 4096) -> bytes: + pass + + @abstractmethod + def write(self, data: bytes) -> None: + pass + + @abstractmethod + def flush_input(self) -> None: + pass + + +@dataclass +class QemuSocketBackend(TerminalBackend): + path: str + connect_timeout: float = 10.0 + io_timeout: float = 0.2 + _sock: socket.socket | None = None + + def open(self) -> None: + if self._sock is not None: + return + sock = socket.socket(socket.AF_UNIX, socket.SOCK_STREAM) + sock.settimeout(self.connect_timeout) + sock.connect(self.path) + sock.setblocking(False) + self._sock = sock + + def close(self) -> None: + if self._sock is None: + return + self._sock.close() + self._sock = None + + def read(self, max_bytes: int = 4096) -> bytes: + if self._sock is None: + raise RuntimeError("QEMU socket is not open") + ready, _, _ = select.select([self._sock], [], [], self.io_timeout) + if not ready: + return b"" + try: + return self._sock.recv(max_bytes) + except BlockingIOError: + return b"" + + def write(self, data: bytes) -> None: + if self._sock is None: + raise RuntimeError("QEMU socket is not open") + self._sock.sendall(data) + + def flush_input(self) -> None: + if self._sock is None: + return + while True: + chunk = self.read() + if not chunk: + break + + +@dataclass +class SerialBackend(TerminalBackend): + port: str + baudrate: int = 115200 + timeout: float = 0.2 + _serial: serial.Serial | None = None + + def open(self) -> None: + if self._serial is not None: + return + self._serial = serial.Serial( + port=self.port, + baudrate=self.baudrate, + timeout=self.timeout, + write_timeout=self.timeout, + ) + # CH340 adapters often need DTR asserted before the target UART TX is enabled. + self._serial.dtr = True + self._serial.rts = False + + def close(self) -> None: + if self._serial is None: + return + self._serial.close() + self._serial = None + + def read(self, max_bytes: int = 4096) -> bytes: + if self._serial is None: + raise RuntimeError("Serial device is not open") + return self._serial.read(max_bytes) + + def write(self, data: bytes) -> None: + if self._serial is None: + raise RuntimeError("Serial device is not open") + self._serial.write(data) + self._serial.flush() + + def flush_input(self) -> None: + if self._serial is None: + return + self._serial.reset_input_buffer() + + +class LogCollector: + """Background reader that continuously captures terminal output.""" + + def __init__( + self, + backend: TerminalBackend, + log_path: Path, + encoding: str = "utf-8", + console: bool = True, + poll_interval: float = 0.05, + ) -> None: + self.backend = backend + self.log_path = log_path + self.encoding = encoding + self.console = console + self.poll_interval = poll_interval + self._lock = threading.Lock() + self._buffer = "" + self._stop = threading.Event() + self._thread: threading.Thread | None = None + self._console_queue: queue.SimpleQueue[str | None] = queue.SimpleQueue() + self._console_thread: threading.Thread | None = None + + def start(self) -> None: + self.log_path.parent.mkdir(parents=True, exist_ok=True) + if self.console: + self._console_thread = threading.Thread( + target=self._console_loop, name="LogCollectorConsole", daemon=True + ) + self._console_thread.start() + self._thread = threading.Thread(target=self._run_loop, name="LogCollector", daemon=True) + self._thread.start() + + def stop(self) -> None: + self._stop.set() + if self._thread is not None: + self._thread.join(timeout=5.0) + self._thread = None + deadline = time.monotonic() + 1.0 + while time.monotonic() < deadline: + chunk = self.backend.read() + if not chunk: + break + self._append(chunk.decode(self.encoding, errors="replace"), emit_console=False) + if self.console: + self._console_queue.put(None) + if self._console_thread is not None: + self._console_thread.join(timeout=5.0) + self._console_thread = None + + def offset(self) -> int: + with self._lock: + return len(self._buffer) + + def tail_since(self, offset: int) -> str: + with self._lock: + if offset < 0 or offset > len(self._buffer): + return self._buffer + return self._buffer[offset:] + + def _append(self, chunk: str, *, emit_console: bool = True) -> None: + if not chunk: + return + with self._lock: + self._buffer += chunk + try: + with self.log_path.open("a", encoding=self.encoding) as fh: + fh.write(chunk) + except OSError: + pass + if emit_console and self.console: + self._console_queue.put(chunk) + + def _console_loop(self) -> None: + while True: + chunk = self._console_queue.get() + if chunk is None: + return + print(chunk, end="", flush=True) + + def _run_loop(self) -> None: + while not self._stop.is_set(): + chunk = self.backend.read() + if chunk: + self._append(chunk.decode(self.encoding, errors="replace")) + continue + time.sleep(self.poll_interval) + + +def _default_log_path() -> Path: + return Path(f"/tmp/hvisor-terminal-{os.getpid()}.log") + + +class Terminal: + """High level terminal wrapper with command helpers.""" + + def __init__( + self, + backend: TerminalBackend, + encoding: str = "utf-8", + log_path: Path | None = None, + console: bool = True, + ) -> None: + self.backend = backend + self.encoding = encoding + self._log_path = log_path or _default_log_path() + self._collector = LogCollector( + backend, self._log_path, encoding=encoding, console=console + ) + self._opened = False + + @classmethod + def from_qemu_socket( + cls, + path: str, + connect_timeout: float = 10.0, + io_timeout: float = 0.2, + encoding: str = "utf-8", + log_path: Path | None = None, + console: bool = True, + ) -> "Terminal": + return cls( + QemuSocketBackend(path=path, connect_timeout=connect_timeout, io_timeout=io_timeout), + encoding=encoding, + log_path=log_path, + console=console, + ) + + @classmethod + def from_serial( + cls, + port: str, + baudrate: int = 115200, + timeout: float = 0.2, + encoding: str = "utf-8", + log_path: Path | None = None, + console: bool = True, + ) -> "Terminal": + return cls( + SerialBackend(port=port, baudrate=baudrate, timeout=timeout), + encoding=encoding, + log_path=log_path, + console=console, + ) + + def open(self) -> None: + if self._opened: + return + self.backend.open() + self._collector.start() + self._opened = True + + def close(self) -> None: + if not self._opened: + return + self._collector.stop() + self.backend.close() + self._opened = False + + def __enter__(self) -> "Terminal": + self.open() + return self + + def __exit__(self, exc_type, exc, tb) -> None: + self.close() + + def flush_input(self) -> None: + self._ensure_open() + self.backend.flush_input() + + def offset(self) -> int: + self._ensure_open() + return self._collector.offset() + + def tail_since(self, offset: int) -> str: + self._ensure_open() + return self._collector.tail_since(offset) + + def run( + self, + case: str, + command: str, + timeout: float = 30.0, + poll_interval: float = 0.05, + wake_interval: float | None = None, + ) -> tuple[int, str]: + """Run a shell command and wait for the compact result marker in the log.""" + self._ensure_open() + run_id = new_marker_id() + offset = self._collector.offset() + wrapped = f"{command}; echo __HV_M_{run_id}:$?" + self.send(wrapped) + + deadline = time.monotonic() + timeout + next_wake = time.monotonic() + wake_interval if wake_interval else None + marker_needle = rf"__HV_M_{run_id}:\d+" + while time.monotonic() < deadline: + chunk = self._collector.tail_since(offset) + if re.search(marker_needle, chunk): + matches = [m for m in HV_M_MARKER_RE.finditer(chunk) if m.group("run_id") == run_id] + if matches: + match = matches[-1] + rc = int(match.group("rc")) + output = chunk[: match.start()] + return rc, output + if next_wake is not None and time.monotonic() >= next_wake: + self.send("") + next_wake = time.monotonic() + wake_interval + time.sleep(poll_interval) + + partial = self._collector.tail_since(offset) + raise TerminalTimeoutError( + f"timed out waiting for run result (case={case}, run_id={run_id}): {command}", + partial_output=partial, + ) + + def wait_pattern( + self, + pattern: str, + timeout: float = 120.0, + poll_interval: float = 0.05, + from_offset: int | None = None, + ) -> bool: + """Wait until regex pattern appears in the collected log.""" + self._ensure_open() + offset = self._collector.offset() if from_offset is None else from_offset + compiled = re.compile(pattern) + deadline = time.monotonic() + timeout + while time.monotonic() < deadline: + chunk = self._collector.tail_since(offset) + if compiled.search(chunk): + return True + time.sleep(poll_interval) + return False + + def send(self, command: str) -> None: + self._ensure_open() + payload = command.rstrip("\n") + "\n" + self.backend.write(payload.encode(self.encoding, errors="replace")) + + def send_one_by_one( + self, + command: str, + char_delay: float = 0.02, + ) -> None: + """Send a command one character at a time for lossy consoles. + + Asterinas' virtio-console currently consumes one byte per interrupt, so + pasting a complete command can drop characters. This helper keeps the + command readable while avoiding that loss. + """ + self._ensure_open() + for char in command.rstrip("\n"): + self.backend.write(char.encode(self.encoding, errors="replace")) + time.sleep(char_delay) + self.backend.write(b"\n") + + def read_for( + self, + duration: float = 2.0, + poll_interval: float = 0.05, + ) -> str: + self._ensure_open() + offset = self._collector.offset() + deadline = time.monotonic() + duration + while time.monotonic() < deadline: + time.sleep(poll_interval) + return self._collector.tail_since(offset) + + def send_until_get( + self, + command: str, + timeout: float = 30.0, + poll_interval: float = 0.05, + include_marker_line: bool = False, + ) -> str: + self._ensure_open() + run_id = new_marker_id() + marker = f"__HV_M_{run_id}:0" + offset = self._collector.offset() + self.send(f"{command}; echo {marker}") + + deadline = time.monotonic() + timeout + while time.monotonic() < deadline: + buf = self._collector.tail_since(offset) + if marker in buf: + if include_marker_line: + return buf + return self._trim_after_marker(buf, marker) + time.sleep(poll_interval) + raise TerminalTimeoutError( + f"timed out waiting for terminal marker: {marker}", + partial_output=self._collector.tail_since(offset), + ) + + def send_until_quiet( + self, + command: str, + quiet_seconds: float = 1.0, + max_duration: float = 30.0, + poll_interval: float = 0.05, + ) -> str: + self._ensure_open() + offset = self._collector.offset() + self.send(command) + return self._wait_quiet(offset, quiet_seconds, max_duration, poll_interval, context=command) + + def send_and_drain( + self, + command: str, + read_duration: float = 0.5, + poll_interval: float = 0.05, + ) -> str: + """Send command and collect best-effort output for a fixed duration.""" + self._ensure_open() + offset = self._collector.offset() + self.send(command) + deadline = time.monotonic() + read_duration + while time.monotonic() < deadline: + time.sleep(poll_interval) + return self._collector.tail_since(offset) + + def read_until_quiet( + self, + quiet_seconds: float = 3.0, + max_duration: float = 120.0, + poll_interval: float = 0.05, + ) -> str: + """Continuously read until quiet for x seconds or total timeout.""" + self._ensure_open() + offset = self._collector.offset() + try: + return self._wait_quiet( + offset, quiet_seconds, max_duration, poll_interval, context="read" + ) + except TerminalTimeoutError: + return self._collector.tail_since(offset) + + def run_until_quiet_with_status( + self, + command: str, + quiet_seconds: float = 1.0, + max_duration: float = 30.0, + poll_interval: float = 0.05, + ) -> tuple[str, int]: + run_id = new_marker_id() + marker = f"__HV_M_{run_id}" + wrapped = f"{command}; echo {marker}:$?" + self._ensure_open() + offset = self._collector.offset() + self.send(wrapped) + + deadline = time.monotonic() + max_duration + marker_pattern = re.compile(re.escape(marker) + r":(\d+)") + rc = -1 + marker_seen_at = 0.0 + + while time.monotonic() < deadline: + buf = self._collector.tail_since(offset) + matches = list(marker_pattern.finditer(buf)) + if matches: + last = matches[-1] + rc = int(last.group(1)) + if marker_seen_at <= 0.0: + marker_seen_at = time.monotonic() + elif marker_seen_at <= 0.0: + time.sleep(poll_interval) + continue + + if marker_seen_at > 0.0 and (time.monotonic() - marker_seen_at) >= quiet_seconds: + cleaned = self._strip_hv_m_marker(buf, marker) + return cleaned, rc + + time.sleep(poll_interval) + + raise TerminalTimeoutError( + f"timed out waiting for command status marker {marker}:$?", + partial_output=self._collector.tail_since(offset), + ) + + def _wait_quiet( + self, + offset: int, + quiet_seconds: float, + max_duration: float, + poll_interval: float, + *, + context: str, + ) -> str: + start = time.monotonic() + deadline = start + max_duration + last_len = self._collector.offset() + last_output_at = start + + while time.monotonic() < deadline: + current_len = self._collector.offset() + if current_len > last_len: + last_len = current_len + last_output_at = time.monotonic() + elif (time.monotonic() - last_output_at) >= quiet_seconds: + return self._collector.tail_since(offset) + + time.sleep(poll_interval) + + raise TerminalTimeoutError( + f"timed out waiting for terminal quiet period after command: {context}", + partial_output=self._collector.tail_since(offset), + ) + + def _ensure_open(self) -> None: + if not self._opened: + self.open() + + @staticmethod + def _trim_after_marker(output: str, marker: str) -> str: + idx = output.find(marker) + if idx < 0: + return output + return output[:idx] + + @staticmethod + def _strip_hv_m_marker(output: str, marker: str) -> str: + pattern = re.compile(re.escape(marker) + r":\d+") + matches = list(pattern.finditer(output)) + if not matches: + return output + return output[: matches[-1].start()] diff --git a/kconfig/Kconfig b/kconfig/Kconfig new file mode 100644 index 000000000..b3bb97868 --- /dev/null +++ b/kconfig/Kconfig @@ -0,0 +1,294 @@ +mainmenu "hvisor platform options" + +menu "Target architecture" +choice + prompt "CPU architecture" + default ARCH_AARCH64 + +config ARCH_AARCH64 + bool "aarch64" + +config ARCH_RISCV64 + bool "riscv64" + +config ARCH_LOONGARCH64 + bool "loongarch64" + +config ARCH_X86_64 + bool "x86_64" + +endchoice +endmenu + +menu "AArch64 options" + depends on ARCH_AARCH64 + +config AARCH64_UEFI_SUPPORT + bool "UEFI memory map virtualization" + default n + +endmenu + +menu "Interrupt controller" + depends on ARCH_AARCH64 || ARCH_RISCV64 || ARCH_LOONGARCH64 + +choice + prompt "GIC version" + optional + default IRQ_GICV3 + depends on ARCH_AARCH64 + +config IRQ_GICV2 + bool "GICv2" + +config IRQ_GICV3 + bool "GICv3" + +endchoice + +config PLIC + bool "PLIC" + depends on ARCH_RISCV64 + default n + +config DP1000_PLIC + bool "DP1000 PLIC variant" + depends on ARCH_RISCV64 && PLIC + default n + +config AIA + bool "AIA (APLIC/IMSIC)" + depends on ARCH_RISCV64 + default n + +config ACLINT + bool "ACLINT (MTI/MSI)" + depends on ARCH_RISCV64 + default n + +config LOONGSON_7A2000 + bool "Loongson 7A2000" + depends on ARCH_LOONGARCH64 + default n + +endmenu + +menu "RISC-V options" + depends on ARCH_RISCV64 + +config RVA23 + bool "RVA23 profile" + default n + select ISA_VECTOR + select ISA_SSTC + select ISA_SVPBMT + select ISA_CMO + help + Enable the RVA23 profile. RVA23 mandates the RISC-V Vector, Sstc, + Svpbmt, and base CMO extensions, so their ISA options are selected + automatically. + +config ISA_VECTOR + bool "V (Vector)" + default n + help + Enable guest Vector state. This sets the VS fields in sstatus and + vsstatus so that guests can execute RISC-V Vector instructions. + +config ISA_SSTC + bool "Sstc (Supervisor-mode timer interrupts)" + default n + help + Indicate that the host platform implements the RISC-V Sstc extension, + allowing hvisor to program stimecmp and vstimecmp. Direct VS-mode + access to vstimecmp is controlled separately for each guest. + +config ISA_SVPBMT + bool "Svpbmt (Page-Based Memory Types)" + default n + help + Enable the RISC-V Svpbmt extension. This sets HENVCFG.PBMTE so that + guests can use page-based memory types in their page-table entries. + +config ISA_CMO + bool "CMO (Base Cache Management Operations)" + default n + help + Enable the RISC-V base Cache Management Operation ISA extensions: + Zicbom for cache-block management, Zicbop for cache-block prefetch, + and Zicboz for cache-block zero. + +config HYPERVISOR_V0_6 + bool "Hypervisor v0.6" + default n + +config EIC7700_SYSREG + bool "EIC7700 system registers" + depends on HYPERVISOR_V0_6 + default n + +config SIFIVE_CCACHE + bool "SiFive ccache" + depends on HYPERVISOR_V0_6 + default n + +endmenu + +menu "LoongArch platform" + depends on ARCH_LOONGARCH64 + +config LOONGSON_3A5000 + bool "Loongson 3A5000 CPU profile" + default n + +config LOONGSON_3A6000 + bool "Loongson 3A6000 CPU profile" + default n +endmenu + +menu "UART" + +config PL011 + bool "PL011" + depends on ARCH_AARCH64 + default n + +config IMX_UART + bool "iMX UART" + depends on ARCH_AARCH64 + default n + +config XUARTPS + bool "XUARTPS" + depends on ARCH_AARCH64 + default n + +config UART_16550 + bool "UART_16550" + depends on ARCH_AARCH64 + default n + +config UART16550A + bool "UART16550A" + depends on ARCH_X86_64 + default n + +config LOONGSON_UART + bool "Loongson UART" + depends on ARCH_LOONGARCH64 + default n + +config SEQUENTIAL_OUTPUT + bool "Wait for UART before writing console output" + depends on ARCH_AARCH64 && (PL011 || UART_16550) + default n +endmenu + +menu "PCIe" + +config PCI + bool "PCI/PCIe support" + default n + +choice + prompt "PCIe Architecture" + depends on PCI + default PCIE_ECAM + +config PCIE_ECAM + bool "ECAM PCIe" + +config PCIE_DWC + bool "DesignWare Core PCIe" + +config PCIE_LOONGARCH64 + bool "LoongArch PCIe" + depends on ARCH_LOONGARCH64 + +endchoice + +config NO_PCIE_BAR_REALLOC + bool "Do not reallocate PCIe BARs (board-specific)" + depends on PCI + default n + +config DWC_MSI + bool "DesignWare native MSI" + depends on PCIE_DWC + default n + +config PCI_INIT_DELAY + bool "Delay PCI init until guest DBI offset 0 access" + depends on PCIE_DWC + default n + +config SRIOV + bool "SR-IOV PF/VF enumeration and passthrough" + depends on PCI + default n + +config VIRTIO_PCI + bool "Virtio over PCI" + depends on PCI && IRQ_GICV3 + default n +endmenu + +menu "IOMMU" + +config IOMMU + bool + default n + +config ARM_SMMU + bool "ARM SMMU" + depends on ARCH_AARCH64 + select IOMMU + default n + +config INTEL_VTD + bool "Intel VT-d" + depends on ARCH_X86_64 + select IOMMU + default n + +config RISCV_IOMMU + bool "RISC-V IOMMU" + depends on ARCH_RISCV64 + select IOMMU + default n + +config SHARE_S2PT + bool "Share stage-2 page tables with IOMMU (RISC-V IOMMU only)" + depends on RISCV_IOMMU + default n + +config VIOMMU + bool "Virtual RISC-V IOMMU" + depends on RISCV_IOMMU + default n +endmenu + +menu "x86-specific options" + depends on ARCH_X86_64 + +config GRAPHICS + bool "Framebuffer / graphics" + default n + +config SPLIT_SCREEN + bool "Split screen layout" + depends on GRAPHICS + default n + +config PRINT_TIMESTAMP + bool "Print timestamp in logs" + default n +endmenu + +menu "Debug" + +config EXTIOI_DEBUG + bool "EXTIOI debug (LoongArch LS7A2000)" + depends on ARCH_LOONGARCH64 + default n +endmenu diff --git a/kconfig/cfg_map.toml b/kconfig/cfg_map.toml new file mode 100644 index 000000000..bb6bd4430 --- /dev/null +++ b/kconfig/cfg_map.toml @@ -0,0 +1,47 @@ +# Kconfig / .config symbol -> rustc cfg name (must match #[cfg(...)] in source). +# Keys are exactly as in .config (CONFIG_*). +[symbols] +CONFIG_IRQ_GICV2 = "irq_gicv2" +CONFIG_IRQ_GICV3 = "irq_gicv3" +CONFIG_AARCH64_UEFI_SUPPORT = "aarch64_uefi_support" +CONFIG_PL011 = "pl011" +CONFIG_IMX_UART = "imx_uart" +CONFIG_XUARTPS = "xuartps" +CONFIG_UART_16550 = "uart_16550" +CONFIG_UART16550A = "uart16550a" +CONFIG_LOONGSON_UART = "loongson_uart" +CONFIG_SEQUENTIAL_OUTPUT = "sequential_output" +CONFIG_PCI = "pci" +CONFIG_PCIE_ECAM = "ecam_pcie" +CONFIG_PCIE_DWC = "dwc_pcie" +CONFIG_PCIE_LOONGARCH64 = "loongarch64_pcie" +CONFIG_NO_PCIE_BAR_REALLOC = "no_pcie_bar_realloc" +CONFIG_DWC_MSI = "dwc_msi" +CONFIG_PCI_INIT_DELAY = "pci_init_delay" +CONFIG_SRIOV = "sriov" +CONFIG_VIRTIO_PCI = "virtio_pci" +CONFIG_IOMMU = "iommu" +CONFIG_SHARE_S2PT = "share_s2pt" +CONFIG_ARM_SMMU = "arm_smmu" +CONFIG_INTEL_VTD = "intel_vtd" +CONFIG_RISCV_IOMMU = "riscv_iommu" +CONFIG_VIOMMU = "viommu" +CONFIG_PLIC = "plic" +CONFIG_DP1000_PLIC = "dp1000_plic" +CONFIG_AIA = "aia" +CONFIG_ACLINT = "aclint" +CONFIG_RVA23 = "rva23" +CONFIG_ISA_VECTOR = "isa_vector" +CONFIG_ISA_SSTC = "isa_sstc" +CONFIG_ISA_SVPBMT = "isa_svpbmt" +CONFIG_ISA_CMO = "isa_cmo" +CONFIG_HYPERVISOR_V0_6 = "hypervisor_v0_6" +CONFIG_EIC7700_SYSREG = "eic7700_sysreg" +CONFIG_SIFIVE_CCACHE = "sifive_ccache" +CONFIG_LOONGSON_7A2000 = "loongson_7a2000" +CONFIG_LOONGSON_3A5000 = "loongson_3a5000" +CONFIG_LOONGSON_3A6000 = "loongson_3a6000" +CONFIG_GRAPHICS = "graphics" +CONFIG_SPLIT_SCREEN = "split_screen" +CONFIG_PRINT_TIMESTAMP = "print_timestamp" +CONFIG_EXTIOI_DEBUG = "extioi_debug" diff --git a/platform/aarch64/dayu200/board.rs b/platform/aarch64/dayu200/board.rs new file mode 100644 index 000000000..6caf0be13 --- /dev/null +++ b/platform/aarch64/dayu200/board.rs @@ -0,0 +1,130 @@ +// Copyright (c) 2025 Syswonder +// hvisor is licensed under Mulan PSL v2. +// You can use this software according to the terms and conditions of the Mulan PSL v2. +// You may obtain a copy of Mulan PSL v2 at: +// http://license.coscl.org.cn/MulanPSL2 +// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR +// FIT FOR A PARTICULAR PURPOSE. +// See the Mulan PSL v2 for more details. +// +// Syswonder Website: +// https://www.syswonder.org +// +// Authors: +// + +use crate::{ + arch::{ + mmu::MemoryType, + zone::{GicConfig, Gicv3Config, HvArchZoneConfig, UefiConfig}, + }, + config::*, +}; + +pub const BOARD_NAME: &str = "dayu200-rk3568"; + +pub const BOARD_NCPUS: usize = 4; +pub const BOARD_UART_BASE: u64 = 0xfe660000; +// pub const BOARD_UART_EMERGENCY_BASE: u64 = 0xfe670000; + +#[rustfmt::skip] +pub static BOARD_MPIDR_MAPPINGS: [u64; BOARD_NCPUS] = [ + 0x0, // cpu0 + 0x100, // cpu1 + 0x200, // cpu2 + 0x300, // cpu3 +]; + +/// Early boot cache invalidate mask (per CPU): bit0->L1(D), bit1->L2, bit2->L3. +pub static BOARD_EARLY_CACHE_INVALIDATE_MASKS: [u64; BOARD_NCPUS] = [0b011; BOARD_NCPUS]; + +/// The physical memory layout of the board. +/// Each address should align to 2M (0x200000). +/// Addresses must be in ascending order. +#[rustfmt::skip] +pub const BOARD_PHYSMEM_LIST: &[(u64, u64, MemoryType)] = &[ + // ( start, end, type) + ( 0x0, 0xf0_000_000, MemoryType::Normal), + ( 0xf0_000_000, 0x100000000, MemoryType::Device), +]; +pub const ROOT_ZONE_DTB_ADDR: u64 = 0x60000000; +pub const ROOT_ZONE_KERNEL_ADDR: u64 = 0x61000000; +pub const ROOT_ZONE_ENTRY: u64 = 0x61000000; +//pub const ROOT_ZONE_CPUS: u64 = (1 << 0) ; +pub const ROOT_ZONE_CPUS: u64 = (1 << 0) | (1 << 1); + +pub const ROOT_ZONE_NAME: &str = "root-linux"; +pub const ROOT_ZONE_MEMORY_REGIONS: [HvConfigMemoryRegion; 8] = [ + HvConfigMemoryRegion { + mem_type: MEM_TYPE_IO, + physical_start: 0x100000, + virtual_start: 0x100000, + size: 0x10000, + }, + HvConfigMemoryRegion { + mem_type: MEM_TYPE_IO, + physical_start: 0xF0000000, + virtual_start: 0xF0000000, + size: 0xD400000, // 到 GIC 之前 + }, + HvConfigMemoryRegion { + mem_type: MEM_TYPE_IO, + physical_start: 0xfd410000, + virtual_start: 0xfd410000, + size: 0x50000, + }, + HvConfigMemoryRegion { + mem_type: MEM_TYPE_IO, + physical_start: 0xfd520000, + virtual_start: 0xfd520000, + size: 0x1AE0000, // GIC 之后到 0xFF000000 + }, + HvConfigMemoryRegion { + mem_type: MEM_TYPE_IO, + physical_start: 0x3c0800000, + virtual_start: 0x3c0800000, + size: 0x400000, + }, // pcie@fe280000 + HvConfigMemoryRegion { + mem_type: MEM_TYPE_RAM, + physical_start: 0x200000, + virtual_start: 0x200000, + size: 0x8200000, + }, // memory + HvConfigMemoryRegion { + mem_type: MEM_TYPE_RAM, + physical_start: 0x9400000, + virtual_start: 0x9400000, + size: 0x76C00000, + }, // memory + HvConfigMemoryRegion { + mem_type: MEM_TYPE_RAM, + physical_start: 0x110000, + virtual_start: 0x110000, + size: 0xf0000, + }, // memory ramoops +]; + +pub const ROOT_ZONE_IRQS_BITMAP: &[BitmapWord] = &get_irqs_bitmap(&[ + 0x33, 0x38, 0x3b, 0x3d, 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x4e, 0x85, 0x8b, 0x8d, 0x96, +]); + +pub const IRQ_WAKEUP_VIRTIO_DEVICE: usize = 32 + 0x6b; + +pub const ROOT_ARCH_ZONE_CONFIG: HvArchZoneConfig = HvArchZoneConfig { + is_aarch32: 0, + gic_config: GicConfig::Gicv3(Gicv3Config { + gicd_base: 0xfd400000, + gicd_size: 0x10000, + gicr_base: 0xfd460000, + gicr_size: 0xc0000, + gits_base: 0, + gits_size: 0, + }), + uefi_config: UefiConfig::NoUefi, +}; + +pub const ROOT_ZONE_IVC_CONFIG: [HvIvcConfig; 0] = []; + +pub const ROOT_PCI_DEVS: [u64; 0] = []; diff --git a/platform/aarch64/dayu200/cargo/config.template.toml b/platform/aarch64/dayu200/cargo/config.template.toml new file mode 100644 index 000000000..b9a3665c8 --- /dev/null +++ b/platform/aarch64/dayu200/cargo/config.template.toml @@ -0,0 +1,6 @@ +[target.aarch64-unknown-none] +rustflags = [ + "-Clink-arg=-Tplatform/__ARCH__/__BOARD__/linker.ld", + "-Ctarget-feature=+a55,+v8a,+strict-align,-neon,-fp-armv8", + "-Cforce-frame-pointers=yes", +] \ No newline at end of file diff --git a/platform/aarch64/dayu200/configs/zone1-ohos-virtio.json b/platform/aarch64/dayu200/configs/zone1-ohos-virtio.json new file mode 100644 index 000000000..8bf59a0e0 --- /dev/null +++ b/platform/aarch64/dayu200/configs/zone1-ohos-virtio.json @@ -0,0 +1,44 @@ +{ + "zones": [ + { + "id": 1, + "memory_region": [ + { + "zone0_ipa": "0x50000000", + "zonex_ipa": "0x50000000", + "size": "0x04000000" + }, + { + "zone0_ipa": "0x10000000", + "zonex_ipa": "0x10000000", + "size": "0x20000000" + } + ], + "devices": [ + { + "type": "console", + "addr": "0xff9d0000", + "len": "0x200", + "irq": 142, + "status": "enable" + }, + { + "type": "net", + "addr": "0xff9e0000", + "len": "0x200", + "irq": 140, + "tap": "tap0", + "mac": [ + "0x02", + "0x16", + "0x3e", + "0x10", + "0x10", + "0x01" + ], + "status": "enable" + } + ] + } + ] +} diff --git a/platform/aarch64/dayu200/configs/zone1-ohos.json b/platform/aarch64/dayu200/configs/zone1-ohos.json new file mode 100644 index 000000000..c8b301a2b --- /dev/null +++ b/platform/aarch64/dayu200/configs/zone1-ohos.json @@ -0,0 +1,89 @@ +{ + "arch": "arm64", + "name": "zone1-ohos", + "zone_id": 1, + "cpus": [ + 2, + 3 + ], + "memory_regions": [ + { + "type": "ram", + "physical_start": "0x10000000", + "virtual_start": "0x10000000", + "size": "0x20000000" + }, + { + "type": "ram", + "physical_start": "0x50000000", + "virtual_start": "0x50000000", + "size": "0x04000000" + }, + { + "type": "virtio", + "physical_start": "0xff9d0000", + "virtual_start": "0xff9d0000", + "size": "0x200" + }, + { + "type": "virtio", + "physical_start": "0xff9e0000", + "virtual_start": "0xff9e0000", + "size": "0x200" + }, + { + "type": "io", + "physical_start": "0x100000", + "virtual_start": "0x100000", + "size": "0x10000" + }, + { + "type": "io", + "physical_start": "0xf0000000", + "virtual_start": "0xf0000000", + "size": "0x00300000" + }, + { + "type": "io", + "physical_start": "0xfd520000", + "virtual_start": "0xfd520000", + "size": "0x1140000" + }, + { + "type": "io", + "physical_start": "0xfd410000", + "virtual_start": "0xfd410000", + "size": "0x50000" + } + ], + "interrupts": [ + "0x82", + "0x8c", + "0x8e" + ], + "ivc_configs": [], + "kernel_filepath": "./zone1-ohos.kernel", + "dtb_filepath": "./zone1-ohos.dtb", + "kernel_load_paddr": "0x50600000", + "dtb_load_paddr": "0x50000000", + "entry_point": "0x50600000", + "kernel_args": "", + "modules": [ + { + "name": "ramdisk", + "filepath": "./zone1-ohos.ramdisk", + "load_paddr": "0x50200000" + } + ], + "arch_config": { + "gic_version": "v3", + "gicd_base": "0xfd400000", + "gicd_size": "0x10000", + "gicr_base": "0xfd460000", + "gicr_size": "0xc0000", + "gits_base": "0x0", + "gits_size": "0x0" + }, + "pci_config": [], + "alloc_pci_devs": [] +} diff --git a/platform/aarch64/dayu200/image/dts/Makefile b/platform/aarch64/dayu200/image/dts/Makefile new file mode 100644 index 000000000..2f795e7fe --- /dev/null +++ b/platform/aarch64/dayu200/image/dts/Makefile @@ -0,0 +1,8 @@ +DTS_FILES := $(wildcard *.dts) +DTB_FILES := $(DTS_FILES:.dts=.dtb) + +all: $(DTB_FILES) +%.dtb: %.dts + dtc -I dts -O dtb $< -o $@ +clean: + rm -f $(DTB_FILES) \ No newline at end of file diff --git a/platform/aarch64/dayu200/image/dts/toybrick.dts b/platform/aarch64/dayu200/image/dts/toybrick.dts new file mode 100644 index 000000000..8a13801ad --- /dev/null +++ b/platform/aarch64/dayu200/image/dts/toybrick.dts @@ -0,0 +1,6246 @@ +/dts-v1/; + +/ { + interrupt-parent = <0x01>; + #address-cells = <0x02>; + #size-cells = <0x02>; + compatible = "rockchip,rk3568-toybrick-dev-linux-x0\0rockchip,rk3568"; + + ddr3-params { + version = <0x100>; + expanded_version = <0x00>; + reserved = <0x00>; + freq_0 = <0x420>; + freq_1 = <0x144>; + freq_2 = <0x210>; + freq_3 = <0x30c>; + freq_4 = <0x00>; + freq_5 = <0x00>; + pd_idle = <0x0d>; + sr_idle = <0x5d>; + sr_mc_gate_idle = <0x00>; + srpd_lite_idle = <0x00>; + standby_idle = <0x00>; + pd_dis_freq = <0x42a>; + sr_dis_freq = <0x320>; + dram_dll_dis_freq = <0x12c>; + phy_dll_dis_freq = <0x00>; + phy_dq_drv_odten = <0x21>; + phy_ca_drv_odten = <0x21>; + phy_clk_drv_odten = <0x21>; + dram_dq_drv_odten = <0x22>; + phy_dq_drv_odtoff = <0x21>; + phy_ca_drv_odtoff = <0x21>; + phy_clk_drv_odtoff = <0x21>; + dram_dq_drv_odtoff = <0x22>; + dram_odt = <0x78>; + phy_odt = <0xa7>; + phy_odt_puup_en = <0x01>; + phy_odt_pudn_en = <0x01>; + dram_dq_odt_en_freq = <0x14d>; + phy_odt_en_freq = <0x14d>; + phy_dq_sr_odten = <0x0f>; + phy_ca_sr_odten = <0x03>; + phy_clk_sr_odten = <0x00>; + phy_dq_sr_odtoff = <0x0f>; + phy_ca_sr_odtoff = <0x03>; + phy_clk_sr_odtoff = <0x00>; + ssmod_downspread = <0x00>; + ssmod_div = <0x00>; + ssmod_spread = <0x00>; + mode_2t = <0x00>; + speed_bin = <0x15>; + dram_ext_temp = <0x00>; + byte_map = <0xe4>; + dq_map_cs0_dq_l = <0x00>; + dq_map_cs0_dq_h = <0x00>; + dq_map_cs1_dq_l = <0x00>; + dq_map_cs1_dq_h = <0x00>; + phandle = <0xbc>; + }; + + ddr4-params { + version = <0x100>; + expanded_version = <0x00>; + reserved = <0x00>; + freq_0 = <0x420>; + freq_1 = <0x144>; + freq_2 = <0x210>; + freq_3 = <0x30c>; + freq_4 = <0x00>; + freq_5 = <0x00>; + pd_idle = <0x0d>; + sr_idle = <0x5d>; + sr_mc_gate_idle = <0x00>; + srpd_lite_idle = <0x00>; + standby_idle = <0x00>; + pd_dis_freq = <0x42a>; + sr_dis_freq = <0x320>; + dram_dll_dis_freq = <0x271>; + phy_dll_dis_freq = <0x00>; + phy_dq_drv_odten = <0x25>; + phy_ca_drv_odten = <0x25>; + phy_clk_drv_odten = <0x25>; + dram_dq_drv_odten = <0x22>; + phy_dq_drv_odtoff = <0x25>; + phy_ca_drv_odtoff = <0x25>; + phy_clk_drv_odtoff = <0x25>; + dram_dq_drv_odtoff = <0x22>; + dram_odt = <0x78>; + phy_odt = <0x8b>; + phy_odt_puup_en = <0x01>; + phy_odt_pudn_en = <0x01>; + dram_dq_odt_en_freq = <0x1f4>; + phy_odt_en_freq = <0x1f4>; + phy_dq_sr_odten = <0x0e>; + phy_ca_sr_odten = <0x01>; + phy_clk_sr_odten = <0x01>; + phy_dq_sr_odtoff = <0x0e>; + phy_ca_sr_odtoff = <0x01>; + phy_clk_sr_odtoff = <0x01>; + ssmod_downspread = <0x00>; + ssmod_div = <0x00>; + ssmod_spread = <0x00>; + mode_2t = <0x00>; + speed_bin = <0x0c>; + dram_ext_temp = <0x00>; + byte_map = <0xe4>; + dq_map_cs0_dq_l = <0x22777788>; + dq_map_cs0_dq_h = <0xd7888877>; + dq_map_cs1_dq_l = <0x22777788>; + dq_map_cs1_dq_h = <0xd7888877>; + phandle = <0xbd>; + }; + + lpddr3-params { + version = <0x100>; + expanded_version = <0x00>; + reserved = <0x00>; + freq_0 = <0x420>; + freq_1 = <0x144>; + freq_2 = <0x210>; + freq_3 = <0x30c>; + freq_4 = <0x00>; + freq_5 = <0x00>; + pd_idle = <0x0d>; + sr_idle = <0x5d>; + sr_mc_gate_idle = <0x00>; + srpd_lite_idle = <0x00>; + standby_idle = <0x00>; + pd_dis_freq = <0x42a>; + sr_dis_freq = <0x320>; + dram_dll_dis_freq = <0x00>; + phy_dll_dis_freq = <0x00>; + phy_dq_drv_odten = <0x25>; + phy_ca_drv_odten = <0x25>; + phy_clk_drv_odten = <0x27>; + dram_dq_drv_odten = <0x22>; + phy_dq_drv_odtoff = <0x25>; + phy_ca_drv_odtoff = <0x25>; + phy_clk_drv_odtoff = <0x27>; + dram_dq_drv_odtoff = <0x22>; + dram_odt = <0x78>; + phy_odt = <0x94>; + phy_odt_puup_en = <0x01>; + phy_odt_pudn_en = <0x01>; + dram_dq_odt_en_freq = <0x14d>; + phy_odt_en_freq = <0x14d>; + phy_dq_sr_odten = <0x0f>; + phy_ca_sr_odten = <0x01>; + phy_clk_sr_odten = <0x0f>; + phy_dq_sr_odtoff = <0x0f>; + phy_ca_sr_odtoff = <0x01>; + phy_clk_sr_odtoff = <0x0f>; + ssmod_downspread = <0x00>; + ssmod_div = <0x00>; + ssmod_spread = <0x00>; + mode_2t = <0x00>; + speed_bin = <0x00>; + dram_ext_temp = <0x00>; + byte_map = <0x8d>; + dq_map_cs0_dq_l = <0x00>; + dq_map_cs0_dq_h = <0x00>; + dq_map_cs1_dq_l = <0x00>; + dq_map_cs1_dq_h = <0x00>; + phandle = <0xbe>; + }; + + lpddr4-params { + version = <0x100>; + expanded_version = <0x00>; + reserved = <0x00>; + freq_0 = <0x618>; + freq_1 = <0x144>; + freq_2 = <0x210>; + freq_3 = <0x30c>; + freq_4 = <0x00>; + freq_5 = <0x00>; + pd_idle = <0x0d>; + sr_idle = <0x5d>; + sr_mc_gate_idle = <0x00>; + srpd_lite_idle = <0x00>; + standby_idle = <0x00>; + pd_dis_freq = <0x42a>; + sr_dis_freq = <0x320>; + dram_dll_dis_freq = <0x00>; + phy_dll_dis_freq = <0x00>; + phy_dq_drv_odten = <0x1e>; + phy_ca_drv_odten = <0x26>; + phy_clk_drv_odten = <0x26>; + dram_dq_drv_odten = <0x28>; + phy_dq_drv_odtoff = <0x1e>; + phy_ca_drv_odtoff = <0x26>; + phy_clk_drv_odtoff = <0x26>; + dram_dq_drv_odtoff = <0x28>; + dram_odt = <0x50>; + phy_odt = <0x3c>; + phy_odt_puup_en = <0x00>; + phy_odt_pudn_en = <0x00>; + dram_dq_odt_en_freq = <0x320>; + phy_odt_en_freq = <0x320>; + phy_dq_sr_odten = <0x00>; + phy_ca_sr_odten = <0x0f>; + phy_clk_sr_odten = <0x0f>; + phy_dq_sr_odtoff = <0x00>; + phy_ca_sr_odtoff = <0x0f>; + phy_clk_sr_odtoff = <0x0f>; + ssmod_downspread = <0x00>; + ssmod_div = <0x00>; + ssmod_spread = <0x00>; + mode_2t = <0x00>; + speed_bin = <0x00>; + dram_ext_temp = <0x00>; + byte_map = <0xe4>; + dq_map_cs0_dq_l = <0x00>; + dq_map_cs0_dq_h = <0x00>; + dq_map_cs1_dq_l = <0x00>; + dq_map_cs1_dq_h = <0x00>; + lp4_ca_odt = <0x78>; + lp4_drv_pu_cal_odten = <0x01>; + lp4_drv_pu_cal_odtoff = <0x01>; + phy_lp4_drv_pulldown_en_odten = <0x00>; + phy_lp4_drv_pulldown_en_odtoff = <0x00>; + lp4_ca_odt_en_freq = <0x320>; + phy_lp4_cs_drv_odten = <0x00>; + phy_lp4_cs_drv_odtoff = <0x00>; + lp4_odte_ck_en = <0x01>; + lp4_odte_cs_en = <0x01>; + lp4_odtd_ca_en = <0x00>; + phy_lp4_dq_vref_odten = <0xa6>; + lp4_dq_vref_odten = <0x12c>; + lp4_ca_vref_odten = <0x17c>; + phy_lp4_dq_vref_odtoff = <0x1a4>; + lp4_dq_vref_odtoff = <0x1a4>; + lp4_ca_vref_odtoff = <0x1a4>; + phandle = <0xbf>; + }; + + lpddr4x-params { + version = <0x100>; + expanded_version = <0x00>; + reserved = <0x00>; + freq_0 = <0x618>; + freq_1 = <0x144>; + freq_2 = <0x210>; + freq_3 = <0x30c>; + freq_4 = <0x00>; + freq_5 = <0x00>; + pd_idle = <0x0d>; + sr_idle = <0x5d>; + sr_mc_gate_idle = <0x00>; + srpd_lite_idle = <0x00>; + standby_idle = <0x00>; + pd_dis_freq = <0x42a>; + sr_dis_freq = <0x320>; + dram_dll_dis_freq = <0x00>; + phy_dll_dis_freq = <0x00>; + phy_dq_drv_odten = <0x1d>; + phy_ca_drv_odten = <0x24>; + phy_clk_drv_odten = <0x24>; + dram_dq_drv_odten = <0x28>; + phy_dq_drv_odtoff = <0x1d>; + phy_ca_drv_odtoff = <0x24>; + phy_clk_drv_odtoff = <0x24>; + dram_dq_drv_odtoff = <0x28>; + dram_odt = <0x50>; + phy_odt = <0x3c>; + phy_odt_puup_en = <0x00>; + phy_odt_pudn_en = <0x00>; + dram_dq_odt_en_freq = <0x320>; + phy_odt_en_freq = <0x320>; + phy_dq_sr_odten = <0x00>; + phy_ca_sr_odten = <0x00>; + phy_clk_sr_odten = <0x00>; + phy_dq_sr_odtoff = <0x00>; + phy_ca_sr_odtoff = <0x00>; + phy_clk_sr_odtoff = <0x00>; + ssmod_downspread = <0x00>; + ssmod_div = <0x00>; + ssmod_spread = <0x00>; + mode_2t = <0x00>; + speed_bin = <0x00>; + dram_ext_temp = <0x00>; + byte_map = <0xe4>; + dq_map_cs0_dq_l = <0x00>; + dq_map_cs0_dq_h = <0x00>; + dq_map_cs1_dq_l = <0x00>; + dq_map_cs1_dq_h = <0x00>; + lp4_ca_odt = <0x78>; + lp4_drv_pu_cal_odten = <0x00>; + lp4_drv_pu_cal_odtoff = <0x00>; + phy_lp4_drv_pulldown_en_odten = <0x00>; + phy_lp4_drv_pulldown_en_odtoff = <0x00>; + lp4_ca_odt_en_freq = <0x320>; + phy_lp4_cs_drv_odten = <0x00>; + phy_lp4_cs_drv_odtoff = <0x00>; + lp4_odte_ck_en = <0x00>; + lp4_odte_cs_en = <0x00>; + lp4_odtd_ca_en = <0x00>; + phy_lp4_dq_vref_odten = <0xa6>; + lp4_dq_vref_odten = <0xe4>; + lp4_ca_vref_odten = <0x157>; + phy_lp4_dq_vref_odtoff = <0x1a4>; + lp4_dq_vref_odtoff = <0x1a4>; + lp4_ca_vref_odtoff = <0x157>; + phandle = <0xc0>; + }; + + aliases { + csi2dphy0 = "/csi2-dphy0"; + csi2dphy1 = "/csi2-dphy1"; + csi2dphy2 = "/csi2-dphy2"; + dsi0 = "/dsi@fe060000"; + dsi1 = "/dsi@fe070000"; + ethernet1 = "/ethernet@fe010000"; + gpio0 = "/pinctrl/gpio0@fdd60000"; + gpio1 = "/pinctrl/gpio1@fe740000"; + gpio2 = "/pinctrl/gpio2@fe750000"; + gpio3 = "/pinctrl/gpio3@fe760000"; + gpio4 = "/pinctrl/gpio4@fe770000"; + i2c0 = "/i2c@fdd40000"; + i2c1 = "/i2c@fe5a0000"; + i2c2 = "/i2c@fe5b0000"; + i2c3 = "/i2c@fe5c0000"; + i2c4 = "/i2c@fe5d0000"; + i2c5 = "/i2c@fe5e0000"; + mmc0 = "/sdhci@fe310000"; + mmc1 = "/dwmmc@fe2b0000"; + mmc2 = "/dwmmc@fe2c0000"; + mmc3 = "/mmc@fe000000"; + serial0 = "/serial@fdd50000"; + serial1 = "/serial@fe650000"; + serial2 = "/serial@fe660000"; + serial3 = "/serial@fe670000"; + serial4 = "/serial@fe680000"; + serial5 = "/serial@fe690000"; + serial6 = "/serial@fe6a0000"; + serial7 = "/serial@fe6b0000"; + serial8 = "/serial@fe6c0000"; + serial9 = "/serial@fe6d0000"; + spi0 = "/spi@fe610000"; + spi1 = "/spi@fe620000"; + spi2 = "/spi@fe630000"; + spi3 = "/spi@fe640000"; + ethernet0 = "/ethernet@fe2a0000"; + lvds0 = "/syscon@fdc60000/lvds"; + lvds1 = "/syscon@fdc60000/lvds1"; + }; + + cpus { + #address-cells = <0x02>; + #size-cells = <0x00>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x00 0x00>; + clocks = <0x02 0x00>; + #cooling-cells = <0x02>; + enable-method = "psci"; + operating-points-v2 = <0x03>; + cpu-idle-states = <0x04>; + dynamic-power-coefficient = <0xbb>; + cpu-supply = <0x05>; + phandle = <0x1f>; + }; + + cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x00 0x100>; + #cooling-cells = <0x02>; + enable-method = "psci"; + operating-points-v2 = <0x03>; + cpu-idle-states = <0x04>; + phandle = <0x20>; + }; + + cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x00 0x200>; + #cooling-cells = <0x02>; + enable-method = "psci"; + operating-points-v2 = <0x03>; + cpu-idle-states = <0x04>; + phandle = <0x21>; + }; + + cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x00 0x300>; + #cooling-cells = <0x02>; + enable-method = "psci"; + operating-points-v2 = <0x03>; + cpu-idle-states = <0x04>; + phandle = <0x22>; + }; + + idle-states { + entry-method = "psci"; + + cpu-sleep { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x10000>; + entry-latency-us = <0x64>; + exit-latency-us = <0x78>; + min-residency-us = <0x3e8>; + phandle = <0x04>; + }; + }; + }; + + opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + mbist-vmin = <0xc96a8 0xdbba0 0xe7ef0>; + nvmem-cells = <0x06 0x07 0x08 0x09 0x0a 0x0b>; + nvmem-cell-names = "leakage\0pvtm\0mbist-vmin\0opp-info\0specification_serial_number\0remark_spec_serial_number"; + rockchip,supported-hw; + rockchip,max-volt = <0x118c30>; + rockchip,pvtm-voltage-sel = <0x00 0x14820 0x00 0x14821 0x153d8 0x01 0x153d9 0x16378 0x02 0x16379 0x186a0 0x03>; + rockchip,pvtm-freq = <0x639c0>; + rockchip,pvtm-volt = <0xdbba0>; + rockchip,pvtm-ch = <0x00 0x05>; + rockchip,pvtm-sample-time = <0x3e8>; + rockchip,pvtm-number = <0x0a>; + rockchip,pvtm-error = <0x3e8>; + rockchip,pvtm-ref-temp = <0x28>; + rockchip,pvtm-temp-prop = <0x1a 0x1a>; + rockchip,thermal-zone = "soc-thermal"; + rockchip,temp-hysteresis = <0x1388>; + rockchip,low-temp = <0x00>; + rockchip,low-temp-adjust-volt = <0x00 0x7c8 0x124f8>; + phandle = <0x03>; + + opp-408000000 { + opp-supported-hw = <0xfb 0xffff>; + opp-hz = <0x00 0x18519600>; + opp-microvolt = <0xcf850 0xcf850 0x118c30>; + clock-latency-ns = <0x9c40>; + }; + + opp-600000000 { + opp-supported-hw = <0xfb 0xffff>; + opp-hz = <0x00 0x23c34600>; + opp-microvolt = <0xcf850 0xcf850 0x118c30>; + clock-latency-ns = <0x9c40>; + }; + + opp-816000000 { + opp-supported-hw = <0xfb 0xffff>; + opp-hz = <0x00 0x30a32c00>; + opp-microvolt = <0xcf850 0xcf850 0x118c30>; + clock-latency-ns = <0x9c40>; + opp-suspend; + }; + + opp-1104000000 { + opp-supported-hw = <0xfb 0xffff>; + opp-hz = <0x00 0x41cdb400>; + opp-microvolt = <0xdbba0 0xdbba0 0x118c30>; + opp-microvolt-L0 = <0xdbba0 0xdbba0 0x118c30>; + opp-microvolt-L1 = <0xcf850 0xcf850 0x118c30>; + opp-microvolt-L2 = <0xcf850 0xcf850 0x118c30>; + opp-microvolt-L3 = <0xcf850 0xcf850 0x118c30>; + clock-latency-ns = <0x9c40>; + }; + + opp-1416000000 { + opp-supported-hw = <0xfb 0xffff>; + opp-hz = <0x00 0x54667200>; + opp-microvolt = <0xfa3e8 0xfa3e8 0x118c30>; + opp-microvolt-L0 = <0xfa3e8 0xfa3e8 0x118c30>; + opp-microvolt-L1 = <0xee098 0xee098 0x118c30>; + opp-microvolt-L2 = <0xe7ef0 0xe7ef0 0x118c30>; + opp-microvolt-L3 = <0xe1d48 0xe1d48 0x118c30>; + clock-latency-ns = <0x9c40>; + }; + + opp-1608000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = <0x00 0x5fd82200>; + opp-microvolt = <0x10c8e0 0x10c8e0 0x118c30>; + opp-microvolt-L0 = <0x10c8e0 0x10c8e0 0x118c30>; + opp-microvolt-L1 = <0x100590 0x100590 0x118c30>; + opp-microvolt-L2 = <0xfa3e8 0xfa3e8 0x118c30>; + opp-microvolt-L3 = <0xf4240 0xf4240 0x118c30>; + clock-latency-ns = <0x9c40>; + }; + + opp-1800000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = <0x00 0x6b49d200>; + opp-microvolt = <0x118c30 0x118c30 0x118c30>; + opp-microvolt-L0 = <0x118c30 0x118c30 0x118c30>; + opp-microvolt-L1 = <0x10c8e0 0x10c8e0 0x118c30>; + opp-microvolt-L2 = <0x106738 0x106738 0x118c30>; + opp-microvolt-L3 = <0x100590 0x100590 0x118c30>; + clock-latency-ns = <0x9c40>; + }; + + opp-1992000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = <0x00 0x76bb8200>; + opp-microvolt = <0x118c30 0x118c30 0x118c30>; + opp-microvolt-L0 = <0x118c30 0x118c30 0x118c30>; + opp-microvolt-L1 = <0x118c30 0x118c30 0x118c30>; + opp-microvolt-L2 = <0x112a88 0x112a88 0x118c30>; + opp-microvolt-L3 = <0x10c8e0 0x10c8e0 0x118c30>; + clock-latency-ns = <0x9c40>; + }; + + opp-j-1008000000 { + opp-supported-hw = <0x04 0xffff>; + opp-hz = <0x00 0x3c14dc00>; + opp-microvolt = <0xcf850 0xcf850 0x118c30>; + clock-latency-ns = <0x9c40>; + }; + + opp-j-1416000000 { + opp-supported-hw = <0x04 0xffff>; + opp-hz = <0x00 0x54667200>; + opp-microvolt = <0xdbba0 0xdbba0 0x118c30>; + clock-latency-ns = <0x9c40>; + }; + + opp-m-1608000000 { + opp-supported-hw = <0x02 0xffff>; + opp-hz = <0x00 0x5fd82200>; + opp-microvolt = <0xf4240 0xf4240 0x118c30>; + clock-latency-ns = <0x9c40>; + }; + }; + + cpuinfo { + compatible = "rockchip,cpuinfo"; + nvmem-cells = <0x0c 0x0d 0x0e>; + nvmem-cell-names = "id\0cpu-version\0cpu-code"; + }; + + display-subsystem { + compatible = "rockchip,display-subsystem"; + memory-region = <0x0f 0x10>; + memory-region-names = "drm-logo\0drm-cubic-lut"; + ports = <0x11>; + devfreq = <0x12>; + + route { + + route-dsi0 { + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <0x13>; + }; + + route-dsi1 { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <0x14>; + }; + + route-edp { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <0x15>; + }; + + route-hdmi { + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <0x16>; + }; + + route-lvds { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <0x17>; + }; + + route-rgb { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <0x18>; + }; + }; + }; + + firmware { + + scmi { + compatible = "arm,scmi-smc"; + arm,smc-id = <0x82000010>; + shmem = <0x19>; + #address-cells = <0x01>; + #size-cells = <0x00>; + + protocol@14 { + reg = <0x14>; + #clock-cells = <0x01>; + rockchip,clk-init = <0x41cdb400>; + phandle = <0x02>; + }; + }; + + sdei { + compatible = "arm,sdei-1.0"; + method = "smc"; + }; + }; + + opp-table-1 { + compatible = "operating-points-v2"; + mbist-vmin = <0xc96a8 0xdbba0 0xe7ef0>; + nvmem-cells = <0x1a 0x07 0x08 0x1b 0x0a 0x0b>; + nvmem-cell-names = "leakage\0pvtm\0mbist-vmin\0opp-info\0specification_serial_number\0remark_spec_serial_number"; + rockchip,supported-hw; + rockchip,max-volt = <0xf4240>; + rockchip,temp-hysteresis = <0x1388>; + rockchip,low-temp = <0x00>; + rockchip,low-temp-adjust-volt = <0x00 0x320 0xc350>; + rockchip,pvtm-voltage-sel = <0x00 0x14820 0x00 0x14821 0x153d8 0x01 0x153d9 0x16378 0x02 0x16379 0x186a0 0x03>; + rockchip,pvtm-ch = <0x00 0x05>; + phandle = <0x70>; + + opp-200000000 { + opp-supported-hw = <0xfb 0xffff>; + opp-hz = <0x00 0xbebc200>; + opp-microvolt = <0xcf850 0xcf850 0xf4240>; + }; + + opp-300000000 { + opp-supported-hw = <0xfb 0xffff>; + opp-hz = <0x00 0x11e1a300>; + opp-microvolt = <0xcf850 0xcf850 0xf4240>; + }; + + opp-400000000 { + opp-supported-hw = <0xfb 0xffff>; + opp-hz = <0x00 0x17d78400>; + opp-microvolt = <0xcf850 0xcf850 0xf4240>; + }; + + opp-600000000 { + opp-supported-hw = <0xfb 0xffff>; + opp-hz = <0x00 0x23c34600>; + opp-microvolt = <0xdbba0 0xdbba0 0xf4240>; + opp-microvolt-L0 = <0xdbba0 0xdbba0 0xf4240>; + opp-microvolt-L1 = <0xd59f8 0xd59f8 0xf4240>; + opp-microvolt-L2 = <0xcf850 0xcf850 0xf4240>; + opp-microvolt-L3 = <0xcf850 0xcf850 0xf4240>; + }; + + opp-700000000 { + opp-supported-hw = <0xfb 0xffff>; + opp-hz = <0x00 0x29b92700>; + opp-microvolt = <0xe7ef0 0xe7ef0 0xf4240>; + opp-microvolt-L0 = <0xe7ef0 0xe7ef0 0xf4240>; + opp-microvolt-L1 = <0xe1d48 0xe1d48 0xf4240>; + opp-microvolt-L2 = <0xdbba0 0xdbba0 0xf4240>; + opp-microvolt-L3 = <0xd59f8 0xd59f8 0xf4240>; + }; + + opp-800000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = <0x00 0x2faf0800>; + opp-microvolt = <0xf4240 0xf4240 0xf4240>; + opp-microvolt-L0 = <0xf4240 0xf4240 0xf4240>; + opp-microvolt-L1 = <0xee098 0xee098 0xf4240>; + opp-microvolt-L2 = <0xe7ef0 0xe7ef0 0xf4240>; + opp-microvolt-L3 = <0xe1d48 0xe1d48 0xf4240>; + }; + + opp-j-600000000 { + opp-supported-hw = <0x04 0xffff>; + opp-hz = <0x00 0x23c34600>; + opp-microvolt = <0xdbba0 0xdbba0 0xf4240>; + }; + + opp-m-800000000 { + opp-supported-hw = <0x02 0xffff>; + opp-hz = <0x00 0x2faf0800>; + opp-microvolt = <0xe7ef0 0xe7ef0 0xf4240>; + }; + }; + + hdmi-sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "rockchip,hdmi"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <0x80>; + status = "okay"; + + simple-audio-card,codec { + sound-dai = <0x1c>; + }; + + simple-audio-card,cpu { + sound-dai = <0x1d>; + }; + }; + + mipi-csi2 { + compatible = "rockchip,rk3568-mipi-csi2"; + rockchip,hw = <0x1e>; + status = "disabled"; + }; + + mpp-srv { + compatible = "rockchip,mpp-service"; + rockchip,taskqueue-count = <0x06>; + rockchip,resetgroup-count = <0x06>; + status = "okay"; + phandle = <0x73>; + }; + + pmu { + compatible = "arm,cortex-a55-pmu"; + interrupts = <0x00 0xe4 0x04 0x00 0xe5 0x04 0x00 0xe6 0x04 0x00 0xe7 0x04>; + interrupt-affinity = <0x1f 0x20 0x21 0x22>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + reserved-memory { + #address-cells = <0x02>; + #size-cells = <0x02>; + ranges; + + drm-logo@0 { + compatible = "rockchip,drm-logo"; + reg = <0x00 0x00 0x00 0x00>; + phandle = <0x0f>; + }; + + drm-cubic-lut@0 { + compatible = "rockchip,drm-cubic-lut"; + reg = <0x00 0x00 0x00 0x00>; + phandle = <0x10>; + }; + + ramoops@110000 { + compatible = "ramoops"; + reg = <0x00 0x110000 0x00 0xf0000>; + record-size = <0x20000>; + console-size = <0x80000>; + ftrace-size = <0x00>; + pmsg-size = <0x00>; + blackbox-size = <0x50000>; + }; + }; + + rockchip-suspend { + compatible = "rockchip,pm-rk3568"; + status = "disabled"; + rockchip,sleep-debug-en = <0x01>; + rockchip,sleep-mode-config = <0x5ec>; + rockchip,wakeup-config = <0x10>; + }; + + rockchip-system-monitor { + compatible = "rockchip,system-monitor"; + rockchip,thermal-zone = "soc-thermal"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <0x01 0x0d 0xf04 0x01 0x0e 0xf04 0x01 0x0b 0xf04 0x01 0x0a 0xf04>; + arm,no-tick-in-suspend; + }; + + external-gmac1-clock { + compatible = "fixed-clock"; + clock-frequency = <0x7735940>; + clock-output-names = "gmac1_clkin"; + #clock-cells = <0x00>; + }; + + xpcs-gmac1-clock { + compatible = "fixed-clock"; + clock-frequency = <0x7735940>; + clock-output-names = "clk_gmac1_xpcs_mii"; + #clock-cells = <0x00>; + }; + + i2s1-mclkin-rx { + compatible = "fixed-clock"; + #clock-cells = <0x00>; + clock-frequency = <0xbb8000>; + clock-output-names = "i2s1_mclkin_rx"; + }; + + i2s1-mclkin-tx { + compatible = "fixed-clock"; + #clock-cells = <0x00>; + clock-frequency = <0xbb8000>; + clock-output-names = "i2s1_mclkin_tx"; + }; + + i2s2-mclkin { + compatible = "fixed-clock"; + #clock-cells = <0x00>; + clock-frequency = <0xbb8000>; + clock-output-names = "i2s2_mclkin"; + }; + + i2s3-mclkin { + compatible = "fixed-clock"; + #clock-cells = <0x00>; + clock-frequency = <0xbb8000>; + clock-output-names = "i2s3_mclkin"; + }; + + mpll { + compatible = "fixed-clock"; + #clock-cells = <0x00>; + clock-frequency = <0x2faf0800>; + clock-output-names = "mpll"; + }; + + xin24m { + compatible = "fixed-clock"; + clock-frequency = <0x16e3600>; + clock-output-names = "xin24m"; + #clock-cells = <0x00>; + }; + + xin32k { + compatible = "fixed-clock"; + clock-frequency = <0x8000>; + clock-output-names = "xin32k"; + pinctrl-0 = <0x23>; + pinctrl-names = "default"; + #clock-cells = <0x00>; + }; + + scmi-shmem@10f000 { + compatible = "arm,scmi-shmem"; + reg = <0x00 0x10f000 0x00 0x100>; + phandle = <0x19>; + }; + + sata@fc400000 { + compatible = "rockchip,rk3568-dwc-ahci\0snps,dwc-ahci"; + reg = <0x00 0xfc400000 0x00 0x1000>; + clocks = <0x24 0x9b 0x24 0x9c 0x24 0x9d>; + clock-names = "sata\0pmalive\0rxoob"; + interrupts = <0x00 0x5f 0x04>; + phys = <0x25 0x01>; + phy-names = "sata-phy"; + ports-implemented = <0x01>; + power-domains = <0x26 0x0f>; + status = "disabled"; + }; + + sata@fc800000 { + compatible = "rockchip,rk3568-dwc-ahci\0snps,dwc-ahci"; + reg = <0x00 0xfc800000 0x00 0x1000>; + clocks = <0x24 0xa0 0x24 0xa1 0x24 0xa2>; + clock-names = "sata\0pmalive\0rxoob"; + interrupts = <0x00 0x60 0x04>; + phys = <0x27 0x01>; + phy-names = "sata-phy"; + ports-implemented = <0x01>; + power-domains = <0x26 0x0f>; + status = "okay"; + }; + + usbdrd { + compatible = "rockchip,rk3568-dwc3\0rockchip,rk3399-dwc3"; + clocks = <0x24 0xa6 0x24 0xa7 0x24 0xa5 0x24 0x7f>; + clock-names = "ref_clk\0suspend_clk\0bus_clk\0pipe_clk"; + #address-cells = <0x02>; + #size-cells = <0x02>; + ranges; + status = "okay"; + + dwc3@fcc00000 { + compatible = "snps,dwc3"; + reg = <0x00 0xfcc00000 0x00 0x400000>; + interrupts = <0x00 0xa9 0x04>; + dr_mode = "otg"; + phy_type = "utmi_wide"; + power-domains = <0x26 0x0f>; + resets = <0x24 0x94>; + reset-names = "usb3-otg"; + snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + snps,dis_rxdet_inp3_quirk; + snps,parkmode-disable-hs-quirk; + snps,parkmode-disable-ss-quirk; + quirk-skip-phy-init; + status = "okay"; + phys = <0x28 0x29 0x04>; + phy-names = "usb2-phy\0usb3-phy"; + extcon = <0x2a>; + }; + }; + + usbhost { + compatible = "rockchip,rk3568-dwc3\0rockchip,rk3399-dwc3"; + clocks = <0x24 0xa9 0x24 0xaa 0x24 0xa8 0x24 0x7f>; + clock-names = "ref_clk\0suspend_clk\0bus_clk\0pipe_clk"; + #address-cells = <0x02>; + #size-cells = <0x02>; + ranges; + status = "okay"; + + dwc3@fd000000 { + compatible = "snps,dwc3"; + reg = <0x00 0xfd000000 0x00 0x400000>; + interrupts = <0x00 0xaa 0x04>; + dr_mode = "host"; + phys = <0x2b 0x25 0x04>; + phy-names = "usb2-phy\0usb3-phy"; + phy_type = "utmi_wide"; + power-domains = <0x26 0x0f>; + resets = <0x24 0x95>; + reset-names = "usb3-host"; + snps,dis_enblslpm_quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + snps,dis_rxdet_inp3_quirk; + snps,parkmode-disable-hs-quirk; + snps,parkmode-disable-ss-quirk; + status = "okay"; + }; + }; + + interrupt-controller@fd400000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <0x03>; + #address-cells = <0x02>; + #size-cells = <0x02>; + ranges; + interrupt-controller; + reg = <0x00 0xfd400000 0x00 0x10000 0x00 0xfd460000 0x00 0xc0000>; + interrupts = <0x01 0x09 0x04>; + phandle = <0x01>; + + interrupt-controller@fd440000 { + compatible = "arm,gic-v3-its"; + msi-controller; + #msi-cells = <0x01>; + reg = <0x00 0xfd440000 0x00 0x20000>; + phandle = <0xc3>; + }; + }; + + usb@fd800000 { + compatible = "generic-ehci"; + reg = <0x00 0xfd800000 0x00 0x40000>; + interrupts = <0x00 0x82 0x04>; + clocks = <0x24 0xbd 0x24 0xbe 0x24 0xbc 0x2c>; + clock-names = "usbhost\0arbiter\0pclk\0utmi"; + phys = <0x2d>; + phy-names = "usb2-phy"; + status = "okay"; + }; + + usb@fd840000 { + compatible = "generic-ohci"; + reg = <0x00 0xfd840000 0x00 0x40000>; + interrupts = <0x00 0x83 0x04>; + clocks = <0x24 0xbd 0x24 0xbe 0x24 0xbc 0x2c>; + clock-names = "usbhost\0arbiter\0pclk\0utmi"; + phys = <0x2d>; + phy-names = "usb2-phy"; + status = "okay"; + }; + + usb@fd880000 { + compatible = "generic-ehci"; + reg = <0x00 0xfd880000 0x00 0x40000>; + interrupts = <0x00 0x85 0x04>; + clocks = <0x24 0xbf 0x24 0xc0 0x24 0xbc 0x2c>; + clock-names = "usbhost\0arbiter\0pclk\0utmi"; + phys = <0x2e>; + phy-names = "usb2-phy"; + status = "okay"; + }; + + usb@fd8c0000 { + compatible = "generic-ohci"; + reg = <0x00 0xfd8c0000 0x00 0x40000>; + interrupts = <0x00 0x86 0x04>; + clocks = <0x24 0xbf 0x24 0xc0 0x24 0xbc 0x2c>; + clock-names = "usbhost\0arbiter\0pclk\0utmi"; + phys = <0x2e>; + phy-names = "usb2-phy"; + status = "okay"; + }; + + syscon@fda00000 { + compatible = "rockchip,rk3568-xpcs\0syscon"; + reg = <0x00 0xfda00000 0x00 0x200000>; + status = "disabled"; + }; + + syscon@fdc20000 { + compatible = "rockchip,rk3568-pmugrf\0syscon\0simple-mfd"; + reg = <0x00 0xfdc20000 0x00 0x10000>; + phandle = <0x3c>; + + io-domains { + compatible = "rockchip,rk3568-pmu-io-voltage-domain"; + status = "okay"; + pmuio1-supply = <0x2f>; + pmuio2-supply = <0x2f>; + vccio1-supply = <0x30>; + vccio3-supply = <0x31>; + vccio4-supply = <0x32>; + vccio5-supply = <0x33>; + vccio6-supply = <0x32>; + vccio7-supply = <0x33>; + }; + + reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x200>; + mode-bootloader = <0x5242c301>; + mode-charge = <0x5242c30b>; + mode-fastboot = <0x5242c309>; + mode-loader = <0x5242c301>; + mode-normal = <0x5242c300>; + mode-recovery = <0x5242c303>; + mode-ums = <0x5242c30c>; + mode-panic = <0x5242c307>; + mode-watchdog = <0x5242c308>; + }; + }; + + syscon@fdc50000 { + compatible = "rockchip,rk3568-pipe-grf\0syscon"; + reg = <0x00 0xfdc50000 0x00 0x1000>; + phandle = <0x128>; + }; + + syscon@fdc60000 { + compatible = "rockchip,rk3568-grf\0syscon\0simple-mfd"; + reg = <0x00 0xfdc60000 0x00 0x10000>; + phandle = <0x3b>; + + io-domains { + compatible = "rockchip,rk3568-io-voltage-domain"; + status = "disabled"; + }; + + lvds { + compatible = "rockchip,rk3568-lvds"; + phys = <0x34>; + phy-names = "phy"; + status = "disabled"; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + #address-cells = <0x01>; + #size-cells = <0x00>; + + endpoint@1 { + reg = <0x01>; + remote-endpoint = <0x17>; + status = "disabled"; + phandle = <0x9e>; + }; + + endpoint@2 { + reg = <0x02>; + remote-endpoint = <0x35>; + status = "disabled"; + phandle = <0xa0>; + }; + }; + }; + }; + + rgb { + compatible = "rockchip,rk3568-rgb"; + pinctrl-names = "default"; + pinctrl-0 = <0x36>; + status = "disabled"; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + #address-cells = <0x01>; + #size-cells = <0x00>; + + endpoint@2 { + reg = <0x02>; + remote-endpoint = <0x18>; + status = "disabled"; + phandle = <0xa1>; + }; + }; + }; + }; + + lvds1 { + compatible = "rockchip,rk3568-lvds"; + phys = <0x37>; + phy-names = "phy"; + status = "disabled"; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + #address-cells = <0x01>; + #size-cells = <0x00>; + + endpoint@0 { + reg = <0x00>; + remote-endpoint = <0x38>; + phandle = <0x9f>; + }; + + endpoint@1 { + reg = <0x01>; + remote-endpoint = <0x39>; + phandle = <0xa2>; + }; + }; + }; + }; + }; + + syscon@fdc80000 { + compatible = "rockchip,pipe-phy-grf\0syscon"; + reg = <0x00 0xfdc80000 0x00 0x1000>; + phandle = <0x129>; + }; + + syscon@fdc90000 { + compatible = "rockchip,pipe-phy-grf\0syscon"; + reg = <0x00 0xfdc90000 0x00 0x1000>; + phandle = <0x12a>; + }; + + syscon@fdca0000 { + compatible = "rockchip,rk3568-usb2phy-grf\0syscon"; + reg = <0x00 0xfdca0000 0x00 0x8000>; + phandle = <0x130>; + }; + + syscon@fdca8000 { + compatible = "rockchip,rk3568-usb2phy-grf\0syscon"; + reg = <0x00 0xfdca8000 0x00 0x8000>; + phandle = <0x133>; + }; + + syscon@fdcb0000 { + compatible = "rockchip,rk3568-edp-phy-grf\0syscon\0simple-mfd"; + reg = <0x00 0xfdcb0000 0x00 0x100>; + clocks = <0x24 0x192>; + + edp-phy { + compatible = "rockchip,rk3568-edp-phy"; + clocks = <0x3a 0x29>; + clock-names = "refclk"; + #phy-cells = <0x00>; + status = "disabled"; + phandle = <0xb7>; + }; + }; + + sram@fdcc0000 { + compatible = "mmio-sram"; + reg = <0x00 0xfdcc0000 0x00 0xb000>; + #address-cells = <0x01>; + #size-cells = <0x01>; + ranges = <0x00 0x00 0xfdcc0000 0xb000>; + + rkvdec-sram@0 { + reg = <0x00 0xb000>; + phandle = <0x7c>; + }; + }; + + clock-controller@fdd00000 { + compatible = "rockchip,rk3568-pmucru"; + reg = <0x00 0xfdd00000 0x00 0x1000>; + rockchip,grf = <0x3b>; + rockchip,pmugrf = <0x3c>; + #clock-cells = <0x01>; + #reset-cells = <0x01>; + assigned-clocks = <0x3a 0x32>; + assigned-clock-parents = <0x3a 0x05>; + phandle = <0x3a>; + }; + + clock-controller@fdd20000 { + compatible = "rockchip,rk3568-cru"; + reg = <0x00 0xfdd20000 0x00 0x1000>; + rockchip,grf = <0x3b>; + #clock-cells = <0x01>; + #reset-cells = <0x01>; + assigned-clocks = <0x3a 0x05 0x24 0x106 0x24 0x10b 0x3a 0x01 0x3a 0x2b 0x24 0x03 0x24 0x19b 0x24 0x09 0x24 0x19c 0x24 0x19d 0x24 0x1a1 0x24 0x19e 0x24 0x19f 0x24 0x1a0 0x24 0x04 0x24 0x10d 0x24 0x10e 0x24 0x173 0x24 0x174 0x24 0x175 0x24 0x176 0x24 0xc9 0x24 0xca 0x24 0x06 0x24 0x7e 0x24 0x7f 0x24 0x3d 0x24 0x41 0x24 0x45 0x24 0x49 0x24 0x4d 0x24 0x4d 0x24 0x55 0x24 0x51 0x24 0x5d 0x24 0xdd>; + assigned-clock-rates = <0x8000 0x11e1a300 0x11e1a300 0xbebc200 0x5f5e100 0x3b9aca00 0x1dcd6500 0x13d92d40 0xee6b280 0x7735940 0x5f5e100 0x3b9aca0 0x2faf080 0x17d7840 0x46cf7100 0x8f0d180 0x5f5e100 0x1dcd6500 0x17d78400 0x8f0d180 0x5f5e100 0x11e1a300 0x8f0d180 0x47868c00 0x17d78400 0x5f5e100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x1dcd6500>; + assigned-clock-parents = <0x3a 0x08 0x24 0x04 0x24 0x04>; + phandle = <0x24>; + }; + + i2c@fdd40000 { + compatible = "rockchip,rk3568-i2c\0rockchip,rk3399-i2c"; + reg = <0x00 0xfdd40000 0x00 0x1000>; + interrupts = <0x00 0x2e 0x04>; + clocks = <0x3a 0x07 0x3a 0x2d>; + clock-names = "i2c\0pclk"; + pinctrl-0 = <0x3d>; + pinctrl-names = "default"; + #address-cells = <0x01>; + #size-cells = <0x00>; + status = "okay"; + + tcs4525@1c { + compatible = "tcs,tcs452x"; + reg = <0x1c>; + vin-supply = <0x3e>; + regulator-compatible = "fan53555-reg"; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <0xadf34>; + regulator-max-microvolt = <0x1535b0>; + regulator-init-microvolt = <0xe7ef0>; + regulator-ramp-delay = <0x8fc>; + fcs,suspend-voltage-selector = <0x01>; + regulator-boot-on; + regulator-always-on; + phandle = <0x05>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <0x3f>; + interrupts = <0x03 0x08>; + pinctrl-names = "default\0pmic-sleep\0pmic-power-off\0pmic-reset"; + pinctrl-0 = <0x40>; + pinctrl-1 = <0x41 0x42>; + pinctrl-2 = <0x43 0x44>; + pinctrl-3 = <0x43 0x45>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <0x01>; + clock-output-names = "rk808-clkout1\0rk808-clkout2"; + pmic-reset-func = <0x00>; + not-save-power-en = <0x01>; + vcc1-supply = <0x46>; + vcc2-supply = <0x46>; + vcc3-supply = <0x46>; + vcc4-supply = <0x46>; + vcc5-supply = <0x46>; + vcc6-supply = <0x46>; + vcc7-supply = <0x46>; + vcc8-supply = <0x46>; + vcc9-supply = <0x46>; + phandle = <0x161>; + + pwrkey { + status = "okay"; + }; + + pinctrl_rk8xx { + gpio-controller; + #gpio-cells = <0x02>; + + rk817_slppin_null { + pins = "gpio_slp"; + function = "pin_fun0"; + }; + + rk817_slppin_slp { + pins = "gpio_slp"; + function = "pin_fun1"; + phandle = <0x42>; + }; + + rk817_slppin_pwrdn { + pins = "gpio_slp"; + function = "pin_fun2"; + phandle = <0x44>; + }; + + rk817_slppin_rst { + pins = "gpio_slp"; + function = "pin_fun3"; + phandle = <0x45>; + }; + }; + + regulators { + + DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x7a120>; + regulator-max-microvolt = <0x149970>; + regulator-init-microvolt = <0xdbba0>; + regulator-ramp-delay = <0x1771>; + regulator-initial-mode = <0x02>; + regulator-name = "vdd_logic"; + phandle = <0x6f>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x7a120>; + regulator-max-microvolt = <0x149970>; + regulator-init-microvolt = <0xdbba0>; + regulator-ramp-delay = <0x1771>; + regulator-initial-mode = <0x02>; + regulator-name = "vdd_gpu"; + phandle = <0x71>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x02>; + regulator-name = "vcc_ddr"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x7a120>; + regulator-max-microvolt = <0x149970>; + regulator-init-microvolt = <0xdbba0>; + regulator-ramp-delay = <0x1771>; + regulator-initial-mode = <0x02>; + regulator-name = "vdd_npu"; + phandle = <0x6b>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + LDO_REG1 { + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <0xdbba0>; + regulator-max-microvolt = <0xdbba0>; + regulator-name = "vdda0v9_image"; + phandle = <0xb4>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0xdbba0>; + regulator-max-microvolt = <0xdbba0>; + regulator-name = "vdda_0v9"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0xdbba0>; + regulator-max-microvolt = <0xdbba0>; + regulator-name = "vdda0v9_pmu"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <0xdbba0>; + }; + }; + + LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x1b7740>; + regulator-max-microvolt = <0x1b7740>; + regulator-name = "vccio_acodec"; + phandle = <0x30>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x1b7740>; + regulator-max-microvolt = <0x325aa0>; + regulator-name = "vccio_sd"; + phandle = <0x31>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x325aa0>; + regulator-max-microvolt = <0x325aa0>; + regulator-name = "vcc3v3_pmu"; + phandle = <0x2f>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <0x325aa0>; + }; + }; + + LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x1b7740>; + regulator-max-microvolt = <0x1b7740>; + regulator-name = "vcca_1v8"; + phandle = <0x127>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x1b7740>; + regulator-max-microvolt = <0x1b7740>; + regulator-name = "vcca1v8_pmu"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <0x1b7740>; + }; + }; + + LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x1b7740>; + regulator-max-microvolt = <0x1b7740>; + regulator-name = "vcca1v8_image"; + phandle = <0xb5>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + DCDC_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x1b7740>; + regulator-max-microvolt = <0x1b7740>; + regulator-name = "vcc_1v8"; + phandle = <0x32>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_3v3"; + phandle = <0x33>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_sd"; + phandle = <0xc4>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + codec { + #sound-dai-cells = <0x00>; + compatible = "rockchip,rk809-codec\0rockchip,rk817-codec"; + clocks = <0x24 0x1a3>; + clock-names = "mclk"; + assigned-clocks = <0x24 0x1a3 0x24 0x1a6>; + assigned-clock-rates = <0xbb8000>; + assigned-clock-parents = <0x24 0x48 0x24 0x48>; + pinctrl-names = "default"; + pinctrl-0 = <0x47>; + hp-volume = <0x14>; + spk-volume = <0x03>; + mic-in-differential; + status = "okay"; + phandle = <0x158>; + }; + }; + }; + + serial@fdd50000 { + compatible = "rockchip,rk3568-uart\0snps,dw-apb-uart"; + reg = <0x00 0xfdd50000 0x00 0x100>; + interrupts = <0x00 0x74 0x04>; + clocks = <0x3a 0x0b 0x3a 0x2c>; + clock-names = "baudclk\0apb_pclk"; + dmas = <0x48 0x00 0x48 0x01>; + pinctrl-0 = <0x49>; + pinctrl-names = "default"; + reg-io-width = <0x04>; + reg-shift = <0x02>; + status = "disabled"; + }; + + pwm@fdd70000 { + compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm"; + reg = <0x00 0xfdd70000 0x00 0x10>; + interrupts = <0x00 0x52 0x04>; + clocks = <0x3a 0x0d 0x3a 0x30>; + clock-names = "pwm\0pclk"; + pinctrl-0 = <0x4a>; + pinctrl-names = "active"; + #pwm-cells = <0x03>; + status = "okay"; + }; + + pwm@fdd70010 { + compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm"; + reg = <0x00 0xfdd70010 0x00 0x10>; + interrupts = <0x00 0x52 0x04>; + clocks = <0x3a 0x0d 0x3a 0x30>; + clock-names = "pwm\0pclk"; + pinctrl-0 = <0x4b>; + pinctrl-names = "active"; + #pwm-cells = <0x03>; + status = "disabled"; + }; + + pwm@fdd70020 { + compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm"; + reg = <0x00 0xfdd70020 0x00 0x10>; + interrupts = <0x00 0x52 0x04>; + clocks = <0x3a 0x0d 0x3a 0x30>; + clock-names = "pwm\0pclk"; + pinctrl-0 = <0x4c>; + pinctrl-names = "active"; + #pwm-cells = <0x03>; + status = "disabled"; + }; + + pwm@fdd70030 { + compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm"; + reg = <0x00 0xfdd70030 0x00 0x10>; + interrupts = <0x00 0x52 0x04 0x00 0x56 0x04>; + clocks = <0x3a 0x0d 0x3a 0x30>; + clock-names = "pwm\0pclk"; + pinctrl-0 = <0x4d>; + pinctrl-names = "active"; + #pwm-cells = <0x03>; + status = "disabled"; + }; + + power-management@fdd90000 { + compatible = "rockchip,rk3568-pmu\0syscon\0simple-mfd"; + reg = <0x00 0xfdd90000 0x00 0x1000>; + + power-controller { + compatible = "rockchip,rk3568-power-controller"; + #power-domain-cells = <0x01>; + #address-cells = <0x01>; + #size-cells = <0x00>; + phandle = <0x26>; + + power-domain@6 { + reg = <0x06>; + clocks = <0x24 0x27 0x24 0x25 0x24 0x26>; + pm_qos = <0x4e>; + }; + + power-domain@7 { + reg = <0x07>; + clocks = <0x24 0x19 0x24 0x1a>; + pm_qos = <0x4f>; + #power-domain-cells = <0x00>; + }; + + power-domain@8 { + reg = <0x08>; + clocks = <0x24 0xcc 0x24 0xcd>; + pm_qos = <0x50 0x51 0x52>; + #power-domain-cells = <0x00>; + }; + + power-domain@9 { + reg = <0x09>; + clocks = <0x24 0xda 0x24 0xdb 0x24 0xdc>; + pm_qos = <0x53 0x54 0x55>; + #power-domain-cells = <0x00>; + }; + + power-domain@10 { + reg = <0x0a>; + clocks = <0x24 0xf1 0x24 0xf2>; + pm_qos = <0x56 0x57 0x58 0x59 0x5a 0x5b>; + #power-domain-cells = <0x00>; + }; + + power-domain@11 { + reg = <0x0b>; + clocks = <0x24 0xed>; + pm_qos = <0x5c>; + #power-domain-cells = <0x00>; + }; + + power-domain@13 { + clocks = <0x24 0x107>; + reg = <0x0d>; + pm_qos = <0x5d>; + #power-domain-cells = <0x00>; + }; + + power-domain@14 { + reg = <0x0e>; + clocks = <0x24 0x102>; + pm_qos = <0x5e 0x5f 0x60>; + #power-domain-cells = <0x00>; + }; + + power-domain@15 { + reg = <0x0f>; + clocks = <0x24 0x7f>; + pm_qos = <0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68>; + #power-domain-cells = <0x00>; + }; + }; + }; + + pvtm@fde00000 { + compatible = "rockchip,rk3568-core-pvtm"; + reg = <0x00 0xfde00000 0x00 0x100>; + #address-cells = <0x01>; + #size-cells = <0x00>; + + pvtm@0 { + reg = <0x00>; + clocks = <0x24 0x13 0x24 0x1c2>; + clock-names = "clk\0pclk"; + resets = <0x24 0x1a 0x24 0x19>; + reset-names = "rts\0rst-p"; + thermal-zone = "soc-thermal"; + }; + }; + + npu@fde40000 { + compatible = "rockchip,rk3568-rknpu\0rockchip,rknpu"; + reg = <0x00 0xfde40000 0x00 0x10000>; + interrupts = <0x00 0x97 0x04>; + clocks = <0x02 0x02 0x24 0x23 0x24 0x28 0x24 0x29>; + clock-names = "scmi_clk\0clk\0aclk\0hclk"; + assigned-clocks = <0x24 0x23>; + assigned-clock-rates = <0x23c34600>; + resets = <0x24 0x2b 0x24 0x2c>; + reset-names = "srst_a\0srst_h"; + power-domains = <0x26 0x06>; + operating-points-v2 = <0x69>; + iommus = <0x6a>; + status = "okay"; + rknpu-supply = <0x6b>; + }; + + npu-opp-table { + compatible = "operating-points-v2"; + mbist-vmin = <0xc96a8 0xdbba0 0xe7ef0>; + nvmem-cells = <0x6c 0x07 0x08 0x6d 0x0a 0x0b>; + nvmem-cell-names = "leakage\0pvtm\0mbist-vmin\0opp-info\0specification_serial_number\0remark_spec_serial_number"; + rockchip,supported-hw; + rockchip,max-volt = <0xf4240>; + rockchip,temp-hysteresis = <0x1388>; + rockchip,low-temp = <0x00>; + rockchip,low-temp-adjust-volt = <0x00 0x3e8 0xc350>; + rockchip,pvtm-voltage-sel = <0x00 0x14820 0x00 0x14821 0x153d8 0x01 0x153d9 0x16378 0x02 0x16379 0x186a0 0x03>; + rockchip,pvtm-ch = <0x00 0x05>; + phandle = <0x69>; + + opp-200000000 { + opp-supported-hw = <0xfb 0xffff>; + opp-hz = <0x00 0xbebc200>; + opp-microvolt = <0xcf850 0xcf850 0xf4240>; + }; + + opp-300000000 { + opp-supported-hw = <0xfb 0xffff>; + opp-hz = <0x00 0x11b3dc40>; + opp-microvolt = <0xcf850 0xcf850 0xf4240>; + }; + + opp-400000000 { + opp-supported-hw = <0xfb 0xffff>; + opp-hz = <0x00 0x17d78400>; + opp-microvolt = <0xcf850 0xcf850 0xf4240>; + }; + + opp-600000000 { + opp-supported-hw = <0xfb 0xffff>; + opp-hz = <0x00 0x23c34600>; + opp-microvolt = <0xcf850 0xcf850 0xf4240>; + }; + + opp-700000000 { + opp-supported-hw = <0xfb 0xffff>; + opp-hz = <0x00 0x29b92700>; + opp-microvolt = <0xd59f8 0xd59f8 0xf4240>; + opp-microvolt-L0 = <0xd59f8 0xd59f8 0xf4240>; + opp-microvolt-L1 = <0xcf850 0xcf850 0xf4240>; + opp-microvolt-L2 = <0xcf850 0xcf850 0xf4240>; + opp-microvolt-L3 = <0xcf850 0xcf850 0xf4240>; + }; + + opp-800000000 { + opp-supported-hw = <0xfb 0xffff>; + opp-hz = <0x00 0x2faf0800>; + opp-microvolt = <0xe1d48 0xe1d48 0xf4240>; + opp-microvolt-L0 = <0xe1d48 0xe1d48 0xf4240>; + opp-microvolt-L1 = <0xdbba0 0xdbba0 0xf4240>; + opp-microvolt-L2 = <0xd59f8 0xd59f8 0xf4240>; + opp-microvolt-L3 = <0xd59f8 0xd59f8 0xf4240>; + }; + + opp-900000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = <0x00 0x35a4e900>; + opp-microvolt = <0xee098 0xee098 0xf4240>; + opp-microvolt-L0 = <0xee098 0xee098 0xf4240>; + opp-microvolt-L1 = <0xe7ef0 0xe7ef0 0xf4240>; + opp-microvolt-L2 = <0xe1d48 0xe1d48 0xf4240>; + opp-microvolt-L3 = <0xdbba0 0xdbba0 0xf4240>; + }; + + opp-1000000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = <0x00 0x3b9aca00>; + opp-microvolt = <0xf4240 0xf4240 0xf4240>; + opp-microvolt-L0 = <0xf4240 0xf4240 0xf4240>; + opp-microvolt-L1 = <0xee098 0xee098 0xf4240>; + opp-microvolt-L2 = <0xe7ef0 0xe7ef0 0xf4240>; + opp-microvolt-L3 = <0xe1d48 0xe1d48 0xf4240>; + status = "disabled"; + }; + + opp-j-600000000 { + opp-supported-hw = <0x04 0xffff>; + opp-hz = <0x00 0x23c34600>; + opp-microvolt = <0xdbba0 0xdbba0 0xf4240>; + }; + + opp-m-900000000 { + opp-supported-hw = <0x02 0xffff>; + opp-hz = <0x00 0x35a4e900>; + opp-microvolt = <0xe1d48 0xe1d48 0xf4240>; + }; + }; + + bus-npu { + compatible = "rockchip,rk3568-bus"; + rockchip,busfreq-policy = "clkfreq"; + clocks = <0x02 0x02>; + clock-names = "bus"; + operating-points-v2 = <0x6e>; + status = "okay"; + bus-supply = <0x6f>; + pvtm-supply = <0x05>; + }; + + bus-npu-opp-table { + compatible = "operating-points-v2"; + opp-shared; + nvmem-cells = <0x07>; + nvmem-cell-names = "pvtm"; + rockchip,pvtm-voltage-sel = <0x00 0x14820 0x00 0x14821 0x16378 0x01 0x16379 0x186a0 0x02>; + rockchip,pvtm-ch = <0x00 0x05>; + phandle = <0x6e>; + + opp-700000000 { + opp-hz = <0x00 0x29b92700>; + opp-microvolt = <0xdbba0>; + opp-microvolt-L0 = <0xdbba0>; + opp-microvolt-L1 = <0xd59f8>; + opp-microvolt-L2 = <0xd59f8>; + }; + + opp-900000000 { + opp-hz = <0x00 0x35a4e900>; + opp-microvolt = <0xdbba0>; + }; + + opp-1000000000 { + opp-hz = <0x00 0x3b9aca00>; + opp-microvolt = <0xe7ef0>; + opp-microvolt-L0 = <0xe7ef0>; + opp-microvolt-L1 = <0xe1d48>; + opp-microvolt-L2 = <0xdbba0>; + }; + }; + + iommu@fde4b000 { + compatible = "rockchip,iommu-v2"; + reg = <0x00 0xfde4b000 0x00 0x40>; + interrupts = <0x00 0x97 0x04>; + interrupt-names = "rknpu_mmu"; + clocks = <0x24 0x28 0x24 0x29>; + clock-names = "aclk\0iface"; + power-domains = <0x26 0x06>; + #iommu-cells = <0x00>; + status = "okay"; + phandle = <0x6a>; + }; + + gpu@fde60000 { + compatible = "arm,mali-bifrost"; + reg = <0x00 0xfde60000 0x00 0x4000>; + interrupts = <0x00 0x27 0x04 0x00 0x29 0x04 0x00 0x28 0x04>; + interrupt-names = "GPU\0MMU\0JOB"; + upthreshold = <0x28>; + downdifferential = <0x0a>; + clocks = <0x02 0x01 0x24 0x1b>; + clock-names = "clk_mali\0clk_gpu"; + power-domains = <0x26 0x07>; + #cooling-cells = <0x02>; + operating-points-v2 = <0x70>; + status = "okay"; + mali-supply = <0x71>; + phandle = <0x11e>; + + power-model { + compatible = "simple-power-model"; + leakage-range = <0x05 0x0f>; + ls = <0xffffa23e 0x5927 0x00>; + static-coefficient = <0x186a0>; + dynamic-coefficient = <0x3b9>; + ts = <0xfffe56a6 0xf87a 0xfffffab5 0x14>; + thermal-zone = "gpu-thermal"; + }; + }; + + pvtm@fde80000 { + compatible = "rockchip,rk3568-gpu-pvtm"; + reg = <0x00 0xfde80000 0x00 0x100>; + #address-cells = <0x01>; + #size-cells = <0x00>; + + pvtm@1 { + reg = <0x01>; + clocks = <0x24 0x1e 0x24 0x1d>; + clock-names = "clk\0pclk"; + resets = <0x24 0x24 0x24 0x23>; + reset-names = "rts\0rst-p"; + thermal-zone = "gpu-thermal"; + }; + }; + + pvtm@fde90000 { + compatible = "rockchip,rk3568-npu-pvtm"; + reg = <0x00 0xfde90000 0x00 0x100>; + #address-cells = <0x01>; + #size-cells = <0x00>; + + pvtm@2 { + reg = <0x02>; + clocks = <0x24 0x2b 0x24 0x2a 0x24 0x25>; + clock-names = "clk\0pclk\0hclk"; + resets = <0x24 0x2e 0x24 0x2d>; + reset-names = "rts\0rst-p"; + thermal-zone = "soc-thermal"; + }; + }; + + vdpu@fdea0400 { + compatible = "rockchip,vpu-decoder-v2"; + reg = <0x00 0xfdea0400 0x00 0x400>; + interrupts = <0x00 0x8b 0x04>; + interrupt-names = "vdpu"; + clocks = <0x24 0xee 0x24 0xef>; + clock-names = "aclk_vcodec\0hclk_vcodec"; + resets = <0x24 0x11a 0x24 0x11b>; + reset-names = "video_a\0video_h"; + iommus = <0x72>; + power-domains = <0x26 0x0b>; + rockchip,srv = <0x73>; + rockchip,taskqueue-node = <0x00>; + rockchip,resetgroup-node = <0x00>; + status = "okay"; + }; + + iommu@fdea0800 { + compatible = "rockchip,iommu-v2"; + reg = <0x00 0xfdea0800 0x00 0x40>; + interrupts = <0x00 0x8a 0x04>; + interrupt-names = "vdpu_mmu"; + clock-names = "aclk\0iface"; + clocks = <0x24 0xee 0x24 0xef>; + power-domains = <0x26 0x0b>; + #iommu-cells = <0x00>; + status = "okay"; + phandle = <0x72>; + }; + + rk_rga@fdeb0000 { + compatible = "rockchip,rga2"; + reg = <0x00 0xfdeb0000 0x00 0x1000>; + interrupts = <0x00 0x5a 0x04>; + clocks = <0x24 0xf3 0x24 0xf4 0x24 0xf5>; + clock-names = "aclk_rga\0hclk_rga\0clk_rga"; + power-domains = <0x26 0x0a>; + status = "okay"; + }; + + ebc@fdec0000 { + compatible = "rockchip,rk3568-ebc-tcon"; + reg = <0x00 0xfdec0000 0x00 0x5000>; + interrupts = <0x00 0x11 0x04>; + clocks = <0x24 0xf9 0x24 0xfa>; + clock-names = "hclk\0dclk"; + power-domains = <0x26 0x0a>; + rockchip,grf = <0x3b>; + pinctrl-names = "default"; + pinctrl-0 = <0x74>; + status = "disabled"; + }; + + jpegd@fded0000 { + compatible = "rockchip,rkv-jpeg-decoder-v1"; + reg = <0x00 0xfded0000 0x00 0x400>; + interrupts = <0x00 0x3e 0x04>; + clocks = <0x24 0xfb 0x24 0xfc>; + clock-names = "aclk_vcodec\0hclk_vcodec"; + rockchip,disable-auto-freq; + resets = <0x24 0x12c 0x24 0x12d>; + reset-names = "video_a\0video_h"; + iommus = <0x75>; + rockchip,srv = <0x73>; + rockchip,taskqueue-node = <0x01>; + rockchip,resetgroup-node = <0x01>; + power-domains = <0x26 0x0a>; + status = "okay"; + }; + + iommu@fded0480 { + compatible = "rockchip,iommu-v2"; + reg = <0x00 0xfded0480 0x00 0x40>; + interrupts = <0x00 0x3d 0x04>; + interrupt-names = "jpegd_mmu"; + clock-names = "aclk\0iface"; + clocks = <0x24 0xfb 0x24 0xfc>; + power-domains = <0x26 0x0a>; + #iommu-cells = <0x00>; + status = "okay"; + phandle = <0x75>; + }; + + vepu@fdee0000 { + compatible = "rockchip,vpu-encoder-v2"; + reg = <0x00 0xfdee0000 0x00 0x400>; + interrupts = <0x00 0x40 0x04>; + clocks = <0x24 0xfd 0x24 0xfe>; + clock-names = "aclk_vcodec\0hclk_vcodec"; + rockchip,disable-auto-freq; + resets = <0x24 0x12e 0x24 0x12f>; + reset-names = "video_a\0video_h"; + iommus = <0x76>; + rockchip,srv = <0x73>; + rockchip,taskqueue-node = <0x02>; + rockchip,resetgroup-node = <0x02>; + power-domains = <0x26 0x0a>; + status = "okay"; + }; + + iommu@fdee0800 { + compatible = "rockchip,iommu-v2"; + reg = <0x00 0xfdee0800 0x00 0x40>; + interrupts = <0x00 0x3f 0x04>; + interrupt-names = "vepu_mmu"; + clocks = <0x24 0xfd 0x24 0xfe>; + clock-names = "aclk\0iface"; + power-domains = <0x26 0x0a>; + #iommu-cells = <0x00>; + status = "okay"; + phandle = <0x76>; + }; + + iep@fdef0000 { + compatible = "rockchip,iep-v2"; + reg = <0x00 0xfdef0000 0x00 0x500>; + interrupts = <0x00 0x38 0x04>; + clocks = <0x24 0xf6 0x24 0xf7 0x24 0xf8>; + clock-names = "aclk\0hclk\0sclk"; + resets = <0x24 0x127 0x24 0x128 0x24 0x129>; + reset-names = "rst_a\0rst_h\0rst_s"; + power-domains = <0x26 0x0a>; + rockchip,srv = <0x73>; + rockchip,taskqueue-node = <0x05>; + rockchip,resetgroup-node = <0x05>; + iommus = <0x77>; + status = "okay"; + }; + + iommu@fdef0800 { + compatible = "rockchip,iommu-v2"; + reg = <0x00 0xfdef0800 0x00 0x100>; + interrupts = <0x00 0x38 0x04>; + interrupt-names = "iep_mmu"; + clocks = <0x24 0xf6 0x24 0xf7>; + clock-names = "aclk\0iface"; + #iommu-cells = <0x00>; + power-domains = <0x26 0x0a>; + status = "okay"; + phandle = <0x77>; + }; + + eink@fdf00000 { + compatible = "rockchip,rk3568-eink-tcon"; + reg = <0x00 0xfdf00000 0x00 0x74>; + interrupts = <0x00 0xb2 0x04>; + clocks = <0x24 0xff 0x24 0x100>; + clock-names = "pclk\0hclk"; + status = "disabled"; + }; + + rkvenc@fdf40000 { + compatible = "rockchip,rkv-encoder-v1"; + reg = <0x00 0xfdf40000 0x00 0x400>; + interrupts = <0x00 0x8c 0x04>; + interrupt-names = "irq_enc"; + clocks = <0x24 0x103 0x24 0x104 0x24 0x105>; + clock-names = "aclk_vcodec\0hclk_vcodec\0clk_core"; + rockchip,normal-rates = <0x11b3dc40 0x00 0x11b3dc40>; + resets = <0x24 0x133 0x24 0x134 0x24 0x135>; + reset-names = "video_a\0video_h\0video_core"; + assigned-clocks = <0x24 0x103 0x24 0x105>; + assigned-clock-rates = <0x11b3dc40 0x11b3dc40>; + iommus = <0x78>; + node-name = "rkvenc"; + rockchip,srv = <0x73>; + rockchip,taskqueue-node = <0x03>; + rockchip,resetgroup-node = <0x03>; + power-domains = <0x26 0x0e>; + operating-points-v2 = <0x79>; + status = "okay"; + venc-supply = <0x6f>; + }; + + rkvenc-opp-table { + compatible = "operating-points-v2"; + nvmem-cells = <0x07>; + nvmem-cell-names = "pvtm"; + rockchip,pvtm-voltage-sel = <0x00 0x14820 0x00 0x14821 0x16378 0x01 0x16379 0x186a0 0x02>; + rockchip,pvtm-ch = <0x00 0x05>; + phandle = <0x79>; + + opp-297000000 { + opp-hz = <0x00 0x11b3dc40>; + opp-microvolt = <0xdbba0>; + opp-microvolt-L0 = <0xdbba0>; + opp-microvolt-L1 = <0xd59f8>; + opp-microvolt-L2 = <0xd59f8>; + }; + + opp-400000000 { + opp-hz = <0x00 0x17d78400>; + opp-microvolt = <0xe7ef0>; + opp-microvolt-L0 = <0xe7ef0>; + opp-microvolt-L1 = <0xe1d48>; + opp-microvolt-L2 = <0xdbba0>; + }; + }; + + iommu@fdf40f00 { + compatible = "rockchip,iommu-v2"; + reg = <0x00 0xfdf40f00 0x00 0x40 0x00 0xfdf40f40 0x00 0x40>; + interrupts = <0x00 0x8d 0x04 0x00 0x8e 0x04>; + interrupt-names = "rkvenc_mmu0\0rkvenc_mmu1"; + clocks = <0x24 0x103 0x24 0x104>; + clock-names = "aclk\0iface"; + rockchip,disable-mmu-reset; + rockchip,enable-cmd-retry; + #iommu-cells = <0x00>; + power-domains = <0x26 0x0e>; + status = "okay"; + phandle = <0x78>; + }; + + rkvdec@fdf80200 { + compatible = "rockchip,rkv-decoder-rk3568\0rockchip,rkv-decoder-v2"; + reg = <0x00 0xfdf80200 0x00 0x400 0x00 0xfdf80100 0x00 0x100>; + reg-names = "regs\0link"; + interrupts = <0x00 0x5b 0x04>; + interrupt-names = "irq_dec"; + clocks = <0x24 0x108 0x24 0x109 0x24 0x10a 0x24 0x10b 0x24 0x10c>; + clock-names = "aclk_vcodec\0hclk_vcodec\0clk_cabac\0clk_core\0clk_hevc_cabac"; + rockchip,normal-rates = <0x11b3dc40 0x00 0x11b3dc40 0x11b3dc40 0x23c34600>; + rockchip,advanced-rates = <0x179a7b00 0x00 0x179a7b00 0x179a7b00 0x23c34600>; + rockchip,default-max-load = <0x1fe000>; + resets = <0x24 0x142 0x24 0x143 0x24 0x144 0x24 0x145 0x24 0x146>; + assigned-clocks = <0x24 0x108 0x24 0x10a 0x24 0x10b 0x24 0x10c>; + assigned-clock-rates = <0x11b3dc40 0x11b3dc40 0x11b3dc40 0x11b3dc40>; + reset-names = "video_a\0video_h\0video_cabac\0video_core\0video_hevc_cabac"; + power-domains = <0x26 0x0d>; + operating-points-v2 = <0x7a>; + vdec-supply = <0x6f>; + iommus = <0x7b>; + rockchip,srv = <0x73>; + rockchip,taskqueue-node = <0x04>; + rockchip,resetgroup-node = <0x04>; + rockchip,sram = <0x7c>; + rockchip,rcb-iova = <0x10000000 0x10000>; + rockchip,rcb-min-width = <0x200>; + rockchip,task-capacity = <0x10>; + status = "okay"; + }; + + rkvdec-opp-table { + compatible = "operating-points-v2"; + nvmem-cells = <0x7d 0x07>; + nvmem-cell-names = "leakage\0pvtm"; + rockchip,leakage-voltage-sel = <0x01 0x50 0x00 0x51 0xfe 0x01>; + rockchip,pvtm-voltage-sel = <0x00 0x14820 0x00 0x14821 0x186a0 0x01>; + rockchip,pvtm-ch = <0x00 0x05>; + phandle = <0x7a>; + + opp-297000000 { + opp-hz = <0x00 0x11b3dc40>; + opp-microvolt = <0xdbba0>; + opp-microvolt-L0 = <0xdbba0>; + opp-microvolt-L1 = <0xd59f8>; + }; + + opp-400000000 { + opp-hz = <0x00 0x17d78400>; + opp-microvolt = <0xdbba0>; + }; + }; + + iommu@fdf80800 { + compatible = "rockchip,iommu-v2"; + reg = <0x00 0xfdf80800 0x00 0x40 0x00 0xfdf80840 0x00 0x40>; + interrupts = <0x00 0x5c 0x04>; + interrupt-names = "rkvdec_mmu"; + clocks = <0x24 0x108 0x24 0x109>; + clock-names = "aclk\0iface"; + power-domains = <0x26 0x0d>; + #iommu-cells = <0x00>; + status = "okay"; + phandle = <0x7b>; + }; + + mipi-csi2-hw@fdfb0000 { + compatible = "rockchip,rk3568-mipi-csi2-hw"; + reg = <0x00 0xfdfb0000 0x00 0x10000>; + reg-names = "csihost_regs"; + interrupts = <0x00 0x08 0x04 0x00 0x09 0x04>; + interrupt-names = "csi-intr1\0csi-intr2"; + clocks = <0x24 0xd5>; + clock-names = "pclk_csi2host"; + resets = <0x24 0xff>; + reset-names = "srst_csihost_p"; + status = "okay"; + phandle = <0x1e>; + }; + + rkcif@fdfe0000 { + compatible = "rockchip,rk3568-cif"; + reg = <0x00 0xfdfe0000 0x00 0x8000>; + reg-names = "cif_regs"; + interrupts = <0x00 0x92 0x04>; + interrupt-names = "cif-intr"; + clocks = <0x24 0xce 0x24 0xcf 0x24 0xd0 0x24 0xd1>; + clock-names = "aclk_cif\0hclk_cif\0dclk_cif\0iclk_cif_g"; + resets = <0x24 0xf7 0x24 0xf8 0x24 0xf9 0x24 0xfb 0x24 0xfa>; + reset-names = "rst_cif_a\0rst_cif_h\0rst_cif_d\0rst_cif_p\0rst_cif_i"; + assigned-clocks = <0x24 0xd0>; + assigned-clock-rates = <0x11e1a300>; + power-domains = <0x26 0x08>; + rockchip,grf = <0x3b>; + iommus = <0x7e>; + status = "disabled"; + phandle = <0x7f>; + }; + + iommu@fdfe0800 { + compatible = "rockchip,iommu-v2"; + reg = <0x00 0xfdfe0800 0x00 0x100>; + interrupts = <0x00 0x92 0x04>; + interrupt-names = "cif_mmu"; + clocks = <0x24 0xce 0x24 0xcf>; + clock-names = "aclk\0iface"; + power-domains = <0x26 0x08>; + rockchip,disable-mmu-reset; + #iommu-cells = <0x00>; + status = "disabled"; + phandle = <0x7e>; + }; + + rkcif_dvp { + compatible = "rockchip,rkcif-dvp"; + rockchip,hw = <0x7f>; + status = "disabled"; + phandle = <0x80>; + }; + + rkcif_dvp_sditf { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <0x80>; + status = "disabled"; + }; + + rkcif_mipi_lvds { + compatible = "rockchip,rkcif-mipi-lvds"; + rockchip,hw = <0x7f>; + status = "disabled"; + phandle = <0x81>; + }; + + rkcif_mipi_lvds_sditf { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <0x81>; + status = "disabled"; + }; + + rkisp@fdff0000 { + compatible = "rockchip,rk3568-rkisp"; + reg = <0x00 0xfdff0000 0x00 0x10000>; + interrupts = <0x00 0x39 0x04 0x00 0x3a 0x04 0x00 0x3c 0x04>; + interrupt-names = "mipi_irq\0mi_irq\0isp_irq"; + clocks = <0x24 0xd2 0x24 0xd3 0x24 0xd4>; + clock-names = "aclk_isp\0hclk_isp\0clk_isp"; + resets = <0x24 0xfd 0x24 0xfc>; + reset-names = "isp\0isp-h"; + rockchip,grf = <0x3b>; + power-domains = <0x26 0x08>; + iommus = <0x82>; + rockchip,iq-feature = <0x3fb 0xfffe67ff>; + status = "okay"; + phandle = <0x83>; + }; + + iommu@fdff1a00 { + compatible = "rockchip,iommu-v2"; + reg = <0x00 0xfdff1a00 0x00 0x100>; + interrupts = <0x00 0x3b 0x04>; + interrupt-names = "isp_mmu"; + clocks = <0x24 0xd2 0x24 0xd3>; + clock-names = "aclk\0iface"; + power-domains = <0x26 0x08>; + #iommu-cells = <0x00>; + rockchip,disable-mmu-reset; + status = "okay"; + phandle = <0x82>; + }; + + rkisp-vir0 { + compatible = "rockchip,rkisp-vir"; + rockchip,hw = <0x83>; + status = "okay"; + + port { + #address-cells = <0x01>; + #size-cells = <0x00>; + + endpoint@0 { + reg = <0x00>; + remote-endpoint = <0x84>; + phandle = <0x12f>; + }; + }; + }; + + rkisp-vir1 { + compatible = "rockchip,rkisp-vir"; + rockchip,hw = <0x83>; + status = "disabled"; + }; + + mmc@fe000000 { + compatible = "rockchip,rk3568-dw-mshc\0rockchip,rk3288-dw-mshc"; + reg = <0x00 0xfe000000 0x00 0x4000>; + interrupts = <0x00 0x64 0x04>; + clocks = <0x24 0xc1 0x24 0xc2 0x24 0x18e 0x24 0x18f>; + clock-names = "biu\0ciu\0ciu-drive\0ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <0x8f0d180>; + resets = <0x24 0xeb>; + reset-names = "reset"; + status = "okay"; + supports-sdio; + bus-width = <0x04>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <0x85>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <0x86 0x87 0x88>; + sd-uhs-sdr104; + }; + + uio@fe010000 { + compatible = "rockchip,uio-gmac"; + reg = <0x00 0xfe010000 0x00 0x10000>; + rockchip,ethernet = <0x89>; + status = "disabled"; + }; + + ethernet@fe010000 { + compatible = "rockchip,rk3568-gmac\0snps,dwmac-4.20a"; + reg = <0x00 0xfe010000 0x00 0x10000>; + interrupts = <0x00 0x20 0x04 0x00 0x1d 0x04>; + interrupt-names = "macirq\0eth_wake_irq"; + clocks = <0x24 0x186 0x24 0x189 0x24 0x189 0x24 0xc7 0x24 0xc3 0x24 0xc4 0x24 0x189 0x24 0xc8 0x24 0xac 0x24 0xab>; + clock-names = "stmmaceth\0mac_clk_rx\0mac_clk_tx\0clk_mac_refout\0aclk_mac\0pclk_mac\0clk_mac_speed\0ptp_ref\0pclk_xpcs\0clk_xpcs_eee"; + resets = <0x24 0xec>; + reset-names = "stmmaceth"; + rockchip,grf = <0x3b>; + snps,axi-config = <0x8a>; + snps,mixed-burst; + snps,mtl-rx-config = <0x8b>; + snps,mtl-tx-config = <0x8c>; + snps,tso; + status = "okay"; + phy-mode = "rgmii"; + clock_in_out = "output"; + snps,reset-gpio = <0x8d 0x19 0x01>; + snps,reset-active-low; + snps,reset-delays-us = <0x00 0x4e20 0x186a0>; + assigned-clocks = <0x24 0x189 0x24 0x186>; + assigned-clock-parents = <0x24 0x187 0x24 0xc5>; + assigned-clock-rates = <0x00 0x7735940>; + pinctrl-names = "default"; + pinctrl-0 = <0x8e 0x8f 0x90 0x91 0x92>; + tx_delay = <0x37>; + rx_delay = <0x0f>; + phy-handle = <0x93>; + phandle = <0x89>; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <0x01>; + #size-cells = <0x00>; + + phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x00>; + phandle = <0x93>; + }; + }; + + stmmac-axi-config { + snps,blen = <0x00 0x00 0x00 0x00 0x10 0x08 0x04>; + snps,rd_osr_lmt = <0x08>; + snps,wr_osr_lmt = <0x04>; + phandle = <0x8a>; + }; + + rx-queues-config { + snps,rx-queues-to-use = <0x01>; + phandle = <0x8b>; + + queue0 { + }; + }; + + tx-queues-config { + snps,tx-queues-to-use = <0x01>; + phandle = <0x8c>; + + queue0 { + }; + }; + }; + + vop@fe040000 { + compatible = "rockchip,rk3568-vop"; + reg = <0x00 0xfe040000 0x00 0x3000 0x00 0xfe044000 0x00 0x1000>; + reg-names = "regs\0gamma_lut"; + interrupts = <0x00 0x94 0x04>; + clocks = <0x24 0xdd 0x24 0xde 0x24 0xdf 0x24 0xe0 0x24 0xe1>; + clock-names = "aclk_vop\0hclk_vop\0dclk_vp0\0dclk_vp1\0dclk_vp2"; + rockchip,aclk-normal-mode-rates = <0x179a7b00>; + rockchip,aclk-advanced-mode-rates = <0x1dcd6500>; + operating-points-v2 = <0x94>; + iommus = <0x95>; + power-domains = <0x26 0x09>; + rockchip,grf = <0x3b>; + status = "okay"; + vop-supply = <0x6f>; + assigned-clocks = <0x24 0xdf 0x24 0xe0>; + assigned-clock-parents = <0x3a 0x02 0x24 0x05>; + disable-afbc-win; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + phandle = <0x11>; + + port@0 { + reg = <0x00>; + #address-cells = <0x01>; + #size-cells = <0x00>; + + endpoint@0 { + reg = <0x00>; + remote-endpoint = <0x96>; + phandle = <0xa3>; + }; + + endpoint@1 { + reg = <0x01>; + remote-endpoint = <0x97>; + phandle = <0x14>; + }; + + endpoint@2 { + reg = <0x02>; + remote-endpoint = <0x98>; + phandle = <0x15>; + }; + + endpoint@3 { + reg = <0x03>; + remote-endpoint = <0x99>; + phandle = <0x16>; + }; + }; + + port@1 { + reg = <0x01>; + #address-cells = <0x01>; + #size-cells = <0x00>; + + endpoint@0 { + reg = <0x00>; + remote-endpoint = <0x9a>; + phandle = <0x13>; + }; + + endpoint@1 { + reg = <0x01>; + remote-endpoint = <0x9b>; + phandle = <0xab>; + }; + + endpoint@2 { + reg = <0x02>; + remote-endpoint = <0x9c>; + phandle = <0xb8>; + }; + + endpoint@3 { + reg = <0x03>; + remote-endpoint = <0x9d>; + phandle = <0xb6>; + }; + + endpoint@4 { + reg = <0x04>; + remote-endpoint = <0x9e>; + phandle = <0x17>; + }; + + endpoint@5 { + reg = <0x05>; + remote-endpoint = <0x9f>; + phandle = <0x38>; + }; + }; + + port@2 { + reg = <0x02>; + #address-cells = <0x01>; + #size-cells = <0x00>; + + endpoint@0 { + reg = <0x00>; + remote-endpoint = <0xa0>; + phandle = <0x35>; + }; + + endpoint@1 { + reg = <0x01>; + remote-endpoint = <0xa1>; + phandle = <0x18>; + }; + + endpoint@2 { + reg = <0x02>; + remote-endpoint = <0xa2>; + phandle = <0x39>; + }; + }; + }; + }; + + vop-opp-table { + compatible = "operating-points-v2"; + nvmem-cells = <0x7d 0x07>; + nvmem-cell-names = "leakage\0pvtm"; + rockchip,leakage-voltage-sel = <0x01 0x50 0x00 0x51 0xfe 0x01>; + rockchip,pvtm-voltage-sel = <0x00 0x14820 0x00 0x14821 0x186a0 0x01>; + rockchip,pvtm-ch = <0x00 0x05>; + phandle = <0x94>; + + opp-396000000 { + opp-hz = <0x00 0x179a7b00>; + opp-microvolt = <0xdbba0 0xdbba0 0xf4240>; + opp-microvolt-L0 = <0xdbba0 0xdbba0 0xf4240>; + opp-microvolt-L1 = <0xd59f8 0xd59f8 0xf4240>; + }; + + opp-500000000 { + opp-hz = <0x00 0x1dcd6500>; + opp-microvolt = <0xe1d48 0xe1d48 0xf4240>; + opp-microvolt-L0 = <0xe1d48 0xe1d48 0xf4240>; + opp-microvolt-L1 = <0xdbba0 0xdbba0 0xf4240>; + }; + }; + + iommu@fe043e00 { + compatible = "rockchip,iommu-v2"; + reg = <0x00 0xfe043e00 0x00 0x100 0x00 0xfe043f00 0x00 0x100>; + interrupts = <0x00 0x94 0x04>; + interrupt-names = "vop_mmu"; + clocks = <0x24 0xdd 0x24 0xde>; + clock-names = "aclk\0iface"; + #iommu-cells = <0x00>; + rockchip,disable-device-link-resume; + status = "okay"; + phandle = <0x95>; + }; + + dsi@fe060000 { + compatible = "rockchip,rk3568-mipi-dsi"; + reg = <0x00 0xfe060000 0x00 0x10000>; + interrupts = <0x00 0x44 0x04>; + clock-names = "pclk\0hclk"; + clocks = <0x24 0xe8 0x24 0xda>; + phy-names = "dphy"; + phys = <0x34>; + power-domains = <0x26 0x09>; + reset-names = "apb"; + resets = <0x24 0x110>; + rockchip,grf = <0x3b>; + #address-cells = <0x01>; + #size-cells = <0x00>; + status = "okay"; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + #address-cells = <0x01>; + #size-cells = <0x00>; + + endpoint@0 { + reg = <0x00>; + remote-endpoint = <0xa3>; + status = "disabled"; + phandle = <0x96>; + }; + + endpoint@1 { + reg = <0x01>; + remote-endpoint = <0x13>; + status = "okay"; + phandle = <0x9a>; + }; + }; + + port@1 { + reg = <0x01>; + + endpoint { + remote-endpoint = <0xa4>; + phandle = <0xaa>; + }; + }; + }; + + panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0x00>; + backlight = <0xa5>; + reset-delay-ms = <0x64>; + enable-delay-ms = <0x78>; + prepare-delay-ms = <0x02>; + unprepare-delay-ms = <0x14>; + disable-delay-ms = <0x32>; + dsi,flags = <0xa03>; + dsi,format = <0x00>; + dsi,lanes = <0x04>; + panel-init-sequence = <0x5640111 0x390004ff 0x98810315 0x20100 0x15000202 0x150002 0x3721500 0x2040015 0x20500 0x15000206 0x9150002 0x7001500 0x2080015 0x20901 0x1500020a 0x150002 0xb001500 0x20c0115 0x20d00 0x1500020e 0x150002 0xf001500 0x2100015 0x21100 0x15000212 0x150002 0x13001500 0x2140015 0x21500 0x15000216 0x150002 0x17001500 0x2180015 0x21900 0x1500021a 0x150002 0x1b001500 0x21c0015 0x21d00 0x1500021e 0x40150002 0x1f801500 0x2200515 0x22102 0x15000222 0x150002 0x23001500 0x2240015 0x22500 0x15000226 0x150002 0x27001500 0x2283315 0x22902 0x1500022a 0x150002 0x2b001500 0x22c0015 0x22d00 0x1500022e 0x150002 0x2f001500 0x2300015 0x23100 0x15000232 0x150002 0x33001500 0x2340415 0x23500 0x15000236 0x150002 0x37001500 0x2383c15 0x23900 0x1500023a 0x40150002 0x3b401500 0x23c0015 0x23d00 0x1500023e 0x150002 0x3f001500 0x2400015 0x24100 0x15000242 0x150002 0x43001500 0x2440015 0x25001 0x15000251 0x23150002 0x52451500 0x2536715 0x25489 0x15000255 0xab150002 0x56011500 0x2572315 0x25845 0x15000259 0x67150002 0x5a891500 0x25bab15 0x25ccd 0x1500025d 0xef150002 0x5e111500 0x25f0115 0x26000 0x15000261 0x15150002 0x62141500 0x2630e15 0x2640f 0x15000265 0xc150002 0x660d1500 0x2670615 0x26802 0x15000269 0x2150002 0x6a021500 0x26b0215 0x26c02 0x1500026d 0x2150002 0x6e071500 0x26f0215 0x27002 0x15000271 0x2150002 0x72021500 0x2730215 0x27402 0x15000275 0x1150002 0x76001500 0x2771415 0x27815 0x15000279 0xe150002 0x7a0f1500 0x27b0c15 0x27c0d 0x1500027d 0x6150002 0x7e021500 0x27f0215 0x28002 0x15000281 0x2150002 0x82021500 0x2830215 0x28407 0x15000285 0x2150002 0x86021500 0x2870215 0x28802 0x15000289 0x2150002 0x8a023900 0x4ff9881 0x4150002 0x6c151500 0x26e2a15 0x26f33 0x1500023a 0x94150002 0x8d1a1500 0x287ba15 0x22676 0x150002b2 0xd1150002 0xb5063900 0x4ff9881 0x1150002 0x220a1500 0x2310015 0x24013 0x15000253 0x84150002 0x558f1500 0x250ae15 0x251ae 0x15000260 0x28150002 0xa00f1500 0x2a11b15 0x2a228 0x150002a3 0x12150002 0xa4151500 0x2a52815 0x2a61b 0x150002a7 0x1e150002 0xa8791500 0x2a91b15 0x2aa27 0x150002ab 0x69150002 0xac191500 0x2ad1815 0x2ae4c 0x150002af 0x21150002 0xb0281500 0x2b15215 0x2b265 0x150002c0 0x4150002 0xc11b1500 0x2c22715 0x2c313 0x150002c4 0x15150002 0xc5281500 0x2c61c15 0x2c71e 0x150002c8 0x79150002 0xc91a1500 0x2ca2715 0x2cb69 0x150002cc 0x1a150002 0xcd181500 0x2ce4c15 0x2cf21 0x150002d0 0x27150002 0xd1521500 0x2d26515 0x2d33f 0x390004ff 0x98810005 0x32012915 0x23500>; + panel-exit-sequence = <0x5320128 0x5c80110>; + power-supply = <0xa6>; + init-delay-ms = <0x14>; + pinctrl-names = "default"; + pinctrl-0 = <0xa7>; + enable-gpios = <0xa8 0x0d 0x00>; + width-mm = <0x44>; + height-mm = <0x79>; + pnel-type = <0x05>; + + display-timings { + native-mode = <0xa9>; + + timing0 { + clock-frequency = <0x47868c0>; + hactive = <0x2d0>; + vactive = <0x500>; + hfront-porch = <0x28>; + hsync-len = <0x0a>; + hback-porch = <0x28>; + vfront-porch = <0x0a>; + vsync-len = <0x24>; + vback-porch = <0x0f>; + hsync-active = <0x00>; + vsync-active = <0x00>; + de-active = <0x00>; + pixelclk-active = <0x00>; + phandle = <0xa9>; + }; + }; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint { + remote-endpoint = <0xaa>; + phandle = <0xa4>; + }; + }; + }; + }; + }; + + dsi@fe070000 { + compatible = "rockchip,rk3568-mipi-dsi"; + reg = <0x00 0xfe070000 0x00 0x10000>; + interrupts = <0x00 0x45 0x04>; + clock-names = "pclk\0hclk"; + clocks = <0x24 0xe9 0x24 0xda>; + phy-names = "dphy"; + phys = <0x37>; + power-domains = <0x26 0x09>; + reset-names = "apb"; + resets = <0x24 0x111>; + rockchip,grf = <0x3b>; + #address-cells = <0x01>; + #size-cells = <0x00>; + status = "disabled"; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + #address-cells = <0x01>; + #size-cells = <0x00>; + + endpoint@0 { + reg = <0x00>; + remote-endpoint = <0x14>; + status = "disabled"; + phandle = <0x97>; + }; + + endpoint@1 { + reg = <0x01>; + remote-endpoint = <0xab>; + status = "disabled"; + phandle = <0x9b>; + }; + }; + + port@1 { + reg = <0x01>; + + endpoint { + remote-endpoint = <0xac>; + phandle = <0xb0>; + }; + }; + }; + + panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0x00>; + backlight = <0xad>; + reset-delay-ms = <0x3c>; + enable-delay-ms = <0x3c>; + prepare-delay-ms = <0x3c>; + unprepare-delay-ms = <0x3c>; + disable-delay-ms = <0x3c>; + dsi,flags = <0xa03>; + dsi,format = <0x00>; + dsi,lanes = <0x04>; + panel-init-sequence = [23 00 02 fe 21 23 00 02 04 00 23 00 02 00 64 23 00 02 2a 00 23 00 02 26 64 23 00 02 54 00 23 00 02 50 64 23 00 02 7b 00 23 00 02 77 64 23 00 02 a2 00 23 00 02 9d 64 23 00 02 c9 00 23 00 02 c5 64 23 00 02 01 71 23 00 02 27 71 23 00 02 51 71 23 00 02 78 71 23 00 02 9e 71 23 00 02 c6 71 23 00 02 02 89 23 00 02 28 89 23 00 02 52 89 23 00 02 79 89 23 00 02 9f 89 23 00 02 c7 89 23 00 02 03 9e 23 00 02 29 9e 23 00 02 53 9e 23 00 02 7a 9e 23 00 02 a0 9e 23 00 02 c8 9e 23 00 02 09 00 23 00 02 05 b0 23 00 02 31 00 23 00 02 2b b0 23 00 02 5a 00 23 00 02 55 b0 23 00 02 80 00 23 00 02 7c b0 23 00 02 a7 00 23 00 02 a3 b0 23 00 02 ce 00 23 00 02 ca b0 23 00 02 06 c0 23 00 02 2d c0 23 00 02 56 c0 23 00 02 7d c0 23 00 02 a4 c0 23 00 02 cb c0 23 00 02 07 cf 23 00 02 2f cf 23 00 02 58 cf 23 00 02 7e cf 23 00 02 a5 cf 23 00 02 cc cf 23 00 02 08 dd 23 00 02 30 dd 23 00 02 59 dd 23 00 02 7f dd 23 00 02 a6 dd 23 00 02 cd dd 23 00 02 0e 15 23 00 02 0a e9 23 00 02 36 15 23 00 02 32 e9 23 00 02 5f 15 23 00 02 5b e9 23 00 02 85 15 23 00 02 81 e9 23 00 02 ad 15 23 00 02 a9 e9 23 00 02 d3 15 23 00 02 cf e9 23 00 02 0b 14 23 00 02 33 14 23 00 02 5c 14 23 00 02 82 14 23 00 02 aa 14 23 00 02 d0 14 23 00 02 0c 36 23 00 02 34 36 23 00 02 5d 36 23 00 02 83 36 23 00 02 ab 36 23 00 02 d1 36 23 00 02 0d 6b 23 00 02 35 6b 23 00 02 5e 6b 23 00 02 84 6b 23 00 02 ac 6b 23 00 02 d2 6b 23 00 02 13 5a 23 00 02 0f 94 23 00 02 3b 5a 23 00 02 37 94 23 00 02 64 5a 23 00 02 60 94 23 00 02 8a 5a 23 00 02 86 94 23 00 02 b2 5a 23 00 02 ae 94 23 00 02 d8 5a 23 00 02 d4 94 23 00 02 10 d1 23 00 02 38 d1 23 00 02 61 d1 23 00 02 87 d1 23 00 02 af d1 23 00 02 d5 d1 23 00 02 11 04 23 00 02 39 04 23 00 02 62 04 23 00 02 88 04 23 00 02 b0 04 23 00 02 d6 04 23 00 02 12 05 23 00 02 3a 05 23 00 02 63 05 23 00 02 89 05 23 00 02 b1 05 23 00 02 d7 05 23 00 02 18 aa 23 00 02 14 36 23 00 02 42 aa 23 00 02 3d 36 23 00 02 69 aa 23 00 02 65 36 23 00 02 8f aa 23 00 02 8b 36 23 00 02 b7 aa 23 00 02 b3 36 23 00 02 dd aa 23 00 02 d9 36 23 00 02 15 74 23 00 02 3f 74 23 00 02 66 74 23 00 02 8c 74 23 00 02 b4 74 23 00 02 da 74 23 00 02 16 9f 23 00 02 40 9f 23 00 02 67 9f 23 00 02 8d 9f 23 00 02 b5 9f 23 00 02 db 9f 23 00 02 17 dc 23 00 02 41 dc 23 00 02 68 dc 23 00 02 8e dc 23 00 02 b6 dc 23 00 02 dc dc 23 00 02 1d ff 23 00 02 19 03 23 00 02 47 ff 23 00 02 43 03 23 00 02 6e ff 23 00 02 6a 03 23 00 02 94 ff 23 00 02 90 03 23 00 02 bc ff 23 00 02 b8 03 23 00 02 e2 ff 23 00 02 de 03 23 00 02 1a 35 23 00 02 44 35 23 00 02 6b 35 23 00 02 91 35 23 00 02 b9 35 23 00 02 df 35 23 00 02 1b 45 23 00 02 45 45 23 00 02 6c 45 23 00 02 92 45 23 00 02 ba 45 23 00 02 e0 45 23 00 02 1c 55 23 00 02 46 55 23 00 02 6d 55 23 00 02 93 55 23 00 02 bb 55 23 00 02 e1 55 23 00 02 22 ff 23 00 02 1e 68 23 00 02 4c ff 23 00 02 48 68 23 00 02 73 ff 23 00 02 6f 68 23 00 02 99 ff 23 00 02 95 68 23 00 02 c1 ff 23 00 02 bd 68 23 00 02 e7 ff 23 00 02 e3 68 23 00 02 1f 7e 23 00 02 49 7e 23 00 02 70 7e 23 00 02 96 7e 23 00 02 be 7e 23 00 02 e4 7e 23 00 02 20 97 23 00 02 4a 97 23 00 02 71 97 23 00 02 97 97 23 00 02 bf 97 23 00 02 e5 97 23 00 02 21 b5 23 00 02 4b b5 23 00 02 72 b5 23 00 02 98 b5 23 00 02 c0 b5 23 00 02 e6 b5 23 00 02 25 f0 23 00 02 23 e8 23 00 02 4f f0 23 00 02 4d e8 23 00 02 76 f0 23 00 02 74 e8 23 00 02 9c f0 23 00 02 9a e8 23 00 02 c4 f0 23 00 02 c2 e8 23 00 02 ea f0 23 00 02 e8 e8 23 00 02 24 ff 23 00 02 4e ff 23 00 02 75 ff 23 00 02 9b ff 23 00 02 c3 ff 23 00 02 e9 ff 23 00 02 fe 3d 23 00 02 00 04 23 00 02 fe 23 23 00 02 08 82 23 00 02 0a 00 23 00 02 0b 00 23 00 02 0c 01 23 00 02 16 00 23 00 02 18 02 23 00 02 1b 04 23 00 02 19 04 23 00 02 1c 81 23 00 02 1f 00 23 00 02 20 03 23 00 02 23 04 23 00 02 21 01 23 00 02 54 63 23 00 02 55 54 23 00 02 6e 45 23 00 02 6d 36 23 00 02 fe 3d 23 00 02 55 78 23 00 02 fe 20 23 00 02 26 30 23 00 02 fe 3d 23 00 02 20 71 23 00 02 50 8f 23 00 02 51 8f 23 00 02 fe 00 23 00 02 35 00 05 78 01 11 05 1e 01 29]; + panel-exit-sequence = <0x5000128 0x5000110>; + power-supply = <0xae>; + + display-timings { + native-mode = <0xaf>; + + timing0 { + clock-frequency = <0x7de2900>; + hactive = <0x438>; + vactive = <0x780>; + hfront-porch = <0x0f>; + hsync-len = <0x02>; + hback-porch = <0x1e>; + vfront-porch = <0x0f>; + vsync-len = <0x02>; + vback-porch = <0x0f>; + hsync-active = <0x00>; + vsync-active = <0x00>; + de-active = <0x00>; + pixelclk-active = <0x01>; + phandle = <0xaf>; + }; + }; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint { + remote-endpoint = <0xb0>; + phandle = <0xac>; + }; + }; + }; + }; + }; + + hdmi@fe0a0000 { + compatible = "rockchip,rk3568-dw-hdmi"; + reg = <0x00 0xfe0a0000 0x00 0x20000>; + interrupts = <0x00 0x2d 0x04>; + clocks = <0x24 0xe6 0x24 0xe7 0x24 0x193 0x3a 0x02 0x24 0xde>; + clock-names = "iahb\0isfr\0cec\0ref\0hclk"; + pinctrl-names = "default"; + pinctrl-0 = <0xb1 0xb2 0xb3>; + power-domains = <0x26 0x09>; + reg-io-width = <0x04>; + rockchip,grf = <0x3b>; + #sound-dai-cells = <0x00>; + status = "okay"; + avdd-0v9-supply = <0xb4>; + avdd-1v8-supply = <0xb5>; + rockchip,phy-table = <0x58834d4 0x8009 0x00 0x270 0x9d5b340 0x800b 0x00 0x26d 0xb1069a8 0x800b 0x00 0x1ed 0x11b3dc40 0x800b 0x00 0x1ad 0x2367b880 0x8029 0x00 0x88 0x00 0x00 0x00 0x00>; + phandle = <0x1c>; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + #address-cells = <0x01>; + #size-cells = <0x00>; + + endpoint@0 { + reg = <0x00>; + remote-endpoint = <0x16>; + status = "okay"; + phandle = <0x99>; + }; + + endpoint@1 { + reg = <0x01>; + remote-endpoint = <0xb6>; + status = "disabled"; + phandle = <0x9d>; + }; + }; + }; + }; + + edp@fe0c0000 { + compatible = "rockchip,rk3568-edp"; + reg = <0x00 0xfe0c0000 0x00 0x10000>; + interrupts = <0x00 0x12 0x04>; + clocks = <0x3a 0x29 0x24 0xea 0x24 0xeb 0x24 0xda>; + clock-names = "dp\0pclk\0spdif\0hclk"; + resets = <0x24 0x113 0x24 0x112>; + reset-names = "dp\0apb"; + phys = <0xb7>; + phy-names = "dp"; + power-domains = <0x26 0x09>; + status = "disabled"; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + #address-cells = <0x01>; + #size-cells = <0x00>; + + endpoint@0 { + reg = <0x00>; + remote-endpoint = <0x15>; + status = "disabled"; + phandle = <0x98>; + }; + + endpoint@1 { + reg = <0x01>; + remote-endpoint = <0xb8>; + status = "disabled"; + phandle = <0x9c>; + }; + }; + }; + }; + + nocp-cpu@fe102000 { + compatible = "rockchip,rk3568-nocp"; + reg = <0x00 0xfe102000 0x00 0x400>; + phandle = <0xba>; + }; + + nocp-gpu-vpu-rga-venc@fe102400 { + compatible = "rockchip,rk3568-nocp"; + reg = <0x00 0xfe102400 0x00 0x400>; + }; + + nocp-vdec@fe102800 { + compatible = "rockchip,rk3568-nocp"; + reg = <0x00 0xfe102800 0x00 0x400>; + }; + + nocp-vi-usb-peri-pipe@fe102c00 { + compatible = "rockchip,rk3568-nocp"; + reg = <0x00 0xfe102c00 0x00 0x400>; + }; + + nocp-vo@fe103000 { + compatible = "rockchip,rk3568-nocp"; + reg = <0x00 0xfe103000 0x00 0x400>; + }; + + qos@fe128000 { + compatible = "rockchip,rk3568-qos\0syscon"; + reg = <0x00 0xfe128000 0x00 0x20>; + phandle = <0x4f>; + }; + + qos@fe138080 { + compatible = "rockchip,rk3568-qos\0syscon"; + reg = <0x00 0xfe138080 0x00 0x20>; + phandle = <0x5e>; + }; + + qos@fe138100 { + compatible = "rockchip,rk3568-qos\0syscon"; + reg = <0x00 0xfe138100 0x00 0x20>; + phandle = <0x5f>; + }; + + qos@fe138180 { + compatible = "rockchip,rk3568-qos\0syscon"; + reg = <0x00 0xfe138180 0x00 0x20>; + phandle = <0x60>; + }; + + qos@fe148000 { + compatible = "rockchip,rk3568-qos\0syscon"; + reg = <0x00 0xfe148000 0x00 0x20>; + phandle = <0x50>; + }; + + qos@fe148080 { + compatible = "rockchip,rk3568-qos\0syscon"; + reg = <0x00 0xfe148080 0x00 0x20>; + phandle = <0x51>; + }; + + qos@fe148100 { + compatible = "rockchip,rk3568-qos\0syscon"; + reg = <0x00 0xfe148100 0x00 0x20>; + phandle = <0x52>; + }; + + qos@fe150000 { + compatible = "rockchip,rk3568-qos\0syscon"; + reg = <0x00 0xfe150000 0x00 0x20>; + phandle = <0x5c>; + }; + + qos@fe158000 { + compatible = "rockchip,rk3568-qos\0syscon"; + reg = <0x00 0xfe158000 0x00 0x20>; + phandle = <0x56>; + }; + + qos@fe158100 { + compatible = "rockchip,rk3568-qos\0syscon"; + reg = <0x00 0xfe158100 0x00 0x20>; + phandle = <0x57>; + }; + + qos@fe158180 { + compatible = "rockchip,rk3568-qos\0syscon"; + reg = <0x00 0xfe158180 0x00 0x20>; + phandle = <0x58>; + }; + + qos@fe158200 { + compatible = "rockchip,rk3568-qos\0syscon"; + reg = <0x00 0xfe158200 0x00 0x20>; + phandle = <0x59>; + }; + + qos@fe158280 { + compatible = "rockchip,rk3568-qos\0syscon"; + reg = <0x00 0xfe158280 0x00 0x20>; + phandle = <0x5a>; + }; + + qos@fe158300 { + compatible = "rockchip,rk3568-qos\0syscon"; + reg = <0x00 0xfe158300 0x00 0x20>; + phandle = <0x5b>; + }; + + qos@fe180000 { + compatible = "rockchip,rk3568-qos\0syscon"; + reg = <0x00 0xfe180000 0x00 0x20>; + phandle = <0x4e>; + }; + + qos@fe190000 { + compatible = "rockchip,rk3568-qos\0syscon"; + reg = <0x00 0xfe190000 0x00 0x20>; + phandle = <0x61>; + }; + + qos@fe190280 { + compatible = "rockchip,rk3568-qos\0syscon"; + reg = <0x00 0xfe190280 0x00 0x20>; + phandle = <0x65>; + }; + + qos@fe190300 { + compatible = "rockchip,rk3568-qos\0syscon"; + reg = <0x00 0xfe190300 0x00 0x20>; + phandle = <0x66>; + }; + + qos@fe190380 { + compatible = "rockchip,rk3568-qos\0syscon"; + reg = <0x00 0xfe190380 0x00 0x20>; + phandle = <0x67>; + }; + + qos@fe190400 { + compatible = "rockchip,rk3568-qos\0syscon"; + reg = <0x00 0xfe190400 0x00 0x20>; + phandle = <0x68>; + }; + + qos@fe198000 { + compatible = "rockchip,rk3568-qos\0syscon"; + reg = <0x00 0xfe198000 0x00 0x20>; + phandle = <0x5d>; + }; + + qos@fe1a8000 { + compatible = "rockchip,rk3568-qos\0syscon"; + reg = <0x00 0xfe1a8000 0x00 0x20>; + phandle = <0x53>; + }; + + qos@fe1a8080 { + compatible = "rockchip,rk3568-qos\0syscon"; + reg = <0x00 0xfe1a8080 0x00 0x20>; + phandle = <0x54>; + }; + + qos@fe1a8100 { + compatible = "rockchip,rk3568-qos\0syscon"; + reg = <0x00 0xfe1a8100 0x00 0x20>; + phandle = <0x55>; + }; + + dfi@fe230000 { + reg = <0x00 0xfe230000 0x00 0x400>; + compatible = "rockchip,rk3568-dfi"; + rockchip,pmugrf = <0x3c>; + status = "okay"; + phandle = <0xb9>; + }; + + dmc { + compatible = "rockchip,rk3568-dmc"; + interrupts = <0x00 0x0a 0x04>; + interrupt-names = "complete"; + devfreq-events = <0xb9 0xba>; + clocks = <0x02 0x03>; + clock-names = "dmc_clk"; + operating-points-v2 = <0xbb>; + vop-bw-dmc-freq = <0x00 0x11e 0x4f1a0 0x11f 0x1869f 0x80e80>; + vop-frame-bw-dmc-freq = <0x00 0x26c 0x4f1a0 0x26d 0x1869f 0xbe6e0>; + cpu-bw-dmc-freq = <0x00 0x15e 0x4f1a0 0x15f 0x190 0x80e80 0x191 0x1869f 0xbe6e0>; + upthreshold = <0x28>; + downdifferential = <0x14>; + system-status-level = <0x01 0x04 0x08 0x08 0x02 0x01 0x10 0x04 0x10000 0x04 0x1000 0x08 0x4000 0x08 0x2000 0x08 0xc00 0x08>; + auto-min-freq = <0x4f1a0>; + auto-freq-en = <0x01>; + #cooling-cells = <0x02>; + status = "okay"; + center-supply = <0x6f>; + phandle = <0x12>; + }; + + dmc-fsp { + compatible = "rockchip,rk3568-dmc-fsp"; + debug_print_level = <0x00>; + ddr3_params = <0xbc>; + ddr4_params = <0xbd>; + lpddr3_params = <0xbe>; + lpddr4_params = <0xbf>; + lpddr4x_params = <0xc0>; + status = "okay"; + }; + + dmc-opp-table { + compatible = "operating-points-v2"; + mbist-vmin = <0xc96a8 0xdbba0 0xe7ef0>; + nvmem-cells = <0x7d 0x07 0x08 0xc1 0x0a 0x0b>; + nvmem-cell-names = "leakage\0pvtm\0mbist-vmin\0opp-info\0specification_serial_number\0remark_spec_serial_number"; + rockchip,supported-hw; + rockchip,max-volt = <0xf4240>; + rockchip,temp-hysteresis = <0x1388>; + rockchip,low-temp = <0x00>; + rockchip,low-temp-adjust-volt = <0x00 0x618 0x124f8>; + rockchip,leakage-voltage-sel = <0x01 0x50 0x00 0x51 0xfe 0x01>; + rockchip,pvtm-voltage-sel = <0x00 0x14820 0x00 0x14821 0x186a0 0x01>; + rockchip,pvtm-ch = <0x00 0x05>; + phandle = <0xbb>; + + opp-1560000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = <0x00 0x5cfbb600>; + opp-microvolt = <0xdbba0 0xdbba0 0xf4240>; + opp-microvolt-L0 = <0xdbba0 0xdbba0 0xf4240>; + opp-microvolt-L1 = <0xd59f8 0xd59f8 0xf4240>; + }; + + opp-j-m-1560000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x5cfbb600>; + opp-microvolt = <0xd59f8 0xd59f8 0xf4240>; + }; + }; + + pcie@fe260000 { + compatible = "rockchip,rk3568-pcie\0snps,dw-pcie"; + reg = <0x03 0xc0000000 0x00 0x400000 0x00 0xfe260000 0x00 0x10000 0x00 0xf4000000 0x00 0x100000>; + reg-names = "pcie-dbi\0pcie-apb\0config"; + interrupts = <0x00 0x4b 0x04 0x00 0x4a 0x04 0x00 0x49 0x04 0x00 0x48 0x04 0x00 0x47 0x04>; + interrupt-names = "sys\0pmc\0msg\0legacy\0err"; + bus-range = <0x00 0x0f>; + clocks = <0x24 0x81 0x24 0x82 0x24 0x83 0x24 0x84 0x24 0x85>; + clock-names = "aclk_mst\0aclk_slv\0aclk_dbi\0pclk\0aux"; + device_type = "pci"; + #interrupt-cells = <0x01>; + interrupt-map-mask = <0x00 0x00 0x00 0x07>; + interrupt-map = <0x00 0x00 0x00 0x01 0xc2 0x00 0x00 0x00 0x00 0x02 0xc2 0x01 0x00 0x00 0x00 0x03 0xc2 0x02 0x00 0x00 0x00 0x04 0xc2 0x03>; + linux,pci-domain = <0x00>; + num-ib-windows = <0x06>; + num-viewport = <0x08>; + num-ob-windows = <0x02>; + max-link-speed = <0x02>; + msi-map = <0x00 0xc3 0x00 0x1000>; + num-lanes = <0x01>; + phys = <0x27 0x02>; + phy-names = "pcie-phy"; + power-domains = <0x26 0x0f>; + ranges = <0x1000000 0x00 0xf4100000 0x00 0xf4100000 0x00 0x100000 0x2000000 0x00 0xf4200000 0x00 0xf4200000 0x00 0x1e00000 0x3000000 0x03 0x00 0x03 0x00 0x00 0x40000000>; + resets = <0x24 0xa1>; + reset-names = "pipe"; + #address-cells = <0x03>; + #size-cells = <0x02>; + status = "disabled"; + + legacy-interrupt-controller { + #address-cells = <0x00>; + #interrupt-cells = <0x01>; + interrupt-controller; + interrupt-parent = <0x01>; + interrupts = <0x00 0x48 0x01>; + phandle = <0xc2>; + }; + }; + + dwmmc@fe2b0000 { + compatible = "rockchip,rk3568-dw-mshc\0rockchip,rk3288-dw-mshc"; + reg = <0x00 0xfe2b0000 0x00 0x4000>; + interrupts = <0x00 0x62 0x04>; + clocks = <0x24 0xb0 0x24 0xb1 0x24 0x18a 0x24 0x18b>; + clock-names = "biu\0ciu\0ciu-drive\0ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <0x8f0d180>; + resets = <0x24 0xd4>; + reset-names = "reset"; + status = "okay"; + supports-sd; + bus-width = <0x04>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <0xc4>; + vqmmc-supply = <0x31>; + pinctrl-names = "default"; + pinctrl-0 = <0xc5 0xc6 0xc7 0xc8>; + }; + + dwmmc@fe2c0000 { + compatible = "rockchip,rk3568-dw-mshc\0rockchip,rk3288-dw-mshc"; + reg = <0x00 0xfe2c0000 0x00 0x4000>; + interrupts = <0x00 0x63 0x04>; + clocks = <0x24 0xb2 0x24 0xb3 0x24 0x18c 0x24 0x18d>; + clock-names = "biu\0ciu\0ciu-drive\0ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <0x8f0d180>; + resets = <0x24 0xd6>; + reset-names = "reset"; + status = "disabled"; + }; + + spi@fe300000 { + compatible = "rockchip,sfc"; + reg = <0x00 0xfe300000 0x00 0x4000>; + interrupts = <0x00 0x65 0x04>; + clocks = <0x24 0x78 0x24 0x76>; + clock-names = "clk_sfc\0hclk_sfc"; + assigned-clocks = <0x24 0x78>; + assigned-clock-rates = <0x5f5e100>; + #address-cells = <0x01>; + #size-cells = <0x00>; + status = "okay"; + }; + + sdhci@fe310000 { + compatible = "rockchip,rk3568-dwcmshc\0rockchip,dwcmshc-sdhci"; + reg = <0x00 0xfe310000 0x00 0x10000>; + interrupts = <0x00 0x13 0x04>; + assigned-clocks = <0x24 0x7b 0x24 0x7d 0x24 0x7c>; + assigned-clock-rates = <0xbebc200 0x16e3600 0xbebc200>; + clocks = <0x24 0x7c 0x24 0x7a 0x24 0x79 0x24 0x7b 0x24 0x7d>; + clock-names = "core\0bus\0axi\0block\0timer"; + resets = <0x24 0x78 0x24 0x76 0x24 0x75 0x24 0x77 0x24 0x79>; + reset-names = "core\0bus\0axi\0block\0timer"; + status = "okay"; + bus-width = <0x08>; + supports-emmc; + non-removable; + max-frequency = <0xbebc200>; + }; + + nandc@fe330000 { + compatible = "rockchip,rk-nandc-v9"; + reg = <0x00 0xfe330000 0x00 0x4000>; + interrupts = <0x00 0x46 0x04>; + nandc_id = <0x00>; + clocks = <0x24 0x75 0x24 0x74>; + clock-names = "clk_nandc\0hclk_nandc"; + status = "okay"; + #address-cells = <0x01>; + #size-cells = <0x00>; + + nand@0 { + reg = <0x00>; + nand-bus-width = <0x08>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <0x10>; + nand-ecc-step-size = <0x400>; + }; + }; + + crypto@fe380000 { + compatible = "rockchip,rk3568-crypto"; + reg = <0x00 0xfe380000 0x00 0x4000>; + interrupts = <0x00 0x04 0x04>; + clocks = <0x24 0x6a 0x24 0x6b 0x24 0x6c 0x24 0x6d>; + clock-names = "aclk\0hclk\0sclk\0apb_pclk"; + assigned-clocks = <0x24 0x6c>; + assigned-clock-rates = <0xbebc200>; + resets = <0x24 0x69>; + reset-names = "crypto-rst"; + status = "disabled"; + }; + + rng@fe388000 { + compatible = "rockchip,cryptov2-rng"; + reg = <0x00 0xfe388000 0x00 0x2000>; + clocks = <0x24 0x70 0x24 0x6f>; + clock-names = "clk_trng\0hclk_trng"; + resets = <0x24 0x6d>; + reset-names = "reset"; + status = "okay"; + }; + + otp@fe38c000 { + compatible = "rockchip,rk3568-otp"; + reg = <0x00 0xfe38c000 0x00 0x4000>; + #address-cells = <0x01>; + #size-cells = <0x01>; + clocks = <0x24 0x73 0x24 0x72 0x24 0x71 0x24 0x181>; + clock-names = "usr\0sbpi\0apb\0phy"; + resets = <0x24 0x1cf>; + reset-names = "otp_phy"; + + cpu-code@2 { + reg = <0x02 0x02>; + phandle = <0x0e>; + }; + + specification-serial-number@7 { + reg = <0x07 0x01>; + bits = <0x00 0x05>; + phandle = <0x0a>; + }; + + cpu-version@8 { + reg = <0x08 0x01>; + bits = <0x03 0x03>; + phandle = <0x0d>; + }; + + mbist-vmin@9 { + reg = <0x09 0x01>; + bits = <0x00 0x04>; + phandle = <0x08>; + }; + + id@a { + reg = <0x0a 0x10>; + phandle = <0x0c>; + }; + + cpu-leakage@1a { + reg = <0x1a 0x01>; + phandle = <0x06>; + }; + + log-leakage@1b { + reg = <0x1b 0x01>; + phandle = <0x7d>; + }; + + npu-leakage@1c { + reg = <0x1c 0x01>; + phandle = <0x6c>; + }; + + gpu-leakage@1d { + reg = <0x1d 0x01>; + phandle = <0x1a>; + }; + + core-pvtm@2a { + reg = <0x2a 0x02>; + phandle = <0x07>; + }; + + cpu-tsadc-trim-l@2e { + reg = <0x2e 0x01>; + phandle = <0x123>; + }; + + cpu-tsadc-trim-h@2f { + reg = <0x2f 0x01>; + bits = <0x00 0x04>; + phandle = <0x124>; + }; + + npu-tsadc-trim-l@30 { + reg = <0x30 0x01>; + phandle = <0x125>; + }; + + npu-tsadc-trim-h@31 { + reg = <0x31 0x01>; + bits = <0x00 0x04>; + phandle = <0x126>; + }; + + tsadc-trim-base-frac@31 { + reg = <0x31 0x01>; + bits = <0x04 0x04>; + phandle = <0x120>; + }; + + tsadc-trim-base@32 { + reg = <0x32 0x01>; + phandle = <0x11f>; + }; + + cpu-opp-info@36 { + reg = <0x36 0x06>; + phandle = <0x09>; + }; + + gpu-opp-info@3c { + reg = <0x3c 0x06>; + phandle = <0x1b>; + }; + + npu-opp-info@42 { + reg = <0x42 0x06>; + phandle = <0x6d>; + }; + + dmc-opp-info@48 { + reg = <0x48 0x06>; + phandle = <0xc1>; + }; + + remark-spec-serial-number@56 { + reg = <0x56 0x01>; + bits = <0x00 0x05>; + phandle = <0x0b>; + }; + }; + + i2s@fe400000 { + compatible = "rockchip,rk3568-i2s-tdm"; + reg = <0x00 0xfe400000 0x00 0x1000>; + interrupts = <0x00 0x34 0x04>; + clocks = <0x24 0x3f 0x24 0x43 0x24 0x39>; + clock-names = "mclk_tx\0mclk_rx\0hclk"; + dmas = <0xc9 0x00>; + dma-names = "tx"; + resets = <0x24 0x50 0x24 0x51>; + reset-names = "tx-m\0rx-m"; + rockchip,cru = <0x24>; + rockchip,grf = <0x3b>; + rockchip,playback-only; + #sound-dai-cells = <0x00>; + status = "okay"; + phandle = <0x1d>; + }; + + i2s@fe410000 { + compatible = "rockchip,rk3568-i2s-tdm"; + reg = <0x00 0xfe410000 0x00 0x1000>; + interrupts = <0x00 0x35 0x04>; + clocks = <0x24 0x47 0x24 0x4b 0x24 0x3a>; + clock-names = "mclk_tx\0mclk_rx\0hclk"; + dmas = <0xc9 0x02 0xc9 0x03>; + dma-names = "tx\0rx"; + resets = <0x24 0x52 0x24 0x53>; + reset-names = "tx-m\0rx-m"; + rockchip,cru = <0x24>; + rockchip,grf = <0x3b>; + pinctrl-names = "default"; + pinctrl-0 = <0xca 0xcb 0xcc 0xcb 0xcd 0xce 0xcf 0xd0 0xd1 0xd2>; + #sound-dai-cells = <0x00>; + status = "okay"; + rockchip,clk-trcm = <0x01>; + phandle = <0xe1>; + }; + + i2s@fe420000 { + compatible = "rockchip,rk3568-i2s-tdm"; + reg = <0x00 0xfe420000 0x00 0x1000>; + interrupts = <0x00 0x36 0x04>; + clocks = <0x24 0x4f 0x24 0x4f 0x24 0x3b>; + clock-names = "mclk_tx\0mclk_rx\0hclk"; + dmas = <0xc9 0x04 0xc9 0x05>; + dma-names = "tx\0rx"; + rockchip,cru = <0x24>; + rockchip,grf = <0x3b>; + rockchip,trcm-sync-tx-only; + pinctrl-names = "default"; + pinctrl-0 = <0xd3 0xd4 0xd5 0xd6>; + #sound-dai-cells = <0x00>; + status = "disabled"; + }; + + i2s@fe430000 { + compatible = "rockchip,rk3568-i2s-tdm"; + reg = <0x00 0xfe430000 0x00 0x1000>; + interrupts = <0x00 0x37 0x04>; + clocks = <0x24 0x53 0x24 0x57 0x24 0x3c>; + clock-names = "mclk_tx\0mclk_rx\0hclk"; + dmas = <0xc9 0x06 0xc9 0x07>; + dma-names = "tx\0rx"; + resets = <0x24 0x55 0x24 0x56>; + reset-names = "tx-m\0rx-m"; + rockchip,cru = <0x24>; + rockchip,grf = <0x3b>; + rockchip,trcm-sync-tx-only; + #sound-dai-cells = <0x00>; + pinctrl-names = "default"; + pinctrl-0 = <0xd7 0xd8 0xd9 0xda>; + status = "okay"; + phandle = <0x152>; + }; + + pdm@fe440000 { + compatible = "rockchip,rk3568-pdm\0rockchip,pdm"; + reg = <0x00 0xfe440000 0x00 0x1000>; + interrupts = <0x00 0x4c 0x04>; + clocks = <0x24 0x5a 0x24 0x59>; + clock-names = "pdm_clk\0pdm_hclk"; + dmas = <0xc9 0x09>; + dma-names = "rx"; + pinctrl-0 = <0xdb 0xdc 0xdd 0xde 0xdf 0xe0>; + pinctrl-names = "default"; + resets = <0x24 0x58>; + reset-names = "pdm-m"; + #sound-dai-cells = <0x00>; + status = "disabled"; + phandle = <0x156>; + }; + + vad@fe450000 { + compatible = "rockchip,rk3568-vad"; + reg = <0x00 0xfe450000 0x00 0x10000>; + reg-names = "vad"; + clocks = <0x24 0x5b>; + clock-names = "hclk"; + interrupts = <0x00 0x89 0x04>; + rockchip,audio-src = <0xe1>; + rockchip,det-channel = <0x00>; + rockchip,mode = <0x00>; + #sound-dai-cells = <0x00>; + status = "disabled"; + rockchip,buffer-time-ms = <0x80>; + phandle = <0x15b>; + }; + + spdif@fe460000 { + compatible = "rockchip,rk3568-spdif"; + reg = <0x00 0xfe460000 0x00 0x1000>; + interrupts = <0x00 0x66 0x04>; + clock-names = "mclk\0hclk"; + clocks = <0x24 0x5f 0x24 0x5c>; + dmas = <0xc9 0x01>; + dma-names = "tx"; + pinctrl-names = "default"; + pinctrl-0 = <0xe2>; + #sound-dai-cells = <0x00>; + status = "okay"; + phandle = <0x159>; + }; + + audpwm@fe470000 { + compatible = "rockchip,rk3568-audio-pwm\0rockchip,audio-pwm-v1"; + reg = <0x00 0xfe470000 0x00 0x1000>; + clocks = <0x24 0x63 0x24 0x60>; + clock-names = "clk\0hclk"; + dmas = <0xc9 0x08>; + dma-names = "tx"; + #sound-dai-cells = <0x00>; + rockchip,sample-width-bits = <0x0b>; + rockchip,interpolat-points = <0x01>; + status = "disabled"; + }; + + codec-digital@fe478000 { + compatible = "rockchip,rk3568-codec-digital\0rockchip,codec-digital-v1"; + reg = <0x00 0xfe478000 0x00 0x1000>; + clocks = <0x24 0x67 0x24 0x66 0x24 0x65 0x24 0x64>; + clock-names = "adc\0dac\0i2c\0pclk"; + pinctrl-names = "default"; + pinctrl-0 = <0xe3>; + resets = <0x24 0x5f>; + reset-names = "reset"; + rockchip,grf = <0x3b>; + #sound-dai-cells = <0x00>; + status = "disabled"; + phandle = <0x153>; + }; + + dma-controller@fe530000 { + compatible = "arm,pl330\0arm,primecell"; + reg = <0x00 0xfe530000 0x00 0x4000>; + interrupts = <0x00 0x0e 0x04 0x00 0x0d 0x04>; + arm,pl330-periph-burst; + clocks = <0x24 0x10d>; + clock-names = "apb_pclk"; + #dma-cells = <0x01>; + phandle = <0x48>; + }; + + dma-controller@fe550000 { + compatible = "arm,pl330\0arm,primecell"; + reg = <0x00 0xfe550000 0x00 0x4000>; + interrupts = <0x00 0x10 0x04 0x00 0x0f 0x04>; + arm,pl330-periph-burst; + clocks = <0x24 0x10d>; + clock-names = "apb_pclk"; + #dma-cells = <0x01>; + phandle = <0xc9>; + }; + + rkscr@fe560000 { + compatible = "rockchip-scr"; + reg = <0x00 0xfe560000 0x00 0x10000>; + interrupts = <0x00 0x61 0x04>; + pinctrl-names = "default"; + pinctrl-0 = <0xe4>; + clocks = <0x24 0x114>; + clock-names = "g_pclk_sim_card"; + status = "disabled"; + }; + + can@fe570000 { + compatible = "rockchip,rk3568-can-2.0"; + reg = <0x00 0xfe570000 0x00 0x1000>; + interrupts = <0x00 0x01 0x04>; + clocks = <0x24 0x141 0x24 0x140>; + clock-names = "baudclk\0apb_pclk"; + resets = <0x24 0x155 0x24 0x154>; + reset-names = "can\0can-apb"; + tx-fifo-depth = <0x01>; + rx-fifo-depth = <0x06>; + status = "disabled"; + assigned-clocks = <0x24 0x141>; + assigned-clock-rates = <0x8f0d180>; + pinctrl-names = "default"; + pinctrl-0 = <0xe5>; + }; + + can@fe580000 { + compatible = "rockchip,rk3568-can-2.0"; + reg = <0x00 0xfe580000 0x00 0x1000>; + interrupts = <0x00 0x02 0x04>; + clocks = <0x24 0x143 0x24 0x142>; + clock-names = "baudclk\0apb_pclk"; + resets = <0x24 0x157 0x24 0x156>; + reset-names = "can\0can-apb"; + tx-fifo-depth = <0x01>; + rx-fifo-depth = <0x06>; + status = "disabled"; + assigned-clocks = <0x24 0x143>; + assigned-clock-rates = <0x8f0d180>; + pinctrl-names = "default"; + pinctrl-0 = <0xe6>; + }; + + can@fe590000 { + compatible = "rockchip,rk3568-can-2.0"; + reg = <0x00 0xfe590000 0x00 0x1000>; + interrupts = <0x00 0x03 0x04>; + clocks = <0x24 0x145 0x24 0x144>; + clock-names = "baudclk\0apb_pclk"; + resets = <0x24 0x159 0x24 0x158>; + reset-names = "can\0can-apb"; + tx-fifo-depth = <0x01>; + rx-fifo-depth = <0x06>; + status = "disabled"; + assigned-clocks = <0x24 0x145>; + assigned-clock-rates = <0x8f0d180>; + pinctrl-names = "default"; + pinctrl-0 = <0xe7>; + }; + + i2c@fe5a0000 { + compatible = "rockchip,rk3568-i2c\0rockchip,rk3399-i2c"; + reg = <0x00 0xfe5a0000 0x00 0x1000>; + interrupts = <0x00 0x2f 0x04>; + clocks = <0x24 0x148 0x24 0x147>; + clock-names = "i2c\0pclk"; + pinctrl-0 = <0xe8>; + pinctrl-names = "default"; + #address-cells = <0x01>; + #size-cells = <0x00>; + status = "okay"; + + gt1x@14 { + compatible = "goodix,gt1x"; + status = "disabled"; + reg = <0x5d>; + pinctrl-names = "default"; + pinctrl-0 = <0xe9>; + goodix,rst-gpio = <0x3f 0x0e 0x00>; + goodix,irq-gpio = <0x3f 0x0d 0x08>; + power-supply = <0xa6>; + }; + + gt9xx@5d { + compatible = "goodix,gt9xx"; + status = "okay"; + reg = <0x5d>; + reset-gpio = <0x3f 0x0e 0x00>; + touch-gpio = <0x3f 0x0d 0x08>; + max-x = <0x1c20>; + max-y = <0x500>; + tp-size = <0x38f>; + pinctrl-names = "default"; + pinctrl-0 = <0xe9>; + power-supply = <0xa6>; + }; + }; + + i2c@fe5b0000 { + compatible = "rockchip,rk3568-i2c\0rockchip,rk3399-i2c"; + reg = <0x00 0xfe5b0000 0x00 0x1000>; + interrupts = <0x00 0x30 0x04>; + clocks = <0x24 0x14a 0x24 0x149>; + clock-names = "i2c\0pclk"; + pinctrl-0 = <0xea>; + pinctrl-names = "default"; + #address-cells = <0x01>; + #size-cells = <0x00>; + status = "disabled"; + }; + + i2c@fe5c0000 { + compatible = "rockchip,rk3568-i2c\0rockchip,rk3399-i2c"; + reg = <0x00 0xfe5c0000 0x00 0x1000>; + interrupts = <0x00 0x31 0x04>; + clocks = <0x24 0x14c 0x24 0x14b>; + clock-names = "i2c\0pclk"; + pinctrl-0 = <0xeb>; + pinctrl-names = "default"; + #address-cells = <0x01>; + #size-cells = <0x00>; + status = "okay"; + + rt5670@1c { + status = "okay"; + #sound-dai-cell = <0x00>; + compatible = "realtek,rt5670"; + reg = <0x1c>; + phandle = <0x167>; + }; + + es7210@40 { + #sound-dai-cells = <0x00>; + compatible = "MicArray_0"; + reg = <0x40>; + clocks = <0x24 0x4c>; + clock-names = "mclk"; + phandle = <0x168>; + }; + + es7210@42 { + compatible = "MicArray_1"; + reg = <0x42>; + }; + }; + + i2c@fe5d0000 { + compatible = "rockchip,rk3568-i2c\0rockchip,rk3399-i2c"; + reg = <0x00 0xfe5d0000 0x00 0x1000>; + interrupts = <0x00 0x32 0x04>; + clocks = <0x24 0x14e 0x24 0x14d>; + clock-names = "i2c\0pclk"; + pinctrl-0 = <0xec>; + pinctrl-names = "default"; + #address-cells = <0x01>; + #size-cells = <0x00>; + status = "okay"; + + gc8034@37 { + compatible = "galaxycore,gc8034"; + reg = <0x37>; + clocks = <0x24 0xd6>; + clock-names = "xvclk"; + power-domains = <0x26 0x08>; + pinctrl-names = "default"; + pinctrl-0 = <0xed>; + reset-gpios = <0x3f 0x1e 0x01>; + pwdn-gpios = <0xee 0x0c 0x01>; + rockchip,grf = <0x3b>; + rockchip,camera-module-index = <0x00>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "RK-CMK-8M-2-v1"; + rockchip,camera-module-lens-name = "CK8401"; + + port { + + endpoint { + remote-endpoint = <0xef>; + data-lanes = <0x01 0x02 0x03 0x04>; + phandle = <0x12d>; + }; + }; + }; + + ov9750_1@36 { + status = "disabled"; + compatible = "ovti,ov9750"; + reg = <0x36>; + clocks = <0x24 0xd6>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <0xed>; + power-domains = <0x26 0x08>; + reset-gpios = <0x3f 0x1e 0x00>; + pwdn-gpios = <0xee 0x0c 0x00>; + rockchip,camera-module-index = <0x00>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT0854-FV1"; + rockchip,camera-module-lens-name = "CHT-842B-MD"; + + port { + + endpoint { + remote-endpoint = <0xf0>; + data-lanes = <0x01 0x02>; + phandle = <0x12c>; + }; + }; + }; + + ov5695@36 { + status = "disabled"; + compatible = "ovti,ov5695"; + reg = <0x36>; + clocks = <0x24 0xd6>; + clock-names = "xvclk"; + power-domains = <0x26 0x08>; + pinctrl-names = "default"; + pinctrl-0 = <0xed>; + reset-gpios = <0x3f 0x1e 0x01>; + pwdn-gpios = <0xee 0x0c 0x01>; + rockchip,camera-module-index = <0x00>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "TongJu"; + rockchip,camera-module-lens-name = "CHT842-MD"; + + port { + + endpoint { + remote-endpoint = <0xf1>; + data-lanes = <0x01 0x02>; + phandle = <0x12e>; + }; + }; + }; + }; + + i2c@fe5e0000 { + compatible = "rockchip,rk3568-i2c\0rockchip,rk3399-i2c"; + reg = <0x00 0xfe5e0000 0x00 0x1000>; + interrupts = <0x00 0x33 0x04>; + clocks = <0x24 0x150 0x24 0x14f>; + clock-names = "i2c\0pclk"; + pinctrl-0 = <0xf2>; + pinctrl-names = "default"; + #address-cells = <0x01>; + #size-cells = <0x00>; + status = "okay"; + + mxc6655xa@15 { + status = "disabled"; + compatible = "gs_mxc6655xa"; + pinctrl-names = "default"; + pinctrl-0 = <0xf3>; + reg = <0x15>; + irq-gpio = <0xa8 0x11 0x08>; + irq_enable = <0x00>; + poll_delay_ms = <0x1e>; + type = <0x02>; + power-off-in-suspend = <0x01>; + layout = <0x01>; + }; + + gs_mxc6655xa@15 { + status = "okay"; + compatible = "gs_mxc6655xa"; + pinctrl-names = "default"; + pinctrl-0 = <0xf3>; + reg = <0x15>; + irq-gpio = <0xa8 0x11 0x08>; + irq_enable = <0x00>; + poll_delay_ms = <0x1e>; + type = <0x02>; + power-off-in-suspend = <0x01>; + layout = <0x01>; + }; + + hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + pinctrl-names = "default"; + pinctrl-0 = <0xf4>; + interrupt-parent = <0x3f>; + interrupts = <0x1b 0x08>; + }; + }; + + timer@fe5f0000 { + compatible = "rockchip,rk3568-timer\0rockchip,rk3288-timer"; + reg = <0x00 0xfe5f0000 0x00 0x1000>; + interrupts = <0x00 0x6d 0x04>; + clocks = <0x24 0x16c 0x24 0x16d>; + clock-names = "pclk\0timer"; + }; + + watchdog@fe600000 { + compatible = "rockchip,rk3568-wdt\0snps,dw-wdt"; + reg = <0x00 0xfe600000 0x00 0x100>; + interrupts = <0x00 0x95 0x04>; + clocks = <0x24 0x116 0x24 0x115>; + clock-names = "tclk\0pclk"; + }; + + spi@fe610000 { + compatible = "rockchip,rk3568-spi\0rockchip,rk3066-spi"; + reg = <0x00 0xfe610000 0x00 0x1000>; + interrupts = <0x00 0x67 0x04>; + clocks = <0x24 0x152 0x24 0x151>; + clock-names = "spiclk\0apb_pclk"; + dmas = <0x48 0x14 0x48 0x15>; + dma-names = "tx\0rx"; + pinctrl-names = "default\0high_speed"; + pinctrl-0 = <0xf5 0xf6 0xf7>; + pinctrl-1 = <0xf5 0xf6 0xf8>; + #address-cells = <0x01>; + #size-cells = <0x00>; + num-cs = <0x02>; + status = "disabled"; + }; + + spi@fe620000 { + compatible = "rockchip,rk3568-spi\0rockchip,rk3066-spi"; + reg = <0x00 0xfe620000 0x00 0x1000>; + interrupts = <0x00 0x68 0x04>; + clocks = <0x24 0x154 0x24 0x153>; + clock-names = "spiclk\0apb_pclk"; + dmas = <0x48 0x16 0x48 0x17>; + dma-names = "tx\0rx"; + pinctrl-names = "default\0high_speed"; + pinctrl-0 = <0xf9 0xfa 0xfb>; + pinctrl-1 = <0xf9 0xfa 0xfc>; + #address-cells = <0x01>; + #size-cells = <0x00>; + num-cs = <0x02>; + status = "disabled"; + }; + + spi@fe630000 { + compatible = "rockchip,rk3568-spi\0rockchip,rk3066-spi"; + reg = <0x00 0xfe630000 0x00 0x1000>; + interrupts = <0x00 0x69 0x04>; + clocks = <0x24 0x156 0x24 0x155>; + clock-names = "spiclk\0apb_pclk"; + dmas = <0x48 0x18 0x48 0x19>; + dma-names = "tx\0rx"; + pinctrl-names = "default\0high_speed"; + pinctrl-0 = <0xfd 0xfe 0xff>; + pinctrl-1 = <0xfd 0xfe 0x100>; + #address-cells = <0x01>; + #size-cells = <0x00>; + num-cs = <0x02>; + status = "disabled"; + }; + + spi@fe640000 { + compatible = "rockchip,rk3568-spi\0rockchip,rk3066-spi"; + reg = <0x00 0xfe640000 0x00 0x1000>; + interrupts = <0x00 0x6a 0x04>; + clocks = <0x24 0x158 0x24 0x157>; + clock-names = "spiclk\0apb_pclk"; + dmas = <0x48 0x1a 0x48 0x1b>; + dma-names = "tx\0rx"; + pinctrl-names = "default\0high_speed"; + pinctrl-0 = <0x101 0x102 0x103>; + pinctrl-1 = <0x101 0x102 0x104>; + #address-cells = <0x01>; + #size-cells = <0x00>; + num-cs = <0x02>; + status = "disabled"; + }; + + serial@fe650000 { + compatible = "rockchip,rk3568-uart\0snps,dw-apb-uart"; + reg = <0x00 0xfe650000 0x00 0x100>; + interrupts = <0x00 0x75 0x04>; + clocks = <0x24 0x11f 0x24 0x11c>; + clock-names = "baudclk\0apb_pclk"; + dmas = <0x48 0x02 0x48 0x03>; + pinctrl-0 = <0x105 0x106>; + pinctrl-names = "default"; + reg-io-width = <0x04>; + reg-shift = <0x02>; + status = "disabled"; + }; + + serial@fe660000 { + compatible = "rockchip,rk3568-uart\0snps,dw-apb-uart"; + reg = <0x00 0xfe660000 0x00 0x100>; + interrupts = <0x00 0x76 0x04>; + clocks = <0x24 0x123 0x24 0x120>; + clock-names = "baudclk\0apb_pclk"; + dmas = <0x48 0x04 0x48 0x05>; + pinctrl-0 = <0x107>; + pinctrl-names = "default"; + reg-io-width = <0x04>; + reg-shift = <0x02>; + status = "disabled"; + }; + + serial@fe670000 { + compatible = "rockchip,rk3568-uart\0snps,dw-apb-uart"; + reg = <0x00 0xfe670000 0x00 0x100>; + interrupts = <0x00 0x77 0x04>; + clocks = <0x24 0x127 0x24 0x124>; + clock-names = "baudclk\0apb_pclk"; + dmas = <0x48 0x06 0x48 0x07>; + pinctrl-0 = <0x108>; + pinctrl-names = "default"; + reg-io-width = <0x04>; + reg-shift = <0x02>; + status = "okay"; + }; + + serial@fe680000 { + compatible = "rockchip,rk3568-uart\0snps,dw-apb-uart"; + reg = <0x00 0xfe680000 0x00 0x100>; + interrupts = <0x00 0x78 0x04>; + clocks = <0x24 0x12b 0x24 0x128>; + clock-names = "baudclk\0apb_pclk"; + dmas = <0x48 0x08 0x48 0x09>; + pinctrl-0 = <0x109>; + pinctrl-names = "default"; + reg-io-width = <0x04>; + reg-shift = <0x02>; + status = "okay"; + }; + + serial@fe690000 { + compatible = "rockchip,rk3568-uart\0snps,dw-apb-uart"; + reg = <0x00 0xfe690000 0x00 0x100>; + interrupts = <0x00 0x79 0x04>; + clocks = <0x24 0x12f 0x24 0x12c>; + clock-names = "baudclk\0apb_pclk"; + dmas = <0x48 0x0a 0x48 0x0b>; + pinctrl-0 = <0x10a>; + pinctrl-names = "default"; + reg-io-width = <0x04>; + reg-shift = <0x02>; + status = "disabled"; + }; + + serial@fe6a0000 { + compatible = "rockchip,rk3568-uart\0snps,dw-apb-uart"; + reg = <0x00 0xfe6a0000 0x00 0x100>; + interrupts = <0x00 0x7a 0x04>; + clocks = <0x24 0x133 0x24 0x130>; + clock-names = "baudclk\0apb_pclk"; + dmas = <0x48 0x0c 0x48 0x0d>; + pinctrl-0 = <0x10b>; + pinctrl-names = "default"; + reg-io-width = <0x04>; + reg-shift = <0x02>; + status = "disabled"; + }; + + serial@fe6b0000 { + compatible = "rockchip,rk3568-uart\0snps,dw-apb-uart"; + reg = <0x00 0xfe6b0000 0x00 0x100>; + interrupts = <0x00 0x7b 0x04>; + clocks = <0x24 0x137 0x24 0x134>; + clock-names = "baudclk\0apb_pclk"; + dmas = <0x48 0x0e 0x48 0x0f>; + pinctrl-0 = <0x10c>; + pinctrl-names = "default"; + reg-io-width = <0x04>; + reg-shift = <0x02>; + status = "disabled"; + }; + + serial@fe6c0000 { + compatible = "rockchip,rk3568-uart\0snps,dw-apb-uart"; + reg = <0x00 0xfe6c0000 0x00 0x100>; + interrupts = <0x00 0x7c 0x04>; + clocks = <0x24 0x13b 0x24 0x138>; + clock-names = "baudclk\0apb_pclk"; + dmas = <0x48 0x10 0x48 0x11>; + pinctrl-0 = <0x10d 0x10e>; + pinctrl-names = "default"; + reg-io-width = <0x04>; + reg-shift = <0x02>; + status = "okay"; + }; + + serial@fe6d0000 { + compatible = "rockchip,rk3568-uart\0snps,dw-apb-uart"; + reg = <0x00 0xfe6d0000 0x00 0x100>; + interrupts = <0x00 0x7d 0x04>; + clocks = <0x24 0x13f 0x24 0x13c>; + clock-names = "baudclk\0apb_pclk"; + dmas = <0x48 0x12 0x48 0x13>; + pinctrl-0 = <0x10f>; + pinctrl-names = "default"; + reg-io-width = <0x04>; + reg-shift = <0x02>; + status = "disabled"; + }; + + pwm@fe6e0000 { + compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm"; + reg = <0x00 0xfe6e0000 0x00 0x10>; + interrupts = <0x00 0x53 0x04>; + clocks = <0x24 0x15a 0x24 0x159>; + clock-names = "pwm\0pclk"; + pinctrl-0 = <0x110>; + pinctrl-names = "active"; + #pwm-cells = <0x03>; + status = "okay"; + phandle = <0x154>; + }; + + pwm@fe6e0010 { + compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm"; + reg = <0x00 0xfe6e0010 0x00 0x10>; + interrupts = <0x00 0x53 0x04>; + clocks = <0x24 0x15a 0x24 0x159>; + clock-names = "pwm\0pclk"; + pinctrl-0 = <0x111>; + pinctrl-names = "active"; + #pwm-cells = <0x03>; + status = "okay"; + phandle = <0x155>; + }; + + pwm@fe6e0020 { + compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm"; + reg = <0x00 0xfe6e0020 0x00 0x10>; + interrupts = <0x00 0x53 0x04>; + clocks = <0x24 0x15a 0x24 0x159>; + clock-names = "pwm\0pclk"; + pinctrl-0 = <0x112>; + pinctrl-names = "active"; + #pwm-cells = <0x03>; + status = "disabled"; + }; + + pwm@fe6e0030 { + compatible = "rockchip,remotectl-pwm"; + reg = <0x00 0xfe6e0030 0x00 0x10>; + interrupts = <0x00 0x53 0x04 0x00 0x57 0x04>; + clocks = <0x24 0x15a 0x24 0x159>; + clock-names = "pwm\0pclk"; + pinctrl-0 = <0x113>; + pinctrl-names = "default"; + #pwm-cells = <0x03>; + status = "okay"; + remote_pwm_id = <0x03>; + handle_cpu_id = <0x01>; + remote_support_psci = <0x00>; + + ir_key1 { + rockchip,usercode = <0x4040>; + rockchip,key_table = <0xf2 0xe8 0xba 0x9e 0xf4 0x67 0xf1 0x6c 0xef 0x69 0xee 0x6a 0xbd 0x66 0xea 0x73 0xe3 0x72 0xe2 0xd9 0xb2 0x74 0xbc 0x71 0xec 0x8b 0xbf 0x190 0xe0 0x191 0xe1 0x192 0xe9 0xb7 0xe6 0xf8 0xe8 0xb9 0xe7 0xba 0xf0 0x184 0xbe 0x175>; + }; + + ir_key2 { + rockchip,usercode = <0xff00>; + rockchip,key_table = <0xf9 0x66 0xbf 0x9e 0xfb 0x8b 0xaa 0xe8 0xb9 0x67 0xe9 0x6c 0xb8 0x69 0xea 0x6a 0xeb 0x72 0xef 0x73 0xf7 0x71 0xe7 0x74 0xfc 0x74 0xa9 0x72 0xa8 0x72 0xe0 0x72 0xa5 0x72 0xab 0xb7 0xb7 0x184 0xe8 0x184 0xf8 0xb8 0xaf 0xb9 0xed 0x72 0xee 0xba 0xb3 0x72 0xf1 0x72 0xf2 0x72 0xf3 0xd9 0xb4 0x72 0xbe 0xd9>; + }; + + ir_key3 { + rockchip,usercode = <0x1dcc>; + rockchip,key_table = <0xee 0xe8 0xf0 0x9e 0xf8 0x67 0xbb 0x6c 0xef 0x69 0xed 0x6a 0xfc 0x66 0xf1 0x73 0xfd 0x72 0xb7 0xd9 0xff 0x74 0xf3 0x71 0xbf 0x8b 0xf9 0x191 0xf5 0x192 0xb3 0x184 0xbe 0x02 0xba 0x03 0xb2 0x04 0xbd 0x05 0xf9 0x06 0xb1 0x07 0xfc 0x08 0xf8 0x09 0xb0 0x0a 0xb6 0x0b 0xb5 0x0e>; + }; + }; + + pwm@fe6f0000 { + compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm"; + reg = <0x00 0xfe6f0000 0x00 0x10>; + interrupts = <0x00 0x54 0x04>; + clocks = <0x24 0x15d 0x24 0x15c>; + clock-names = "pwm\0pclk"; + pinctrl-0 = <0x114>; + pinctrl-names = "active"; + #pwm-cells = <0x03>; + status = "disabled"; + }; + + pwm@fe6f0010 { + compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm"; + reg = <0x00 0xfe6f0010 0x00 0x10>; + clocks = <0x24 0x15d 0x24 0x15c>; + clock-names = "pwm\0pclk"; + pinctrl-0 = <0x115>; + pinctrl-names = "active"; + #pwm-cells = <0x03>; + status = "disabled"; + }; + + pwm@fe6f0020 { + compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm"; + reg = <0x00 0xfe6f0020 0x00 0x10>; + interrupts = <0x00 0x54 0x04>; + clocks = <0x24 0x15d 0x24 0x15c>; + clock-names = "pwm\0pclk"; + pinctrl-0 = <0x116>; + pinctrl-names = "active"; + #pwm-cells = <0x03>; + status = "disabled"; + }; + + pwm@fe6f0030 { + compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm"; + reg = <0x00 0xfe6f0030 0x00 0x10>; + interrupts = <0x00 0x54 0x04 0x00 0x58 0x04>; + clocks = <0x24 0x15d 0x24 0x15c>; + clock-names = "pwm\0pclk"; + pinctrl-0 = <0x117>; + pinctrl-names = "active"; + #pwm-cells = <0x03>; + status = "disabled"; + }; + + pwm@fe700000 { + compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm"; + reg = <0x00 0xfe700000 0x00 0x10>; + interrupts = <0x00 0x55 0x04>; + clocks = <0x24 0x160 0x24 0x15f>; + clock-names = "pwm\0pclk"; + pinctrl-0 = <0x118>; + pinctrl-names = "active"; + #pwm-cells = <0x03>; + status = "disabled"; + }; + + pwm@fe700010 { + compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm"; + reg = <0x00 0xfe700010 0x00 0x10>; + interrupts = <0x00 0x55 0x04>; + clocks = <0x24 0x160 0x24 0x15f>; + clock-names = "pwm\0pclk"; + pinctrl-0 = <0x119>; + pinctrl-names = "active"; + #pwm-cells = <0x03>; + status = "disabled"; + }; + + pwm@fe700020 { + compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm"; + reg = <0x00 0xfe700020 0x00 0x10>; + interrupts = <0x00 0x55 0x04>; + clocks = <0x24 0x160 0x24 0x15f>; + clock-names = "pwm\0pclk"; + pinctrl-0 = <0x11a>; + pinctrl-names = "active"; + #pwm-cells = <0x03>; + status = "disabled"; + }; + + pwm@fe700030 { + compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm"; + reg = <0x00 0xfe700030 0x00 0x10>; + interrupts = <0x00 0x55 0x04 0x00 0x59 0x04>; + clocks = <0x24 0x160 0x24 0x15f>; + clock-names = "pwm\0pclk"; + pinctrl-0 = <0x11b>; + pinctrl-names = "active"; + #pwm-cells = <0x03>; + status = "disabled"; + }; + + thermal-zones { + + soc-thermal { + polling-delay-passive = <0x14>; + polling-delay = <0x3e8>; + sustainable-power = <0x389>; + thermal-sensors = <0x11c 0x00>; + + trips { + + trip-point-0 { + temperature = <0x124f8>; + hysteresis = <0x7d0>; + type = "passive"; + }; + + trip-point-1 { + temperature = <0x14c08>; + hysteresis = <0x7d0>; + type = "passive"; + phandle = <0x11d>; + }; + + soc-crit { + temperature = <0x1c138>; + hysteresis = <0x7d0>; + type = "critical"; + }; + }; + + cooling-maps { + + map0 { + trip = <0x11d>; + cooling-device = <0x1f 0xffffffff 0xffffffff>; + contribution = <0x400>; + }; + + map1 { + trip = <0x11d>; + cooling-device = <0x11e 0xffffffff 0xffffffff>; + contribution = <0x400>; + }; + }; + }; + + gpu-thermal { + polling-delay-passive = <0x14>; + polling-delay = <0x3e8>; + thermal-sensors = <0x11c 0x01>; + + trips { + + gpu-crit { + temperature = <0x1c138>; + hysteresis = <0x7d0>; + type = "critical"; + }; + }; + }; + }; + + tsadc@fe710000 { + compatible = "rockchip,rk3568-tsadc"; + reg = <0x00 0xfe710000 0x00 0x100>; + interrupts = <0x00 0x73 0x04>; + assigned-clocks = <0x24 0x110 0x24 0x111>; + assigned-clock-rates = <0x1036640 0xaae60>; + clocks = <0x24 0x111 0x24 0x10f>; + clock-names = "tsadc\0apb_pclk"; + resets = <0x24 0x182 0x24 0x181 0x24 0x1d7>; + reset-names = "tsadc\0tsadc-apb\0tsadc-phy"; + rockchip,grf = <0x3b>; + nvmem-cells = <0x11f 0x120>; + nvmem-cell-names = "trim_base\0trim_base_frac"; + rockchip,hw-tshut-temp = <0x1d4c0>; + rockchip,hw-tshut-mode = <0x00>; + rockchip,hw-tshut-polarity = <0x00>; + pinctrl-names = "gpio\0otpout"; + pinctrl-0 = <0x121>; + pinctrl-1 = <0x122>; + #address-cells = <0x01>; + #size-cells = <0x00>; + #thermal-sensor-cells = <0x01>; + status = "okay"; + phandle = <0x11c>; + + tsadc@0 { + reg = <0x00>; + nvmem-cells = <0x123 0x124>; + nvmem-cell-names = "trim_l\0trim_h"; + }; + + tsadc@1 { + reg = <0x01>; + nvmem-cells = <0x125 0x126>; + nvmem-cell-names = "trim_l\0trim_h"; + }; + }; + + saradc@fe720000 { + compatible = "rockchip,rk3568-saradc\0rockchip,rk3399-saradc"; + reg = <0x00 0xfe720000 0x00 0x100>; + interrupts = <0x00 0x5d 0x04>; + clocks = <0x24 0x113 0x24 0x112>; + clock-names = "saradc\0apb_pclk"; + resets = <0x24 0x180>; + reset-names = "saradc-apb"; + #io-channel-cells = <0x01>; + status = "okay"; + vref-supply = <0x127>; + phandle = <0x150>; + }; + + mailbox@fe780000 { + compatible = "rockchip,rk3568-mailbox\0rockchip,rk3368-mailbox"; + reg = <0x00 0xfe780000 0x00 0x1000>; + interrupts = <0x00 0xb7 0x04 0x00 0xb8 0x04 0x00 0xb9 0x04 0x00 0xba 0x04>; + clocks = <0x24 0x11b>; + clock-names = "pclk_mailbox"; + #mbox-cells = <0x01>; + status = "disabled"; + }; + + phy@fe830000 { + compatible = "rockchip,rk3568-naneng-combphy"; + reg = <0x00 0xfe830000 0x00 0x100>; + clocks = <0x3a 0x22 0x24 0x17d 0x24 0x7f>; + clock-names = "refclk\0apbclk\0pipe_clk"; + assigned-clocks = <0x3a 0x22>; + assigned-clock-rates = <0x5f5e100>; + resets = <0x24 0x1c6 0x24 0x1c7>; + reset-names = "combphy-apb\0combphy"; + rockchip,pipe-grf = <0x128>; + rockchip,pipe-phy-grf = <0x129>; + #phy-cells = <0x01>; + status = "okay"; + phandle = <0x25>; + }; + + phy@fe840000 { + compatible = "rockchip,rk3568-naneng-combphy"; + reg = <0x00 0xfe840000 0x00 0x100>; + clocks = <0x3a 0x25 0x24 0x17e 0x24 0x7f>; + clock-names = "refclk\0apbclk\0pipe_clk"; + assigned-clocks = <0x3a 0x25>; + assigned-clock-rates = <0x5f5e100>; + resets = <0x24 0x1c8 0x24 0x1c9>; + reset-names = "combphy-apb\0combphy"; + rockchip,pipe-grf = <0x128>; + rockchip,pipe-phy-grf = <0x12a>; + #phy-cells = <0x01>; + status = "okay"; + phandle = <0x27>; + }; + + phy@fe850000 { + compatible = "rockchip,rk3568-dsi-dphy\0rockchip,rk3568-video-phy"; + reg = <0x00 0xfe850000 0x00 0x10000 0x00 0xfe060000 0x00 0x10000>; + reg-names = "phy\0host"; + clocks = <0x3a 0x17 0x24 0x17a 0x24 0xe8>; + clock-names = "ref\0pclk\0pclk_host"; + #clock-cells = <0x00>; + resets = <0x24 0x1bb>; + reset-names = "apb"; + power-domains = <0x26 0x09>; + #phy-cells = <0x00>; + status = "okay"; + phandle = <0x34>; + }; + + phy@fe860000 { + compatible = "rockchip,rk3568-dsi-dphy\0rockchip,rk3568-video-phy"; + reg = <0x00 0xfe860000 0x00 0x10000 0x00 0xfe070000 0x00 0x10000>; + reg-names = "phy\0host"; + clocks = <0x3a 0x19 0x24 0x17b 0x24 0xe9>; + clock-names = "ref\0pclk\0pclk_host"; + #clock-cells = <0x00>; + resets = <0x24 0x1bc>; + reset-names = "apb"; + power-domains = <0x26 0x09>; + #phy-cells = <0x00>; + status = "disabled"; + phandle = <0x37>; + }; + + csi2-dphy-hw@fe870000 { + compatible = "rockchip,rk3568-csi2-dphy-hw"; + reg = <0x00 0xfe870000 0x00 0x1000>; + clocks = <0x24 0x179>; + clock-names = "pclk"; + rockchip,grf = <0x3b>; + status = "okay"; + phandle = <0x12b>; + }; + + csi2-dphy0 { + compatible = "rockchip,rk3568-csi2-dphy"; + rockchip,hw = <0x12b>; + status = "okay"; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + #address-cells = <0x01>; + #size-cells = <0x00>; + + endpoint@1 { + reg = <0x01>; + remote-endpoint = <0x12c>; + data-lanes = <0x01 0x02>; + phandle = <0xf0>; + }; + + endpoint@2 { + reg = <0x02>; + remote-endpoint = <0x12d>; + data-lanes = <0x01 0x02 0x03 0x04>; + phandle = <0xef>; + }; + + endpoint@3 { + reg = <0x03>; + remote-endpoint = <0x12e>; + data-lanes = <0x01 0x02>; + phandle = <0xf1>; + }; + }; + + port@1 { + reg = <0x01>; + #address-cells = <0x01>; + #size-cells = <0x00>; + + endpoint@0 { + reg = <0x00>; + remote-endpoint = <0x12f>; + phandle = <0x84>; + }; + }; + }; + }; + + csi2-dphy1 { + compatible = "rockchip,rk3568-csi2-dphy"; + rockchip,hw = <0x12b>; + status = "disabled"; + }; + + csi2-dphy2 { + compatible = "rockchip,rk3568-csi2-dphy"; + rockchip,hw = <0x12b>; + status = "disabled"; + }; + + usb2-phy@fe8a0000 { + compatible = "rockchip,rk3568-usb2phy"; + reg = <0x00 0xfe8a0000 0x00 0x10000>; + clocks = <0x3a 0x13>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy"; + interrupts = <0x00 0x87 0x04>; + rockchip,usbgrf = <0x130>; + #clock-cells = <0x00>; + assigned-clocks = <0x24 0x0b>; + assigned-clock-parents = <0x2a>; + status = "okay"; + phandle = <0x2a>; + + host-port { + #phy-cells = <0x00>; + status = "okay"; + phy-supply = <0x131>; + phandle = <0x2b>; + }; + + otg-port { + #phy-cells = <0x00>; + status = "okay"; + vbus-supply = <0x132>; + phandle = <0x28>; + }; + }; + + usb2-phy@fe8b0000 { + compatible = "rockchip,rk3568-usb2phy"; + reg = <0x00 0xfe8b0000 0x00 0x10000>; + clocks = <0x3a 0x15>; + clock-names = "phyclk"; + interrupts = <0x00 0x88 0x04>; + rockchip,usbgrf = <0x133>; + #clock-cells = <0x00>; + status = "okay"; + phandle = <0x2c>; + + host-port { + #phy-cells = <0x00>; + status = "okay"; + phy-supply = <0x131>; + phandle = <0x2e>; + }; + + otg-port { + #phy-cells = <0x00>; + status = "okay"; + phy-supply = <0x131>; + phandle = <0x2d>; + }; + }; + + pinctrl { + compatible = "rockchip,rk3568-pinctrl"; + rockchip,grf = <0x3b>; + rockchip,pmu = <0x3c>; + #address-cells = <0x02>; + #size-cells = <0x02>; + ranges; + + gpio0@fdd60000 { + compatible = "rockchip,gpio-bank"; + reg = <0x00 0xfdd60000 0x00 0x100>; + interrupts = <0x00 0x21 0x04>; + clocks = <0x3a 0x2e 0x3a 0x0c>; + gpio-controller; + #gpio-cells = <0x02>; + interrupt-controller; + #interrupt-cells = <0x02>; + phandle = <0x3f>; + }; + + gpio1@fe740000 { + compatible = "rockchip,gpio-bank"; + reg = <0x00 0xfe740000 0x00 0x100>; + interrupts = <0x00 0x22 0x04>; + clocks = <0x24 0x163 0x24 0x164>; + gpio-controller; + #gpio-cells = <0x02>; + interrupt-controller; + #interrupt-cells = <0x02>; + }; + + gpio2@fe750000 { + compatible = "rockchip,gpio-bank"; + reg = <0x00 0xfe750000 0x00 0x100>; + interrupts = <0x00 0x23 0x04>; + clocks = <0x24 0x165 0x24 0x166>; + gpio-controller; + #gpio-cells = <0x02>; + interrupt-controller; + #interrupt-cells = <0x02>; + phandle = <0x8d>; + }; + + gpio3@fe760000 { + compatible = "rockchip,gpio-bank"; + reg = <0x00 0xfe760000 0x00 0x100>; + interrupts = <0x00 0x24 0x04>; + clocks = <0x24 0x167 0x24 0x168>; + gpio-controller; + #gpio-cells = <0x02>; + interrupt-controller; + #interrupt-cells = <0x02>; + phandle = <0xa8>; + }; + + gpio4@fe770000 { + compatible = "rockchip,gpio-bank"; + reg = <0x00 0xfe770000 0x00 0x100>; + interrupts = <0x00 0x25 0x04>; + clocks = <0x24 0x169 0x24 0x16a>; + gpio-controller; + #gpio-cells = <0x02>; + interrupt-controller; + #interrupt-cells = <0x02>; + phandle = <0xee>; + }; + + pcfg-pull-up { + bias-pull-up; + phandle = <0x136>; + }; + + pcfg-pull-down { + bias-pull-down; + phandle = <0x13e>; + }; + + pcfg-pull-none { + bias-disable; + phandle = <0x134>; + }; + + pcfg-pull-none-drv-level-1 { + bias-disable; + drive-strength = <0x01>; + phandle = <0x138>; + }; + + pcfg-pull-none-drv-level-2 { + bias-disable; + drive-strength = <0x02>; + phandle = <0x137>; + }; + + pcfg-pull-none-drv-level-3 { + bias-disable; + drive-strength = <0x03>; + phandle = <0x13d>; + }; + + pcfg-pull-up-drv-level-1 { + bias-pull-up; + drive-strength = <0x01>; + phandle = <0x13c>; + }; + + pcfg-pull-up-drv-level-2 { + bias-pull-up; + drive-strength = <0x02>; + phandle = <0x135>; + }; + + pcfg-pull-up-drv-level-4 { + bias-pull-up; + drive-strength = <0x04>; + phandle = <0x13a>; + }; + + pcfg-pull-none-smt { + bias-disable; + input-schmitt-enable; + phandle = <0x139>; + }; + + pcfg-output-high { + output-high; + phandle = <0x13f>; + }; + + pcfg-output-low-pull-down { + output-low; + bias-pull-down; + phandle = <0x13b>; + }; + + acodec { + + acodec-pins { + rockchip,pins = <0x01 0x09 0x05 0x134 0x01 0x01 0x05 0x134 0x01 0x00 0x05 0x134 0x01 0x07 0x05 0x134 0x01 0x08 0x05 0x134 0x01 0x03 0x05 0x134 0x01 0x05 0x05 0x134>; + phandle = <0xe3>; + }; + }; + + cam { + + camera-pwr { + rockchip,pins = <0x00 0x11 0x00 0x134>; + phandle = <0x169>; + }; + }; + + can0 { + + can0m1-pins { + rockchip,pins = <0x02 0x02 0x04 0x134 0x02 0x01 0x04 0x134>; + phandle = <0xe5>; + }; + }; + + can1 { + + can1m1-pins { + rockchip,pins = <0x04 0x12 0x03 0x134 0x04 0x13 0x03 0x134>; + phandle = <0xe6>; + }; + }; + + can2 { + + can2m1-pins { + rockchip,pins = <0x02 0x09 0x04 0x134 0x02 0x0a 0x04 0x134>; + phandle = <0xe7>; + }; + }; + + cif { + + cif-clk { + rockchip,pins = <0x04 0x10 0x01 0x134>; + phandle = <0xed>; + }; + }; + + clk32k { + + clk32k-out0 { + rockchip,pins = <0x00 0x08 0x02 0x134>; + phandle = <0x23>; + }; + }; + + ebc { + + ebc-pins { + rockchip,pins = <0x04 0x10 0x02 0x134 0x04 0x0b 0x02 0x134 0x04 0x0c 0x02 0x134 0x04 0x06 0x02 0x134 0x04 0x11 0x02 0x134 0x03 0x16 0x02 0x134 0x03 0x17 0x02 0x134 0x03 0x18 0x02 0x134 0x03 0x19 0x02 0x134 0x03 0x1a 0x02 0x134 0x03 0x1b 0x02 0x134 0x03 0x1c 0x02 0x134 0x03 0x1d 0x02 0x134 0x03 0x1e 0x02 0x134 0x03 0x1f 0x02 0x134 0x04 0x00 0x02 0x134 0x04 0x01 0x02 0x134 0x04 0x02 0x02 0x134 0x04 0x03 0x02 0x134 0x04 0x04 0x02 0x134 0x04 0x05 0x02 0x134 0x04 0x0e 0x02 0x134 0x04 0x0f 0x02 0x134>; + phandle = <0x74>; + }; + }; + + gmac0 { + + gmac0-miim { + rockchip,pins = <0x02 0x13 0x02 0x134 0x02 0x14 0x02 0x134>; + phandle = <0x148>; + }; + + gmac0-rx-bus2 { + rockchip,pins = <0x02 0x0e 0x01 0x134 0x02 0x0f 0x02 0x134 0x02 0x10 0x02 0x134>; + phandle = <0x14a>; + }; + + gmac0-tx-bus2 { + rockchip,pins = <0x02 0x0b 0x01 0x137 0x02 0x0c 0x01 0x137 0x02 0x0d 0x01 0x134>; + phandle = <0x149>; + }; + + gmac0-rgmii-clk { + rockchip,pins = <0x02 0x05 0x02 0x134 0x02 0x08 0x02 0x138>; + phandle = <0x14b>; + }; + + gmac0-rgmii-bus { + rockchip,pins = <0x02 0x03 0x02 0x134 0x02 0x04 0x02 0x134 0x02 0x06 0x02 0x137 0x02 0x07 0x02 0x137>; + phandle = <0x14c>; + }; + }; + + gmac1 { + + gmac1m1-miim { + rockchip,pins = <0x04 0x0e 0x03 0x134 0x04 0x0f 0x03 0x134>; + phandle = <0x8e>; + }; + + gmac1m1-rx-bus2 { + rockchip,pins = <0x04 0x07 0x03 0x134 0x04 0x08 0x03 0x134 0x04 0x09 0x03 0x134>; + phandle = <0x90>; + }; + + gmac1m1-tx-bus2 { + rockchip,pins = <0x04 0x04 0x03 0x137 0x04 0x05 0x03 0x137 0x04 0x06 0x03 0x134>; + phandle = <0x8f>; + }; + + gmac1m1-rgmii-clk { + rockchip,pins = <0x04 0x03 0x03 0x134 0x04 0x00 0x03 0x138>; + phandle = <0x91>; + }; + + gmac1m1-rgmii-bus { + rockchip,pins = <0x04 0x01 0x03 0x134 0x04 0x02 0x03 0x134 0x03 0x1e 0x03 0x137 0x03 0x1f 0x03 0x137>; + phandle = <0x92>; + }; + }; + + hdmitx { + + hdmitxm0-cec { + rockchip,pins = <0x04 0x19 0x01 0x134>; + phandle = <0xb3>; + }; + + hdmitx-scl { + rockchip,pins = <0x04 0x17 0x01 0x134>; + phandle = <0xb1>; + }; + + hdmitx-sda { + rockchip,pins = <0x04 0x18 0x01 0x134>; + phandle = <0xb2>; + }; + }; + + i2c0 { + + i2c0-xfer { + rockchip,pins = <0x00 0x09 0x01 0x139 0x00 0x0a 0x01 0x139>; + phandle = <0x3d>; + }; + }; + + i2c1 { + + i2c1-xfer { + rockchip,pins = <0x00 0x0b 0x01 0x139 0x00 0x0c 0x01 0x139>; + phandle = <0xe8>; + }; + }; + + i2c2 { + + i2c2m0-xfer { + rockchip,pins = <0x00 0x0d 0x01 0x139 0x00 0x0e 0x01 0x139>; + phandle = <0xea>; + }; + }; + + i2c3 { + + i2c3m0-xfer { + rockchip,pins = <0x01 0x01 0x01 0x139 0x01 0x00 0x01 0x139>; + phandle = <0xeb>; + }; + }; + + i2c4 { + + i2c4m0-xfer { + rockchip,pins = <0x04 0x0b 0x01 0x139 0x04 0x0a 0x01 0x139>; + phandle = <0xec>; + }; + }; + + i2c5 { + + i2c5m0-xfer { + rockchip,pins = <0x03 0x0b 0x04 0x139 0x03 0x0c 0x04 0x139>; + phandle = <0xf2>; + }; + }; + + i2s1 { + + i2s1m0-lrckrx { + rockchip,pins = <0x01 0x06 0x01 0x13a>; + phandle = <0xcd>; + }; + + i2s1m0-lrcktx { + rockchip,pins = <0x01 0x05 0x01 0x13a>; + phandle = <0xcc>; + }; + + i2s1m0-mclk { + rockchip,pins = <0x01 0x02 0x01 0x13a>; + phandle = <0x47>; + }; + + i2s1m0-sclkrx { + rockchip,pins = <0x01 0x04 0x01 0x13a>; + phandle = <0xcb>; + }; + + i2s1m0-sclktx { + rockchip,pins = <0x01 0x03 0x01 0x13a>; + phandle = <0xca>; + }; + + i2s1m0-sdi0 { + rockchip,pins = <0x01 0x0b 0x01 0x13a>; + phandle = <0xcf>; + }; + + i2s1m0-sdi1 { + rockchip,pins = <0x01 0x0a 0x02 0x13a>; + phandle = <0xd0>; + }; + + i2s1m0-sdi2 { + rockchip,pins = <0x01 0x09 0x02 0x13a>; + phandle = <0xd1>; + }; + + i2s1m0-sdi3 { + rockchip,pins = <0x01 0x08 0x02 0x13a>; + phandle = <0xd2>; + }; + + i2s1m0-sdo0 { + rockchip,pins = <0x01 0x07 0x01 0x13a>; + phandle = <0xce>; + }; + }; + + i2s2 { + + i2s2m0-lrcktx { + rockchip,pins = <0x02 0x13 0x01 0x139>; + phandle = <0xd4>; + }; + + i2s2m0-sclktx { + rockchip,pins = <0x02 0x12 0x01 0x139>; + phandle = <0xd3>; + }; + + i2s2m0-sdi { + rockchip,pins = <0x02 0x15 0x01 0x134>; + phandle = <0xd5>; + }; + + i2s2m0-sdo { + rockchip,pins = <0x02 0x14 0x01 0x134>; + phandle = <0xd6>; + }; + }; + + i2s3 { + + i2s3m0-lrck { + rockchip,pins = <0x03 0x04 0x04 0x139>; + phandle = <0xd8>; + }; + + i2s3m0-sclk { + rockchip,pins = <0x03 0x03 0x04 0x139>; + phandle = <0xd7>; + }; + + i2s3m0-sdi { + rockchip,pins = <0x03 0x06 0x04 0x134>; + phandle = <0xd9>; + }; + + i2s3m0-sdo { + rockchip,pins = <0x03 0x05 0x04 0x134>; + phandle = <0xda>; + }; + }; + + lcdc { + + lcdc-ctl { + rockchip,pins = <0x03 0x00 0x01 0x134 0x02 0x18 0x01 0x134 0x02 0x19 0x01 0x134 0x02 0x1a 0x01 0x134 0x02 0x1b 0x01 0x134 0x02 0x1c 0x01 0x134 0x02 0x1d 0x01 0x134 0x02 0x1e 0x01 0x134 0x02 0x1f 0x01 0x134 0x03 0x01 0x01 0x134 0x03 0x02 0x01 0x134 0x03 0x03 0x01 0x134 0x03 0x04 0x01 0x134 0x03 0x05 0x01 0x134 0x03 0x06 0x01 0x134 0x03 0x07 0x01 0x134 0x03 0x08 0x01 0x134 0x03 0x09 0x01 0x134 0x03 0x0a 0x01 0x134 0x03 0x0b 0x01 0x134 0x03 0x0c 0x01 0x134 0x03 0x0d 0x01 0x134 0x03 0x0e 0x01 0x134 0x03 0x0f 0x01 0x134 0x03 0x10 0x01 0x134 0x03 0x13 0x01 0x134 0x03 0x11 0x01 0x134 0x03 0x12 0x01 0x134>; + phandle = <0x36>; + }; + }; + + pdm { + + pdmm0-clk { + rockchip,pins = <0x01 0x06 0x03 0x134>; + phandle = <0xdb>; + }; + + pdmm0-clk1 { + rockchip,pins = <0x01 0x04 0x03 0x134>; + phandle = <0xdc>; + }; + + pdmm0-sdi0 { + rockchip,pins = <0x01 0x0b 0x02 0x134>; + phandle = <0xdd>; + }; + + pdmm0-sdi1 { + rockchip,pins = <0x01 0x0a 0x03 0x134>; + phandle = <0xde>; + }; + + pdmm0-sdi2 { + rockchip,pins = <0x01 0x09 0x03 0x134>; + phandle = <0xdf>; + }; + + pdmm0-sdi3 { + rockchip,pins = <0x01 0x08 0x03 0x134>; + phandle = <0xe0>; + }; + }; + + pmic { + + pmic_int { + rockchip,pins = <0x00 0x03 0x00 0x136>; + phandle = <0x40>; + }; + + soc_slppin_pin { + rockchip,pins = <0x00 0x02 0x00 0x13b>; + phandle = <0x43>; + }; + + soc_slppin_slp { + rockchip,pins = <0x00 0x02 0x01 0x136>; + phandle = <0x41>; + }; + + soc_slppin_rst { + rockchip,pins = <0x00 0x02 0x02 0x134>; + }; + }; + + pwm0 { + + pwm0m0-pins { + rockchip,pins = <0x00 0x0f 0x01 0x134>; + phandle = <0x4a>; + }; + }; + + pwm1 { + + pwm1m0-pins { + rockchip,pins = <0x00 0x10 0x01 0x134>; + phandle = <0x4b>; + }; + }; + + pwm2 { + + pwm2m0-pins { + rockchip,pins = <0x00 0x11 0x01 0x134>; + phandle = <0x4c>; + }; + }; + + pwm3 { + + pwm3-pins { + rockchip,pins = <0x00 0x12 0x01 0x134>; + phandle = <0x4d>; + }; + }; + + pwm4 { + + pwm4-pins { + rockchip,pins = <0x00 0x13 0x01 0x134>; + phandle = <0x110>; + }; + }; + + pwm5 { + + pwm5-pins { + rockchip,pins = <0x00 0x14 0x01 0x134>; + phandle = <0x111>; + }; + }; + + pwm6 { + + pwm6-pins { + rockchip,pins = <0x00 0x15 0x01 0x134>; + phandle = <0x112>; + }; + }; + + pwm7 { + + pwm7-pins { + rockchip,pins = <0x00 0x16 0x01 0x134>; + phandle = <0x113>; + }; + }; + + pwm8 { + + pwm8m0-pins { + rockchip,pins = <0x03 0x09 0x05 0x134>; + phandle = <0x114>; + }; + }; + + pwm9 { + + pwm9m0-pins { + rockchip,pins = <0x03 0x0a 0x05 0x134>; + phandle = <0x115>; + }; + }; + + pwm10 { + + pwm10m0-pins { + rockchip,pins = <0x03 0x0d 0x05 0x134>; + phandle = <0x116>; + }; + }; + + pwm11 { + + pwm11m0-pins { + rockchip,pins = <0x03 0x0e 0x05 0x134>; + phandle = <0x117>; + }; + }; + + pwm12 { + + pwm12m0-pins { + rockchip,pins = <0x03 0x0f 0x02 0x134>; + phandle = <0x118>; + }; + }; + + pwm13 { + + pwm13m0-pins { + rockchip,pins = <0x03 0x10 0x02 0x134>; + phandle = <0x119>; + }; + }; + + pwm14 { + + pwm14m0-pins { + rockchip,pins = <0x03 0x14 0x01 0x134>; + phandle = <0x11a>; + }; + }; + + pwm15 { + + pwm15m0-pins { + rockchip,pins = <0x03 0x15 0x01 0x134>; + phandle = <0x11b>; + }; + }; + + scr { + + scr-pins { + rockchip,pins = <0x01 0x02 0x03 0x134 0x01 0x07 0x03 0x136 0x01 0x03 0x03 0x136 0x01 0x05 0x03 0x134>; + phandle = <0xe4>; + }; + }; + + sdmmc0 { + + sdmmc0-bus4 { + rockchip,pins = <0x01 0x1d 0x01 0x135 0x01 0x1e 0x01 0x135 0x01 0x1f 0x01 0x135 0x02 0x00 0x01 0x135>; + phandle = <0xc5>; + }; + + sdmmc0-clk { + rockchip,pins = <0x02 0x02 0x01 0x135>; + phandle = <0xc6>; + }; + + sdmmc0-cmd { + rockchip,pins = <0x02 0x01 0x01 0x135>; + phandle = <0xc7>; + }; + + sdmmc0-det { + rockchip,pins = <0x00 0x04 0x01 0x136>; + phandle = <0xc8>; + }; + }; + + sdmmc2 { + + sdmmc2m0-bus4 { + rockchip,pins = <0x03 0x16 0x03 0x135 0x03 0x17 0x03 0x135 0x03 0x18 0x03 0x135 0x03 0x19 0x03 0x135>; + phandle = <0x86>; + }; + + sdmmc2m0-clk { + rockchip,pins = <0x03 0x1b 0x03 0x135>; + phandle = <0x88>; + }; + + sdmmc2m0-cmd { + rockchip,pins = <0x03 0x1a 0x03 0x135>; + phandle = <0x87>; + }; + }; + + spdif { + + spdifm0-tx { + rockchip,pins = <0x01 0x04 0x04 0x134>; + phandle = <0xe2>; + }; + }; + + spi0 { + + spi0m0-pins { + rockchip,pins = <0x00 0x0d 0x02 0x134 0x00 0x15 0x02 0x134 0x00 0x0e 0x02 0x134>; + phandle = <0xf7>; + }; + + spi0m0-cs0 { + rockchip,pins = <0x00 0x16 0x02 0x134>; + phandle = <0xf5>; + }; + + spi0m0-cs1 { + rockchip,pins = <0x00 0x14 0x02 0x134>; + phandle = <0xf6>; + }; + }; + + spi1 { + + spi1m0-pins { + rockchip,pins = <0x02 0x0d 0x03 0x134 0x02 0x0e 0x03 0x134 0x02 0x0f 0x04 0x134>; + phandle = <0xfb>; + }; + + spi1m0-cs0 { + rockchip,pins = <0x02 0x10 0x04 0x134>; + phandle = <0xf9>; + }; + + spi1m0-cs1 { + rockchip,pins = <0x02 0x16 0x03 0x134>; + phandle = <0xfa>; + }; + }; + + spi2 { + + spi2m0-pins { + rockchip,pins = <0x02 0x11 0x04 0x134 0x02 0x12 0x04 0x134 0x02 0x13 0x04 0x134>; + phandle = <0xff>; + }; + + spi2m0-cs0 { + rockchip,pins = <0x02 0x14 0x04 0x134>; + phandle = <0xfd>; + }; + + spi2m0-cs1 { + rockchip,pins = <0x02 0x15 0x04 0x134>; + phandle = <0xfe>; + }; + }; + + spi3 { + + spi3m0-pins { + rockchip,pins = <0x04 0x0b 0x04 0x134 0x04 0x08 0x04 0x134 0x04 0x0a 0x04 0x134>; + phandle = <0x103>; + }; + + spi3m0-cs0 { + rockchip,pins = <0x04 0x06 0x04 0x134>; + phandle = <0x101>; + }; + + spi3m0-cs1 { + rockchip,pins = <0x04 0x07 0x04 0x134>; + phandle = <0x102>; + }; + }; + + tsadc { + + tsadc-shutorg { + rockchip,pins = <0x00 0x01 0x02 0x134>; + phandle = <0x122>; + }; + }; + + uart0 { + + uart0-xfer { + rockchip,pins = <0x00 0x10 0x03 0x136 0x00 0x11 0x03 0x136>; + phandle = <0x49>; + }; + }; + + uart1 { + + uart1m0-xfer { + rockchip,pins = <0x02 0x0b 0x02 0x136 0x02 0x0c 0x02 0x136>; + phandle = <0x105>; + }; + + uart1m0-ctsn { + rockchip,pins = <0x02 0x0e 0x02 0x134>; + phandle = <0x106>; + }; + }; + + uart2 { + + uart2m0-xfer { + rockchip,pins = <0x00 0x18 0x01 0x136 0x00 0x19 0x01 0x136>; + phandle = <0x107>; + }; + }; + + uart3 { + + uart3m1-xfer { + rockchip,pins = <0x03 0x10 0x04 0x136 0x03 0x0f 0x04 0x136>; + phandle = <0x108>; + }; + }; + + uart4 { + + uart4m1-xfer { + rockchip,pins = <0x03 0x09 0x04 0x136 0x03 0x0a 0x04 0x136>; + phandle = <0x109>; + }; + }; + + uart5 { + + uart5m0-xfer { + rockchip,pins = <0x02 0x01 0x03 0x136 0x02 0x02 0x03 0x136>; + phandle = <0x10a>; + }; + }; + + uart6 { + + uart6m0-xfer { + rockchip,pins = <0x02 0x03 0x03 0x136 0x02 0x04 0x03 0x136>; + phandle = <0x10b>; + }; + }; + + uart7 { + + uart7m0-xfer { + rockchip,pins = <0x02 0x05 0x03 0x136 0x02 0x06 0x03 0x136>; + phandle = <0x10c>; + }; + }; + + uart8 { + + uart8m0-xfer { + rockchip,pins = <0x02 0x16 0x02 0x136 0x02 0x15 0x03 0x136>; + phandle = <0x10d>; + }; + + uart8m0-ctsn { + rockchip,pins = <0x02 0x0a 0x03 0x134>; + phandle = <0x10e>; + }; + + uart8m0-rtsn { + rockchip,pins = <0x02 0x09 0x03 0x134>; + phandle = <0x164>; + }; + }; + + uart9 { + + uart9m0-xfer { + rockchip,pins = <0x02 0x07 0x03 0x136 0x02 0x08 0x03 0x136>; + phandle = <0x10f>; + }; + }; + + spi0-hs { + + spi0m0-pins { + rockchip,pins = <0x00 0x0d 0x02 0x13c 0x00 0x15 0x02 0x13c 0x00 0x0e 0x02 0x13c>; + phandle = <0xf8>; + }; + }; + + spi1-hs { + + spi1m0-pins { + rockchip,pins = <0x02 0x0d 0x03 0x13c 0x02 0x0e 0x03 0x13c 0x02 0x0f 0x04 0x13c>; + phandle = <0xfc>; + }; + }; + + spi2-hs { + + spi2m0-pins { + rockchip,pins = <0x02 0x11 0x04 0x13c 0x02 0x12 0x04 0x13c 0x02 0x13 0x04 0x13c>; + phandle = <0x100>; + }; + }; + + spi3-hs { + + spi3m0-pins { + rockchip,pins = <0x04 0x0b 0x04 0x13c 0x04 0x08 0x04 0x13c 0x04 0x0a 0x04 0x13c>; + phandle = <0x104>; + }; + }; + + gpio-func { + + tsadc-gpio-func { + rockchip,pins = <0x00 0x01 0x00 0x134>; + phandle = <0x121>; + }; + }; + + mxc6655xa { + + mxc6655xa_irq_gpio { + rockchip,pins = <0x03 0x11 0x00 0x134>; + phandle = <0xf3>; + }; + }; + + touch { + + touch-gpio { + rockchip,pins = <0x00 0x0d 0x00 0x136 0x00 0x0e 0x00 0x134>; + phandle = <0xe9>; + }; + }; + + sdio-pwrseq { + + wifi-enable-h { + rockchip,pins = <0x03 0x1d 0x00 0x134>; + phandle = <0x162>; + }; + }; + + usb { + + vcc5v0-host-en { + rockchip,pins = <0x00 0x06 0x00 0x134>; + phandle = <0x15f>; + }; + + vcc5v0-otg-en { + rockchip,pins = <0x00 0x05 0x00 0x134>; + phandle = <0x160>; + }; + }; + + wireless-bluetooth { + + uart8-gpios { + rockchip,pins = <0x02 0x09 0x00 0x134>; + phandle = <0x165>; + }; + }; + + headphone { + + hp-det { + rockchip,pins = <0x03 0x13 0x00 0x13e>; + phandle = <0x166>; + }; + }; + + leds-gpio { + rockchip,pins = <0x04 0x12 0x00 0x136 0x04 0x13 0x00 0x136 0x04 0x15 0x00 0x136>; + }; + + wireless-wlan { + + wifi-host-wake-irq { + rockchip,pins = <0x03 0x1c 0x00 0x13e>; + phandle = <0x163>; + }; + }; + + rtc { + + rtc-int { + rockchip,pins = <0x00 0x1b 0x00 0x136>; + phandle = <0xf4>; + }; + }; + + mipi_pwren { + + mipi_power_en { + rockchip,pins = <0x03 0x0d 0x00 0x13f>; + phandle = <0xa7>; + }; + }; + }; + + edac { + compatible = "rockchip,rk3568-edac"; + interrupts = <0x00 0xad 0x04 0x00 0xaf 0x04>; + interrupt-names = "ce\0ue"; + status = "disabled"; + }; + + external-gmac0-clock { + compatible = "fixed-clock"; + clock-frequency = <0x7735940>; + clock-output-names = "gmac0_clkin"; + #clock-cells = <0x00>; + }; + + xpcs-gmac0-clock { + compatible = "fixed-clock"; + clock-frequency = <0x7735940>; + clock-output-names = "clk_gmac0_xpcs_mii"; + #clock-cells = <0x00>; + }; + + sata@fc000000 { + compatible = "rockchip,rk3568-dwc-ahci\0snps,dwc-ahci"; + reg = <0x00 0xfc000000 0x00 0x1000>; + clocks = <0x24 0x96 0x24 0x97 0x24 0x98>; + clock-names = "sata\0pmalive\0rxoob"; + interrupts = <0x00 0x5e 0x04>; + interrupt-names = "hostc"; + phys = <0x29 0x01>; + phy-names = "sata-phy"; + ports-implemented = <0x01>; + power-domains = <0x26 0x0f>; + status = "disabled"; + }; + + syscon@fdc70000 { + compatible = "rockchip,pipe-phy-grf\0syscon"; + reg = <0x00 0xfdc70000 0x00 0x1000>; + phandle = <0x14e>; + }; + + syscon@fdcb8000 { + compatible = "rockchip,pcie30-phy-grf\0syscon"; + reg = <0x00 0xfdcb8000 0x00 0x10000>; + phandle = <0x14f>; + }; + + qos@fe190080 { + compatible = "rockchip,rk3568-qos\0syscon"; + reg = <0x00 0xfe190080 0x00 0x20>; + phandle = <0x62>; + }; + + qos@fe190100 { + compatible = "rockchip,rk3568-qos\0syscon"; + reg = <0x00 0xfe190100 0x00 0x20>; + phandle = <0x63>; + }; + + qos@fe190200 { + compatible = "rockchip,rk3568-qos\0syscon"; + reg = <0x00 0xfe190200 0x00 0x20>; + phandle = <0x64>; + }; + + pcie@fe270000 { + compatible = "rockchip,rk3568-pcie\0snps,dw-pcie"; + #address-cells = <0x03>; + #size-cells = <0x02>; + bus-range = <0x10 0x1f>; + clocks = <0x24 0x88 0x24 0x89 0x24 0x8a 0x24 0x8b 0x24 0x8c>; + clock-names = "aclk_mst\0aclk_slv\0aclk_dbi\0pclk\0aux"; + device_type = "pci"; + interrupts = <0x00 0xa0 0x04 0x00 0x9f 0x04 0x00 0x9e 0x04 0x00 0x9d 0x04 0x00 0x9c 0x04>; + interrupt-names = "sys\0pmc\0msg\0legacy\0err"; + #interrupt-cells = <0x01>; + interrupt-map-mask = <0x00 0x00 0x00 0x07>; + interrupt-map = <0x00 0x00 0x00 0x01 0x140 0x00 0x00 0x00 0x00 0x02 0x140 0x01 0x00 0x00 0x00 0x03 0x140 0x02 0x00 0x00 0x00 0x04 0x140 0x03>; + linux,pci-domain = <0x01>; + num-ib-windows = <0x06>; + num-ob-windows = <0x02>; + num-viewport = <0x08>; + max-link-speed = <0x03>; + msi-map = <0x1000 0xc3 0x1000 0x1000>; + num-lanes = <0x01>; + phys = <0x141>; + phy-names = "pcie-phy"; + power-domains = <0x26 0x0f>; + reg = <0x03 0xc0400000 0x00 0x400000 0x00 0xfe270000 0x00 0x10000 0x00 0xf2000000 0x00 0x100000>; + reg-names = "pcie-dbi\0pcie-apb\0config"; + ranges = <0x1000000 0x00 0xf2100000 0x00 0xf2100000 0x00 0x100000 0x2000000 0x00 0xf2200000 0x00 0xf2200000 0x00 0x1e00000 0x3000000 0x03 0x40000000 0x03 0x40000000 0x00 0x40000000>; + resets = <0x24 0xb1>; + reset-names = "pipe"; + status = "disabled"; + + legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0x00>; + #interrupt-cells = <0x01>; + interrupt-parent = <0x01>; + interrupts = <0x00 0x9d 0x01>; + phandle = <0x140>; + }; + }; + + pcie@fe280000 { + compatible = "rockchip,rk3568-pcie\0snps,dw-pcie"; + #address-cells = <0x03>; + #size-cells = <0x02>; + bus-range = <0x20 0x2f>; + clocks = <0x24 0x8f 0x24 0x90 0x24 0x91 0x24 0x92 0x24 0x93>; + clock-names = "aclk_mst\0aclk_slv\0aclk_dbi\0pclk\0aux"; + device_type = "pci"; + interrupts = <0x00 0xa5 0x04 0x00 0xa4 0x04 0x00 0xa3 0x04 0x00 0xa2 0x04 0x00 0xa1 0x04>; + interrupt-names = "sys\0pmc\0msg\0legacy\0err"; + #interrupt-cells = <0x01>; + interrupt-map-mask = <0x00 0x00 0x00 0x07>; + interrupt-map = <0x00 0x00 0x00 0x01 0x142 0x00 0x00 0x00 0x00 0x02 0x142 0x01 0x00 0x00 0x00 0x03 0x142 0x02 0x00 0x00 0x00 0x04 0x142 0x03>; + linux,pci-domain = <0x02>; + num-ib-windows = <0x06>; + num-viewport = <0x08>; + num-ob-windows = <0x02>; + max-link-speed = <0x03>; + msi-map = <0x2000 0xc3 0x2000 0x1000>; + num-lanes = <0x02>; + phys = <0x141>; + phy-names = "pcie-phy"; + power-domains = <0x26 0x0f>; + reg = <0x03 0xc0800000 0x00 0x400000 0x00 0xfe280000 0x00 0x10000 0x00 0xf0000000 0x00 0x100000>; + reg-names = "pcie-dbi\0pcie-apb\0config"; + ranges = <0x1000000 0x00 0xf0100000 0x00 0xf0100000 0x00 0x100000 0x2000000 0x00 0xf0200000 0x00 0xf0200000 0x00 0x1e00000 0x3000000 0x03 0x80000000 0x03 0x80000000 0x00 0x40000000>; + resets = <0x24 0xc1>; + reset-names = "pipe"; + status = "okay"; + reset-gpios = <0x8d 0x1e 0x00>; + vpcie3v3-supply = <0x143>; + + legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0x00>; + #interrupt-cells = <0x01>; + interrupt-parent = <0x01>; + interrupts = <0x00 0xa2 0x01>; + phandle = <0x142>; + }; + }; + + uio@fe2a0000 { + compatible = "rockchip,uio-gmac"; + reg = <0x00 0xfe2a0000 0x00 0x10000>; + rockchip,ethernet = <0x144>; + status = "disabled"; + }; + + ethernet@fe2a0000 { + compatible = "rockchip,rk3568-gmac\0snps,dwmac-4.20a"; + reg = <0x00 0xfe2a0000 0x00 0x10000>; + interrupts = <0x00 0x1b 0x04 0x00 0x18 0x04>; + interrupt-names = "macirq\0eth_wake_irq"; + clocks = <0x24 0x182 0x24 0x185 0x24 0x185 0x24 0xb8 0x24 0xb4 0x24 0xb5 0x24 0x185 0x24 0xb9 0x24 0xac 0x24 0xab>; + clock-names = "stmmaceth\0mac_clk_rx\0mac_clk_tx\0clk_mac_refout\0aclk_mac\0pclk_mac\0clk_mac_speed\0ptp_ref\0pclk_xpcs\0clk_xpcs_eee"; + resets = <0x24 0xd7>; + reset-names = "stmmaceth"; + rockchip,grf = <0x3b>; + snps,axi-config = <0x145>; + snps,mixed-burst; + snps,mtl-rx-config = <0x146>; + snps,mtl-tx-config = <0x147>; + snps,tso; + status = "okay"; + phy-mode = "rgmii"; + clock_in_out = "output"; + snps,reset-gpio = <0x8d 0x1b 0x01>; + snps,reset-active-low; + snps,reset-delays-us = <0x00 0x4e20 0x186a0>; + assigned-clocks = <0x24 0x185 0x24 0x182>; + assigned-clock-parents = <0x24 0x183 0x24 0xb6>; + assigned-clock-rates = <0x00 0x7735940>; + pinctrl-names = "default"; + pinctrl-0 = <0x148 0x149 0x14a 0x14b 0x14c>; + tx_delay = <0x2d>; + rx_delay = <0x13>; + phy-handle = <0x14d>; + phandle = <0x144>; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <0x01>; + #size-cells = <0x00>; + + phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x00>; + phandle = <0x14d>; + }; + }; + + stmmac-axi-config { + snps,blen = <0x00 0x00 0x00 0x00 0x10 0x08 0x04>; + snps,rd_osr_lmt = <0x08>; + snps,wr_osr_lmt = <0x04>; + phandle = <0x145>; + }; + + rx-queues-config { + snps,rx-queues-to-use = <0x01>; + phandle = <0x146>; + + queue0 { + }; + }; + + tx-queues-config { + snps,tx-queues-to-use = <0x01>; + phandle = <0x147>; + + queue0 { + }; + }; + }; + + phy@fe820000 { + compatible = "rockchip,rk3568-naneng-combphy"; + reg = <0x00 0xfe820000 0x00 0x100>; + clocks = <0x3a 0x1f 0x24 0x17c 0x24 0x7f>; + clock-names = "refclk\0apbclk\0pipe_clk"; + assigned-clocks = <0x3a 0x1f>; + assigned-clock-rates = <0x5f5e100>; + resets = <0x24 0x1c4 0x24 0x1c5>; + reset-names = "combphy-apb\0combphy"; + rockchip,pipe-grf = <0x128>; + rockchip,pipe-phy-grf = <0x14e>; + #phy-cells = <0x01>; + status = "okay"; + phandle = <0x29>; + }; + + phy@fe8c0000 { + compatible = "rockchip,rk3568-pcie3-phy"; + reg = <0x00 0xfe8c0000 0x00 0x20000>; + #phy-cells = <0x00>; + clocks = <0x3a 0x26 0x3a 0x27 0x24 0x177>; + clock-names = "refclk_m\0refclk_n\0pclk"; + resets = <0x24 0x1be>; + reset-names = "phy"; + rockchip,pipe-grf = <0x128>; + rockchip,phy-grf = <0x14f>; + status = "okay"; + phandle = <0x141>; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <0x150 0x00>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <0x1b7740>; + poll-interval = <0x64>; + + vol-up-key { + label = "volume up"; + linux,code = <0x73>; + press-threshold-microvolt = <0x4e20>; + }; + + vol-down-key { + label = "volume down"; + linux,code = <0x72>; + press-threshold-microvolt = <0x61a80>; + }; + + menu-key { + label = "menu"; + linux,code = <0x8b>; + press-threshold-microvolt = <0x1312d0>; + }; + + mute-key { + linux,code = <0x71>; + label = "mute"; + press-threshold-microvolt = <0xcf850>; + }; + }; + + audiopwmout-diff { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,audiopwmout-diff"; + simple-audio-card,mclk-fs = <0x100>; + simple-audio-card,bitclock-master = <0x151>; + simple-audio-card,frame-master = <0x151>; + + simple-audio-card,cpu { + sound-dai = <0x152>; + }; + + simple-audio-card,codec { + sound-dai = <0x153>; + phandle = <0x151>; + }; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <0x154 0x00 0x61a8 0x00>; + brightness-levels = <0x00 0x14 0x14 0x15 0x15 0x16 0x16 0x17 0x17 0x18 0x18 0x19 0x19 0x1a 0x1a 0x1b 0x1b 0x1c 0x1c 0x1d 0x1d 0x1e 0x1e 0x1f 0x1f 0x20 0x20 0x21 0x21 0x22 0x22 0x23 0x23 0x24 0x24 0x25 0x25 0x26 0x26 0x27 0x28 0x29 0x2a 0x2b 0x2c 0x2d 0x2e 0x2f 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3a 0x3b 0x3c 0x3d 0x3e 0x3f 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4a 0x4b 0x4c 0x4d 0x4e 0x4f 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5a 0x5b 0x5c 0x5d 0x5e 0x5f 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6a 0x6b 0x6c 0x6d 0x6e 0x6f 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7a 0x7b 0x7c 0x7d 0x7e 0x7f 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9a 0x9b 0x9c 0x9d 0x9e 0x9f 0xa0 0xa1 0xa2 0xa3 0xa4 0xa5 0xa6 0xa7 0xa8 0xa9 0xaa 0xab 0xac 0xad 0xae 0xaf 0xb0 0xb1 0xb2 0xb3 0xb4 0xb5 0xb6 0xb7 0xb8 0xb9 0xba 0xbb 0xbc 0xbd 0xbe 0xbf 0xc0 0xc1 0xc2 0xc3 0xc4 0xc5 0xc6 0xc7 0xc8 0xc9 0xca 0xcb 0xcc 0xcd 0xce 0xcf 0xd0 0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 0xd7 0xd8 0xd9 0xda 0xdb 0xdc 0xdd 0xde 0xdf 0xe0 0xe1 0xe2 0xe3 0xe4 0xe5 0xe6 0xe7 0xe8 0xe9 0xea 0xeb 0xec 0xed 0xee 0xef 0xf0 0xf1 0xf2 0xf3 0xf4 0xf5 0xf6 0xf7 0xf8 0xf9 0xfa 0xfb 0xfc 0xfd 0xfe 0xff>; + default-brightness-level = <0xc8>; + status = "okay"; + phandle = <0xa5>; + }; + + backlight1 { + compatible = "pwm-backlight"; + pwms = <0x155 0x00 0x61a8 0x00>; + brightness-levels = <0x00 0x14 0x14 0x15 0x15 0x16 0x16 0x17 0x17 0x18 0x18 0x19 0x19 0x1a 0x1a 0x1b 0x1b 0x1c 0x1c 0x1d 0x1d 0x1e 0x1e 0x1f 0x1f 0x20 0x20 0x21 0x21 0x22 0x22 0x23 0x23 0x24 0x24 0x25 0x25 0x26 0x26 0x27 0x28 0x29 0x2a 0x2b 0x2c 0x2d 0x2e 0x2f 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3a 0x3b 0x3c 0x3d 0x3e 0x3f 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4a 0x4b 0x4c 0x4d 0x4e 0x4f 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5a 0x5b 0x5c 0x5d 0x5e 0x5f 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6a 0x6b 0x6c 0x6d 0x6e 0x6f 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7a 0x7b 0x7c 0x7d 0x7e 0x7f 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9a 0x9b 0x9c 0x9d 0x9e 0x9f 0xa0 0xa1 0xa2 0xa3 0xa4 0xa5 0xa6 0xa7 0xa8 0xa9 0xaa 0xab 0xac 0xad 0xae 0xaf 0xb0 0xb1 0xb2 0xb3 0xb4 0xb5 0xb6 0xb7 0xb8 0xb9 0xba 0xbb 0xbc 0xbd 0xbe 0xbf 0xc0 0xc1 0xc2 0xc3 0xc4 0xc5 0xc6 0xc7 0xc8 0xc9 0xca 0xcb 0xcc 0xcd 0xce 0xcf 0xd0 0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 0xd7 0xd8 0xd9 0xda 0xdb 0xdc 0xdd 0xde 0xdf 0xe0 0xe1 0xe2 0xe3 0xe4 0xe5 0xe6 0xe7 0xe8 0xe9 0xea 0xeb 0xec 0xed 0xee 0xef 0xf0 0xf1 0xf2 0xf3 0xf4 0xf5 0xf6 0xf7 0xf8 0xf9 0xfa 0xfb 0xfc 0xfd 0xfe 0xff>; + default-brightness-level = <0xc8>; + phandle = <0xad>; + }; + + dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0xb71b00>; + regulator-max-microvolt = <0xb71b00>; + phandle = <0x15e>; + }; + + leds { + compatible = "gpio-leds"; + + work { + gpios = <0x3f 0x10 0x00>; + linux,default-trigger = "heartbeat"; + }; + }; + + dummy-codec { + status = "disabled"; + compatible = "rockchip,dummy-codec"; + #sound-dai-cells = <0x00>; + phandle = <0x157>; + }; + + pdm-mic-array { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,name = "rockchip,pdm-mic-array"; + + simple-audio-card,cpu { + sound-dai = <0x156>; + }; + + simple-audio-card,codec { + sound-dai = <0x157>; + }; + }; + + rk809-sound { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,rk809-codec"; + simple-audio-card,mclk-fs = <0x100>; + + simple-audio-card,cpu { + sound-dai = <0xe1>; + }; + + simple-audio-card,codec { + sound-dai = <0x158>; + }; + }; + + spdif-sound { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,name = "ROCKCHIP,SPDIF"; + + simple-audio-card,cpu { + sound-dai = <0x159>; + }; + + simple-audio-card,codec { + sound-dai = <0x15a>; + }; + }; + + spdif-out { + status = "okay"; + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0x00>; + phandle = <0x15a>; + }; + + vad-sound { + status = "disabled"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip,rk3568-vad"; + rockchip,cpu = <0xe1>; + rockchip,codec = <0x158 0x15b>; + }; + + bt-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "dsp_b"; + simple-audio-card,bitclock-inversion = <0x01>; + simple-audio-card,mclk-fs = <0x100>; + simple-audio-card,name = "rockchip,bt"; + #simple-audio-card,bitclock-master = <0x15c>; + #simple-audio-card,frame-master = <0x15c>; + + simple-audio-card,cpu { + sound-dai = <0x152>; + }; + + simple-audio-card,codec { + #sound-dai-cells = <0x00>; + sound-dai = <0x15d>; + phandle = <0x15c>; + }; + }; + + bt-sco { + compatible = "delta,dfbmcs320"; + #sound-dai-cells = <0x00>; + status = "okay"; + phandle = <0x15d>; + }; + + vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x325aa0>; + regulator-max-microvolt = <0x325aa0>; + vin-supply = <0x15e>; + phandle = <0x46>; + }; + + vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x4c4b40>; + regulator-max-microvolt = <0x4c4b40>; + vin-supply = <0x15e>; + phandle = <0x3e>; + }; + + vcc5v0-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <0x3f 0x06 0x00>; + pinctrl-names = "default"; + pinctrl-0 = <0x15f>; + regulator-name = "vcc5v0_host"; + regulator-always-on; + phandle = <0x131>; + }; + + vcc5v0-otg-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <0x3f 0x05 0x00>; + pinctrl-names = "default"; + pinctrl-0 = <0x160>; + regulator-name = "vcc5v0_otg"; + phandle = <0x132>; + }; + + vcc3v3-lcd0-n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd0_n"; + regulator-boot-on; + gpio = <0x3f 0x17 0x00>; + enable-active-high; + phandle = <0xa6>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3-lcd1-n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd1_n"; + regulator-boot-on; + gpio = <0x3f 0x15 0x00>; + enable-active-high; + phandle = <0xae>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <0x161 0x01>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <0x162>; + post-power-on-delay-ms = <0x14>; + reset-gpios = <0xa8 0x1d 0x01>; + status = "okay"; + phandle = <0x85>; + }; + + wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <0x3b>; + wifi_chip_type = "ap6398s"; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <0x163>; + WIFI,host_wake_irq = <0xa8 0x1c 0x00>; + }; + + wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <0x161 0x01>; + clock-names = "ext_clock"; + uart_rts_gpios = <0x8d 0x09 0x01>; + pinctrl-names = "default\0rts_gpio"; + pinctrl-0 = <0x164>; + pinctrl-1 = <0x165>; + BT,reset_gpio = <0xa8 0x00 0x00>; + BT,wake_gpio = <0xa8 0x02 0x00>; + BT,wake_host_irq = <0xa8 0x01 0x00>; + status = "okay"; + }; + + test-power { + status = "okay"; + }; + + rk-headset { + compatible = "rockchip_headset"; + headset_gpio = <0xa8 0x13 0x01>; + pinctrl-names = "default"; + pinctrl-0 = <0x166>; + io-channels = <0x150 0x01>; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led@1 { + gpios = <0xee 0x12 0x00>; + label = "blue"; + retain-state-suspended; + }; + + led@2 { + gpios = <0xee 0x13 0x00>; + label = "red"; + retain-state-suspended; + }; + + led@3 { + gpios = <0xee 0x15 0x00>; + label = "green"; + retain-state-suspended; + }; + }; + + rt5672-sound { + compatible = "rockchip-rt5670"; + status = "disabled"; + + dais { + + dai0 { + audio-codec = <0x167>; + audio-controller = <0xe1>; + format = "i2s"; + }; + + dai1 { + audio-codec = <0x167>; + audio-controller = <0xe1>; + format = "i2s"; + }; + + dai2 { + audio-codec = <0x168>; + audio-controller = <0xe1>; + format = "i2s"; + }; + }; + }; + + vcc2v5-ddr { + compatible = "regulator-fixed"; + regulator-name = "vcc2v5-sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x2625a0>; + regulator-max-microvolt = <0x2625a0>; + vin-supply = <0x46>; + }; + + gpio-regulator { + compatible = "regulator-gpio"; + regulator-name = "pcie30_3v3"; + regulator-min-microvolt = <0x186a0>; + regulator-max-microvolt = <0x325aa0>; + gpios = <0x3f 0x1c 0x00>; + gpios-states = <0x01>; + states = <0x186a0 0x00 0x325aa0 0x01>; + phandle = <0x143>; + }; + + pcie30-avdd0v9 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0xdbba0>; + regulator-max-microvolt = <0xdbba0>; + vin-supply = <0x46>; + }; + + pcie30-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x1b7740>; + regulator-max-microvolt = <0x1b7740>; + vin-supply = <0x46>; + }; + + vcc3v3-bu { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_bu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x325aa0>; + regulator-max-microvolt = <0x325aa0>; + vin-supply = <0x3e>; + }; + + rk809-sound-micarray { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,rk809-codec"; + simple-audio-card,mclk-fs = <0x100>; + + simple-audio-card,dai-link@0 { + format = "i2s"; + + cpu { + sound-dai = <0xe1>; + }; + + codec { + sound-dai = <0x158 0x00>; + }; + }; + + simple-audio-card,dai-link@1 { + format = "i2s"; + + cpu { + sound-dai = <0xe1>; + }; + + codec { + sound-dai = <0x168>; + }; + }; + }; + + vcc-camera-regulator { + compatible = "regulator-fixed"; + gpio = <0x3f 0x11 0x00>; + pinctrl-names = "default"; + pinctrl-0 = <0x169>; + regulator-name = "vcc_camera"; + enable-active-high; + regulator-always-on; + regulator-boot-on; + }; + + chosen { + bootargs = "earlycon=uart8250,mmio32,0xfe660000 console=ttyFIQ0 ohos.boot.eng_mode=on root=PARTUUID=614e0000-0000 hardware=rk3568 default_boot_device=fe310000.sdhci rw rootwait ohos.required_mount.system=/dev/block/platform/fe310000.sdhci/by-name/system@/usr@ext4@ro,barrier=1@wait,required ohos.required_mount.vendor=/dev/block/platform/fe310000.sdhci/by-name/vendor@/vendor@ext4@ro,barrier=1@wait,required ohos.required_mount.misc=/dev/block/platform/fe310000.sdhci/by-name/misc@none@none@none@wait,required ohos.required_mount.bootctrl=/dev/block/platform/fe310000.sdhci/by-name/bootctrl@none@none@none@wait,required"; + }; + + fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <0x02>; + rockchip,wake-irq = <0x00>; + rockchip,irq-mode-enable = <0x01>; + rockchip,baudrate = <0x16e360>; + interrupts = <0x00 0xfc 0x08>; + pinctrl-names = "default"; + pinctrl-0 = <0x107>; + status = "okay"; + }; + + debug@fd904000 { + compatible = "rockchip,debug"; + reg = <0x00 0xfd904000 0x00 0x1000 0x00 0xfd905000 0x00 0x1000 0x00 0xfd906000 0x00 0x1000 0x00 0xfd907000 0x00 0x1000>; + }; + + cspmu@fd90c000 { + compatible = "rockchip,cspmu"; + reg = <0x00 0xfd90c000 0x00 0x1000 0x00 0xfd90d000 0x00 0x1000 0x00 0xfd90e000 0x00 0x1000 0x00 0xfd90f000 0x00 0x1000>; + }; + + trusted_core { + compatible = "trusted_core"; + interrupts = <0x00 0x49 0x04>; + }; +}; diff --git a/platform/aarch64/dayu200/image/dts/zone0.dts b/platform/aarch64/dayu200/image/dts/zone0.dts new file mode 100644 index 000000000..cc12e692e --- /dev/null +++ b/platform/aarch64/dayu200/image/dts/zone0.dts @@ -0,0 +1,2289 @@ +/dts-v1/; + +/ { + interrupt-parent = <0x01>; + #address-cells = <0x02>; + #size-cells = <0x02>; + compatible = "rockchip,rk3568-toybrick-dev-linux-x0\0rockchip,rk3568"; + + ddr3-params { + version = <0x100>; + expanded_version = <0x00>; + reserved = <0x00>; + freq_0 = <0x420>; + freq_1 = <0x144>; + freq_2 = <0x210>; + freq_3 = <0x30c>; + freq_4 = <0x00>; + freq_5 = <0x00>; + pd_idle = <0x0d>; + sr_idle = <0x5d>; + sr_mc_gate_idle = <0x00>; + srpd_lite_idle = <0x00>; + standby_idle = <0x00>; + pd_dis_freq = <0x42a>; + sr_dis_freq = <0x320>; + dram_dll_dis_freq = <0x12c>; + phy_dll_dis_freq = <0x00>; + phy_dq_drv_odten = <0x21>; + phy_ca_drv_odten = <0x21>; + phy_clk_drv_odten = <0x21>; + dram_dq_drv_odten = <0x22>; + phy_dq_drv_odtoff = <0x21>; + phy_ca_drv_odtoff = <0x21>; + phy_clk_drv_odtoff = <0x21>; + dram_dq_drv_odtoff = <0x22>; + dram_odt = <0x78>; + phy_odt = <0xa7>; + phy_odt_puup_en = <0x01>; + phy_odt_pudn_en = <0x01>; + dram_dq_odt_en_freq = <0x14d>; + phy_odt_en_freq = <0x14d>; + phy_dq_sr_odten = <0x0f>; + phy_ca_sr_odten = <0x03>; + phy_clk_sr_odten = <0x00>; + phy_dq_sr_odtoff = <0x0f>; + phy_ca_sr_odtoff = <0x03>; + phy_clk_sr_odtoff = <0x00>; + ssmod_downspread = <0x00>; + ssmod_div = <0x00>; + ssmod_spread = <0x00>; + mode_2t = <0x00>; + speed_bin = <0x15>; + dram_ext_temp = <0x00>; + byte_map = <0xe4>; + dq_map_cs0_dq_l = <0x00>; + dq_map_cs0_dq_h = <0x00>; + dq_map_cs1_dq_l = <0x00>; + dq_map_cs1_dq_h = <0x00>; + phandle = <0xbc>; + }; + + ddr4-params { + version = <0x100>; + expanded_version = <0x00>; + reserved = <0x00>; + freq_0 = <0x420>; + freq_1 = <0x144>; + freq_2 = <0x210>; + freq_3 = <0x30c>; + freq_4 = <0x00>; + freq_5 = <0x00>; + pd_idle = <0x0d>; + sr_idle = <0x5d>; + sr_mc_gate_idle = <0x00>; + srpd_lite_idle = <0x00>; + standby_idle = <0x00>; + pd_dis_freq = <0x42a>; + sr_dis_freq = <0x320>; + dram_dll_dis_freq = <0x271>; + phy_dll_dis_freq = <0x00>; + phy_dq_drv_odten = <0x25>; + phy_ca_drv_odten = <0x25>; + phy_clk_drv_odten = <0x25>; + dram_dq_drv_odten = <0x22>; + phy_dq_drv_odtoff = <0x25>; + phy_ca_drv_odtoff = <0x25>; + phy_clk_drv_odtoff = <0x25>; + dram_dq_drv_odtoff = <0x22>; + dram_odt = <0x78>; + phy_odt = <0x8b>; + phy_odt_puup_en = <0x01>; + phy_odt_pudn_en = <0x01>; + dram_dq_odt_en_freq = <0x1f4>; + phy_odt_en_freq = <0x1f4>; + phy_dq_sr_odten = <0x0e>; + phy_ca_sr_odten = <0x01>; + phy_clk_sr_odten = <0x01>; + phy_dq_sr_odtoff = <0x0e>; + phy_ca_sr_odtoff = <0x01>; + phy_clk_sr_odtoff = <0x01>; + ssmod_downspread = <0x00>; + ssmod_div = <0x00>; + ssmod_spread = <0x00>; + mode_2t = <0x00>; + speed_bin = <0x0c>; + dram_ext_temp = <0x00>; + byte_map = <0xe4>; + dq_map_cs0_dq_l = <0x22777788>; + dq_map_cs0_dq_h = <0xd7888877>; + dq_map_cs1_dq_l = <0x22777788>; + dq_map_cs1_dq_h = <0xd7888877>; + phandle = <0xbd>; + }; + + lpddr3-params { + version = <0x100>; + expanded_version = <0x00>; + reserved = <0x00>; + freq_0 = <0x420>; + freq_1 = <0x144>; + freq_2 = <0x210>; + freq_3 = <0x30c>; + freq_4 = <0x00>; + freq_5 = <0x00>; + pd_idle = <0x0d>; + sr_idle = <0x5d>; + sr_mc_gate_idle = <0x00>; + srpd_lite_idle = <0x00>; + standby_idle = <0x00>; + pd_dis_freq = <0x42a>; + sr_dis_freq = <0x320>; + dram_dll_dis_freq = <0x00>; + phy_dll_dis_freq = <0x00>; + phy_dq_drv_odten = <0x25>; + phy_ca_drv_odten = <0x25>; + phy_clk_drv_odten = <0x27>; + dram_dq_drv_odten = <0x22>; + phy_dq_drv_odtoff = <0x25>; + phy_ca_drv_odtoff = <0x25>; + phy_clk_drv_odtoff = <0x27>; + dram_dq_drv_odtoff = <0x22>; + dram_odt = <0x78>; + phy_odt = <0x94>; + phy_odt_puup_en = <0x01>; + phy_odt_pudn_en = <0x01>; + dram_dq_odt_en_freq = <0x14d>; + phy_odt_en_freq = <0x14d>; + phy_dq_sr_odten = <0x0f>; + phy_ca_sr_odten = <0x01>; + phy_clk_sr_odten = <0x0f>; + phy_dq_sr_odtoff = <0x0f>; + phy_ca_sr_odtoff = <0x01>; + phy_clk_sr_odtoff = <0x0f>; + ssmod_downspread = <0x00>; + ssmod_div = <0x00>; + ssmod_spread = <0x00>; + mode_2t = <0x00>; + speed_bin = <0x00>; + dram_ext_temp = <0x00>; + byte_map = <0x8d>; + dq_map_cs0_dq_l = <0x00>; + dq_map_cs0_dq_h = <0x00>; + dq_map_cs1_dq_l = <0x00>; + dq_map_cs1_dq_h = <0x00>; + phandle = <0xbe>; + }; + + lpddr4-params { + version = <0x100>; + expanded_version = <0x00>; + reserved = <0x00>; + freq_0 = <0x618>; + freq_1 = <0x144>; + freq_2 = <0x210>; + freq_3 = <0x30c>; + freq_4 = <0x00>; + freq_5 = <0x00>; + pd_idle = <0x0d>; + sr_idle = <0x5d>; + sr_mc_gate_idle = <0x00>; + srpd_lite_idle = <0x00>; + standby_idle = <0x00>; + pd_dis_freq = <0x42a>; + sr_dis_freq = <0x320>; + dram_dll_dis_freq = <0x00>; + phy_dll_dis_freq = <0x00>; + phy_dq_drv_odten = <0x1e>; + phy_ca_drv_odten = <0x26>; + phy_clk_drv_odten = <0x26>; + dram_dq_drv_odten = <0x28>; + phy_dq_drv_odtoff = <0x1e>; + phy_ca_drv_odtoff = <0x26>; + phy_clk_drv_odtoff = <0x26>; + dram_dq_drv_odtoff = <0x28>; + dram_odt = <0x50>; + phy_odt = <0x3c>; + phy_odt_puup_en = <0x00>; + phy_odt_pudn_en = <0x00>; + dram_dq_odt_en_freq = <0x320>; + phy_odt_en_freq = <0x320>; + phy_dq_sr_odten = <0x00>; + phy_ca_sr_odten = <0x0f>; + phy_clk_sr_odten = <0x0f>; + phy_dq_sr_odtoff = <0x00>; + phy_ca_sr_odtoff = <0x0f>; + phy_clk_sr_odtoff = <0x0f>; + ssmod_downspread = <0x00>; + ssmod_div = <0x00>; + ssmod_spread = <0x00>; + mode_2t = <0x00>; + speed_bin = <0x00>; + dram_ext_temp = <0x00>; + byte_map = <0xe4>; + dq_map_cs0_dq_l = <0x00>; + dq_map_cs0_dq_h = <0x00>; + dq_map_cs1_dq_l = <0x00>; + dq_map_cs1_dq_h = <0x00>; + lp4_ca_odt = <0x78>; + lp4_drv_pu_cal_odten = <0x01>; + lp4_drv_pu_cal_odtoff = <0x01>; + phy_lp4_drv_pulldown_en_odten = <0x00>; + phy_lp4_drv_pulldown_en_odtoff = <0x00>; + lp4_ca_odt_en_freq = <0x320>; + phy_lp4_cs_drv_odten = <0x00>; + phy_lp4_cs_drv_odtoff = <0x00>; + lp4_odte_ck_en = <0x01>; + lp4_odte_cs_en = <0x01>; + lp4_odtd_ca_en = <0x00>; + phy_lp4_dq_vref_odten = <0xa6>; + lp4_dq_vref_odten = <0x12c>; + lp4_ca_vref_odten = <0x17c>; + phy_lp4_dq_vref_odtoff = <0x1a4>; + lp4_dq_vref_odtoff = <0x1a4>; + lp4_ca_vref_odtoff = <0x1a4>; + phandle = <0xbf>; + }; + + lpddr4x-params { + version = <0x100>; + expanded_version = <0x00>; + reserved = <0x00>; + freq_0 = <0x618>; + freq_1 = <0x144>; + freq_2 = <0x210>; + freq_3 = <0x30c>; + freq_4 = <0x00>; + freq_5 = <0x00>; + pd_idle = <0x0d>; + sr_idle = <0x5d>; + sr_mc_gate_idle = <0x00>; + srpd_lite_idle = <0x00>; + standby_idle = <0x00>; + pd_dis_freq = <0x42a>; + sr_dis_freq = <0x320>; + dram_dll_dis_freq = <0x00>; + phy_dll_dis_freq = <0x00>; + phy_dq_drv_odten = <0x1d>; + phy_ca_drv_odten = <0x24>; + phy_clk_drv_odten = <0x24>; + dram_dq_drv_odten = <0x28>; + phy_dq_drv_odtoff = <0x1d>; + phy_ca_drv_odtoff = <0x24>; + phy_clk_drv_odtoff = <0x24>; + dram_dq_drv_odtoff = <0x28>; + dram_odt = <0x50>; + phy_odt = <0x3c>; + phy_odt_puup_en = <0x00>; + phy_odt_pudn_en = <0x00>; + dram_dq_odt_en_freq = <0x320>; + phy_odt_en_freq = <0x320>; + phy_dq_sr_odten = <0x00>; + phy_ca_sr_odten = <0x00>; + phy_clk_sr_odten = <0x00>; + phy_dq_sr_odtoff = <0x00>; + phy_ca_sr_odtoff = <0x00>; + phy_clk_sr_odtoff = <0x00>; + ssmod_downspread = <0x00>; + ssmod_div = <0x00>; + ssmod_spread = <0x00>; + mode_2t = <0x00>; + speed_bin = <0x00>; + dram_ext_temp = <0x00>; + byte_map = <0xe4>; + dq_map_cs0_dq_l = <0x00>; + dq_map_cs0_dq_h = <0x00>; + dq_map_cs1_dq_l = <0x00>; + dq_map_cs1_dq_h = <0x00>; + lp4_ca_odt = <0x78>; + lp4_drv_pu_cal_odten = <0x00>; + lp4_drv_pu_cal_odtoff = <0x00>; + phy_lp4_drv_pulldown_en_odten = <0x00>; + phy_lp4_drv_pulldown_en_odtoff = <0x00>; + lp4_ca_odt_en_freq = <0x320>; + phy_lp4_cs_drv_odten = <0x00>; + phy_lp4_cs_drv_odtoff = <0x00>; + lp4_odte_ck_en = <0x00>; + lp4_odte_cs_en = <0x00>; + lp4_odtd_ca_en = <0x00>; + phy_lp4_dq_vref_odten = <0xa6>; + lp4_dq_vref_odten = <0xe4>; + lp4_ca_vref_odten = <0x157>; + phy_lp4_dq_vref_odtoff = <0x1a4>; + lp4_dq_vref_odtoff = <0x1a4>; + lp4_ca_vref_odtoff = <0x157>; + phandle = <0xc0>; + }; + + aliases { + csi2dphy0 = "/csi2-dphy0"; + csi2dphy1 = "/csi2-dphy1"; + csi2dphy2 = "/csi2-dphy2"; + dsi0 = "/dsi@fe060000"; + dsi1 = "/dsi@fe070000"; + ethernet1 = "/ethernet@fe010000"; + gpio0 = "/pinctrl/gpio0@fdd60000"; + gpio1 = "/pinctrl/gpio1@fe740000"; + gpio2 = "/pinctrl/gpio2@fe750000"; + gpio3 = "/pinctrl/gpio3@fe760000"; + gpio4 = "/pinctrl/gpio4@fe770000"; + i2c0 = "/i2c@fdd40000"; + i2c1 = "/i2c@fe5a0000"; + i2c2 = "/i2c@fe5b0000"; + i2c3 = "/i2c@fe5c0000"; + i2c4 = "/i2c@fe5d0000"; + i2c5 = "/i2c@fe5e0000"; + mmc0 = "/sdhci@fe310000"; + mmc1 = "/dwmmc@fe2b0000"; + mmc2 = "/dwmmc@fe2c0000"; + mmc3 = "/mmc@fe000000"; + serial0 = "/serial@fdd50000"; + serial1 = "/serial@fe650000"; + serial2 = "/serial@fe660000"; + serial3 = "/serial@fe670000"; + serial4 = "/serial@fe680000"; + serial5 = "/serial@fe690000"; + serial6 = "/serial@fe6a0000"; + serial7 = "/serial@fe6b0000"; + serial8 = "/serial@fe6c0000"; + serial9 = "/serial@fe6d0000"; + spi0 = "/spi@fe610000"; + spi1 = "/spi@fe620000"; + spi2 = "/spi@fe630000"; + spi3 = "/spi@fe640000"; + ethernet0 = "/ethernet@fe2a0000"; + lvds0 = "/syscon@fdc60000/lvds"; + lvds1 = "/syscon@fdc60000/lvds1"; + }; + + memory { + device_type = "memory"; + reg = <0x00 0x200000 0x00 0x8200000 + 0x00 0x9400000 0x00 0x76c00000 + 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00>; + }; + + cpus { + #address-cells = <0x02>; + #size-cells = <0x00>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x00 0x00>; + clocks = <0x02 0x00>; + #cooling-cells = <0x02>; + enable-method = "psci"; + operating-points-v2 = <0x03>; + cpu-idle-states = <0x04>; + dynamic-power-coefficient = <0xbb>; + cpu-supply = <0x05>; + phandle = <0x1f>; + }; + + cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x00 0x100>; + #cooling-cells = <0x02>; + enable-method = "psci"; + operating-points-v2 = <0x03>; + cpu-idle-states = <0x04>; + phandle = <0x20>; + }; + + // cpu@200 { + // device_type = "cpu"; + // compatible = "arm,cortex-a55"; + // reg = <0x00 0x200>; + // #cooling-cells = <0x02>; + // enable-method = "psci"; + // operating-points-v2 = <0x03>; + // cpu-idle-states = <0x04>; + // phandle = <0x21>; + // }; + + // cpu@300 { + // device_type = "cpu"; + // compatible = "arm,cortex-a55"; + // reg = <0x00 0x300>; + // #cooling-cells = <0x02>; + // enable-method = "psci"; + // operating-points-v2 = <0x03>; + // cpu-idle-states = <0x04>; + // phandle = <0x22>; + // }; + + idle-states { + entry-method = "psci"; + + cpu-sleep { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x10000>; + entry-latency-us = <0x64>; + exit-latency-us = <0x78>; + min-residency-us = <0x3e8>; + phandle = <0x04>; + }; + }; + }; + + firmware { + + scmi { + compatible = "arm,scmi-smc"; + arm,smc-id = <0x82000010>; + shmem = <0x19>; + #address-cells = <0x01>; + #size-cells = <0x00>; + + protocol@14 { + reg = <0x14>; + #clock-cells = <0x01>; + rockchip,clk-init = <0x41cdb400>; + phandle = <0x02>; + }; + }; + + sdei { + compatible = "arm,sdei-1.0"; + method = "smc"; + }; + }; + + pmu { + compatible = "arm,cortex-a55-pmu"; + interrupts = <0x00 0xe4 0x04 0x00 0xe5 0x04 0x00 0xe6 0x04 0x00 0xe7 0x04>; + interrupt-affinity = <0x1f 0x20 0x21 0x22>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + reserved-memory { + #size-cells = <0x02>; + ranges; + #address-cells = <0x02>; + + hvisor@40400000 { + no-map; + reg = <0x00 0x40400000 0x00 0x4900000>; + }; + + ohos-zone1-bootarea { + no-map; + reg = <0x00 0x50000000 0x00 0x04000000>; + // [0x5000_0000, 0x5020_0000), 2 MiB, device-tree-blob + // [0x5020_0000, 0x5060_0000), 4 MiB, ramdisk + // [0x5060_0000, 0x5360_0000), 48 MiB, kernel + // [0x5360_0000, 0x5400_0000) free + }; + + ohos-zone1-memory { + no-map; + reg = <0x00 0x10000000 0x00 0x20000000>; + }; + }; + + rockchip-suspend { + compatible = "rockchip,pm-rk3568"; + status = "disabled"; + rockchip,sleep-debug-en = <0x01>; + rockchip,sleep-mode-config = <0x5ec>; + rockchip,wakeup-config = <0x10>; + }; + + rockchip-system-monitor { + compatible = "rockchip,system-monitor"; + rockchip,thermal-zone = "soc-thermal"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <0x01 0x0d 0xf04 0x01 0x0e 0xf04 0x01 0x0b 0xf04 0x01 0x0a 0xf04>; + arm,no-tick-in-suspend; + }; + + // RK3568 板级外部固定时钟源 - 24 MHz 晶振 + // 这是 SoC 时钟树的基础输入之一，CRU/PMUCRU、UART、I2C、SPI、MMC、USB、音频等很多时钟最终都会从它派生或依赖它 + xin24m { + compatible = "fixed-clock"; + clock-frequency = <0x16e3600>; + clock-output-names = "xin24m"; + #clock-cells = <0x00>; + }; + + // 32.768 kHz 低速时钟。常用于 RTC、低功耗/休眠、PMU、蓝牙/WiFi 低功耗时钟、always-on 逻辑等 + xin32k { + compatible = "fixed-clock"; + clock-frequency = <0x8000>; + clock-output-names = "xin32k"; + pinctrl-0 = <0x23>; + pinctrl-names = "default"; + #clock-cells = <0x00>; + }; + + // important + scmi-shmem@10f000 { + compatible = "arm,scmi-shmem"; + reg = <0x00 0x10f000 0x00 0x100>; + phandle = <0x19>; + }; + + interrupt-controller@fd400000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <0x03>; + #address-cells = <0x02>; + #size-cells = <0x02>; + ranges; + interrupt-controller; + reg = <0x00 0xfd400000 0x00 0x10000 0x00 0xfd460000 0x00 0xc0000>; + interrupts = <0x01 0x09 0x04>; + phandle = <0x01>; + + // interrupt-controller@fd440000 { + // compatible = "arm,gic-v3-its"; + // msi-controller; + // #msi-cells = <0x01>; + // reg = <0x00 0xfd440000 0x00 0x20000>; + // phandle = <0xc3>; + // }; + }; + + syscon@fda00000 { + compatible = "rockchip,rk3568-xpcs\0syscon"; + reg = <0x00 0xfda00000 0x00 0x200000>; + status = "disabled"; + }; + + syscon@fdc20000 { + compatible = "rockchip,rk3568-pmugrf\0syscon\0simple-mfd"; + reg = <0x00 0xfdc20000 0x00 0x10000>; + phandle = <0x3c>; + + io-domains { + compatible = "rockchip,rk3568-pmu-io-voltage-domain"; + status = "okay"; + pmuio1-supply = <0x2f>; + pmuio2-supply = <0x2f>; + vccio1-supply = <0x30>; + vccio3-supply = <0x31>; + vccio4-supply = <0x32>; + vccio5-supply = <0x33>; + vccio6-supply = <0x32>; + vccio7-supply = <0x33>; + }; + + reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x200>; + mode-bootloader = <0x5242c301>; + mode-charge = <0x5242c30b>; + mode-fastboot = <0x5242c309>; + mode-loader = <0x5242c301>; + mode-normal = <0x5242c300>; + mode-recovery = <0x5242c303>; + mode-ums = <0x5242c30c>; + mode-panic = <0x5242c307>; + mode-watchdog = <0x5242c308>; + }; + }; + + syscon@fdc50000 { + compatible = "rockchip,rk3568-pipe-grf\0syscon"; + reg = <0x00 0xfdc50000 0x00 0x1000>; + phandle = <0x128>; + }; + + syscon@fdc60000 { + compatible = "rockchip,rk3568-grf\0syscon\0simple-mfd"; + reg = <0x00 0xfdc60000 0x00 0x10000>; + phandle = <0x3b>; + + io-domains { + compatible = "rockchip,rk3568-io-voltage-domain"; + status = "disabled"; + }; + + lvds { + compatible = "rockchip,rk3568-lvds"; + phys = <0x34>; + phy-names = "phy"; + status = "disabled"; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + #address-cells = <0x01>; + #size-cells = <0x00>; + + endpoint@1 { + reg = <0x01>; + remote-endpoint = <0x17>; + status = "disabled"; + phandle = <0x9e>; + }; + + endpoint@2 { + reg = <0x02>; + remote-endpoint = <0x35>; + status = "disabled"; + phandle = <0xa0>; + }; + }; + }; + }; + + rgb { + compatible = "rockchip,rk3568-rgb"; + pinctrl-names = "default"; + pinctrl-0 = <0x36>; + status = "disabled"; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + #address-cells = <0x01>; + #size-cells = <0x00>; + + endpoint@2 { + reg = <0x02>; + remote-endpoint = <0x18>; + status = "disabled"; + phandle = <0xa1>; + }; + }; + }; + }; + + lvds1 { + compatible = "rockchip,rk3568-lvds"; + phys = <0x37>; + phy-names = "phy"; + status = "disabled"; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + #address-cells = <0x01>; + #size-cells = <0x00>; + + endpoint@0 { + reg = <0x00>; + remote-endpoint = <0x38>; + phandle = <0x9f>; + }; + + endpoint@1 { + reg = <0x01>; + remote-endpoint = <0x39>; + phandle = <0xa2>; + }; + }; + }; + }; + }; + + syscon@fdc80000 { + compatible = "rockchip,pipe-phy-grf\0syscon"; + reg = <0x00 0xfdc80000 0x00 0x1000>; + phandle = <0x129>; + }; + + syscon@fdc90000 { + compatible = "rockchip,pipe-phy-grf\0syscon"; + reg = <0x00 0xfdc90000 0x00 0x1000>; + phandle = <0x12a>; + }; + + syscon@fdca0000 { + compatible = "rockchip,rk3568-usb2phy-grf\0syscon"; + reg = <0x00 0xfdca0000 0x00 0x8000>; + phandle = <0x130>; + }; + + syscon@fdca8000 { + compatible = "rockchip,rk3568-usb2phy-grf\0syscon"; + reg = <0x00 0xfdca8000 0x00 0x8000>; + phandle = <0x133>; + }; + + syscon@fdcb0000 { + compatible = "rockchip,rk3568-edp-phy-grf\0syscon\0simple-mfd"; + reg = <0x00 0xfdcb0000 0x00 0x100>; + clocks = <0x24 0x192>; + + edp-phy { + compatible = "rockchip,rk3568-edp-phy"; + clocks = <0x3a 0x29>; + clock-names = "refclk"; + #phy-cells = <0x00>; + status = "disabled"; + phandle = <0xb7>; + }; + }; + + sram@fdcc0000 { + compatible = "mmio-sram"; + reg = <0x00 0xfdcc0000 0x00 0xb000>; + #address-cells = <0x01>; + #size-cells = <0x01>; + ranges = <0x00 0x00 0xfdcc0000 0xb000>; + + rkvdec-sram@0 { + reg = <0x00 0xb000>; + phandle = <0x7c>; + }; + }; + + clock-controller@fdd00000 { + compatible = "rockchip,rk3568-pmucru"; + reg = <0x00 0xfdd00000 0x00 0x1000>; + rockchip,grf = <0x3b>; + rockchip,pmugrf = <0x3c>; + #clock-cells = <0x01>; + #reset-cells = <0x01>; + assigned-clocks = <0x3a 0x32>; + assigned-clock-parents = <0x3a 0x05>; + phandle = <0x3a>; + }; + + clock-controller@fdd20000 { + compatible = "rockchip,rk3568-cru"; + reg = <0x00 0xfdd20000 0x00 0x1000>; + rockchip,grf = <0x3b>; + #clock-cells = <0x01>; + #reset-cells = <0x01>; + assigned-clocks = <0x3a 0x05 0x24 0x106 0x24 0x10b 0x3a 0x01 0x3a 0x2b 0x24 0x03 0x24 0x19b 0x24 0x09 0x24 0x19c 0x24 0x19d 0x24 0x1a1 0x24 0x19e 0x24 0x19f 0x24 0x1a0 0x24 0x04 0x24 0x10d 0x24 0x10e 0x24 0x173 0x24 0x174 0x24 0x175 0x24 0x176 0x24 0xc9 0x24 0xca 0x24 0x06 0x24 0x7e 0x24 0x7f 0x24 0x3d 0x24 0x41 0x24 0x45 0x24 0x49 0x24 0x4d 0x24 0x4d 0x24 0x55 0x24 0x51 0x24 0x5d 0x24 0xdd>; + assigned-clock-rates = <0x8000 0x11e1a300 0x11e1a300 0xbebc200 0x5f5e100 0x3b9aca00 0x1dcd6500 0x13d92d40 0xee6b280 0x7735940 0x5f5e100 0x3b9aca0 0x2faf080 0x17d7840 0x46cf7100 0x8f0d180 0x5f5e100 0x1dcd6500 0x17d78400 0x8f0d180 0x5f5e100 0x11e1a300 0x8f0d180 0x47868c00 0x17d78400 0x5f5e100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x1dcd6500>; + assigned-clock-parents = <0x3a 0x08 0x24 0x04 0x24 0x04>; + phandle = <0x24>; + }; + + i2c@fdd40000 { + compatible = "rockchip,rk3568-i2c\0rockchip,rk3399-i2c"; + reg = <0x00 0xfdd40000 0x00 0x1000>; + interrupts = <0x00 0x2e 0x04>; + clocks = <0x3a 0x07 0x3a 0x2d>; + clock-names = "i2c\0pclk"; + pinctrl-0 = <0x3d>; + pinctrl-names = "default"; + #address-cells = <0x01>; + #size-cells = <0x00>; + status = "okay"; + + tcs4525@1c { + compatible = "tcs,tcs452x"; + reg = <0x1c>; + vin-supply = <0x3e>; + regulator-compatible = "fan53555-reg"; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <0xadf34>; + regulator-max-microvolt = <0x1535b0>; + regulator-init-microvolt = <0xe7ef0>; + regulator-ramp-delay = <0x8fc>; + fcs,suspend-voltage-selector = <0x01>; + regulator-boot-on; + regulator-always-on; + phandle = <0x05>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <0x3f>; + interrupts = <0x03 0x08>; + pinctrl-names = "default\0pmic-sleep\0pmic-power-off\0pmic-reset"; + pinctrl-0 = <0x40>; + pinctrl-1 = <0x41 0x42>; + pinctrl-2 = <0x43 0x44>; + pinctrl-3 = <0x43 0x45>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <0x01>; + clock-output-names = "rk808-clkout1\0rk808-clkout2"; + pmic-reset-func = <0x00>; + not-save-power-en = <0x01>; + vcc1-supply = <0x46>; + vcc2-supply = <0x46>; + vcc3-supply = <0x46>; + vcc4-supply = <0x46>; + vcc5-supply = <0x46>; + vcc6-supply = <0x46>; + vcc7-supply = <0x46>; + vcc8-supply = <0x46>; + vcc9-supply = <0x46>; + phandle = <0x161>; + + pwrkey { + status = "okay"; + }; + + pinctrl_rk8xx { + gpio-controller; + #gpio-cells = <0x02>; + + rk817_slppin_null { + pins = "gpio_slp"; + function = "pin_fun0"; + }; + + rk817_slppin_slp { + pins = "gpio_slp"; + function = "pin_fun1"; + phandle = <0x42>; + }; + + rk817_slppin_pwrdn { + pins = "gpio_slp"; + function = "pin_fun2"; + phandle = <0x44>; + }; + + rk817_slppin_rst { + pins = "gpio_slp"; + function = "pin_fun3"; + phandle = <0x45>; + }; + }; + + regulators { + + DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x7a120>; + regulator-max-microvolt = <0x149970>; + regulator-init-microvolt = <0xdbba0>; + regulator-ramp-delay = <0x1771>; + regulator-initial-mode = <0x02>; + regulator-name = "vdd_logic"; + phandle = <0x6f>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x7a120>; + regulator-max-microvolt = <0x149970>; + regulator-init-microvolt = <0xdbba0>; + regulator-ramp-delay = <0x1771>; + regulator-initial-mode = <0x02>; + regulator-name = "vdd_gpu"; + phandle = <0x71>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x02>; + regulator-name = "vcc_ddr"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x7a120>; + regulator-max-microvolt = <0x149970>; + regulator-init-microvolt = <0xdbba0>; + regulator-ramp-delay = <0x1771>; + regulator-initial-mode = <0x02>; + regulator-name = "vdd_npu"; + phandle = <0x6b>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + LDO_REG1 { + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <0xdbba0>; + regulator-max-microvolt = <0xdbba0>; + regulator-name = "vdda0v9_image"; + phandle = <0xb4>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0xdbba0>; + regulator-max-microvolt = <0xdbba0>; + regulator-name = "vdda_0v9"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0xdbba0>; + regulator-max-microvolt = <0xdbba0>; + regulator-name = "vdda0v9_pmu"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <0xdbba0>; + }; + }; + + LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x1b7740>; + regulator-max-microvolt = <0x1b7740>; + regulator-name = "vccio_acodec"; + phandle = <0x30>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x1b7740>; + regulator-max-microvolt = <0x325aa0>; + regulator-name = "vccio_sd"; + phandle = <0x31>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x325aa0>; + regulator-max-microvolt = <0x325aa0>; + regulator-name = "vcc3v3_pmu"; + phandle = <0x2f>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <0x325aa0>; + }; + }; + + LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x1b7740>; + regulator-max-microvolt = <0x1b7740>; + regulator-name = "vcca_1v8"; + phandle = <0x127>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x1b7740>; + regulator-max-microvolt = <0x1b7740>; + regulator-name = "vcca1v8_pmu"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <0x1b7740>; + }; + }; + + LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x1b7740>; + regulator-max-microvolt = <0x1b7740>; + regulator-name = "vcca1v8_image"; + phandle = <0xb5>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + DCDC_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x1b7740>; + regulator-max-microvolt = <0x1b7740>; + regulator-name = "vcc_1v8"; + phandle = <0x32>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_3v3"; + phandle = <0x33>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_sd"; + phandle = <0xc4>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + codec { + #sound-dai-cells = <0x00>; + compatible = "rockchip,rk809-codec\0rockchip,rk817-codec"; + clocks = <0x24 0x1a3>; + clock-names = "mclk"; + assigned-clocks = <0x24 0x1a3 0x24 0x1a6>; + assigned-clock-rates = <0xbb8000>; + assigned-clock-parents = <0x24 0x48 0x24 0x48>; + pinctrl-names = "default"; + pinctrl-0 = <0x47>; + hp-volume = <0x14>; + spk-volume = <0x03>; + mic-in-differential; + status = "disabled"; + phandle = <0x158>; + }; + }; + }; + + power-management@fdd90000 { + compatible = "rockchip,rk3568-pmu\0syscon\0simple-mfd"; + reg = <0x00 0xfdd90000 0x00 0x1000>; + + power-controller { + compatible = "rockchip,rk3568-power-controller"; + #power-domain-cells = <0x01>; + #address-cells = <0x01>; + #size-cells = <0x00>; + phandle = <0x26>; + + power-domain@6 { + reg = <0x06>; + clocks = <0x24 0x27 0x24 0x25 0x24 0x26>; + pm_qos = <0x4e>; + }; + + power-domain@7 { + reg = <0x07>; + clocks = <0x24 0x19 0x24 0x1a>; + pm_qos = <0x4f>; + #power-domain-cells = <0x00>; + }; + + power-domain@8 { + reg = <0x08>; + clocks = <0x24 0xcc 0x24 0xcd>; + pm_qos = <0x50 0x51 0x52>; + #power-domain-cells = <0x00>; + }; + + power-domain@9 { + reg = <0x09>; + clocks = <0x24 0xda 0x24 0xdb 0x24 0xdc>; + pm_qos = <0x53 0x54 0x55>; + #power-domain-cells = <0x00>; + }; + + power-domain@10 { + reg = <0x0a>; + clocks = <0x24 0xf1 0x24 0xf2>; + pm_qos = <0x56 0x57 0x58 0x59 0x5a 0x5b>; + #power-domain-cells = <0x00>; + }; + + power-domain@11 { + reg = <0x0b>; + clocks = <0x24 0xed>; + pm_qos = <0x5c>; + #power-domain-cells = <0x00>; + }; + + power-domain@13 { + clocks = <0x24 0x107>; + reg = <0x0d>; + pm_qos = <0x5d>; + #power-domain-cells = <0x00>; + }; + + power-domain@14 { + reg = <0x0e>; + clocks = <0x24 0x102>; + pm_qos = <0x5e 0x5f 0x60>; + #power-domain-cells = <0x00>; + }; + + power-domain@15 { + reg = <0x0f>; + clocks = <0x24 0x7f>; + pm_qos = <0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68>; + #power-domain-cells = <0x00>; + }; + }; + }; + + spi@fe300000 { + compatible = "rockchip,sfc"; + reg = <0x00 0xfe300000 0x00 0x4000>; + interrupts = <0x00 0x65 0x04>; + clocks = <0x24 0x78 0x24 0x76>; + clock-names = "clk_sfc\0hclk_sfc"; + assigned-clocks = <0x24 0x78>; + assigned-clock-rates = <0x5f5e100>; + #address-cells = <0x01>; + #size-cells = <0x00>; + status = "disabled"; + }; + + uio@fe010000 { + compatible = "rockchip,uio-gmac"; + reg = <0x00 0xfe010000 0x00 0x10000>; + rockchip,ethernet = <0x89>; + status = "disabled"; + }; + + ethernet@fe010000 { + compatible = "rockchip,rk3568-gmac\0snps,dwmac-4.20a"; + reg = <0x00 0xfe010000 0x00 0x10000>; + interrupts = <0x00 0x20 0x04 0x00 0x1d 0x04>; + interrupt-names = "macirq\0eth_wake_irq"; + clocks = <0x24 0x186 0x24 0x189 0x24 0x189 0x24 0xc7 0x24 0xc3 0x24 0xc4 0x24 0x189 0x24 0xc8 0x24 0xac 0x24 0xab>; + clock-names = "stmmaceth\0mac_clk_rx\0mac_clk_tx\0clk_mac_refout\0aclk_mac\0pclk_mac\0clk_mac_speed\0ptp_ref\0pclk_xpcs\0clk_xpcs_eee"; + resets = <0x24 0xec>; + reset-names = "stmmaceth"; + rockchip,grf = <0x3b>; + snps,axi-config = <0x8a>; + snps,mixed-burst; + snps,mtl-rx-config = <0x8b>; + snps,mtl-tx-config = <0x8c>; + snps,tso; + status = "okay"; + phy-mode = "rgmii"; + clock_in_out = "output"; + snps,reset-gpio = <0x8d 0x19 0x01>; + snps,reset-active-low; + snps,reset-delays-us = <0x00 0x4e20 0x186a0>; + assigned-clocks = <0x24 0x189 0x24 0x186>; + assigned-clock-parents = <0x24 0x187 0x24 0xc5>; + assigned-clock-rates = <0x00 0x7735940>; + pinctrl-names = "default"; + pinctrl-0 = <0x8e 0x8f 0x90 0x91 0x92>; + tx_delay = <0x37>; + rx_delay = <0x0f>; + phy-handle = <0x93>; + phandle = <0x89>; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <0x01>; + #size-cells = <0x00>; + + phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x00>; + phandle = <0x93>; + }; + }; + + stmmac-axi-config { + snps,blen = <0x00 0x00 0x00 0x00 0x10 0x08 0x04>; + snps,rd_osr_lmt = <0x08>; + snps,wr_osr_lmt = <0x04>; + phandle = <0x8a>; + }; + + rx-queues-config { + snps,rx-queues-to-use = <0x01>; + phandle = <0x8b>; + + queue0 { + }; + }; + + tx-queues-config { + snps,tx-queues-to-use = <0x01>; + phandle = <0x8c>; + + queue0 { + }; + }; + }; + + sdhci@fe310000 { + compatible = "rockchip,rk3568-dwcmshc\0rockchip,dwcmshc-sdhci"; + reg = <0x00 0xfe310000 0x00 0x10000>; + interrupts = <0x00 0x13 0x04>; + assigned-clocks = <0x24 0x7b 0x24 0x7d 0x24 0x7c>; + assigned-clock-rates = <0xbebc200 0x16e3600 0xbebc200>; + clocks = <0x24 0x7c 0x24 0x7a 0x24 0x79 0x24 0x7b 0x24 0x7d>; + clock-names = "core\0bus\0axi\0block\0timer"; + resets = <0x24 0x78 0x24 0x76 0x24 0x75 0x24 0x77 0x24 0x79>; + reset-names = "core\0bus\0axi\0block\0timer"; + status = "okay"; + bus-width = <0x08>; + supports-emmc; + non-removable; + max-frequency = <0xbebc200>; + }; + + timer@fe5f0000 { + compatible = "rockchip,rk3568-timer\0rockchip,rk3288-timer"; + reg = <0x00 0xfe5f0000 0x00 0x1000>; + interrupts = <0x00 0x6d 0x04>; + clocks = <0x24 0x16c 0x24 0x16d>; + clock-names = "pclk\0timer"; + }; + + serial@fe660000 { + compatible = "rockchip,rk3568-uart\0snps,dw-apb-uart"; + reg = <0x00 0xfe660000 0x00 0x100>; + interrupts = <0x00 0x76 0x04>; + clocks = <0x24 0x123 0x24 0x120>; + clock-names = "baudclk\0apb_pclk"; + dmas = <0x48 0x04 0x48 0x05>; + pinctrl-0 = <0x107>; + pinctrl-names = "default"; + reg-io-width = <0x04>; + reg-shift = <0x02>; + status = "okay"; + }; + + serial@fe670000 { + compatible = "rockchip,rk3568-uart\0snps,dw-apb-uart"; + reg = <0x00 0xfe670000 0x00 0x100>; + interrupts = <0x00 0x77 0x04>; + clocks = <0x24 0x127 0x24 0x124>; + clock-names = "baudclk\0apb_pclk"; + dmas = <0x48 0x06 0x48 0x07>; + pinctrl-0 = <0x108>; + pinctrl-names = "default"; + reg-io-width = <0x04>; + reg-shift = <0x02>; + status = "disabled"; + }; + + pinctrl { + compatible = "rockchip,rk3568-pinctrl"; + rockchip,grf = <0x3b>; + rockchip,pmu = <0x3c>; + #address-cells = <0x02>; + #size-cells = <0x02>; + ranges; + + gpio0@fdd60000 { + compatible = "rockchip,gpio-bank"; + reg = <0x00 0xfdd60000 0x00 0x100>; + interrupts = <0x00 0x21 0x04>; + clocks = <0x3a 0x2e 0x3a 0x0c>; + gpio-controller; + #gpio-cells = <0x02>; + interrupt-controller; + #interrupt-cells = <0x02>; + phandle = <0x3f>; + }; + + gpio1@fe740000 { + compatible = "rockchip,gpio-bank"; + reg = <0x00 0xfe740000 0x00 0x100>; + interrupts = <0x00 0x22 0x04>; + clocks = <0x24 0x163 0x24 0x164>; + gpio-controller; + #gpio-cells = <0x02>; + interrupt-controller; + #interrupt-cells = <0x02>; + }; + + gpio2@fe750000 { + compatible = "rockchip,gpio-bank"; + reg = <0x00 0xfe750000 0x00 0x100>; + interrupts = <0x00 0x23 0x04>; + clocks = <0x24 0x165 0x24 0x166>; + gpio-controller; + #gpio-cells = <0x02>; + interrupt-controller; + #interrupt-cells = <0x02>; + phandle = <0x8d>; + }; + + gpio3@fe760000 { + compatible = "rockchip,gpio-bank"; + reg = <0x00 0xfe760000 0x00 0x100>; + interrupts = <0x00 0x24 0x04>; + clocks = <0x24 0x167 0x24 0x168>; + gpio-controller; + #gpio-cells = <0x02>; + interrupt-controller; + #interrupt-cells = <0x02>; + phandle = <0xa8>; + }; + + gpio4@fe770000 { + compatible = "rockchip,gpio-bank"; + reg = <0x00 0xfe770000 0x00 0x100>; + interrupts = <0x00 0x25 0x04>; + clocks = <0x24 0x169 0x24 0x16a>; + gpio-controller; + #gpio-cells = <0x02>; + interrupt-controller; + #interrupt-cells = <0x02>; + phandle = <0xee>; + }; + + pcfg-pull-up { + bias-pull-up; + phandle = <0x136>; + }; + + pcfg-pull-down { + bias-pull-down; + phandle = <0x13e>; + }; + + pcfg-pull-none { + bias-disable; + phandle = <0x134>; + }; + + pcfg-pull-none-drv-level-1 { + bias-disable; + drive-strength = <0x01>; + phandle = <0x138>; + }; + + pcfg-pull-none-drv-level-2 { + bias-disable; + drive-strength = <0x02>; + phandle = <0x137>; + }; + + pcfg-pull-none-drv-level-3 { + bias-disable; + drive-strength = <0x03>; + phandle = <0x13d>; + }; + + pcfg-pull-up-drv-level-1 { + bias-pull-up; + drive-strength = <0x01>; + phandle = <0x13c>; + }; + + pcfg-pull-up-drv-level-2 { + bias-pull-up; + drive-strength = <0x02>; + phandle = <0x135>; + }; + + pcfg-pull-up-drv-level-4 { + bias-pull-up; + drive-strength = <0x04>; + phandle = <0x13a>; + }; + + pcfg-pull-none-smt { + bias-disable; + input-schmitt-enable; + phandle = <0x139>; + }; + + pcfg-output-high { + output-high; + phandle = <0x13f>; + }; + + pcfg-output-low-pull-down { + output-low; + bias-pull-down; + phandle = <0x13b>; + }; + + acodec { + + acodec-pins { + rockchip,pins = <0x01 0x09 0x05 0x134 0x01 0x01 0x05 0x134 0x01 0x00 0x05 0x134 0x01 0x07 0x05 0x134 0x01 0x08 0x05 0x134 0x01 0x03 0x05 0x134 0x01 0x05 0x05 0x134>; + phandle = <0xe3>; + }; + }; + + cam { + + camera-pwr { + rockchip,pins = <0x00 0x11 0x00 0x134>; + phandle = <0x169>; + }; + }; + + can0 { + + can0m1-pins { + rockchip,pins = <0x02 0x02 0x04 0x134 0x02 0x01 0x04 0x134>; + phandle = <0xe5>; + }; + }; + + can1 { + + can1m1-pins { + rockchip,pins = <0x04 0x12 0x03 0x134 0x04 0x13 0x03 0x134>; + phandle = <0xe6>; + }; + }; + + can2 { + + can2m1-pins { + rockchip,pins = <0x02 0x09 0x04 0x134 0x02 0x0a 0x04 0x134>; + phandle = <0xe7>; + }; + }; + + cif { + + cif-clk { + rockchip,pins = <0x04 0x10 0x01 0x134>; + phandle = <0xed>; + }; + }; + + clk32k { + + clk32k-out0 { + rockchip,pins = <0x00 0x08 0x02 0x134>; + phandle = <0x23>; + }; + }; + + ebc { + + ebc-pins { + rockchip,pins = <0x04 0x10 0x02 0x134 0x04 0x0b 0x02 0x134 0x04 0x0c 0x02 0x134 0x04 0x06 0x02 0x134 0x04 0x11 0x02 0x134 0x03 0x16 0x02 0x134 0x03 0x17 0x02 0x134 0x03 0x18 0x02 0x134 0x03 0x19 0x02 0x134 0x03 0x1a 0x02 0x134 0x03 0x1b 0x02 0x134 0x03 0x1c 0x02 0x134 0x03 0x1d 0x02 0x134 0x03 0x1e 0x02 0x134 0x03 0x1f 0x02 0x134 0x04 0x00 0x02 0x134 0x04 0x01 0x02 0x134 0x04 0x02 0x02 0x134 0x04 0x03 0x02 0x134 0x04 0x04 0x02 0x134 0x04 0x05 0x02 0x134 0x04 0x0e 0x02 0x134 0x04 0x0f 0x02 0x134>; + phandle = <0x74>; + }; + }; + + gmac0 { + + gmac0-miim { + rockchip,pins = <0x02 0x13 0x02 0x134 0x02 0x14 0x02 0x134>; + phandle = <0x148>; + }; + + gmac0-rx-bus2 { + rockchip,pins = <0x02 0x0e 0x01 0x134 0x02 0x0f 0x02 0x134 0x02 0x10 0x02 0x134>; + phandle = <0x14a>; + }; + + gmac0-tx-bus2 { + rockchip,pins = <0x02 0x0b 0x01 0x137 0x02 0x0c 0x01 0x137 0x02 0x0d 0x01 0x134>; + phandle = <0x149>; + }; + + gmac0-rgmii-clk { + rockchip,pins = <0x02 0x05 0x02 0x134 0x02 0x08 0x02 0x138>; + phandle = <0x14b>; + }; + + gmac0-rgmii-bus { + rockchip,pins = <0x02 0x03 0x02 0x134 0x02 0x04 0x02 0x134 0x02 0x06 0x02 0x137 0x02 0x07 0x02 0x137>; + phandle = <0x14c>; + }; + }; + + gmac1 { + + gmac1m1-miim { + rockchip,pins = <0x04 0x0e 0x03 0x134 0x04 0x0f 0x03 0x134>; + phandle = <0x8e>; + }; + + gmac1m1-rx-bus2 { + rockchip,pins = <0x04 0x07 0x03 0x134 0x04 0x08 0x03 0x134 0x04 0x09 0x03 0x134>; + phandle = <0x90>; + }; + + gmac1m1-tx-bus2 { + rockchip,pins = <0x04 0x04 0x03 0x137 0x04 0x05 0x03 0x137 0x04 0x06 0x03 0x134>; + phandle = <0x8f>; + }; + + gmac1m1-rgmii-clk { + rockchip,pins = <0x04 0x03 0x03 0x134 0x04 0x00 0x03 0x138>; + phandle = <0x91>; + }; + + gmac1m1-rgmii-bus { + rockchip,pins = <0x04 0x01 0x03 0x134 0x04 0x02 0x03 0x134 0x03 0x1e 0x03 0x137 0x03 0x1f 0x03 0x137>; + phandle = <0x92>; + }; + }; + + hdmitx { + + hdmitxm0-cec { + rockchip,pins = <0x04 0x19 0x01 0x134>; + phandle = <0xb3>; + }; + + hdmitx-scl { + rockchip,pins = <0x04 0x17 0x01 0x134>; + phandle = <0xb1>; + }; + + hdmitx-sda { + rockchip,pins = <0x04 0x18 0x01 0x134>; + phandle = <0xb2>; + }; + }; + + i2c0 { + + i2c0-xfer { + rockchip,pins = <0x00 0x09 0x01 0x139 0x00 0x0a 0x01 0x139>; + phandle = <0x3d>; + }; + }; + + i2c1 { + + i2c1-xfer { + rockchip,pins = <0x00 0x0b 0x01 0x139 0x00 0x0c 0x01 0x139>; + phandle = <0xe8>; + }; + }; + + i2c2 { + + i2c2m0-xfer { + rockchip,pins = <0x00 0x0d 0x01 0x139 0x00 0x0e 0x01 0x139>; + phandle = <0xea>; + }; + }; + + i2c3 { + + i2c3m0-xfer { + rockchip,pins = <0x01 0x01 0x01 0x139 0x01 0x00 0x01 0x139>; + phandle = <0xeb>; + }; + }; + + i2c4 { + + i2c4m0-xfer { + rockchip,pins = <0x04 0x0b 0x01 0x139 0x04 0x0a 0x01 0x139>; + phandle = <0xec>; + }; + }; + + i2c5 { + + i2c5m0-xfer { + rockchip,pins = <0x03 0x0b 0x04 0x139 0x03 0x0c 0x04 0x139>; + phandle = <0xf2>; + }; + }; + + i2s1 { + + i2s1m0-lrckrx { + rockchip,pins = <0x01 0x06 0x01 0x13a>; + phandle = <0xcd>; + }; + + i2s1m0-lrcktx { + rockchip,pins = <0x01 0x05 0x01 0x13a>; + phandle = <0xcc>; + }; + + i2s1m0-mclk { + rockchip,pins = <0x01 0x02 0x01 0x13a>; + phandle = <0x47>; + }; + + i2s1m0-sclkrx { + rockchip,pins = <0x01 0x04 0x01 0x13a>; + phandle = <0xcb>; + }; + + i2s1m0-sclktx { + rockchip,pins = <0x01 0x03 0x01 0x13a>; + phandle = <0xca>; + }; + + i2s1m0-sdi0 { + rockchip,pins = <0x01 0x0b 0x01 0x13a>; + phandle = <0xcf>; + }; + + i2s1m0-sdi1 { + rockchip,pins = <0x01 0x0a 0x02 0x13a>; + phandle = <0xd0>; + }; + + i2s1m0-sdi2 { + rockchip,pins = <0x01 0x09 0x02 0x13a>; + phandle = <0xd1>; + }; + + i2s1m0-sdi3 { + rockchip,pins = <0x01 0x08 0x02 0x13a>; + phandle = <0xd2>; + }; + + i2s1m0-sdo0 { + rockchip,pins = <0x01 0x07 0x01 0x13a>; + phandle = <0xce>; + }; + }; + + i2s2 { + + i2s2m0-lrcktx { + rockchip,pins = <0x02 0x13 0x01 0x139>; + phandle = <0xd4>; + }; + + i2s2m0-sclktx { + rockchip,pins = <0x02 0x12 0x01 0x139>; + phandle = <0xd3>; + }; + + i2s2m0-sdi { + rockchip,pins = <0x02 0x15 0x01 0x134>; + phandle = <0xd5>; + }; + + i2s2m0-sdo { + rockchip,pins = <0x02 0x14 0x01 0x134>; + phandle = <0xd6>; + }; + }; + + i2s3 { + + i2s3m0-lrck { + rockchip,pins = <0x03 0x04 0x04 0x139>; + phandle = <0xd8>; + }; + + i2s3m0-sclk { + rockchip,pins = <0x03 0x03 0x04 0x139>; + phandle = <0xd7>; + }; + + i2s3m0-sdi { + rockchip,pins = <0x03 0x06 0x04 0x134>; + phandle = <0xd9>; + }; + + i2s3m0-sdo { + rockchip,pins = <0x03 0x05 0x04 0x134>; + phandle = <0xda>; + }; + }; + + lcdc { + + lcdc-ctl { + rockchip,pins = <0x03 0x00 0x01 0x134 0x02 0x18 0x01 0x134 0x02 0x19 0x01 0x134 0x02 0x1a 0x01 0x134 0x02 0x1b 0x01 0x134 0x02 0x1c 0x01 0x134 0x02 0x1d 0x01 0x134 0x02 0x1e 0x01 0x134 0x02 0x1f 0x01 0x134 0x03 0x01 0x01 0x134 0x03 0x02 0x01 0x134 0x03 0x03 0x01 0x134 0x03 0x04 0x01 0x134 0x03 0x05 0x01 0x134 0x03 0x06 0x01 0x134 0x03 0x07 0x01 0x134 0x03 0x08 0x01 0x134 0x03 0x09 0x01 0x134 0x03 0x0a 0x01 0x134 0x03 0x0b 0x01 0x134 0x03 0x0c 0x01 0x134 0x03 0x0d 0x01 0x134 0x03 0x0e 0x01 0x134 0x03 0x0f 0x01 0x134 0x03 0x10 0x01 0x134 0x03 0x13 0x01 0x134 0x03 0x11 0x01 0x134 0x03 0x12 0x01 0x134>; + phandle = <0x36>; + }; + }; + + pdm { + + pdmm0-clk { + rockchip,pins = <0x01 0x06 0x03 0x134>; + phandle = <0xdb>; + }; + + pdmm0-clk1 { + rockchip,pins = <0x01 0x04 0x03 0x134>; + phandle = <0xdc>; + }; + + pdmm0-sdi0 { + rockchip,pins = <0x01 0x0b 0x02 0x134>; + phandle = <0xdd>; + }; + + pdmm0-sdi1 { + rockchip,pins = <0x01 0x0a 0x03 0x134>; + phandle = <0xde>; + }; + + pdmm0-sdi2 { + rockchip,pins = <0x01 0x09 0x03 0x134>; + phandle = <0xdf>; + }; + + pdmm0-sdi3 { + rockchip,pins = <0x01 0x08 0x03 0x134>; + phandle = <0xe0>; + }; + }; + + pmic { + + pmic_int { + rockchip,pins = <0x00 0x03 0x00 0x136>; + phandle = <0x40>; + }; + + soc_slppin_pin { + rockchip,pins = <0x00 0x02 0x00 0x13b>; + phandle = <0x43>; + }; + + soc_slppin_slp { + rockchip,pins = <0x00 0x02 0x01 0x136>; + phandle = <0x41>; + }; + + soc_slppin_rst { + rockchip,pins = <0x00 0x02 0x02 0x134>; + }; + }; + + pwm0 { + + pwm0m0-pins { + rockchip,pins = <0x00 0x0f 0x01 0x134>; + phandle = <0x4a>; + }; + }; + + pwm1 { + + pwm1m0-pins { + rockchip,pins = <0x00 0x10 0x01 0x134>; + phandle = <0x4b>; + }; + }; + + pwm2 { + + pwm2m0-pins { + rockchip,pins = <0x00 0x11 0x01 0x134>; + phandle = <0x4c>; + }; + }; + + pwm3 { + + pwm3-pins { + rockchip,pins = <0x00 0x12 0x01 0x134>; + phandle = <0x4d>; + }; + }; + + pwm4 { + + pwm4-pins { + rockchip,pins = <0x00 0x13 0x01 0x134>; + phandle = <0x110>; + }; + }; + + pwm5 { + + pwm5-pins { + rockchip,pins = <0x00 0x14 0x01 0x134>; + phandle = <0x111>; + }; + }; + + pwm6 { + + pwm6-pins { + rockchip,pins = <0x00 0x15 0x01 0x134>; + phandle = <0x112>; + }; + }; + + pwm7 { + + pwm7-pins { + rockchip,pins = <0x00 0x16 0x01 0x134>; + phandle = <0x113>; + }; + }; + + pwm8 { + + pwm8m0-pins { + rockchip,pins = <0x03 0x09 0x05 0x134>; + phandle = <0x114>; + }; + }; + + pwm9 { + + pwm9m0-pins { + rockchip,pins = <0x03 0x0a 0x05 0x134>; + phandle = <0x115>; + }; + }; + + pwm10 { + + pwm10m0-pins { + rockchip,pins = <0x03 0x0d 0x05 0x134>; + phandle = <0x116>; + }; + }; + + pwm11 { + + pwm11m0-pins { + rockchip,pins = <0x03 0x0e 0x05 0x134>; + phandle = <0x117>; + }; + }; + + pwm12 { + + pwm12m0-pins { + rockchip,pins = <0x03 0x0f 0x02 0x134>; + phandle = <0x118>; + }; + }; + + pwm13 { + + pwm13m0-pins { + rockchip,pins = <0x03 0x10 0x02 0x134>; + phandle = <0x119>; + }; + }; + + pwm14 { + + pwm14m0-pins { + rockchip,pins = <0x03 0x14 0x01 0x134>; + phandle = <0x11a>; + }; + }; + + pwm15 { + + pwm15m0-pins { + rockchip,pins = <0x03 0x15 0x01 0x134>; + phandle = <0x11b>; + }; + }; + + scr { + + scr-pins { + rockchip,pins = <0x01 0x02 0x03 0x134 0x01 0x07 0x03 0x136 0x01 0x03 0x03 0x136 0x01 0x05 0x03 0x134>; + phandle = <0xe4>; + }; + }; + + sdmmc0 { + + sdmmc0-bus4 { + rockchip,pins = <0x01 0x1d 0x01 0x135 0x01 0x1e 0x01 0x135 0x01 0x1f 0x01 0x135 0x02 0x00 0x01 0x135>; + phandle = <0xc5>; + }; + + sdmmc0-clk { + rockchip,pins = <0x02 0x02 0x01 0x135>; + phandle = <0xc6>; + }; + + sdmmc0-cmd { + rockchip,pins = <0x02 0x01 0x01 0x135>; + phandle = <0xc7>; + }; + + sdmmc0-det { + rockchip,pins = <0x00 0x04 0x01 0x136>; + phandle = <0xc8>; + }; + }; + + sdmmc2 { + + sdmmc2m0-bus4 { + rockchip,pins = <0x03 0x16 0x03 0x135 0x03 0x17 0x03 0x135 0x03 0x18 0x03 0x135 0x03 0x19 0x03 0x135>; + phandle = <0x86>; + }; + + sdmmc2m0-clk { + rockchip,pins = <0x03 0x1b 0x03 0x135>; + phandle = <0x88>; + }; + + sdmmc2m0-cmd { + rockchip,pins = <0x03 0x1a 0x03 0x135>; + phandle = <0x87>; + }; + }; + + spdif { + + spdifm0-tx { + rockchip,pins = <0x01 0x04 0x04 0x134>; + phandle = <0xe2>; + }; + }; + + spi0 { + + spi0m0-pins { + rockchip,pins = <0x00 0x0d 0x02 0x134 0x00 0x15 0x02 0x134 0x00 0x0e 0x02 0x134>; + phandle = <0xf7>; + }; + + spi0m0-cs0 { + rockchip,pins = <0x00 0x16 0x02 0x134>; + phandle = <0xf5>; + }; + + spi0m0-cs1 { + rockchip,pins = <0x00 0x14 0x02 0x134>; + phandle = <0xf6>; + }; + }; + + spi1 { + + spi1m0-pins { + rockchip,pins = <0x02 0x0d 0x03 0x134 0x02 0x0e 0x03 0x134 0x02 0x0f 0x04 0x134>; + phandle = <0xfb>; + }; + + spi1m0-cs0 { + rockchip,pins = <0x02 0x10 0x04 0x134>; + phandle = <0xf9>; + }; + + spi1m0-cs1 { + rockchip,pins = <0x02 0x16 0x03 0x134>; + phandle = <0xfa>; + }; + }; + + spi2 { + + spi2m0-pins { + rockchip,pins = <0x02 0x11 0x04 0x134 0x02 0x12 0x04 0x134 0x02 0x13 0x04 0x134>; + phandle = <0xff>; + }; + + spi2m0-cs0 { + rockchip,pins = <0x02 0x14 0x04 0x134>; + phandle = <0xfd>; + }; + + spi2m0-cs1 { + rockchip,pins = <0x02 0x15 0x04 0x134>; + phandle = <0xfe>; + }; + }; + + spi3 { + + spi3m0-pins { + rockchip,pins = <0x04 0x0b 0x04 0x134 0x04 0x08 0x04 0x134 0x04 0x0a 0x04 0x134>; + phandle = <0x103>; + }; + + spi3m0-cs0 { + rockchip,pins = <0x04 0x06 0x04 0x134>; + phandle = <0x101>; + }; + + spi3m0-cs1 { + rockchip,pins = <0x04 0x07 0x04 0x134>; + phandle = <0x102>; + }; + }; + + tsadc { + + tsadc-shutorg { + rockchip,pins = <0x00 0x01 0x02 0x134>; + phandle = <0x122>; + }; + }; + + uart0 { + + uart0-xfer { + rockchip,pins = <0x00 0x10 0x03 0x136 0x00 0x11 0x03 0x136>; + phandle = <0x49>; + }; + }; + + uart1 { + + uart1m0-xfer { + rockchip,pins = <0x02 0x0b 0x02 0x136 0x02 0x0c 0x02 0x136>; + phandle = <0x105>; + }; + + uart1m0-ctsn { + rockchip,pins = <0x02 0x0e 0x02 0x134>; + phandle = <0x106>; + }; + }; + + uart2 { + + uart2m0-xfer { + rockchip,pins = <0x00 0x18 0x01 0x136 0x00 0x19 0x01 0x136>; + phandle = <0x107>; + }; + }; + + uart3 { + + uart3m1-xfer { + rockchip,pins = <0x03 0x10 0x04 0x136 0x03 0x0f 0x04 0x136>; + phandle = <0x108>; + }; + }; + + uart4 { + + uart4m1-xfer { + rockchip,pins = <0x03 0x09 0x04 0x136 0x03 0x0a 0x04 0x136>; + phandle = <0x109>; + }; + }; + + uart5 { + + uart5m0-xfer { + rockchip,pins = <0x02 0x01 0x03 0x136 0x02 0x02 0x03 0x136>; + phandle = <0x10a>; + }; + }; + + uart6 { + + uart6m0-xfer { + rockchip,pins = <0x02 0x03 0x03 0x136 0x02 0x04 0x03 0x136>; + phandle = <0x10b>; + }; + }; + + uart7 { + + uart7m0-xfer { + rockchip,pins = <0x02 0x05 0x03 0x136 0x02 0x06 0x03 0x136>; + phandle = <0x10c>; + }; + }; + + uart8 { + + uart8m0-xfer { + rockchip,pins = <0x02 0x16 0x02 0x136 0x02 0x15 0x03 0x136>; + phandle = <0x10d>; + }; + + uart8m0-ctsn { + rockchip,pins = <0x02 0x0a 0x03 0x134>; + phandle = <0x10e>; + }; + + uart8m0-rtsn { + rockchip,pins = <0x02 0x09 0x03 0x134>; + phandle = <0x164>; + }; + }; + + uart9 { + + uart9m0-xfer { + rockchip,pins = <0x02 0x07 0x03 0x136 0x02 0x08 0x03 0x136>; + phandle = <0x10f>; + }; + }; + + spi0-hs { + + spi0m0-pins { + rockchip,pins = <0x00 0x0d 0x02 0x13c 0x00 0x15 0x02 0x13c 0x00 0x0e 0x02 0x13c>; + phandle = <0xf8>; + }; + }; + + spi1-hs { + + spi1m0-pins { + rockchip,pins = <0x02 0x0d 0x03 0x13c 0x02 0x0e 0x03 0x13c 0x02 0x0f 0x04 0x13c>; + phandle = <0xfc>; + }; + }; + + spi2-hs { + + spi2m0-pins { + rockchip,pins = <0x02 0x11 0x04 0x13c 0x02 0x12 0x04 0x13c 0x02 0x13 0x04 0x13c>; + phandle = <0x100>; + }; + }; + + spi3-hs { + + spi3m0-pins { + rockchip,pins = <0x04 0x0b 0x04 0x13c 0x04 0x08 0x04 0x13c 0x04 0x0a 0x04 0x13c>; + phandle = <0x104>; + }; + }; + + gpio-func { + + tsadc-gpio-func { + rockchip,pins = <0x00 0x01 0x00 0x134>; + phandle = <0x121>; + }; + }; + + mxc6655xa { + + mxc6655xa_irq_gpio { + rockchip,pins = <0x03 0x11 0x00 0x134>; + phandle = <0xf3>; + }; + }; + + touch { + + touch-gpio { + rockchip,pins = <0x00 0x0d 0x00 0x136 0x00 0x0e 0x00 0x134>; + phandle = <0xe9>; + }; + }; + + sdio-pwrseq { + + wifi-enable-h { + rockchip,pins = <0x03 0x1d 0x00 0x134>; + phandle = <0x162>; + }; + }; + + usb { + + vcc5v0-host-en { + rockchip,pins = <0x00 0x06 0x00 0x134>; + phandle = <0x15f>; + }; + + vcc5v0-otg-en { + rockchip,pins = <0x00 0x05 0x00 0x134>; + phandle = <0x160>; + }; + }; + + wireless-bluetooth { + + uart8-gpios { + rockchip,pins = <0x02 0x09 0x00 0x134>; + phandle = <0x165>; + }; + }; + + headphone { + + hp-det { + rockchip,pins = <0x03 0x13 0x00 0x13e>; + phandle = <0x166>; + }; + }; + + leds-gpio { + rockchip,pins = <0x04 0x12 0x00 0x136 0x04 0x13 0x00 0x136 0x04 0x15 0x00 0x136>; + }; + + wireless-wlan { + + wifi-host-wake-irq { + rockchip,pins = <0x03 0x1c 0x00 0x13e>; + phandle = <0x163>; + }; + }; + + rtc { + + rtc-int { + rockchip,pins = <0x00 0x1b 0x00 0x136>; + phandle = <0xf4>; + }; + }; + + mipi_pwren { + + mipi_power_en { + rockchip,pins = <0x03 0x0d 0x00 0x13f>; + phandle = <0xa7>; + }; + }; + }; + + chosen { + bootargs = "earlycon=uart8250,mmio32,0xfe660000 console=ttyS2,1500000n8 ohos.boot.eng_mode=on root=PARTUUID=614e0000-0000 hardware=rk3568 default_boot_device=fe310000.sdhci rw rootwait ohos.required_mount.system=/dev/block/platform/fe310000.sdhci/by-name/system@/usr@ext4@ro,barrier=1@wait,required ohos.required_mount.vendor=/dev/block/platform/fe310000.sdhci/by-name/vendor@/vendor@ext4@ro,barrier=1@wait,required ohos.required_mount.misc=/dev/block/platform/fe310000.sdhci/by-name/misc@none@none@none@wait,required ohos.required_mount.bootctrl=/dev/block/platform/fe310000.sdhci/by-name/bootctrl@none@none@none@wait,required"; + linux,initrd-start = <0x00 0xa200000>; + linux,initrd-end = <0x00 0xa600000>; + }; + + hvisor_virtio_device { + compatible = "hvisor"; + interrupt-parent = <0x01>; + interrupts = <0x00 0x6b 0x01>; + }; +}; diff --git a/platform/aarch64/dayu200/image/dts/zone1-ohos.dts b/platform/aarch64/dayu200/image/dts/zone1-ohos.dts new file mode 100644 index 000000000..ef7840cd6 --- /dev/null +++ b/platform/aarch64/dayu200/image/dts/zone1-ohos.dts @@ -0,0 +1,937 @@ +/dts-v1/; + +/ { + interrupt-parent = <0x01>; + #address-cells = <0x02>; + #size-cells = <0x02>; + compatible = "rockchip,rk3568-toybrick-dev-linux-x0\0rockchip,rk3568"; + + aliases { + dsi0 = "/dsi@fe060000"; + gpio3 = "/pinctrl/gpio3@fe760000"; + serial2 = "/serial@fe660000"; + mmc1 = "/dwmmc@fe2b0000"; + }; + + memory { + device_type = "memory"; + reg = <0x00 0x50000000 0x00 0x04000000 + 0x00 0x10000000 0x00 0x20000000 + 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00>; + }; + + cpus { + #address-cells = <0x02>; + #size-cells = <0x00>; + + // cpu@0 { + // device_type = "cpu"; + // compatible = "arm,cortex-a55"; + // reg = <0x00 0x00>; + // clocks = <0x02 0x00>; + // #cooling-cells = <0x02>; + // enable-method = "psci"; + // operating-points-v2 = <0x03>; + // cpu-idle-states = <0x04>; + // dynamic-power-coefficient = <0xbb>; + // cpu-supply = <0x05>; + // phandle = <0x1f>; + // }; + + // cpu@100 { + // device_type = "cpu"; + // compatible = "arm,cortex-a55"; + // reg = <0x00 0x100>; + // #cooling-cells = <0x02>; + // enable-method = "psci"; + // operating-points-v2 = <0x03>; + // cpu-idle-states = <0x04>; + // phandle = <0x20>; + // }; + + cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x00 0x200>; + #cooling-cells = <0x02>; + enable-method = "psci"; + operating-points-v2 = <0x03>; + cpu-idle-states = <0x04>; + phandle = <0x21>; + }; + + cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x00 0x300>; + #cooling-cells = <0x02>; + enable-method = "psci"; + operating-points-v2 = <0x03>; + cpu-idle-states = <0x04>; + phandle = <0x22>; + }; + + idle-states { + entry-method = "psci"; + + cpu-sleep { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x10000>; + entry-latency-us = <0x64>; + exit-latency-us = <0x78>; + min-residency-us = <0x3e8>; + phandle = <0x04>; + }; + }; + }; + + firmware { + + scmi { + compatible = "arm,scmi-smc"; + arm,smc-id = <0x82000010>; + shmem = <0x19>; + #address-cells = <0x01>; + #size-cells = <0x00>; + + protocol@14 { + reg = <0x14>; + #clock-cells = <0x01>; + rockchip,clk-init = <0x41cdb400>; + phandle = <0x02>; + }; + }; + + sdei { + compatible = "arm,sdei-1.0"; + method = "smc"; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + reserved-memory { + #address-cells = <0x02>; + #size-cells = <0x02>; + ranges; + + drm-logo@0 { + compatible = "rockchip,drm-logo"; + reg = <0x00 0x00 0x00 0x00>; + phandle = <0x0f>; + }; + + drm-cubic-lut@0 { + compatible = "rockchip,drm-cubic-lut"; + reg = <0x00 0x00 0x00 0x00>; + phandle = <0x10>; + }; + }; + + display-subsystem { + compatible = "rockchip,display-subsystem"; + memory-region = <0x0f 0x10>; + memory-region-names = "drm-logo\0drm-cubic-lut"; + ports = <0x11>; + + route { + + route-dsi0 { + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <0x13>; + }; + + route-dsi1 { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <0x14>; + }; + + route-edp { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <0x15>; + }; + + route-hdmi { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <0x16>; + }; + + route-lvds { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <0x17>; + }; + + route-rgb { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <0x18>; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <0x01 0x0d 0xf04 0x01 0x0e 0xf04 0x01 0x0b 0xf04 0x01 0x0a 0xf04>; + arm,no-tick-in-suspend; + }; + + // important + xin24m { + compatible = "fixed-clock"; + clock-frequency = <0x16e3600>; + clock-output-names = "xin24m"; + #clock-cells = <0x00>; + }; + + // important + xin32k { + compatible = "fixed-clock"; + clock-frequency = <0x8000>; + clock-output-names = "xin32k"; + pinctrl-0 = <0x23>; + pinctrl-names = "default"; + #clock-cells = <0x00>; + }; + + // important + scmi-shmem@10f000 { + compatible = "arm,scmi-shmem"; + reg = <0x00 0x10f000 0x00 0x100>; + phandle = <0x19>; + }; + + interrupt-controller@fd400000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <0x03>; + #address-cells = <0x02>; + #size-cells = <0x02>; + ranges; + interrupt-controller; + reg = <0x00 0xfd400000 0x00 0x10000 0x00 0xfd460000 0x00 0xc0000>; + interrupts = <0x01 0x09 0x04>; + phandle = <0x01>; + }; + + + syscon@fdc20000 { + compatible = "rockchip,rk3568-pmugrf\0syscon\0simple-mfd"; + reg = <0x00 0xfdc20000 0x00 0x10000>; + phandle = <0x3c>; + }; + + syscon@fdc60000 { + compatible = "rockchip,rk3568-grf\0syscon\0simple-mfd"; + reg = <0x00 0xfdc60000 0x00 0x10000>; + phandle = <0x3b>; + }; + + + clock-controller@fdd00000 { + compatible = "rockchip,rk3568-pmucru"; + reg = <0x00 0xfdd00000 0x00 0x1000>; + rockchip,grf = <0x3b>; + rockchip,pmugrf = <0x3c>; + #clock-cells = <0x01>; + #reset-cells = <0x01>; + assigned-clocks = <0x3a 0x32>; + assigned-clock-parents = <0x3a 0x05>; + phandle = <0x3a>; + }; + + clock-controller@fdd20000 { + compatible = "rockchip,rk3568-cru"; + reg = <0x00 0xfdd20000 0x00 0x1000>; + rockchip,grf = <0x3b>; + #clock-cells = <0x01>; + #reset-cells = <0x01>; + assigned-clocks = <0x3a 0x05 0x24 0x106 0x24 0x10b 0x3a 0x01 0x3a 0x2b 0x24 0x03 0x24 0x19b 0x24 0x09 0x24 0x19c 0x24 0x19d 0x24 0x1a1 0x24 0x19e 0x24 0x19f 0x24 0x1a0 0x24 0x04 0x24 0x10d 0x24 0x10e 0x24 0x173 0x24 0x174 0x24 0x175 0x24 0x176 0x24 0xc9 0x24 0xca 0x24 0x06 0x24 0x7e 0x24 0x7f 0x24 0x3d 0x24 0x41 0x24 0x45 0x24 0x49 0x24 0x4d 0x24 0x4d 0x24 0x55 0x24 0x51 0x24 0x5d 0x24 0xdd>; + assigned-clock-rates = <0x8000 0x11e1a300 0x11e1a300 0xbebc200 0x5f5e100 0x3b9aca00 0x1dcd6500 0x13d92d40 0xee6b280 0x7735940 0x5f5e100 0x3b9aca0 0x2faf080 0x17d7840 0x46cf7100 0x8f0d180 0x5f5e100 0x1dcd6500 0x17d78400 0x8f0d180 0x5f5e100 0x11e1a300 0x8f0d180 0x47868c00 0x17d78400 0x5f5e100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x1dcd6500>; + assigned-clock-parents = <0x3a 0x08 0x24 0x04 0x24 0x04>; + phandle = <0x24>; + }; + + power-management@fdd90000 { + compatible = "rockchip,rk3568-pmu\0syscon\0simple-mfd"; + reg = <0x00 0xfdd90000 0x00 0x1000>; + + power-controller { + compatible = "rockchip,rk3568-power-controller"; + #power-domain-cells = <0x01>; + #address-cells = <0x01>; + #size-cells = <0x00>; + phandle = <0x26>; + + power-domain@6 { + reg = <0x06>; + clocks = <0x24 0x27 0x24 0x25 0x24 0x26>; + pm_qos = <0x4e>; + }; + + power-domain@7 { + reg = <0x07>; + clocks = <0x24 0x19 0x24 0x1a>; + pm_qos = <0x4f>; + #power-domain-cells = <0x00>; + }; + + power-domain@8 { + reg = <0x08>; + clocks = <0x24 0xcc 0x24 0xcd>; + pm_qos = <0x50 0x51 0x52>; + #power-domain-cells = <0x00>; + }; + + power-domain@9 { + reg = <0x09>; + clocks = <0x24 0xda 0x24 0xdb 0x24 0xdc>; + pm_qos = <0x53 0x54 0x55>; + #power-domain-cells = <0x00>; + }; + + power-domain@10 { + reg = <0x0a>; + clocks = <0x24 0xf1 0x24 0xf2>; + pm_qos = <0x56 0x57 0x58 0x59 0x5a 0x5b>; + #power-domain-cells = <0x00>; + }; + + power-domain@11 { + reg = <0x0b>; + clocks = <0x24 0xed>; + pm_qos = <0x5c>; + #power-domain-cells = <0x00>; + }; + + power-domain@13 { + clocks = <0x24 0x107>; + reg = <0x0d>; + pm_qos = <0x5d>; + #power-domain-cells = <0x00>; + }; + + power-domain@14 { + reg = <0x0e>; + clocks = <0x24 0x102>; + pm_qos = <0x5e 0x5f 0x60>; + #power-domain-cells = <0x00>; + }; + + power-domain@15 { + reg = <0x0f>; + clocks = <0x24 0x7f>; + pm_qos = <0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68>; + #power-domain-cells = <0x00>; + }; + }; + }; + + vdd-gpu { + compatible = "regulator-fixed"; + regulator-name = "vdd_gpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0xdbba0>; + regulator-max-microvolt = <0xdbba0>; + phandle = <0x71>; + }; + + gpu@fde60000 { + compatible = "arm,mali-bifrost"; + reg = <0x00 0xfde60000 0x00 0x4000>; + interrupts = <0x00 0x27 0x04 0x00 0x29 0x04 0x00 0x28 0x04>; + interrupt-names = "GPU\0MMU\0JOB"; + upthreshold = <0x28>; + downdifferential = <0x0a>; + clocks = <0x02 0x01 0x24 0x1b>; + clock-names = "clk_mali\0clk_gpu"; + power-domains = <0x26 0x07>; + #cooling-cells = <0x02>; + status = "okay"; + mali-supply = <0x71>; + phandle = <0x11e>; + }; + + vop@fe040000 { + compatible = "rockchip,rk3568-vop"; + reg = <0x00 0xfe040000 0x00 0x3000 0x00 0xfe044000 0x00 0x1000>; + reg-names = "regs\0gamma_lut"; + interrupts = <0x00 0x94 0x04>; + clocks = <0x24 0xdd 0x24 0xde 0x24 0xdf 0x24 0xe0 0x24 0xe1>; + clock-names = "aclk_vop\0hclk_vop\0dclk_vp0\0dclk_vp1\0dclk_vp2"; + rockchip,aclk-normal-mode-rates = <0x179a7b00>; + rockchip,aclk-advanced-mode-rates = <0x1dcd6500>; + iommus = <0x95>; + power-domains = <0x26 0x09>; + rockchip,grf = <0x3b>; + status = "okay"; + assigned-clocks = <0x24 0xdf 0x24 0xe0>; + assigned-clock-parents = <0x3a 0x02 0x24 0x05>; + disable-afbc-win; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + phandle = <0x11>; + + port@0 { + reg = <0x00>; + #address-cells = <0x01>; + #size-cells = <0x00>; + + endpoint@0 { + reg = <0x00>; + phandle = <0xa3>; + }; + + endpoint@1 { + reg = <0x01>; + phandle = <0x14>; + }; + + endpoint@2 { + reg = <0x02>; + phandle = <0x15>; + }; + + endpoint@3 { + reg = <0x03>; + phandle = <0x16>; + }; + }; + + port@1 { + reg = <0x01>; + #address-cells = <0x01>; + #size-cells = <0x00>; + + endpoint@0 { + reg = <0x00>; + remote-endpoint = <0x9a>; + phandle = <0x13>; + }; + + endpoint@1 { + reg = <0x01>; + phandle = <0xab>; + }; + + endpoint@2 { + reg = <0x02>; + phandle = <0xb8>; + }; + + endpoint@3 { + reg = <0x03>; + phandle = <0xb6>; + }; + + endpoint@4 { + reg = <0x04>; + phandle = <0x17>; + }; + + endpoint@5 { + reg = <0x05>; + phandle = <0x38>; + }; + }; + + port@2 { + reg = <0x02>; + #address-cells = <0x01>; + #size-cells = <0x00>; + + endpoint@0 { + reg = <0x00>; + phandle = <0x35>; + }; + + endpoint@1 { + reg = <0x01>; + phandle = <0x18>; + }; + + endpoint@2 { + reg = <0x02>; + phandle = <0x39>; + }; + }; + }; + }; + + iommu@fe043e00 { + compatible = "rockchip,iommu-v2"; + reg = <0x00 0xfe043e00 0x00 0x100 0x00 0xfe043f00 0x00 0x100>; + interrupts = <0x00 0x94 0x04>; + interrupt-names = "vop_mmu"; + clocks = <0x24 0xdd 0x24 0xde>; + clock-names = "aclk\0iface"; + #iommu-cells = <0x00>; + rockchip,disable-device-link-resume; + status = "okay"; + phandle = <0x95>; + }; + + dsi@fe060000 { + compatible = "rockchip,rk3568-mipi-dsi"; + reg = <0x00 0xfe060000 0x00 0x10000>; + interrupts = <0x00 0x44 0x04>; + clock-names = "pclk\0hclk"; + clocks = <0x24 0xe8 0x24 0xda>; + phy-names = "dphy"; + phys = <0x34>; + power-domains = <0x26 0x09>; + reset-names = "apb"; + resets = <0x24 0x110>; + rockchip,grf = <0x3b>; + #address-cells = <0x01>; + #size-cells = <0x00>; + status = "okay"; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + #address-cells = <0x01>; + #size-cells = <0x00>; + + endpoint@1 { + reg = <0x01>; + remote-endpoint = <0x13>; + status = "okay"; + phandle = <0x9a>; + }; + }; + + port@1 { + reg = <0x01>; + + endpoint { + remote-endpoint = <0xa4>; + phandle = <0xaa>; + }; + }; + }; + + panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0x00>; + backlight = <0xa5>; + reset-delay-ms = <0x64>; + enable-delay-ms = <0x78>; + prepare-delay-ms = <0x02>; + unprepare-delay-ms = <0x14>; + disable-delay-ms = <0x32>; + dsi,flags = <0xa03>; + dsi,format = <0x00>; + dsi,lanes = <0x04>; + panel-init-sequence = <0x5640111 0x390004ff 0x98810315 0x20100 0x15000202 0x150002 0x3721500 0x2040015 0x20500 0x15000206 0x9150002 0x7001500 0x2080015 0x20901 0x1500020a 0x150002 0xb001500 0x20c0115 0x20d00 0x1500020e 0x150002 0xf001500 0x2100015 0x21100 0x15000212 0x150002 0x13001500 0x2140015 0x21500 0x15000216 0x150002 0x17001500 0x2180015 0x21900 0x1500021a 0x150002 0x1b001500 0x21c0015 0x21d00 0x1500021e 0x40150002 0x1f801500 0x2200515 0x22102 0x15000222 0x150002 0x23001500 0x2240015 0x22500 0x15000226 0x150002 0x27001500 0x2283315 0x22902 0x1500022a 0x150002 0x2b001500 0x22c0015 0x22d00 0x1500022e 0x150002 0x2f001500 0x2300015 0x23100 0x15000232 0x150002 0x33001500 0x2340415 0x23500 0x15000236 0x150002 0x37001500 0x2383c15 0x23900 0x1500023a 0x40150002 0x3b401500 0x23c0015 0x23d00 0x1500023e 0x150002 0x3f001500 0x2400015 0x24100 0x15000242 0x150002 0x43001500 0x2440015 0x25001 0x15000251 0x23150002 0x52451500 0x2536715 0x25489 0x15000255 0xab150002 0x56011500 0x2572315 0x25845 0x15000259 0x67150002 0x5a891500 0x25bab15 0x25ccd 0x1500025d 0xef150002 0x5e111500 0x25f0115 0x26000 0x15000261 0x15150002 0x62141500 0x2630e15 0x2640f 0x15000265 0xc150002 0x660d1500 0x2670615 0x26802 0x15000269 0x2150002 0x6a021500 0x26b0215 0x26c02 0x1500026d 0x2150002 0x6e071500 0x26f0215 0x27002 0x15000271 0x2150002 0x72021500 0x2730215 0x27402 0x15000275 0x1150002 0x76001500 0x2771415 0x27815 0x15000279 0xe150002 0x7a0f1500 0x27b0c15 0x27c0d 0x1500027d 0x6150002 0x7e021500 0x27f0215 0x28002 0x15000281 0x2150002 0x82021500 0x2830215 0x28407 0x15000285 0x2150002 0x86021500 0x2870215 0x28802 0x15000289 0x2150002 0x8a023900 0x4ff9881 0x4150002 0x6c151500 0x26e2a15 0x26f33 0x1500023a 0x94150002 0x8d1a1500 0x287ba15 0x22676 0x150002b2 0xd1150002 0xb5063900 0x4ff9881 0x1150002 0x220a1500 0x2310015 0x24013 0x15000253 0x84150002 0x558f1500 0x250ae15 0x251ae 0x15000260 0x28150002 0xa00f1500 0x2a11b15 0x2a228 0x150002a3 0x12150002 0xa4151500 0x2a52815 0x2a61b 0x150002a7 0x1e150002 0xa8791500 0x2a91b15 0x2aa27 0x150002ab 0x69150002 0xac191500 0x2ad1815 0x2ae4c 0x150002af 0x21150002 0xb0281500 0x2b15215 0x2b265 0x150002c0 0x4150002 0xc11b1500 0x2c22715 0x2c313 0x150002c4 0x15150002 0xc5281500 0x2c61c15 0x2c71e 0x150002c8 0x79150002 0xc91a1500 0x2ca2715 0x2cb69 0x150002cc 0x1a150002 0xcd181500 0x2ce4c15 0x2cf21 0x150002d0 0x27150002 0xd1521500 0x2d26515 0x2d33f 0x390004ff 0x98810005 0x32012915 0x23500>; + panel-exit-sequence = <0x5320128 0x5c80110>; + power-supply = <0xa6>; + init-delay-ms = <0x14>; + pinctrl-names = "default"; + pinctrl-0 = <0xa7>; + enable-gpios = <0xa8 0x0d 0x00>; + width-mm = <0x44>; + height-mm = <0x79>; + pnel-type = <0x05>; + + display-timings { + native-mode = <0xa9>; + + timing0 { + clock-frequency = <0x47868c0>; + hactive = <0x2d0>; + vactive = <0x500>; + hfront-porch = <0x28>; + hsync-len = <0x0a>; + hback-porch = <0x28>; + vfront-porch = <0x0a>; + vsync-len = <0x24>; + vback-porch = <0x0f>; + hsync-active = <0x00>; + vsync-active = <0x00>; + de-active = <0x00>; + pixelclk-active = <0x00>; + phandle = <0xa9>; + }; + }; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint { + remote-endpoint = <0xaa>; + phandle = <0xa4>; + }; + }; + }; + }; + }; + + dwmmc@fe2b0000 { + compatible = "rockchip,rk3568-dw-mshc\0rockchip,rk3288-dw-mshc"; + reg = <0x00 0xfe2b0000 0x00 0x4000>; + interrupts = <0x00 0x62 0x04>; + clocks = <0x24 0xb0 0x24 0xb1 0x24 0x18a 0x24 0x18b>; + clock-names = "biu\0ciu\0ciu-drive\0ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <0x8f0d180>; + resets = <0x24 0xd4>; + reset-names = "reset"; + status = "okay"; + supports-sd; + bus-width = <0x04>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + no-1-8-v; + pinctrl-names = "default"; + pinctrl-0 = <0xc5 0xc6 0xc7 0xc8>; + }; + + pwm@fe6e0000 { + compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm"; + reg = <0x00 0xfe6e0000 0x00 0x10>; + interrupts = <0x00 0x53 0x04>; + clocks = <0x24 0x15a 0x24 0x159>; + clock-names = "pwm\0pclk"; + pinctrl-0 = <0x110>; + pinctrl-names = "active"; + #pwm-cells = <0x03>; + status = "okay"; + phandle = <0x154>; + }; + + phy@fe850000 { + compatible = "rockchip,rk3568-dsi-dphy\0rockchip,rk3568-video-phy"; + reg = <0x00 0xfe850000 0x00 0x10000 0x00 0xfe060000 0x00 0x10000>; + reg-names = "phy\0host"; + clocks = <0x3a 0x17 0x24 0x17a 0x24 0xe8>; + clock-names = "ref\0pclk\0pclk_host"; + #clock-cells = <0x00>; + resets = <0x24 0x1bb>; + reset-names = "apb"; + power-domains = <0x26 0x09>; + #phy-cells = <0x00>; + status = "okay"; + phandle = <0x34>; + }; + + pinctrl { + compatible = "rockchip,rk3568-pinctrl"; + rockchip,grf = <0x3b>; + rockchip,pmu = <0x3c>; + #address-cells = <0x02>; + #size-cells = <0x02>; + ranges; + + gpio0@fdd60000 { + compatible = "rockchip,gpio-bank"; + reg = <0x00 0xfdd60000 0x00 0x100>; + interrupts = <0x00 0x21 0x04>; + clocks = <0x3a 0x2e 0x3a 0x0c>; + gpio-controller; + #gpio-cells = <0x02>; + interrupt-controller; + #interrupt-cells = <0x02>; + phandle = <0x3f>; + }; + + gpio3@fe760000 { + compatible = "rockchip,gpio-bank"; + reg = <0x00 0xfe760000 0x00 0x100>; + interrupts = <0x00 0x24 0x04>; + clocks = <0x24 0x167 0x24 0x168>; + gpio-controller; + #gpio-cells = <0x02>; + interrupt-controller; + #interrupt-cells = <0x02>; + phandle = <0xa8>; + }; + + pcfg-pull-up { + bias-pull-up; + phandle = <0x136>; + }; + + pcfg-pull-down { + bias-pull-down; + phandle = <0x13e>; + }; + + pcfg-pull-none { + bias-disable; + phandle = <0x134>; + }; + + pcfg-pull-none-drv-level-1 { + bias-disable; + drive-strength = <0x01>; + phandle = <0x138>; + }; + + pcfg-pull-none-drv-level-2 { + bias-disable; + drive-strength = <0x02>; + phandle = <0x137>; + }; + + pcfg-pull-none-drv-level-3 { + bias-disable; + drive-strength = <0x03>; + phandle = <0x13d>; + }; + + pcfg-pull-up-drv-level-1 { + bias-pull-up; + drive-strength = <0x01>; + phandle = <0x13c>; + }; + + pcfg-pull-up-drv-level-2 { + bias-pull-up; + drive-strength = <0x02>; + phandle = <0x135>; + }; + + pcfg-pull-up-drv-level-4 { + bias-pull-up; + drive-strength = <0x04>; + phandle = <0x13a>; + }; + + pcfg-pull-none-smt { + bias-disable; + input-schmitt-enable; + phandle = <0x139>; + }; + + pcfg-output-high { + output-high; + phandle = <0x13f>; + }; + + pcfg-output-low-pull-down { + output-low; + bias-pull-down; + phandle = <0x13b>; + }; + + clk32k { + + clk32k-out0 { + rockchip,pins = <0x00 0x08 0x02 0x134>; + phandle = <0x23>; + }; + }; + + sdmmc0 { + + sdmmc0-bus4 { + rockchip,pins = <0x01 0x1d 0x01 0x135 0x01 0x1e 0x01 0x135 0x01 0x1f 0x01 0x135 0x02 0x00 0x01 0x135>; + phandle = <0xc5>; + }; + + sdmmc0-clk { + rockchip,pins = <0x02 0x02 0x01 0x135>; + phandle = <0xc6>; + }; + + sdmmc0-cmd { + rockchip,pins = <0x02 0x01 0x01 0x135>; + phandle = <0xc7>; + }; + + sdmmc0-det { + rockchip,pins = <0x00 0x04 0x01 0x136>; + phandle = <0xc8>; + }; + }; + + uart2 { + + uart2m0-xfer { + rockchip,pins = <0x00 0x18 0x01 0x136 0x00 0x19 0x01 0x136>; + phandle = <0x107>; + }; + }; + + pwm4 { + + pwm4-pins { + rockchip,pins = <0x00 0x13 0x01 0x134>; + phandle = <0x110>; + }; + }; + + mipi_pwren { + + mipi_power_en { + rockchip,pins = <0x03 0x0d 0x00 0x13f>; + phandle = <0xa7>; + }; + }; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <0x154 0x00 0x61a8 0x00>; + brightness-levels = <0x00 0x14 0x14 0x15 0x15 0x16 0x16 0x17 0x17 0x18 0x18 0x19 0x19 0x1a 0x1a 0x1b 0x1b 0x1c 0x1c 0x1d 0x1d 0x1e 0x1e 0x1f 0x1f 0x20 0x20 0x21 0x21 0x22 0x22 0x23 0x23 0x24 0x24 0x25 0x25 0x26 0x26 0x27 0x28 0x29 0x2a 0x2b 0x2c 0x2d 0x2e 0x2f 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3a 0x3b 0x3c 0x3d 0x3e 0x3f 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4a 0x4b 0x4c 0x4d 0x4e 0x4f 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5a 0x5b 0x5c 0x5d 0x5e 0x5f 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6a 0x6b 0x6c 0x6d 0x6e 0x6f 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7a 0x7b 0x7c 0x7d 0x7e 0x7f 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9a 0x9b 0x9c 0x9d 0x9e 0x9f 0xa0 0xa1 0xa2 0xa3 0xa4 0xa5 0xa6 0xa7 0xa8 0xa9 0xaa 0xab 0xac 0xad 0xae 0xaf 0xb0 0xb1 0xb2 0xb3 0xb4 0xb5 0xb6 0xb7 0xb8 0xb9 0xba 0xbb 0xbc 0xbd 0xbe 0xbf 0xc0 0xc1 0xc2 0xc3 0xc4 0xc5 0xc6 0xc7 0xc8 0xc9 0xca 0xcb 0xcc 0xcd 0xce 0xcf 0xd0 0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 0xd7 0xd8 0xd9 0xda 0xdb 0xdc 0xdd 0xde 0xdf 0xe0 0xe1 0xe2 0xe3 0xe4 0xe5 0xe6 0xe7 0xe8 0xe9 0xea 0xeb 0xec 0xed 0xee 0xef 0xf0 0xf1 0xf2 0xf3 0xf4 0xf5 0xf6 0xf7 0xf8 0xf9 0xfa 0xfb 0xfc 0xfd 0xfe 0xff>; + default-brightness-level = <0xc8>; + status = "okay"; + phandle = <0xa5>; + }; + + vcc3v3-lcd0-n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd0_n"; + regulator-boot-on; + gpio = <0x3f 0x17 0x00>; + enable-active-high; + phandle = <0xa6>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + virtio_mmio@ff9d0000 { + dma-coherent; + interrupt-parent = <0x01>; + interrupts = <0x00 0x6e 0x01>; + reg = <0x00 0xff9d0000 0x00 0x200>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@ff9e0000 { + dma-coherent; + interrupt-parent = <0x01>; + interrupts = <0x00 0x6c 0x01>; + reg = <0x00 0xff9e0000 0x00 0x200>; + compatible = "virtio,mmio"; + }; + + chosen { + bootargs = "earlycon=virtio,mmio,0xff9d0000 console=hvc0 ignore_loglevel loglevel=8 initcall_debug clk_ignore_unused pd_ignore_unused bootslots=0 ohos.boot.eng_mode=on root=PARTUUID=614e0000-0000 hardware=rk3568 default_boot_device=fe2b0000.dwmmc rw rootwait ohos.required_mount.system=/dev/block/platform/fe2b0000.dwmmc/by-name/system@/usr@ext4@ro,barrier=1@wait,required ohos.required_mount.vendor=/dev/block/platform/fe2b0000.dwmmc/by-name/vendor@/vendor@ext4@ro,barrier=1@wait,required ohos.required_mount.misc=/dev/block/platform/fe2b0000.dwmmc/by-name/misc@none@none@none@wait,required ohos.required_mount.bootctrl=/dev/block/platform/fe2b0000.dwmmc/by-name/bootctrl@none@none@none@wait,required"; + stdout-path = "/virtio_mmio@ff9d0000"; + linux,initrd-start = <0x00 0x50200000>; + linux,initrd-end = <0x00 0x50600000>; + }; +}; + + +// 请勿删除这段注释。裸启动修改集中放这里。需要启用时取消整段注释；需要关闭时注释整段。（已经通过反编译确定改动有效了） +&{/} { + memory { + device_type = "memory"; + reg = <0x00 0x200000 0x00 0x8200000 + 0x00 0x9400000 0x00 0x76c00000 + 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00>; + }; + + reserved-memory { + #size-cells = <0x02>; + ranges; + #address-cells = <0x02>; + + hvisor@40400000 { + no-map; + reg = <0x00 0x40400000 0x00 0x4900000>; + }; + + ohos-zone1-bootarea { + no-map; + reg = <0x00 0x50000000 0x00 0x04000000>; + // [0x5000_0000, 0x5020_0000), 2 MiB, device-tree-blob + // [0x5020_0000, 0x5060_0000), 4 MiB, ramdisk + // [0x5060_0000, 0x5360_0000), 48 MiB, kernel + // [0x5360_0000, 0x5400_0000) free + }; + + ohos-zone1-memory { + no-map; + reg = <0x00 0x10000000 0x00 0x20000000>; + }; + }; + + serial@fe660000 { + compatible = "rockchip,rk3568-uart\0snps,dw-apb-uart"; + reg = <0x00 0xfe660000 0x00 0x100>; + interrupts = <0x00 0x76 0x04>; + clocks = <0x24 0x123 0x24 0x120>; + clock-names = "baudclk\0apb_pclk"; + dmas = <0x48 0x04 0x48 0x05>; + pinctrl-0 = <0x107>; + pinctrl-names = "default"; + reg-io-width = <0x04>; + reg-shift = <0x02>; + status = "okay"; + }; + + chosen { + bootargs = "earlycon=uart8250,mmio32,0xfe660000 console=ttyS2,1500000n8 enforcing=0 ignore_loglevel loglevel=8 initcall_debug clk_ignore_unused pd_ignore_unused bootslots=0 ohos.boot.eng_mode=on root=PARTUUID=614e0000-0000 hardware=rk3568 default_boot_device=fe2b0000.dwmmc rw rootwait ohos.required_mount.system=/dev/block/platform/fe2b0000.dwmmc/by-name/system@/usr@ext4@ro,barrier=1@wait,required ohos.required_mount.vendor=/dev/block/platform/fe2b0000.dwmmc/by-name/vendor@/vendor@ext4@ro,barrier=1@wait,required ohos.required_mount.misc=/dev/block/platform/fe2b0000.dwmmc/by-name/misc@none@none@none@wait,required ohos.required_mount.bootctrl=/dev/block/platform/fe2b0000.dwmmc/by-name/bootctrl@none@none@none@wait,required"; + linux,initrd-start = <0x00 0xa200000>; + linux,initrd-end = <0x00 0xa600000>; + }; + + virtio_mmio@ff9e0000 { + status = "disabled"; + }; + + virtio_mmio@ff9d0000 { + status = "disabled"; + }; +}; diff --git a/platform/aarch64/dayu200/kconfig/defconfig b/platform/aarch64/dayu200/kconfig/defconfig new file mode 100644 index 000000000..242faa328 --- /dev/null +++ b/platform/aarch64/dayu200/kconfig/defconfig @@ -0,0 +1,3 @@ +CONFIG_ARCH_AARCH64=y +CONFIG_IRQ_GICV3=y +CONFIG_UART_16550=y diff --git a/platform/aarch64/dayu200/linker.ld b/platform/aarch64/dayu200/linker.ld new file mode 100644 index 000000000..5add6faa1 --- /dev/null +++ b/platform/aarch64/dayu200/linker.ld @@ -0,0 +1,68 @@ +ENTRY(arch_entry) +BASE_ADDRESS = 0x40400000; +CPU_NUM = 4; + +SECTIONS +{ + . = BASE_ADDRESS; + skernel = .; + + .boot : { + *(.text.boot) + *(.data.boot) + } + + stext = .; + .text : { + *(.text.entry) + *(.text .text.*) + } + + . = ALIGN(4K); + etext = .; + srodata = .; + .rodata : { + *(.rodata .rodata.*) + *(.srodata .srodata.*) + } + + . = ALIGN(4K); + erodata = .; + sdata = .; + .data : { + *(.data .data.*) + *(.sdata .sdata.*) + } + + . = ALIGN(4K); + edata = .; + .bss : { + *(.bss.stack) + sbss = .; + *(.bss .bss.*) + *(.sbss .sbss.*) + } + + . = ALIGN(4K); + _percpu_start = .; + _percpu_end = _percpu_start + SIZEOF(.percpu); + .percpu 0x0 (NOLOAD) : AT(_percpu_start) { + _percpu_load_start = .; + *(.percpu .percpu.*) + _percpu_load_end = .; + . = _percpu_load_start + ALIGN(64) * CPU_NUM; + } + . = _percpu_end; + + . = ALIGN(4K); + ebss = .; + ekernel = .; + + /DISCARD/ : { + *(.eh_frame) + } + . = ALIGN(4K); + __core_end = .; +} + +__hv_end = __core_end + HV_EXTENDED_SIZE; diff --git a/platform/aarch64/dayu200/platform.mk b/platform/aarch64/dayu200/platform.mk new file mode 100644 index 000000000..3e0f80cfa --- /dev/null +++ b/platform/aarch64/dayu200/platform.mk @@ -0,0 +1,8 @@ +$(hvisor_bin): elf + @if ! command -v mkimage > /dev/null; then \ + sudo apt update && sudo apt install u-boot-tools; \ + fi && \ + $(OBJCOPY) $(hvisor_elf) --strip-all -O binary $(hvisor_bin).tmp && \ + mkimage -n hvisor_img -A arm64 -O linux -C none -T kernel -a 0x40400000 \ + -e 0x40400000 -d $(hvisor_bin).tmp $(hvisor_bin) && \ + rm -rf $(hvisor_bin).tmp \ No newline at end of file diff --git a/platform/aarch64/imx8mp/board.rs b/platform/aarch64/imx8mp/board.rs index c9b5ece0b..6d920944f 100644 --- a/platform/aarch64/imx8mp/board.rs +++ b/platform/aarch64/imx8mp/board.rs @@ -16,11 +16,14 @@ use crate::{ arch::{ mmu::MemoryType, - zone::{GicConfig, Gicv3Config, HvArchZoneConfig}, + zone::{GicConfig, Gicv3Config, HvArchZoneConfig, UefiConfig}, }, config::*, }; +use crate::pci::vpci_dev::VpciDevType; +use crate::pci_dev; + pub const BOARD_NAME: &str = "imx8mp"; pub const BOARD_NCPUS: usize = 4; @@ -34,6 +37,9 @@ pub static BOARD_MPIDR_MAPPINGS: [u64; BOARD_NCPUS] = [ 0x3, // cpu3 ]; +/// Early boot cache invalidate mask (per CPU): bit0->L1(D), bit1->L2, bit2->L3. +pub static BOARD_EARLY_CACHE_INVALIDATE_MASKS: [u64; BOARD_NCPUS] = [0b011; BOARD_NCPUS]; + /// The physical memory layout of the board. /// Each address should align to 2M (0x200000). /// Addresses must be in ascending order. @@ -107,14 +113,23 @@ pub const ROOT_ZONE_MEMORY_REGIONS: [HvConfigMemoryRegion; 8] = [ // virtual_start: 0x30890000, // size: 0x1000, // }, // serial + // 0x32f00000 + // HvConfigMemoryRegion { + // mem_type: MEM_TYPE_IO, + // physical_start: 0x32f00000, + // virtual_start: 0x32f00000, + // size: 0x10000, + // }, // pcie-phy ]; pub const IRQ_WAKEUP_VIRTIO_DEVICE: usize = 32 + 0x20; pub const ROOT_ZONE_IRQS_BITMAP: &[BitmapWord] = &get_irqs_bitmap(&[ 35, 36, 37, 38, 45, 52, 55, 56, 57, 59, 64, 67, 75, 96, 97, 98, 99, 100, 101, 102, 103, 104, - 105, 135, 150, 151, 152, 162, + 105, 135, 150, 151, 152, 162, 172, 159, ]); +pub const ROOT_ZONE_IVC_CONFIG: [HvIvcConfig; 0] = []; + pub const ROOT_ARCH_ZONE_CONFIG: HvArchZoneConfig = HvArchZoneConfig { is_aarch32: 0, gic_config: GicConfig::Gicv3(Gicv3Config { @@ -125,6 +140,42 @@ pub const ROOT_ARCH_ZONE_CONFIG: HvArchZoneConfig = HvArchZoneConfig { gits_base: 0, gits_size: 0, }), + uefi_config: UefiConfig::NoUefi }; -pub const ROOT_ZONE_IVC_CONFIG: [HvIvcConfig; 0] = []; +pub const ROOT_PCI_CONFIG: &[HvPciConfig] = &[HvPciConfig { + ecam_base: 0x33800000, + ecam_size: 0x400000, + io_base: 0x1ff80000, + io_size: 0x10000, + pci_io_base: 0x0, + mem32_base: 0x1800_0000, + mem32_size: 0x7f0_0000, + pci_mem32_base: 0x1800_0000, + mem64_base: 0x0, + mem64_size: 0x0, + pci_mem64_base: 0x0, + bus_range_begin: 0x0, + bus_range_end: 0x1f, + domain: 0x0, +}]; + +pub const ROOT_DWC_ATU_CONFIG: &[HvDwcAtuConfig] = &[HvDwcAtuConfig { + ecam_base: 0x33800000, + dbi_base: 0x33800000, + dbi_size: 0x400000, + apb_base: 0x0, + apb_size: 0x0, + cfg_base: 0x1ff00000, + cfg_size: 0x80000, + io_cfg_atu_shared: 1, + io_atu_index: 1, + dw_msi_irq: 172, +}]; + +pub const ROOT_PCI_DEVS: [HvPciDevConfig; 2] = [ + pci_dev!(0x0, 0x00, 0x0, 0x0 => 0x0, 0x0, 0x0, VpciDevType::Physical), + pci_dev!(0x0, 0x01, 0x0, 0x0 => 0x1, 0x0, 0x0, VpciDevType::Physical), + // pci_dev!(0x0, 0x02, 0x10, 0x0 => 0x02, 0x10, 0x0, VpciDevType::Physical), // SRIOV VF + // pci_dev!(0x0, 0x02, 0x10, 0x4 => 0x02, 0x10, 0x4, VpciDevType::Physical), // SRIOV VF +]; diff --git a/platform/aarch64/imx8mp/cargo/features b/platform/aarch64/imx8mp/cargo/features deleted file mode 100644 index 7acf44c69..000000000 --- a/platform/aarch64/imx8mp/cargo/features +++ /dev/null @@ -1,2 +0,0 @@ -gicv3 -imx_uart diff --git a/platform/aarch64/imx8mp/configs/zone1-linux.json b/platform/aarch64/imx8mp/configs/zone1-linux.json index dd7d732a8..086101e5c 100644 --- a/platform/aarch64/imx8mp/configs/zone1-linux.json +++ b/platform/aarch64/imx8mp/configs/zone1-linux.json @@ -2,80 +2,154 @@ "arch": "arm64", "name": "linux2", "zone_id": 1, - "cpus": [2, 3], + "cpus": [ + 2, + 3 + ], "memory_regions": [ { "type": "ram", "physical_start": "0x50000000", - "virtual_start": "0x50000000", + "virtual_start": "0x50000000", "size": "0x30000000" }, { "type": "io", "physical_start": "0x30a60000", - "virtual_start": "0x30a60000", + "virtual_start": "0x30a60000", "size": "0x10000" }, { "type": "virtio", "physical_start": "0xa003c00", - "virtual_start": "0xa003c00", + "virtual_start": "0xa003c00", "size": "0x200" }, { "type": "virtio", "physical_start": "0xa003800", - "virtual_start": "0xa003800", + "virtual_start": "0xa003800", "size": "0x200" }, { "type": "virtio", "physical_start": "0xa003600", - "virtual_start": "0xa003600", + "virtual_start": "0xa003600", "size": "0x200" }, { "type": "io", "physical_start": "0x38000000", - "virtual_start": "0x38000000", + "virtual_start": "0x38000000", "size": "0x10000" }, { "type": "io", "physical_start": "0x38500000", - "virtual_start": "0x38500000", + "virtual_start": "0x38500000", "size": "0x20000" }, { "type": "io", "physical_start": "0x32e80000", - "virtual_start": "0x32e80000", + "virtual_start": "0x32e80000", "size": "0x20000" }, { "type": "io", "physical_start": "0x30c00000", - "virtual_start": "0x30c00000", + "virtual_start": "0x30c00000", "size": "0x400000" }, { "type": "io", "physical_start": "0x32fc0000", - "virtual_start": "0x32fc0000", + "virtual_start": "0x32fc0000", "size": "0x20000" } ], - "interrupts": [35, 37, 38, 45, 56, 57, 61, 75, 76, 78, 135, 162], + "interrupts": [ + 35, + 37, + 38, + 45, + 56, + 57, + 61, + 75, + 76, + 78, + 135, + 162, + 172 + ], "ivc_configs": [], "kernel_filepath": "./Image", "dtb_filepath": "./linux2.dtb", "kernel_load_paddr": "0x50400000", - "dtb_load_paddr": "0x50000000", - "entry_point": "0x50400000", + "dtb_load_paddr": "0x50000000", + "entry_point": "0x50400000", "arch_config": { + "gic_version": "v3", "gicd_base": "0x38800000", "gicd_size": "0x10000", "gicr_base": "0x38880000", - "gicr_size": "0xc0000" - } -} + "gicr_size": "0xc0000", + "is_aarch32": false + }, + "pci_config": [ + { + "ecam_base": "0x33800000", + "ecam_size": "0x400000", + "io_base": "0x1ff80000", + "io_size": "0x10000", + "pci_io_base": "0x0", + "mem32_base": "0x18000000", + "mem32_size": "0x7f00000", + "pci_mem32_base": "0x18000000", + "mem64_base": "0x0", + "mem64_size": "0x0", + "pci_mem64_base": "0x0", + "bus_range_begin": "0x0", + "bus_range_end": "0x1f", + "domain": "0x0" + } + ], + "dwc_atu_config": [ + { + "ecam_base": "0x33800000", + "dbi_base": "0x33800000", + "dbi_size": "0x400000", + "apb_base": "0x0", + "apb_size": "0x0", + "cfg_base": "0x1ff00000", + "cfg_size": "0x10000", + "io_cfg_atu_shared": 1, + "io_atu_index": 1, + "dw_msi_irq": 172 + } + ], + "num_pci_devs": 2, + "alloc_pci_devs": [ + { + "domain": "0x0", + "bus": "0x0", + "device": "0x0", + "function": "0x0", + "v_bus": "0x0", + "v_device": "0x0", + "v_function": "0x0", + "dev_type": "0" + }, + { + "domain": "0x0", + "bus": "0x1", + "device": "0x0", + "function": "0x1", + "v_bus": "0x1", + "v_device": "0x0", + "v_function": "0x0", + "dev_type": "0" + } + ] +} \ No newline at end of file diff --git a/platform/aarch64/imx8mp/kconfig/defconfig b/platform/aarch64/imx8mp/kconfig/defconfig new file mode 100644 index 000000000..83416cbda --- /dev/null +++ b/platform/aarch64/imx8mp/kconfig/defconfig @@ -0,0 +1,9 @@ +CONFIG_ARCH_AARCH64=y +CONFIG_IMX_UART=y +CONFIG_IRQ_GICV3=y +CONFIG_PCI=y +CONFIG_PCIE_DWC=y +CONFIG_NO_PCIE_BAR_REALLOC=y +CONFIG_DWC_MSI=y +CONFIG_PCI_INIT_DELAY=y +CONFIG_SRIOV=y diff --git a/platform/aarch64/imx8mp/platform.mk b/platform/aarch64/imx8mp/platform.mk index 5e5809f0f..d4014f9a9 100644 --- a/platform/aarch64/imx8mp/platform.mk +++ b/platform/aarch64/imx8mp/platform.mk @@ -1,6 +1,6 @@ QEMU := qemu-system-aarch64 -ifeq ($(findstring gicv3, $(FEATURES)),gicv3) +ifneq ($(shell grep -Fx CONFIG_IRQ_GICV3=y platform/$(ARCH)/$(BOARD)/kconfig/defconfig 2>/dev/null),) UBOOT := $(image_dir)/bootloader/u-boot-atf.bin zone0_dtb := $(image_dir)/devicetree/linux1.dtb QEMU_ARGS := -machine virt,secure=on,gic-version=3,virtualization=on,iommu=smmuv3 diff --git a/platform/aarch64/jeston-orin/board.rs b/platform/aarch64/jeston-orin/board.rs new file mode 100644 index 000000000..af1a79709 --- /dev/null +++ b/platform/aarch64/jeston-orin/board.rs @@ -0,0 +1,138 @@ +// Copyright (c) 2025 Syswonder +// hvisor is licensed under Mulan PSL v2. +// You can use this software according to the terms and conditions of the Mulan PSL v2. +// You may obtain a copy of Mulan PSL v2 at: +// http://license.coscl.org.cn/MulanPSL2 +// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR +// FIT FOR A PARTICULAR PURPOSE. +// See the Mulan PSL v2 for more details. +// +// Syswonder Website: +// https://www.syswonder.org +// +// Authors: +// +use crate::{ + arch::{ + mmu::MemoryType, + zone::{GicConfig, Gicv3Config, HvArchZoneConfig, Uefi, UefiConfig}, + }, + config::*, +}; + +pub const BOARD_NAME: &str = "jeston-orin"; +pub const BOARD_NCPUS: usize = 6; +pub const BOARD_UART_BASE: u64 = 0xc280000; +pub static BOARD_EARLY_CACHE_INVALIDATE_MASKS: [u64; BOARD_NCPUS] = [0b111; BOARD_NCPUS]; +#[rustfmt::skip] +pub static BOARD_MPIDR_MAPPINGS: [u64; BOARD_NCPUS] = [ + 0x0, // cpu0 + 0x100, // cpu1 + 0x200, // cpu2 + 0x300, // cpu3 + 0x10200, // cpu4 + 0x10300, // cpu5 +]; + +/// The physical memory layout of the board. +/// Each address should align to 2M (0x200000). +/// Addresses must be in ascending order. +#[rustfmt::skip] +pub const BOARD_PHYSMEM_LIST: &[(u64, u64, MemoryType)] = &[ + // ( start, end, type) + ( 0x00000000, 0x080000000, MemoryType::Device), + ( 0x80000000, 0x280000000, MemoryType::Normal), + (0x2000000000, 0x2500000000, MemoryType::Device), + (0x3000000000, 0x4000000000, MemoryType::Device) +]; + +pub const ROOT_ZONE_DTB_ADDR: u64 = 0xA0000000; +pub const ROOT_ZONE_KERNEL_ADDR: u64 = 0xA0400000; +pub const ROOT_ZONE_ENTRY: u64 = 0xA0400000; +pub const ROOT_ZONE_CPUS: u64 = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3); + +pub const ROOT_ZONE_NAME: &str = "root-linux"; + +pub const ROOT_ZONE_MEMORY_REGIONS: &[HvConfigMemoryRegion] = &[ + HvConfigMemoryRegion { + mem_type: MEM_TYPE_RAM, + physical_start: 0x90000000, + virtual_start: 0x90000000, + size: 0x2E000000, // 1G + }, // ram + HvConfigMemoryRegion { + mem_type: MEM_TYPE_RAM, + physical_start: 0xC2000000, + virtual_start: 0xC2000000, + size: 0x3E000000, // 1G + }, // ram + HvConfigMemoryRegion { + mem_type: MEM_TYPE_RAM, + physical_start: 0x100000000, + virtual_start: 0x100000000, + size: 0x100000000, // 1G + }, // ram + HvConfigMemoryRegion { + mem_type: MEM_TYPE_RAM, + physical_start: 0x260000000, + virtual_start: 0x260000000, + size: 0x10000000, + }, // ram - UEFI + HvConfigMemoryRegion { + mem_type: MEM_TYPE_IO, + physical_start: 0x00000000, + virtual_start: 0x00000000, + size: 0x0f400000, + }, // general + HvConfigMemoryRegion { + mem_type: MEM_TYPE_IO, + physical_start: 0x10000000, + virtual_start: 0x10000000, + size: 0x70000000, + }, // general + HvConfigMemoryRegion { + mem_type: MEM_TYPE_IO, + physical_start: 0x2000000000, + virtual_start: 0x2000000000, + size: 0x500000000, + }, // pcie + HvConfigMemoryRegion { + mem_type: MEM_TYPE_IO, + physical_start: 0x3000000000, + virtual_start: 0x3000000000, + size: 0x1000000000, + }, // pcie +]; + +pub const IRQ_WAKEUP_VIRTIO_DEVICE: usize = 32 + 0x20; + +// serial-c - phy - pcie - phy - hsp - timer - hsp - phy - phy - memory-controller - external-memory-controller +// pcie - phy - phy +// bpmp-fabric +// gpu +// host1x +pub const ROOT_ZONE_IRQS_BITMAP: &[BitmapWord] = &get_irqs_bitmap(&[ + 146, 372, 83, 84, 373, 165, 166, 167, 168, 208, 152, 153, 154, 155, 156, 157, 158, 159, 374, + 375, 255, 256, 64, 388, 389, 253, 254, 206, 99, 100, 102, 103, 480, 481, 482, 483, 484, 485, + 486, 487, +]); + +pub const ROOT_ARCH_ZONE_CONFIG: HvArchZoneConfig = HvArchZoneConfig { + is_aarch32: 0, + gic_config: GicConfig::Gicv3(Gicv3Config { + gicd_base: 0xf400000, + gicd_size: 0x10000, + gicr_base: 0xf440000, + gicr_size: 0x200000, + gits_base: 0x0, + gits_size: 0x0, + }), + uefi_config: UefiConfig::Uefi(Uefi { + memory_map_addr: 0xB0000000, + memory_map_size: 0x990, + sys_map_addr: 0xB1000000, + }), +}; + +pub const ROOT_ZONE_IVC_CONFIG: [HvIvcConfig; 0] = []; diff --git a/platform/aarch64/jeston-orin/cargo/config.template.toml b/platform/aarch64/jeston-orin/cargo/config.template.toml new file mode 100644 index 000000000..85e2f56c7 --- /dev/null +++ b/platform/aarch64/jeston-orin/cargo/config.template.toml @@ -0,0 +1,7 @@ +[target.aarch64-unknown-none] +runner = "platform/__ARCH__/__BOARD__/test/runner.sh" +rustflags = [ + "-Clink-arg=-Tplatform/__ARCH__/__BOARD__/linker.ld", + "-Ctarget-feature=+a72,+v8a,+strict-align,-neon,-fp-armv8", + "-Cforce-frame-pointers=yes", +] \ No newline at end of file diff --git a/platform/aarch64/jeston-orin/image/dts/Makefile b/platform/aarch64/jeston-orin/image/dts/Makefile new file mode 100644 index 000000000..2f795e7fe --- /dev/null +++ b/platform/aarch64/jeston-orin/image/dts/Makefile @@ -0,0 +1,8 @@ +DTS_FILES := $(wildcard *.dts) +DTB_FILES := $(DTS_FILES:.dts=.dtb) + +all: $(DTB_FILES) +%.dtb: %.dts + dtc -I dts -O dtb $< -o $@ +clean: + rm -f $(DTB_FILES) \ No newline at end of file diff --git a/platform/aarch64/jeston-orin/image/dts/zone0.dts b/platform/aarch64/jeston-orin/image/dts/zone0.dts new file mode 100644 index 000000000..c730eceae --- /dev/null +++ b/platform/aarch64/jeston-orin/image/dts/zone0.dts @@ -0,0 +1,547 @@ +/dts-v1/; + +/ { + #address-cells = <0x02>; + model = "NVIDIA Jetson Orin Nano Engineering Reference Developer Kit Super"; + serial-number = "1421425085427\0"; + #size-cells = <0x02>; + interrupt-parent = <0x01>; + compatible = "nvidia,p3768-0000+p3767-0005-super\0nvidia,p3767-0005\0nvidia,tegra234"; + + pwm-fan { + cooling-levels = <0x00 0x58 0xbb 0xff>; + compatible = "pwm-fan"; + phandle = <0x1f0>; + pwms = <0x1f5 0x00 0xb116>; + #cooling-cells = <0x02>; + }; + + bus@0 { + #address-cells = <0x02>; + #size-cells = <0x02>; + compatible = "simple-bus"; + ranges = <0x00 0x00 0x00 0x00 0x100 0x00>; + + pwm@32a0000 { + assigned-clocks = <0x03 0x6b>; + assigned-clock-parents = <0x03 0x66>; + resets = <0x03 0x46>; + clocks = <0x03 0x6b>; + #pwm-cells = <0x02>; + compatible = "nvidia,tegra234-pwm\0nvidia,tegra194-pwm"; + status = "okay"; + reg = <0x00 0x32a0000 0x00 0x10000>; + phandle = <0x1f5>; + reset-names = "pwm"; + }; + + phy@3e40000 { + nvidia,bpmp = <0x03 0x04>; + reg-names = "ctl"; + interrupts = <0x00 0x154 0x04>; + #phy-cells = <0x00>; + compatible = "nvidia,tegra234-p2u"; + interrupt-names = "intr"; + reg = <0x00 0x3e40000 0x00 0x10000>; + phandle = <0x112>; + }; + + pcie@14160000 { + power-domains = <0x03 0x08>; + #address-cells = <0x03>; + dma-coherent; + interconnect-names = "dma-mem\0write"; + phy-names = "p2u-0\0p2u-1\0p2u-2\0p2u-3"; + nvidia,bpmp = <0x03 0x04>; + bus-range = <0x00 0xff>; + clock-names = "core"; + interconnects = <0x57 0xe0 0x58 0x57 0xe1 0x58>; + reg-names = "appl\0config\0atu_dma\0dbi\0ecam"; + nvidia,aspm-l0s-entrance-latency-us = <0x03>; + resets = <0x03 0x7d 0x03 0x78>; + interrupts = <0x00 0x33 0x04 0x00 0x34 0x04>; + clocks = <0x03 0xe0>; + interrupt-map = <0x00 0x00 0x00 0x00 0x01 0x00 0x33 0x04>; + #size-cells = <0x02>; + max-link-speed = <0x03>; + device_type = "pci"; + interrupt-map-mask = <0x00 0x00 0x00 0x00>; + num-lanes = <0x04>; + compatible = "nvidia,tegra234-pcie"; + vddio-pex-ctl-supply = <0xf5>; + ranges = <0x43000000 0x21 0x40000000 0x21 0x40000000 0x02 0xe8000000 0x2000000 0x00 0x40000000 0x24 0x28000000 0x00 0x8000000 0x1000000 0x00 0x36100000 0x00 0x36100000 0x00 0x100000>; + #interrupt-cells = <0x01>; + status = "okay"; + interrupt-names = "intr\0msi"; + phys = <0x112 0x113 0x114 0x115>; + num-viewport = <0x08>; + reg = <0x00 0x14160000 0x00 0x20000 0x00 0x36000000 0x00 0x40000 0x00 0x36040000 0x00 0x40000 0x00 0x36080000 0x00 0x40000 0x24 0x30000000 0x00 0x10000000>; + linux,pci-domain = <0x04>; + reset-names = "apb\0core"; + nvidia,aspm-pwr-on-t-us = <0x14>; + nvidia,aspm-cmrt-us = <0x3c>; + }; + + phy@3e50000 { + nvidia,bpmp = <0x03 0x05>; + reg-names = "ctl"; + interrupts = <0x00 0x155 0x04>; + #phy-cells = <0x00>; + compatible = "nvidia,tegra234-p2u"; + interrupt-names = "intr"; + reg = <0x00 0x3e50000 0x00 0x10000>; + phandle = <0x113>; + }; + + hsp@c150000 { + interrupts = <0x00 0x85 0x04 0x00 0x86 0x04 0x00 0x87 0x04 0x00 0x88 0x04>; + #mbox-cells = <0x02>; + compatible = "nvidia,tegra234-hsp\0nvidia,tegra194-hsp"; + interrupt-names = "shared1\0shared2\0shared3\0shared4"; + reg = <0x00 0xc150000 0x00 0x90000>; + phandle = <0x143>; + }; + + hsp@3c00000 { + interrupts = <0x00 0xb0 0x04 0x00 0x78 0x04 0x00 0x79 0x04 0x00 0x7a 0x04 0x00 0x7b 0x04 0x00 0x7c 0x04 0x00 0x7d 0x04 0x00 0x7e 0x04 0x00 0x7f 0x04>; + #mbox-cells = <0x02>; + compatible = "nvidia,tegra234-hsp\0nvidia,tegra194-hsp"; + interrupt-names = "doorbell\0shared0\0shared1\0shared2\0shared3\0shared4\0shared5\0shared6\0shared7"; + reg = <0x00 0x3c00000 0x00 0xa0000>; + phandle = <0x121>; + }; + + phy@3e60000 { + nvidia,bpmp = <0x03 0x06>; + reg-names = "ctl"; + interrupts = <0x00 0x156 0x04>; + #phy-cells = <0x00>; + compatible = "nvidia,tegra234-p2u"; + interrupt-names = "intr"; + reg = <0x00 0x3e60000 0x00 0x10000>; + phandle = <0x114>; + }; + + interrupt-controller@f400000 { + #redistributor-regions = <0x01>; + interrupts = <0x01 0x09 0xf04>; + interrupt-parent = <0x01>; + compatible = "arm,gic-v3"; + #interrupt-cells = <0x03>; + reg = <0x00 0xf400000 0x00 0x10000 0x00 0xf440000 0x00 0x200000>; + phandle = <0x01>; + interrupt-controller; + }; + + + phy@3e70000 { + nvidia,bpmp = <0x03 0x07>; + reg-names = "ctl"; + interrupts = <0x00 0x157 0x04>; + #phy-cells = <0x00>; + compatible = "nvidia,tegra234-p2u"; + interrupt-names = "intr"; + reg = <0x00 0x3e70000 0x00 0x10000>; + phandle = <0x115>; + }; + + + memory-controller@2c00000 { + dma-ranges = <0x00 0x00 0x00 0x00 0x80 0x00>; + #address-cells = <0x02>; + reg-names = "sid\0broadcast\0ch0\0ch1\0ch2\0ch3\0ch4\0ch5\0ch6\0ch7\0ch8\0ch9\0ch10\0ch11\0ch12\0ch13\0ch14\0ch15"; + interrupts = <0x00 0xdf 0x04>; + #interconnect-cells = <0x01>; + #size-cells = <0x02>; + compatible = "nvidia,tegra234-mc"; + ranges = <0x00 0x1700000 0x00 0x1700000 0x00 0x100000 0x00 0x2b80000 0x00 0x2b80000 0x00 0x40000 0x00 0x2c00000 0x00 0x2c00000 0x00 0x100000>; + status = "okay"; + reg = <0x00 0x2c00000 0x00 0x10000 0x00 0x2c10000 0x00 0x10000 0x00 0x2c20000 0x00 0x10000 0x00 0x2c30000 0x00 0x10000 0x00 0x2c40000 0x00 0x10000 0x00 0x2c50000 0x00 0x10000 0x00 0x2b80000 0x00 0x10000 0x00 0x2b90000 0x00 0x10000 0x00 0x2ba0000 0x00 0x10000 0x00 0x2bb0000 0x00 0x10000 0x00 0x1700000 0x00 0x10000 0x00 0x1710000 0x00 0x10000 0x00 0x1720000 0x00 0x10000 0x00 0x1730000 0x00 0x10000 0x00 0x1740000 0x00 0x10000 0x00 0x1750000 0x00 0x10000 0x00 0x1760000 0x00 0x10000 0x00 0x1770000 0x00 0x10000>; + phandle = <0x57>; + + external-memory-controller@2c60000 { + nvidia,bpmp = <0x03>; + clock-names = "emc"; + interrupts = <0x00 0xe0 0x04>; + clocks = <0x03 0x1f>; + #interconnect-cells = <0x00>; + compatible = "nvidia,tegra234-emc"; + status = "okay"; + reg = <0x00 0x2c60000 0x00 0x90000 0x00 0x1780000 0x00 0x80000>; + phandle = <0x58>; + }; + }; + }; + + psci { + method = "smc"; + compatible = "arm,psci-1.0"; + status = "okay"; + }; + + + sram@40000000 { + #address-cells = <0x01>; + #size-cells = <0x01>; + compatible = "nvidia,tegra234-sysram\0mmio-sram"; + ranges = <0x00 0x00 0x40000000 0x80000>; + reg = <0x00 0x40000000 0x00 0x80000>; + no-memory-wc; + + sram@71000 { + label = "cpu-bpmp-rx"; + reg = <0x71000 0x1000>; + phandle = <0x123>; + pool; + }; + + sram@70000 { + label = "cpu-bpmp-tx"; + reg = <0x70000 0x1000>; + phandle = <0x122>; + pool; + }; + }; + + timer { + always-on; + interrupts = <0x01 0x0d 0xf08 0x01 0x0e 0xf08 0x01 0x0b 0xf08 0x01 0x0a 0xf08>; + interrupt-parent = <0x01>; + compatible = "arm,armv8-timer"; + }; + + bpmp { + shmem = <0x122 0x123>; + #reset-cells = <0x01>; + interconnect-names = "read\0write\0dma-mem\0dma-write"; + interconnects = <0x57 0x93 0x58 0x57 0x94 0x58 0x57 0x95 0x58 0x57 0x96 0x58>; + #clock-cells = <0x01>; + #power-domain-cells = <0x01>; + compatible = "nvidia,tegra234-bpmp\0nvidia,tegra186-bpmp"; + phandle = <0x03>; + mboxes = <0x121 0x00 0x13>; + }; + + regulator-vdd-1v8-ao { + regulator-max-microvolt = <0x1b7740>; + regulator-always-on; + regulator-min-microvolt = <0x1b7740>; + regulator-name = "VDD_1V8_AO"; + compatible = "regulator-fixed"; + phandle = <0xf5>; + vin-supply = <0xf7>; + }; + + aliases { + serial0 = "/serial"; + }; + + firmware { + + optee { + method = "smc"; + compatible = "linaro,optee-tz"; + status = "okay"; + }; + + uefi { + firmware-media-overlays-applied; + }; + + ftpm { + compatible = "microsoft,ftpm"; + status = "okay"; + }; + }; + + chosen { + linux,uefi-mmap-size = <0x990>; + linux,uefi-mmap-start = <0x00 0xB0000000>; + linux,uefi-mmap-desc-size = <0x30>; + linux,uefi-mmap-desc-ver = <0x01>; + linux,uefi-secure-boot = <0x02>; + // linux,uefi-system-table = <0x02 0x6d820018>; + linux,uefi-system-table = <0x00 0xB1000000>; + linux,initrd-start = <0x00 0xA5000000>; + linux,initrd-end = <0x00 0xB0000000>; + // bootargs = "BOOT_IMAGE=/boot/Image root=PARTUUID=df60643d-4ac4-42f9-9e93-96b84bb83837 rw rootwait rootfstype=ext4 loglevel=8 mminit_loglevel=4 earlycon=uart8250,mmio32,0xc280000 psci.debug=1 nokaslr systemd.log_level=info systemd.log_target=console console=ttyTCU0,115200"; + bootargs = "BOOT_IMAGE=/boot/Image root=/dev/nvme0n1p1 rw rootwait rootfstype=ext4 loglevel=7 panic_on_rcu_stall=1 systemd.show_status=false mminit_loglevel=4 console=ttyTCU0,115200"; + kaslr-seed = <0x00 0x00>; + ids = [33 37 36 37 2d 30 30 30 35 2d 33 30 30 00 20 33 37 36 38 2d 30 30 30 30 2d 34 30 30 00 20 0a 33 37 36 37 2d 30 30 30 35 2d 33 30 30 00 20 33 37 36 38 2d 30 30 30 30 2d 34 30 30 00 20 0a]; + nvidia,tegra-joint_xpu_rail; + nvidia,sku = "699-13767-0005-300 R.1\0\0\0\0\0\0\0\0"; + stdout-path = "serial0:115200n8"; + + odm-data { + gbe-uphy-config-8; + hsstp-lane-map-3; + hsio-uphy-config-0; + }; + }; + + regulator-vdd-5v0-sys { + regulator-max-microvolt = <0x4c4b40>; + regulator-always-on; + regulator-min-microvolt = <0x4c4b40>; + regulator-name = "VDD_5V0_SYS"; + compatible = "regulator-fixed"; + phandle = <0xf7>; + }; + + serial { + compatible = "nvidia,tegra234-tcu\0nvidia,tegra194-tcu"; + status = "okay"; + phandle = <0x254>; + mboxes = <0x121 0x01 0x00 0x143 0x01 0x80000001>; + mbox-names = "rx\0tx"; + }; + + pmu { + interrupts = <0x01 0x07 0x04>; + compatible = "arm,cortex-a78-pmu"; + status = "okay"; + }; + + cpus { + #address-cells = <0x01>; + #size-cells = <0x00>; + + l3-cache0 { + cache-size = <0x200000>; + cache-level = <0x03>; + cache-sets = <0x800>; + cache-unified; + compatible = "cache"; + cache-line-size = <0x40>; + phandle = <0x140>; + }; + + l2-cache13 { + cache-size = <0x40000>; + cache-level = <0x02>; + cache-sets = <0x200>; + cache-unified; + compatible = "cache"; + cache-line-size = <0x40>; + next-level-cache = <0x141>; + phandle = <0x12e>; + }; + + cpu@300 { + d-cache-line-size = <0x40>; + interconnects = <0x57 0x3eb 0x58>; + i-cache-line-size = <0x40>; + cpu-idle-states = <0x126>; + device_type = "cpu"; + compatible = "arm,cortex-a78"; + d-cache-size = <0x10000>; + next-level-cache = <0x129>; + i-cache-size = <0x10000>; + reg = <0x300>; + enable-method = "psci"; + phandle = <0x137>; + d-cache-sets = <0x100>; + i-cache-sets = <0x100>; + }; + + l2-cache03 { + cache-size = <0x40000>; + cache-level = <0x02>; + cache-sets = <0x200>; + cache-unified; + compatible = "cache"; + cache-line-size = <0x40>; + next-level-cache = <0x140>; + phandle = <0x129>; + }; + + l2-cache01 { + cache-size = <0x40000>; + cache-level = <0x02>; + cache-sets = <0x200>; + cache-unified; + compatible = "cache"; + cache-line-size = <0x40>; + next-level-cache = <0x140>; + phandle = <0x127>; + }; + + idle-states { + entry-method = "psci"; + + c7 { + idle-state-name = "Core powergate"; + wakeup-latency-us = <0x1388>; + arm,psci-suspend-param = <0x40000007>; + compatible = "arm,idle-state"; + status = "okay"; + phandle = <0x126>; + min-residency-us = <0x7530>; + }; + }; + + cpu-map { + + cluster0 { + + core3 { + cpu = <0x137>; + }; + + core1 { + cpu = <0x135>; + }; + + core2 { + cpu = <0x136>; + }; + + core0 { + cpu = <0x134>; + }; + }; + + cluster1 { + + core1 { + cpu = <0x13b>; + }; + + core0 { + cpu = <0x13a>; + }; + }; + }; + + cpu@200 { + d-cache-line-size = <0x40>; + interconnects = <0x57 0x3eb 0x58>; + i-cache-line-size = <0x40>; + cpu-idle-states = <0x126>; + device_type = "cpu"; + compatible = "arm,cortex-a78"; + d-cache-size = <0x10000>; + next-level-cache = <0x128>; + i-cache-size = <0x10000>; + reg = <0x200>; + enable-method = "psci"; + phandle = <0x136>; + d-cache-sets = <0x100>; + i-cache-sets = <0x100>; + #cooling-cells = <0x02>; + }; + + l3-cache1 { + cache-size = <0x200000>; + cache-level = <0x03>; + cache-sets = <0x800>; + cache-unified; + compatible = "cache"; + cache-line-size = <0x40>; + phandle = <0x141>; + }; + + cpu@0 { + d-cache-line-size = <0x40>; + interconnects = <0x57 0x3eb 0x58>; + i-cache-line-size = <0x40>; + cpu-idle-states = <0x126>; + device_type = "cpu"; + compatible = "arm,cortex-a78"; + d-cache-size = <0x10000>; + next-level-cache = <0x125>; + i-cache-size = <0x10000>; + reg = <0x00>; + enable-method = "psci"; + phandle = <0x134>; + d-cache-sets = <0x100>; + i-cache-sets = <0x100>; + #cooling-cells = <0x02>; + }; + + cpu@10300 { + d-cache-line-size = <0x40>; + interconnects = <0x57 0x3ec 0x58>; + i-cache-line-size = <0x40>; + cpu-idle-states = <0x126>; + device_type = "cpu"; + compatible = "arm,cortex-a78"; + d-cache-size = <0x10000>; + next-level-cache = <0x12e>; + i-cache-size = <0x10000>; + reg = <0x10300>; + enable-method = "psci"; + phandle = <0x13b>; + d-cache-sets = <0x100>; + i-cache-sets = <0x100>; + }; + + l2-cache12 { + cache-size = <0x40000>; + cache-level = <0x02>; + cache-sets = <0x200>; + cache-unified; + compatible = "cache"; + cache-line-size = <0x40>; + next-level-cache = <0x141>; + phandle = <0x12d>; + }; + + l2-cache02 { + cache-size = <0x40000>; + cache-level = <0x02>; + cache-sets = <0x200>; + cache-unified; + compatible = "cache"; + cache-line-size = <0x40>; + next-level-cache = <0x140>; + phandle = <0x128>; + }; + + cpu@100 { + d-cache-line-size = <0x40>; + interconnects = <0x57 0x3eb 0x58>; + i-cache-line-size = <0x40>; + cpu-idle-states = <0x126>; + device_type = "cpu"; + compatible = "arm,cortex-a78"; + d-cache-size = <0x10000>; + next-level-cache = <0x127>; + i-cache-size = <0x10000>; + reg = <0x100>; + enable-method = "psci"; + phandle = <0x135>; + d-cache-sets = <0x100>; + i-cache-sets = <0x100>; + }; + + l2-cache00 { + cache-size = <0x40000>; + cache-level = <0x02>; + cache-sets = <0x200>; + cache-unified; + compatible = "cache"; + cache-line-size = <0x40>; + next-level-cache = <0x140>; + phandle = <0x125>; + }; + + cpu@10200 { + d-cache-line-size = <0x40>; + interconnects = <0x57 0x3ec 0x58>; + i-cache-line-size = <0x40>; + cpu-idle-states = <0x126>; + device_type = "cpu"; + compatible = "arm,cortex-a78"; + d-cache-size = <0x10000>; + next-level-cache = <0x12d>; + i-cache-size = <0x10000>; + reg = <0x10200>; + enable-method = "psci"; + phandle = <0x13a>; + d-cache-sets = <0x100>; + i-cache-sets = <0x100>; + #cooling-cells = <0x02>; + }; + }; +}; diff --git a/platform/aarch64/jeston-orin/kconfig/defconfig b/platform/aarch64/jeston-orin/kconfig/defconfig new file mode 100644 index 000000000..0c271ad7e --- /dev/null +++ b/platform/aarch64/jeston-orin/kconfig/defconfig @@ -0,0 +1,5 @@ +CONFIG_AARCH64_UEFI_SUPPORT=y +CONFIG_ARCH_AARCH64=y +CONFIG_IRQ_GICV3=y +CONFIG_SEQUENTIAL_OUTPUT=y +CONFIG_UART_16550=y diff --git a/platform/aarch64/jeston-orin/linker.ld b/platform/aarch64/jeston-orin/linker.ld new file mode 100644 index 000000000..5f97efffe --- /dev/null +++ b/platform/aarch64/jeston-orin/linker.ld @@ -0,0 +1,63 @@ +ENTRY(arch_entry) +BASE_ADDRESS = 0x81000000; +CPU_NUM = 6; + +SECTIONS +{ + . = BASE_ADDRESS; + skernel = .; + + stext = .; + .text : { + *(.text.entry) + *(.text .text.*) + } + + . = ALIGN(4K); + etext = .; + srodata = .; + .rodata : { + *(.rodata .rodata.*) + *(.srodata .srodata.*) + } + + . = ALIGN(4K); + erodata = .; + sdata = .; + .data : { + *(.data .data.*) + *(.sdata .sdata.*) + } + + . = ALIGN(4K); + edata = .; + .bss : { + *(.bss.stack) + sbss = .; + *(.bss .bss.*) + *(.sbss .sbss.*) + } + + . = ALIGN(4K); + _percpu_start = .; + _percpu_end = _percpu_start + SIZEOF(.percpu); + .percpu 0x0 (NOLOAD) : AT(_percpu_start) { + _percpu_load_start = .; + *(.percpu .percpu.*) + _percpu_load_end = .; + . = _percpu_load_start + ALIGN(64) * CPU_NUM; + } + . = _percpu_end; + + . = ALIGN(4K); + ebss = .; + ekernel = .; + + /DISCARD/ : { + *(.eh_frame) + } + . = ALIGN(4K); + __core_end = .; +} + +__hv_end = __core_end + HV_EXTENDED_SIZE; \ No newline at end of file diff --git a/platform/aarch64/jeston-orin/platform.mk b/platform/aarch64/jeston-orin/platform.mk new file mode 100644 index 000000000..7c36c413a --- /dev/null +++ b/platform/aarch64/jeston-orin/platform.mk @@ -0,0 +1,45 @@ +QEMU := qemu-system-aarch64 + +UBOOT := $(image_dir)/bootloader/u-boot-v2.bin +zone0_dtb := $(image_dir)/dts/zone0.dtb +QEMU_ARGS := -machine virt,secure=on,gic-version=2,virtualization=on,iommu=smmuv3 +MESSAGE := "Note: Feature contains gicv2" + +FSIMG1 := $(image_dir)/virtdisk/rootfs1.ext4 +FSIMG2 := $(image_dir)/virtdisk/rootfs2.ext4 + +zone0_kernel := $(image_dir)/kernel/Image + +QEMU_ARGS += -global arm-smmuv3.stage=2 + +QEMU_ARGS += -cpu cortex-a72 +QEMU_ARGS += -smp 4 +QEMU_ARGS += -m 2G +QEMU_ARGS += -nographic +QEMU_ARGS += -bios $(UBOOT) + +QEMU_ARGS += -device loader,file="$(hvisor_bin)",addr=0x40400000,force-raw=on +QEMU_ARGS += -device loader,file="$(zone0_kernel)",addr=0xa0400000,force-raw=on +QEMU_ARGS += -device loader,file="$(zone0_dtb)",addr=0xa0000000,force-raw=on + +QEMU_ARGS += -drive if=none,file=$(FSIMG1),id=Xa003e000,format=raw +QEMU_ARGS += -device virtio-blk-device,drive=Xa003e000,bus=virtio-mmio-bus.31 + +$(hvisor_bin): elf + @if ! command -v mkimage > /dev/null; then \ + sudo apt update && sudo apt install u-boot-tools; \ + fi && \ + $(OBJCOPY) $(hvisor_elf) --strip-all -O binary $(hvisor_bin).tmp && \ + mkimage -n hvisor_img -A arm64 -O linux -C none -T kernel -a 0x81000000 \ + -e 0x81000000 -d $(hvisor_bin).tmp $(hvisor_bin) + +QEMU_ARGS += -netdev type=user,id=net1 +QEMU_ARGS += -device virtio-net-pci,netdev=net1,disable-legacy=on,disable-modern=off,iommu_platform=on + +# QEMU_ARGS += -device pci-testdev + +QEMU_ARGS += -netdev type=user,id=net2 +QEMU_ARGS += -device virtio-net-pci,netdev=net2,disable-legacy=on,disable-modern=off,iommu_platform=on + +QEMU_ARGS += -netdev type=user,id=net3 +QEMU_ARGS += -device virtio-net-pci,netdev=net3,disable-legacy=on,disable-modern=off,iommu_platform=on \ No newline at end of file diff --git a/platform/aarch64/jeston-orin/test/runner.sh b/platform/aarch64/jeston-orin/test/runner.sh new file mode 100755 index 000000000..5cf40efe7 --- /dev/null +++ b/platform/aarch64/jeston-orin/test/runner.sh @@ -0,0 +1,76 @@ +#!/bin/bash + +set -e + +PWD=$(pwd) +THIS=$(basename $0) +CARGO_BUILD_INPUT_ARG0=$1 + +ARCH=${ARCH} +BOARD=${BOARD} + +UBOOT_GICV3=u-boot-atf.bin + +HVISOR_ELF=$CARGO_BUILD_INPUT_ARG0 +HVISOR_BIN_TMP=$HVISOR_ELF.bin.tmp +HVISOR_BIN=$HVISOR_ELF.bin + +OBJCOPY=rust-objcopy + +YELLOW='\033[1;33m' +END='\033[0m' + +info() { + # echo "${YELLOW}[INFO | $THIS] $1${END}" + echo "[INFO | $THIS] $1" +} + +# check if mkimage is installed +if ! command -v mkimage &>/dev/null; then + if command -v apt &>/dev/null; then + sudo apt update && sudo apt install -y u-boot-tools + elif command -v brew &>/dev/null; then + brew install u-boot-tools + else + info "You need to install u-boot-tools to run this script (mkimage)" + exit 1 + fi +fi + +info "Running cargo test with env: ARCH=$ARCH, BOARD=$BOARD" + +info "Building hvisor with $CARGO_BUILD_INPUT_ARG0" +info "PWD=$PWD, running cargo test" +$OBJCOPY $HVISOR_ELF --strip-all -O binary $HVISOR_BIN_TMP + +if [ "$ARCH" == "aarch64" ]; then + mkimage -n hvisor_img -A arm64 -O linux -C none -T kernel -a 0x40400000 \ + -e 0x40400000 -d $HVISOR_BIN_TMP $HVISOR_BIN + + info "Running QEMU with $HVISOR_BIN" + + AARCH64_GIC_TEST_VERSION=3 + info "Using GIC version: $AARCH64_GIC_TEST_VERSION" + + UBOOT=$UBOOT_GICV3 + UBOOT=$PWD/platform/$ARCH/$BOARD/image/bootloader/$UBOOT + info "Using U-Boot: $UBOOT" + + + qemu-system-aarch64 \ + -machine virt,secure=on,gic-version=${AARCH64_GIC_TEST_VERSION},virtualization=on,iommu=smmuv3 \ + -cpu cortex-a57 -smp 4 -m 3G -nographic \ + -semihosting \ + -bios $UBOOT \ + -drive if=pflash,format=raw,index=1,file=flash.img \ + -device loader,file=$HVISOR_BIN,addr=0x40400000,force-raw=on \ + -global arm-smmuv3.stage=2 + + exit 0 +elif [ "$ARCH" == "riscv64" ]; then + info "riscv64 auto test is not supported yet" + exit 1 +else + info "Unsupported ARCH: $ARCH" + exit 1 +fi diff --git a/platform/aarch64/ok6254-c/board.rs b/platform/aarch64/ok6254-c/board.rs index 959098852..60149895b 100644 --- a/platform/aarch64/ok6254-c/board.rs +++ b/platform/aarch64/ok6254-c/board.rs @@ -17,7 +17,7 @@ use crate::{ arch::{ mmu::MemoryType, - zone::{GicConfig, Gicv3Config, HvArchZoneConfig}, + zone::{GicConfig, Gicv3Config, HvArchZoneConfig, UefiConfig}, }, config::*, }; @@ -34,6 +34,9 @@ pub static BOARD_MPIDR_MAPPINGS: [u64; BOARD_NCPUS] = [ 0x3, // cpu3 ]; +/// Early boot cache invalidate mask (per CPU): bit0->L1(D), bit1->L2, bit2->L3. +pub static BOARD_EARLY_CACHE_INVALIDATE_MASKS: [u64; BOARD_NCPUS] = [0b011; BOARD_NCPUS]; + /// The physical memory layout of the board. /// Each address should align to 2M (0x200000). /// Addresses must be in ascending order. @@ -141,6 +144,7 @@ pub const ROOT_ARCH_ZONE_CONFIG: HvArchZoneConfig = HvArchZoneConfig { gits_base: 0, gits_size: 0, }), + uefi_config: UefiConfig::NoUefi }; pub const ROOT_ZONE_IVC_CONFIG: [HvIvcConfig; 0] = []; diff --git a/platform/aarch64/ok6254-c/cargo/features b/platform/aarch64/ok6254-c/cargo/features deleted file mode 100644 index afa594897..000000000 --- a/platform/aarch64/ok6254-c/cargo/features +++ /dev/null @@ -1,2 +0,0 @@ -gicv3 -uart_16550 diff --git a/platform/aarch64/ok6254-c/configs/zone1-linux.json b/platform/aarch64/ok6254-c/configs/zone1-linux.json index 11f5038c7..46acb982c 100644 --- a/platform/aarch64/ok6254-c/configs/zone1-linux.json +++ b/platform/aarch64/ok6254-c/configs/zone1-linux.json @@ -82,5 +82,6 @@ "gicr_size": "0xc0000", "gits_base": "0x1820000", "gits_size": "0x10000" - } -} \ No newline at end of file + }, + "pci_config": [] +} diff --git a/platform/aarch64/ok6254-c/kconfig/defconfig b/platform/aarch64/ok6254-c/kconfig/defconfig new file mode 100644 index 000000000..242faa328 --- /dev/null +++ b/platform/aarch64/ok6254-c/kconfig/defconfig @@ -0,0 +1,3 @@ +CONFIG_ARCH_AARCH64=y +CONFIG_IRQ_GICV3=y +CONFIG_UART_16550=y diff --git a/platform/aarch64/phytium-pi/board.rs b/platform/aarch64/phytium-pi/board.rs index 127b8ff61..595eec266 100644 --- a/platform/aarch64/phytium-pi/board.rs +++ b/platform/aarch64/phytium-pi/board.rs @@ -16,7 +16,7 @@ use crate::{ arch::{ mmu::MemoryType, - zone::{GicConfig, Gicv3Config, HvArchZoneConfig}, + zone::{GicConfig, Gicv3Config, HvArchZoneConfig, UefiConfig}, }, config::*, }; @@ -34,6 +34,9 @@ pub static BOARD_MPIDR_MAPPINGS: [u64; BOARD_NCPUS] = [ 0x100, // cpu3 ]; +/// Early boot cache invalidate mask (per CPU): bit0->L1(D), bit1->L2, bit2->L3. +pub static BOARD_EARLY_CACHE_INVALIDATE_MASKS: [u64; BOARD_NCPUS] = [0b011; BOARD_NCPUS]; + /// The physical memory layout of the board. /// Each address should align to 2M (0x200000). /// Addresses must be in ascending order. @@ -146,6 +149,7 @@ pub const ROOT_ARCH_ZONE_CONFIG: HvArchZoneConfig = HvArchZoneConfig { gits_base: 0, gits_size: 0, }), + uefi_config: UefiConfig::NoUefi }; pub const ROOT_ZONE_IVC_CONFIG: [HvIvcConfig; 0] = []; diff --git a/platform/aarch64/phytium-pi/cargo/features b/platform/aarch64/phytium-pi/cargo/features deleted file mode 100644 index 416c6913e..000000000 --- a/platform/aarch64/phytium-pi/cargo/features +++ /dev/null @@ -1,2 +0,0 @@ -gicv3 -pl011 \ No newline at end of file diff --git a/platform/aarch64/phytium-pi/configs/zone1-linux.json b/platform/aarch64/phytium-pi/configs/zone1-linux.json index 5bf7d154b..96925802b 100644 --- a/platform/aarch64/phytium-pi/configs/zone1-linux.json +++ b/platform/aarch64/phytium-pi/configs/zone1-linux.json @@ -50,5 +50,6 @@ "gicr_size": "0x80000", "gits_base": "0x0", "gits_size": "0x0" - } + }, + "pci_config": [] } diff --git a/platform/aarch64/phytium-pi/kconfig/defconfig b/platform/aarch64/phytium-pi/kconfig/defconfig new file mode 100644 index 000000000..f24edf758 --- /dev/null +++ b/platform/aarch64/phytium-pi/kconfig/defconfig @@ -0,0 +1,3 @@ +CONFIG_ARCH_AARCH64=y +CONFIG_IRQ_GICV3=y +CONFIG_PL011=y diff --git a/platform/aarch64/phytium-pi/platform.mk b/platform/aarch64/phytium-pi/platform.mk index 061516bcc..46c773778 100644 --- a/platform/aarch64/phytium-pi/platform.mk +++ b/platform/aarch64/phytium-pi/platform.mk @@ -1,6 +1,6 @@ QEMU := qemu-system-aarch64 -ifeq ($(findstring gicv3, $(FEATURES)),gicv3) +ifneq ($(shell grep -Fx CONFIG_IRQ_GICV3=y platform/$(ARCH)/$(BOARD)/kconfig/defconfig 2>/dev/null),) UBOOT := $(image_dir)/bootloader/u-boot-atf.bin zone0_dtb := $(image_dir)/devicetree/linux1.dtb QEMU_ARGS := -machine virt,secure=on,gic-version=3,virtualization=on,iommu=smmuv3 diff --git a/platform/aarch64/phytium-pi/scripts/boot_zone1.sh b/platform/aarch64/phytium-pi/scripts/boot_zone1.sh new file mode 100755 index 000000000..442b107d2 --- /dev/null +++ b/platform/aarch64/phytium-pi/scripts/boot_zone1.sh @@ -0,0 +1,10 @@ +#!/bin/bash + +insmod hvisor.ko 2>/dev/null || true +mount -t proc proc /proc 2>/dev/null || true +mount -t sysfs sysfs /sys 2>/dev/null || true +rm -f nohup.out +mkdir -p /dev/pts +mount -t devpts devpts /dev/pts 2>/dev/null || true +./hvisor virtio start zone1-linux-virtio.json & +./hvisor zone start zone1-linux.json diff --git a/platform/aarch64/qemu-gicv2/board.rs b/platform/aarch64/qemu-gicv2/board.rs index 26c0f7152..562844500 100644 --- a/platform/aarch64/qemu-gicv2/board.rs +++ b/platform/aarch64/qemu-gicv2/board.rs @@ -16,7 +16,7 @@ use crate::{ arch::{ mmu::MemoryType, - zone::{GicConfig, Gicv2Config, HvArchZoneConfig}, + zone::{GicConfig, Gicv2Config, HvArchZoneConfig, UefiConfig}, }, config::*, pci::vpci_dev::VpciDevType, @@ -48,26 +48,52 @@ pub const BOARD_PHYSMEM_LIST: &[(u64, u64, MemoryType)] = &[ (0x4010000000, 0x4020000000, MemoryType::Device), ]; +/// Early boot cache invalidate mask (per CPU): bit0->L1(D), bit1->L2, bit2->L3. +pub static BOARD_EARLY_CACHE_INVALIDATE_MASKS: [u64; BOARD_NCPUS] = [0b011; BOARD_NCPUS]; pub const ROOT_ZONE_DTB_ADDR: u64 = 0xa0000000; pub const ROOT_ZONE_KERNEL_ADDR: u64 = 0xa0400000; pub const ROOT_ZONE_ENTRY: u64 = 0xa0400000; -pub const ROOT_ZONE_CPUS: u64 = (1 << 0) | (1 << 1); +pub const ROOT_ZONE_CPUS: u64 = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3); pub const ROOT_ZONE_NAME: &str = "root-linux"; -pub const ROOT_ZONE_MEMORY_REGIONS: [HvConfigMemoryRegion; 3] = [ +pub const ROOT_ZONE_MEMORY_REGIONS: [HvConfigMemoryRegion; 7] = [ HvConfigMemoryRegion { mem_type: MEM_TYPE_RAM, physical_start: 0x50000000, virtual_start: 0x50000000, size: 0x70000000, }, // ram + HvConfigMemoryRegion { + mem_type: MEM_TYPE_IO, + physical_start: 0x00000000, + virtual_start: 0x00000000, + size: 0x08000000, + }, // flash HvConfigMemoryRegion { mem_type: MEM_TYPE_IO, physical_start: 0x9000000, virtual_start: 0x9000000, size: 0x1000, }, // serial + HvConfigMemoryRegion { + mem_type: MEM_TYPE_IO, + physical_start: 0x9010000, + virtual_start: 0x9010000, + size: 0x1000, + }, // rtc + HvConfigMemoryRegion { + mem_type: MEM_TYPE_IO, + physical_start: 0x9020000, + virtual_start: 0x9020000, + size: 0x1000, + }, // fw-cfg + HvConfigMemoryRegion { + mem_type: MEM_TYPE_IO, + physical_start: 0xc000000, + virtual_start: 0xc000000, + size: 0x2000000, + }, // platform-bus HvConfigMemoryRegion { mem_type: MEM_TYPE_IO, physical_start: 0xa000000, @@ -77,9 +103,11 @@ pub const ROOT_ZONE_MEMORY_REGIONS: [HvConfigMemoryRegion; 3] = [ ]; pub const IRQ_WAKEUP_VIRTIO_DEVICE: usize = 32 + 0x20; + // 35 36 37 38 -> pcie intx# // 65 -> ivc -pub const ROOT_ZONE_IRQS_BITMAP: &[BitmapWord] = &get_irqs_bitmap(&[33, 64, 77, 79, 35, 36, 37, 38, 65]); +pub const ROOT_ZONE_IRQS_BITMAP: &[BitmapWord] = + &get_irqs_bitmap(&[33, 64, 77, 79, 35, 36, 37, 38, 65]); pub const ROOT_ARCH_ZONE_CONFIG: HvArchZoneConfig = HvArchZoneConfig { is_aarch32: 0, @@ -94,32 +122,30 @@ pub const ROOT_ARCH_ZONE_CONFIG: HvArchZoneConfig = HvArchZoneConfig { gicv_base: 0x8040000, gicv_size: 0x10000, }), + uefi_config: UefiConfig::NoUefi }; - -pub const ROOT_PCI_CONFIG: [HvPciConfig; 1] = [ - HvPciConfig { - ecam_base: 0x4010000000, - ecam_size: 0x10000000, - io_base: 0x3eff0000, - io_size: 0x10000, - pci_io_base: 0x0, - mem32_base: 0x10000000, - mem32_size: 0x2eff0000, - pci_mem32_base: 0x10000000, - mem64_base: 0x8000000000, - mem64_size: 0x8000000000, - pci_mem64_base: 0x8000000000, - bus_range_begin: 0x0, - bus_range_end: 0xff, - domain: 0x0, - } -]; +pub const ROOT_PCI_CONFIG: [HvPciConfig; 1] = [HvPciConfig { + ecam_base: 0x4010000000, + ecam_size: 0x10000000, + io_base: 0x3eff0000, + io_size: 0x10000, + pci_io_base: 0x0, + mem32_base: 0x10000000, + mem32_size: 0x2eff0000, + pci_mem32_base: 0x10000000, + mem64_base: 0x8000000000, + mem64_size: 0x8000000000, + pci_mem64_base: 0x8000000000, + bus_range_begin: 0x0, + bus_range_end: 0xff, + domain: 0x0, +}]; pub const ROOT_ZONE_IVC_CONFIG: [HvIvcConfig; 0] = []; pub const ROOT_PCI_DEVS: [HvPciDevConfig; 3] = [ - pci_dev!(0x0, 0x0, 0x0, 0x0, VpciDevType::Physical), - pci_dev!(0x0, 0x0, 0x1, 0x0, VpciDevType::Physical), - pci_dev!(0x0, 0x0, 0x2, 0x0, VpciDevType::Physical), + pci_dev!(0x0, 0x0, 0x0, 0x0 => 0x0, 0x0, 0x0, VpciDevType::Physical), + pci_dev!(0x0, 0x0, 0x1, 0x0 => 0x0, 0x1, 0x0, VpciDevType::Physical), + pci_dev!(0x0, 0x0, 0x2, 0x0 => 0x0, 0x2, 0x0, VpciDevType::Physical), ]; diff --git a/platform/aarch64/qemu-gicv2/cargo/features b/platform/aarch64/qemu-gicv2/cargo/features deleted file mode 100644 index e0ed82fd3..000000000 --- a/platform/aarch64/qemu-gicv2/cargo/features +++ /dev/null @@ -1,4 +0,0 @@ -gicv2 -pl011 -arm_smmu -pci diff --git a/platform/aarch64/qemu-gicv2/configs/zone1-linux.json b/platform/aarch64/qemu-gicv2/configs/zone1-linux.json index f2b3ca640..496842efa 100644 --- a/platform/aarch64/qemu-gicv2/configs/zone1-linux.json +++ b/platform/aarch64/qemu-gicv2/configs/zone1-linux.json @@ -48,5 +48,6 @@ "gich_size": "0x10000", "gicv_base": "0x8040000", "gicv_size": "0x10000" - } -} \ No newline at end of file + }, + "pci_config": [] +} diff --git a/platform/aarch64/qemu-gicv2/kconfig/defconfig b/platform/aarch64/qemu-gicv2/kconfig/defconfig new file mode 100644 index 000000000..fb8f4ff36 --- /dev/null +++ b/platform/aarch64/qemu-gicv2/kconfig/defconfig @@ -0,0 +1,7 @@ +CONFIG_ARCH_AARCH64=y +CONFIG_ARM_SMMU=y +CONFIG_IOMMU=y +CONFIG_IRQ_GICV2=y +CONFIG_PCI=y +CONFIG_PCIE_ECAM=y +CONFIG_PL011=y diff --git a/platform/aarch64/qemu-gicv2/test/runner.sh b/platform/aarch64/qemu-gicv2/test/runner.sh index 78d0a9644..9522e647f 100755 --- a/platform/aarch64/qemu-gicv2/test/runner.sh +++ b/platform/aarch64/qemu-gicv2/test/runner.sh @@ -6,13 +6,9 @@ PWD=$(pwd) THIS=$(basename $0) CARGO_BUILD_INPUT_ARG0=$1 -# capture env: FEATURES, ARCH - ARCH=${ARCH} -FEATURES=${FEATURES} BOARD=${BOARD} -UBOOT_GICV3=u-boot-atf.bin UBOOT_GICV2=u-boot-v2.bin HVISOR_ELF=$CARGO_BUILD_INPUT_ARG0 @@ -41,7 +37,7 @@ if ! command -v mkimage &>/dev/null; then fi fi -info "Running cargo test with env: ARCH=$ARCH, FEATURES=$FEATURES, BOARD=$BOARD" +info "Running cargo test with env: ARCH=$ARCH, BOARD=$BOARD" info "Building hvisor with $CARGO_BUILD_INPUT_ARG0" info "PWD=$PWD, running cargo test" @@ -53,17 +49,10 @@ if [ "$ARCH" == "aarch64" ]; then info "Running QEMU with $HVISOR_BIN" - # if we have gicv2,gicv3 in FEATURES, we get the number from it - AARCH64_GIC_TEST_VERSION=3 - if [[ $FEATURES == *"gicv2"* ]]; then - AARCH64_GIC_TEST_VERSION=2 - fi + AARCH64_GIC_TEST_VERSION=2 info "Using GIC version: $AARCH64_GIC_TEST_VERSION" - UBOOT=$UBOOT_GICV3 - if [ $AARCH64_GIC_TEST_VERSION -eq 2 ]; then - UBOOT=$UBOOT_GICV2 - fi + UBOOT=$UBOOT_GICV2 UBOOT=$PWD/platform/$ARCH/$BOARD/image/bootloader/$UBOOT info "Using U-Boot: $UBOOT" diff --git a/platform/aarch64/qemu-gicv3/board.rs b/platform/aarch64/qemu-gicv3/board.rs index 119c357cc..9048090a4 100644 --- a/platform/aarch64/qemu-gicv3/board.rs +++ b/platform/aarch64/qemu-gicv3/board.rs @@ -16,7 +16,7 @@ use crate::{ arch::{ mmu::MemoryType, - zone::{GicConfig, Gicv3Config, HvArchZoneConfig}, + zone::{GicConfig, Gicv3Config, HvArchZoneConfig, UefiConfig}, }, config::*, pci::vpci_dev::VpciDevType, @@ -29,7 +29,7 @@ pub const BOARD_NAME: &str = "qemu-gicv3"; pub const BOARD_NCPUS: usize = 4; pub const BOARD_UART_BASE: u64 = 0x9000000; - +pub static BOARD_EARLY_CACHE_INVALIDATE_MASKS: [u64; BOARD_NCPUS] = [0b011; BOARD_NCPUS]; #[rustfmt::skip] pub static BOARD_MPIDR_MAPPINGS: [u64; BOARD_NCPUS] = [ 0x0, // cpu0 @@ -49,6 +49,7 @@ pub const BOARD_PHYSMEM_LIST: &[(u64, u64, MemoryType)] = &[ (0x4010000000, 0x4020000000, MemoryType::Device), ]; +/// Early boot cache invalidate mask (per CPU): bit0->L1(D), bit1->L2, bit2->L3. pub const ROOT_ZONE_DTB_ADDR: u64 = 0xa0000000; pub const ROOT_ZONE_KERNEL_ADDR: u64 = 0xa0400000; pub const ROOT_ZONE_ENTRY: u64 = 0xa0400000; @@ -69,6 +70,24 @@ pub const ROOT_ZONE_MEMORY_REGIONS: &[HvConfigMemoryRegion] = &[ virtual_start: 0x9000000, size: 0x1000, }, // serial + HvConfigMemoryRegion { + mem_type: MEM_TYPE_IO, + physical_start: 0x9010000, + virtual_start: 0x9010000, + size: 0x1000, + }, // rtc + HvConfigMemoryRegion { + mem_type: MEM_TYPE_IO, + physical_start: 0x00000000, + virtual_start: 0x00000000, + size: 0x08000000, + }, // flash + HvConfigMemoryRegion { + mem_type: MEM_TYPE_IO, + physical_start: 0x9020000, + virtual_start: 0x9020000, + size: 0x1000, + }, // fw-cfg HvConfigMemoryRegion { mem_type: MEM_TYPE_IO, physical_start: 0xa000000, @@ -78,10 +97,17 @@ pub const ROOT_ZONE_MEMORY_REGIONS: &[HvConfigMemoryRegion] = &[ ]; pub const IRQ_WAKEUP_VIRTIO_DEVICE: usize = 32 + 0x20; +pub const IRQ_WAKEUP_VIRTIO_PCI_CONFIG: usize = 32 + 0x21; +pub const IRQ_WAKEUP_VIRTIO_PCI_DATA: usize = 32 + 0x22; // 35 36 37 38 -> pcie intx# +// 45 46 47 48 -> timer +// 34 -> pl031 +// 33 -> pl011 +// 79 -> virtio // 65 -> ivc -pub const ROOT_ZONE_IRQS_BITMAP: &[BitmapWord] = - &get_irqs_bitmap(&[33, 64, 77, 79, 35, 36, 37, 38, 65]); +pub const ROOT_ZONE_IRQS_BITMAP: &[BitmapWord] = &get_irqs_bitmap(&[ + 33, 34, 39, 45, 46, 47, 48, 64, 77, 79, 35, 36, 37, 38, 65, 66, 67, +]); pub const ROOT_ARCH_ZONE_CONFIG: HvArchZoneConfig = HvArchZoneConfig { is_aarch32: 0, @@ -93,6 +119,7 @@ pub const ROOT_ARCH_ZONE_CONFIG: HvArchZoneConfig = HvArchZoneConfig { gits_base: 0x8080000, gits_size: 0x20000, }), + uefi_config: UefiConfig::NoUefi, }; pub const ROOT_PCI_CONFIG: [HvPciConfig; 1] = [HvPciConfig { @@ -115,8 +142,8 @@ pub const ROOT_PCI_CONFIG: [HvPciConfig; 1] = [HvPciConfig { pub const ROOT_ZONE_IVC_CONFIG: [HvIvcConfig; 0] = []; pub const ROOT_PCI_DEVS: &[HvPciDevConfig] = &[ - pci_dev!(0x0, 0x0, 0x0, 0x0, VpciDevType::Physical), - pci_dev!(0x0, 0x0, 0x1, 0x0, VpciDevType::Physical), - // pci_dev!(0x0, 0x0, 0x3, 0x0, VpciDevType::Physical), - pci_dev!(0x0, 0x0, 0x5, 0x0, VpciDevType::StandardVdev), + pci_dev!(0x0, 0x0, 0x0, 0x0 => 0x0, 0x0, 0x0, VpciDevType::Physical), + pci_dev!(0x0, 0x0, 0x1, 0x0 => 0x0, 0x3, 0x0, VpciDevType::Physical), + // pci_dev!(0x0, 0x0, 0x3, 0x0 => 0x0, 0x3, 0x0, VpciDevType::Physical), + // pci_dev!(0x0, 0x0, 0x5, 0x0 => 0x0, 0x5, 0x0, VpciDevType::StandardVdev), ]; diff --git a/platform/aarch64/qemu-gicv3/cargo/features b/platform/aarch64/qemu-gicv3/cargo/features deleted file mode 100644 index d9b303955..000000000 --- a/platform/aarch64/qemu-gicv3/cargo/features +++ /dev/null @@ -1,5 +0,0 @@ -gicv3 -pl011 -arm_smmu -pci -ecam_pcie \ No newline at end of file diff --git a/platform/aarch64/qemu-gicv3/configs/zone1-linux.json b/platform/aarch64/qemu-gicv3/configs/zone1-linux.json index b9b5d68db..b73f0bc98 100644 --- a/platform/aarch64/qemu-gicv3/configs/zone1-linux.json +++ b/platform/aarch64/qemu-gicv3/configs/zone1-linux.json @@ -1,12 +1,15 @@ { "name": "linux2", "zone_id": 1, - "cpus": [2, 3], + "cpus": [ + 3, + 4 + ], "memory_regions": [ { "type": "ram", "physical_start": "0x50000000", - "virtual_start": "0x50000000", + "virtual_start": "0x50000000", "size": "0x30000000" }, { @@ -37,8 +40,8 @@ "kernel_filepath": "./Image", "dtb_filepath": "./zone1-linux.dtb", "kernel_load_paddr": "0x50400000", - "dtb_load_paddr": "0x50000000", - "entry_point": "0x50400000", + "dtb_load_paddr": "0x50000000", + "entry_point": "0x50400000", "arch_config": { "gic_version": "v3", "gicd_base": "0x8000000", @@ -49,22 +52,24 @@ "gits_size": "0x20000", "is_aarch32": false }, - "pci_config": [{ - "ecam_base": "0x4010000000", - "ecam_size": "0x10000000", - "io_base": "0x3eff0000", - "io_size": "0x10000", - "pci_io_base": "0x0", - "mem32_base": "0x10000000", - "mem32_size": "0x2eff0000", - "pci_mem32_base": "0x10000000", - "mem64_base": "0x8000000000", - "mem64_size": "0x8000000000", - "pci_mem64_base": "0x8000000000", - "bus_range_begin": "0x0", - "bus_range_end": "0x1f", - "domain": "0x0" - }], + "pci_config": [ + { + "ecam_base": "0x4010000000", + "ecam_size": "0x10000000", + "io_base": "0x3eff0000", + "io_size": "0x10000", + "pci_io_base": "0x0", + "mem32_base": "0x10000000", + "mem32_size": "0x2eff0000", + "pci_mem32_base": "0x10000000", + "mem64_base": "0x8000000000", + "mem64_size": "0x8000000000", + "pci_mem64_base": "0x8000000000", + "bus_range_begin": "0x0", + "bus_range_end": "0x1f", + "domain": "0x0" + } + ], "num_pci_devs": 2, "alloc_pci_devs": [ { @@ -72,13 +77,19 @@ "bus": "0x0", "device": "0x0", "function": "0x0", + "v_bus": "0x0", + "v_device": "0x0", + "v_function": "0x0", "dev_type": "0" }, { "domain": "0x0", "bus": "0x0", - "device": "0x1", + "device": "0x2", "function": "0x0", + "v_bus": "0x0", + "v_device": "0x1", + "v_function": "0x0", "dev_type": "0" } ] diff --git a/platform/aarch64/qemu-gicv3/configs/zone1-ruxos.json b/platform/aarch64/qemu-gicv3/configs/zone1-ruxos.json index 0622aba27..c612ddbf0 100644 --- a/platform/aarch64/qemu-gicv3/configs/zone1-ruxos.json +++ b/platform/aarch64/qemu-gicv3/configs/zone1-ruxos.json @@ -39,5 +39,6 @@ "gicr_size": "0xf60000", "gits_base": "0x8080000", "gits_size": "0x20000" - } -} \ No newline at end of file + }, + "pci_config": [] +} diff --git a/platform/aarch64/qemu-gicv3/image/dts/zone0.dts b/platform/aarch64/qemu-gicv3/image/dts/zone0.dts index 1c9d79cb0..cb99f895e 100644 --- a/platform/aarch64/qemu-gicv3/image/dts/zone0.dts +++ b/platform/aarch64/qemu-gicv3/image/dts/zone0.dts @@ -355,4 +355,16 @@ interrupt-parent = <0x01>; interrupts = <0x00 0x20 0x01>; }; -}; \ No newline at end of file + + hvisor_virtio_pci_config { + compatible = "hvisor"; + interrupt-parent = <0x01>; + interrupts = <0x00 0x21 0x01>; + }; + + hvisor_virtio_pci_data { + compatible = "hvisor"; + interrupt-parent = <0x01>; + interrupts = <0x00 0x22 0x01>; + }; +}; diff --git a/platform/aarch64/qemu-gicv3/kconfig/defconfig b/platform/aarch64/qemu-gicv3/kconfig/defconfig new file mode 100644 index 000000000..674eecc5a --- /dev/null +++ b/platform/aarch64/qemu-gicv3/kconfig/defconfig @@ -0,0 +1,8 @@ +CONFIG_ARCH_AARCH64=y +CONFIG_ARM_SMMU=y +CONFIG_IOMMU=y +CONFIG_IRQ_GICV3=y +CONFIG_PCI=y +CONFIG_PCIE_ECAM=y +CONFIG_PL011=y +CONFIG_VIRTIO_PCI=y diff --git a/platform/aarch64/qemu-gicv3/scripts/boot_zone1.sh b/platform/aarch64/qemu-gicv3/scripts/boot_zone1.sh new file mode 100644 index 000000000..740d624ff --- /dev/null +++ b/platform/aarch64/qemu-gicv3/scripts/boot_zone1.sh @@ -0,0 +1,9 @@ +#!/bin/bash + +insmod hvisor.ko +mount -t proc proc /proc +mount -t sysfs sysfs /sys +mkdir -p /dev/pts +mount -t devpts devpts /dev/pts +./hvisor virtio start zone1-linux-virtio.json & +./hvisor zone start zone1-linux.json \ No newline at end of file diff --git a/platform/aarch64/qemu-gicv3/scripts/insmod.sh b/platform/aarch64/qemu-gicv3/scripts/insmod.sh new file mode 100644 index 000000000..268bb6aa0 --- /dev/null +++ b/platform/aarch64/qemu-gicv3/scripts/insmod.sh @@ -0,0 +1,3 @@ +#!/bin/bash + +insmod hvisor.ko \ No newline at end of file diff --git a/platform/aarch64/qemu-gicv3/scripts/setup.sh b/platform/aarch64/qemu-gicv3/scripts/setup.sh new file mode 100644 index 000000000..167eaee08 --- /dev/null +++ b/platform/aarch64/qemu-gicv3/scripts/setup.sh @@ -0,0 +1,4 @@ +#!/bin/bash + +mount -t proc proc /proc +mount -t sysfs sysfs /sys \ No newline at end of file diff --git a/platform/aarch64/qemu-gicv3/scripts/start_zone1.sh b/platform/aarch64/qemu-gicv3/scripts/start_zone1.sh new file mode 100644 index 000000000..a33a32a9f --- /dev/null +++ b/platform/aarch64/qemu-gicv3/scripts/start_zone1.sh @@ -0,0 +1,3 @@ +#!/bin/bash + +./hvisor zone start zone1-linux.json \ No newline at end of file diff --git a/platform/aarch64/qemu-gicv3/scripts/stop_zone1.sh b/platform/aarch64/qemu-gicv3/scripts/stop_zone1.sh new file mode 100644 index 000000000..8d4a6d14c --- /dev/null +++ b/platform/aarch64/qemu-gicv3/scripts/stop_zone1.sh @@ -0,0 +1,3 @@ +#!/bin/bash + +./hvisor zone shutdown -id 1 \ No newline at end of file diff --git a/platform/aarch64/qemu-gicv3/scripts/virtio_start.sh b/platform/aarch64/qemu-gicv3/scripts/virtio_start.sh new file mode 100644 index 000000000..8c3397da0 --- /dev/null +++ b/platform/aarch64/qemu-gicv3/scripts/virtio_start.sh @@ -0,0 +1,5 @@ +#!/bin/bash + +mkdir -p /dev/pts +mount -t devpts devpts /dev/pts +./hvisor virtio start zone1-linux-virtio.json & \ No newline at end of file diff --git a/platform/aarch64/qemu-gicv3/test/runner.sh b/platform/aarch64/qemu-gicv3/test/runner.sh index 78d0a9644..5cf40efe7 100755 --- a/platform/aarch64/qemu-gicv3/test/runner.sh +++ b/platform/aarch64/qemu-gicv3/test/runner.sh @@ -6,14 +6,10 @@ PWD=$(pwd) THIS=$(basename $0) CARGO_BUILD_INPUT_ARG0=$1 -# capture env: FEATURES, ARCH - ARCH=${ARCH} -FEATURES=${FEATURES} BOARD=${BOARD} UBOOT_GICV3=u-boot-atf.bin -UBOOT_GICV2=u-boot-v2.bin HVISOR_ELF=$CARGO_BUILD_INPUT_ARG0 HVISOR_BIN_TMP=$HVISOR_ELF.bin.tmp @@ -41,7 +37,7 @@ if ! command -v mkimage &>/dev/null; then fi fi -info "Running cargo test with env: ARCH=$ARCH, FEATURES=$FEATURES, BOARD=$BOARD" +info "Running cargo test with env: ARCH=$ARCH, BOARD=$BOARD" info "Building hvisor with $CARGO_BUILD_INPUT_ARG0" info "PWD=$PWD, running cargo test" @@ -53,17 +49,10 @@ if [ "$ARCH" == "aarch64" ]; then info "Running QEMU with $HVISOR_BIN" - # if we have gicv2,gicv3 in FEATURES, we get the number from it AARCH64_GIC_TEST_VERSION=3 - if [[ $FEATURES == *"gicv2"* ]]; then - AARCH64_GIC_TEST_VERSION=2 - fi info "Using GIC version: $AARCH64_GIC_TEST_VERSION" UBOOT=$UBOOT_GICV3 - if [ $AARCH64_GIC_TEST_VERSION -eq 2 ]; then - UBOOT=$UBOOT_GICV2 - fi UBOOT=$PWD/platform/$ARCH/$BOARD/image/bootloader/$UBOOT info "Using U-Boot: $UBOOT" diff --git a/platform/aarch64/rk3568/board.rs b/platform/aarch64/rk3568/board.rs index 32ed5d3ca..adaf8923e 100644 --- a/platform/aarch64/rk3568/board.rs +++ b/platform/aarch64/rk3568/board.rs @@ -18,7 +18,7 @@ use crate::pci_dev; use crate::{ arch::{ mmu::MemoryType, - zone::{GicConfig, Gicv3Config, HvArchZoneConfig}, + zone::{GicConfig, Gicv3Config, HvArchZoneConfig, UefiConfig}, }, config::*, pci::vpci_dev::VpciDevType, @@ -37,6 +37,9 @@ pub static BOARD_MPIDR_MAPPINGS: [u64; BOARD_NCPUS] = [ 0x300, // cpu3 ]; +/// Early boot cache invalidate mask (per CPU): bit0->L1(D), bit1->L2, bit2->L3. +pub static BOARD_EARLY_CACHE_INVALIDATE_MASKS: [u64; BOARD_NCPUS] = [0b011; BOARD_NCPUS]; + /// The physical memory layout of the board. /// Each address should align to 2M (0x200000). /// Addresses must be in ascending order. @@ -57,42 +60,81 @@ pub const ROOT_ZONE_CPUS: u64 = (1 << 0) | (1 << 1); pub const ROOT_ZONE_NAME: &str = "root-linux"; pub const ROOT_ZONE_MEMORY_REGIONS: &[HvConfigMemoryRegion] = &[ - // HvConfigMemoryRegion { - // mem_type: MEM_TYPE_IO, - // physical_start: 0x3c0400000, - // virtual_start: 0x3c0400000, - // size: 0x400000, - // }, //pcie - // HvConfigMemoryRegion { - // mem_type: MEM_TYPE_IO, - // physical_start: 0xfe270000, - // virtual_start: 0xfe270000, - // size: 0x10000, - // }, //pcie + // pcie@fe260000 (domain 0) + HvConfigMemoryRegion { + mem_type: MEM_TYPE_IO, + physical_start: 0xf4000000, + virtual_start: 0xf4000000, + size: 0x100000, + }, + HvConfigMemoryRegion { + mem_type: MEM_TYPE_IO, + physical_start: 0xf4100000, + virtual_start: 0xf4100000, + size: 0x100000, + }, + HvConfigMemoryRegion { + mem_type: MEM_TYPE_IO, + physical_start: 0xf4200000, + virtual_start: 0xf4200000, + size: 0x1e00000, + }, + HvConfigMemoryRegion { + mem_type: MEM_TYPE_IO, + physical_start: 0x300000000, + virtual_start: 0x300000000, + size: 0x40000000, + }, + // pcie@fe270000 (domain 1) HvConfigMemoryRegion { mem_type: MEM_TYPE_IO, physical_start: 0xf2000000, virtual_start: 0xf2000000, size: 0x100000, - }, //pcie + }, HvConfigMemoryRegion { mem_type: MEM_TYPE_IO, physical_start: 0xf2100000, virtual_start: 0xf2100000, size: 0x100000, - }, //pcie + }, HvConfigMemoryRegion { mem_type: MEM_TYPE_IO, physical_start: 0xf2200000, virtual_start: 0xf2200000, size: 0x1e00000, - }, //pcie + }, HvConfigMemoryRegion { mem_type: MEM_TYPE_IO, physical_start: 0x340000000, virtual_start: 0x340000000, size: 0x40000000, - }, //pcie + }, + // pcie@fe280000 (domain 2) + HvConfigMemoryRegion { + mem_type: MEM_TYPE_IO, + physical_start: 0xf0000000, + virtual_start: 0xf0000000, + size: 0x100000, + }, + HvConfigMemoryRegion { + mem_type: MEM_TYPE_IO, + physical_start: 0xf0100000, + virtual_start: 0xf0100000, + size: 0x100000, + }, + HvConfigMemoryRegion { + mem_type: MEM_TYPE_IO, + physical_start: 0xf0200000, + virtual_start: 0xf0200000, + size: 0x1e00000, + }, + HvConfigMemoryRegion { + mem_type: MEM_TYPE_IO, + physical_start: 0x380000000, + virtual_start: 0x380000000, + size: 0x40000000, + }, HvConfigMemoryRegion { mem_type: MEM_TYPE_IO, physical_start: 0xfdcb8000, @@ -139,8 +181,14 @@ pub const ROOT_ZONE_MEMORY_REGIONS: &[HvConfigMemoryRegion] = &[ mem_type: MEM_TYPE_RAM, physical_start: 0x9400000, virtual_start: 0x9400000, - size: 0xe6c00000, - }, // memory + size: 0x56c00000, + }, // memory (before hvisor) + HvConfigMemoryRegion { + mem_type: MEM_TYPE_RAM, + physical_start: 0x64600000, + virtual_start: 0x64600000, + size: 0x8ba00000, + }, // memory (after hvisor) HvConfigMemoryRegion { mem_type: MEM_TYPE_RAM, physical_start: 0x0, @@ -160,11 +208,11 @@ pub const ROOT_ZONE_MEMORY_REGIONS: &[HvConfigMemoryRegion] = &[ // size: 0x1000, // }, //scmi-shmem HvConfigMemoryRegion { - mem_type: MEM_TYPE_RAM, + mem_type: MEM_TYPE_IO, physical_start: 0xfd440000, virtual_start: 0xfd440000, size: 0x20000, - }, // its + }, // its passthrough HvConfigMemoryRegion { mem_type: MEM_TYPE_RAM, physical_start: 0x1f0000000, @@ -267,12 +315,24 @@ pub const ROOT_ZONE_MEMORY_REGIONS: &[HvConfigMemoryRegion] = &[ virtual_start: 0xFE310000, size: 0x10000, }, //sdhci + HvConfigMemoryRegion { + mem_type: MEM_TYPE_IO, + physical_start: 0xfe010000, + virtual_start: 0xfe010000, + size: 0x10000, + }, // gmac1 ethernet@fe010000 + HvConfigMemoryRegion { + mem_type: MEM_TYPE_IO, + physical_start: 0xfda00000, + virtual_start: 0xfda00000, + size: 0x200000, + }, // xpcs syscon for gmac RGMII ]; -pub const IRQ_WAKEUP_VIRTIO_DEVICE: usize = 32 + 0x20; +pub const IRQ_WAKEUP_VIRTIO_DEVICE: usize = 32 + 0x26; pub const ROOT_ZONE_IRQS_BITMAP: &[BitmapWord] = &get_irqs_bitmap(&[ - 0x84, 0x98, 0x40, 0x104, 0x105, 0x106, 0x107, 0x2d, 0x2e, 0x2b, 0x2a, 0x29, 0x33, 0x96, 0x11c, - 0x44, 0x43, 0x42, 0x41, 0x8d, + 0x84, 0x98, 0x46, 0x20, 0x1d, 0x104, 0x105, 0x106, 0x107, 0x108, 0x2d, 0x2e, 0x2b, 0x2a, 0x29, + 0x33, 0x96, 0x11c, 0x44, 0x43, 0x42, 0x41, 0x8d, 0x48, 0x49, 0x9d, 0x9e, 0xa2, 0xa3, ]); pub const ROOT_ARCH_ZONE_CONFIG: HvArchZoneConfig = HvArchZoneConfig { @@ -282,27 +342,28 @@ pub const ROOT_ARCH_ZONE_CONFIG: HvArchZoneConfig = HvArchZoneConfig { gicd_size: 0x10000, gicr_base: 0xfd460000, gicr_size: 0xc0000, - gits_base: 0xfd440000, - gits_size: 0x20000, + gits_base: 0, + gits_size: 0, }), + uefi_config: UefiConfig::NoUefi }; pub const ROOT_PCI_CONFIG: &[HvPciConfig] = &[ - // HvPciConfig { - // ecam_base: 0xfe260000, - // ecam_size: 0x400000, - // io_base: 0xf4100000, - // io_size: 0x100000, - // pci_io_base: 0xf4100000, - // mem32_base: 0xf4200000, - // mem32_size: 0x1e00000, - // pci_mem32_base: 0xf4200000, - // mem64_base: 0x300000000, - // mem64_size: 0x40000000, - // pci_mem64_base: 0x300000000, - // bus_range_begin: 0x0, - // bus_range_end: 0x10, - // domain: 0x0, - // }, + HvPciConfig { + ecam_base: 0x3c0000000, + ecam_size: 0x400000, + io_base: 0xf4100000, + io_size: 0x100000, + pci_io_base: 0xf4100000, + mem32_base: 0xf4200000, + mem32_size: 0x1e00000, + pci_mem32_base: 0xf4200000, + mem64_base: 0x300000000, + mem64_size: 0x40000000, + pci_mem64_base: 0x300000000, + bus_range_begin: 0x0, + bus_range_end: 0x10, + domain: 0x0, + }, HvPciConfig { ecam_base: 0x3c0400000, ecam_size: 0x400000, @@ -319,38 +380,68 @@ pub const ROOT_PCI_CONFIG: &[HvPciConfig] = &[ bus_range_end: 0x1f, domain: 0x1, }, - // HvPciConfig { - // ecam_base: 0xfe280000, - // ecam_size: 0x400000, - // io_base: 0xf0100000, - // io_size: 0x100000, - // pci_io_base: 0xf0100000, - // mem32_base: 0xf0200000, - // mem32_size: 0x1e00000, - // pci_mem32_base: 0xf0200000, - // mem64_base: 0x380000000, - // mem64_size: 0x40000000, - // pci_mem64_base: 0x380000000, - // bus_range_begin: 0x20, - // bus_range_end: 0x2f, - // domain: 0x2, - // } + HvPciConfig { + ecam_base: 0x3c0800000, + ecam_size: 0x400000, + io_base: 0xf0100000, + io_size: 0x100000, + pci_io_base: 0xf0100000, + mem32_base: 0xf0200000, + mem32_size: 0x1e00000, + pci_mem32_base: 0xf0200000, + mem64_base: 0x380000000, + mem64_size: 0x40000000, + pci_mem64_base: 0x380000000, + bus_range_begin: 0x20, + bus_range_end: 0x2f, + domain: 0x2, + }, ]; pub const ROOT_ZONE_IVC_CONFIG: [HvIvcConfig; 0] = []; -pub const ROOT_DWC_ATU_CONFIG: &[HvDwcAtuConfig] = &[HvDwcAtuConfig { - ecam_base: 0x3c0400000, - dbi_base: 0x3c0400000, - dbi_size: 0x10000, - apb_base: 0xfe270000, - apb_size: 0x10000, - cfg_base: 0xf2000000, - cfg_size: 0x80000 * 2, - io_cfg_atu_shared: 0, -}]; +pub const ROOT_DWC_ATU_CONFIG: &[HvDwcAtuConfig] = &[ + HvDwcAtuConfig { + ecam_base: 0x3c0000000, + dbi_base: 0x3c0000000, + dbi_size: 0x10000, + apb_base: 0xfe260000, + apb_size: 0x10000, + cfg_base: 0xf4000000, + cfg_size: 0x80000 * 2, + io_cfg_atu_shared: 0, + io_atu_index: 0, + dw_msi_irq: 0x49, // pcie@fe260000 msg irq + }, + HvDwcAtuConfig { + ecam_base: 0x3c0400000, + dbi_base: 0x3c0400000, + dbi_size: 0x10000, + apb_base: 0xfe270000, + apb_size: 0x10000, + cfg_base: 0xf2000000, + cfg_size: 0x80000 * 2, + io_cfg_atu_shared: 0, + io_atu_index: 0, + dw_msi_irq: 0x9e, // pcie@fe270000 msg irq + }, + HvDwcAtuConfig { + ecam_base: 0x3c0800000, + dbi_base: 0x3c0800000, + dbi_size: 0x10000, + apb_base: 0xfe280000, + apb_size: 0x10000, + cfg_base: 0xf0000000, + cfg_size: 0x80000 * 2, + io_cfg_atu_shared: 0, + io_atu_index: 0, + dw_msi_irq: 0xa3, // pcie@fe280000 msg irq + }, +]; -pub const ROOT_PCI_DEVS: [HvPciDevConfig; 2] = [ - pci_dev!(0x0, 0x00, 0x0, 0x0, VpciDevType::Physical), - pci_dev!(0x0, 0x01, 0x0, 0x0, VpciDevType::Physical), +pub const ROOT_PCI_DEVS: [HvPciDevConfig; 4] = [ + pci_dev!(0x1, 0x10, 0x0, 0x0 => 0x10, 0x0, 0x0, VpciDevType::Physical), + pci_dev!(0x1, 0x11, 0x0, 0x0 => 0x11, 0x0, 0x0, VpciDevType::Physical), + pci_dev!(0x2, 0x20, 0x0, 0x0 => 0x20, 0x0, 0x0, VpciDevType::Physical), + pci_dev!(0x2, 0x21, 0x0, 0x0 => 0x21, 0x0, 0x0, VpciDevType::Physical), ]; diff --git a/platform/aarch64/rk3568/cargo/features b/platform/aarch64/rk3568/cargo/features deleted file mode 100644 index 0b11e0fab..000000000 --- a/platform/aarch64/rk3568/cargo/features +++ /dev/null @@ -1,5 +0,0 @@ -gicv3 -uart_16550 -pci -dwc_pcie -no_pcie_bar_realloc \ No newline at end of file diff --git a/platform/aarch64/rk3568/configs/linux2.json b/platform/aarch64/rk3568/configs/linux2.json index 275d310ee..f3c070d89 100644 --- a/platform/aarch64/rk3568/configs/linux2.json +++ b/platform/aarch64/rk3568/configs/linux2.json @@ -6,9 +6,9 @@ "memory_regions": [ { "type": "ram", - "physical_start": "0x40000000", - "virtual_start": "0x40000000", - "size": "0x20000000" + "physical_start": "0x50000000", + "virtual_start": "0x50000000", + "size": "0x25000000" }, { "type": "io", @@ -33,9 +33,9 @@ "ivc_configs": [], "kernel_filepath": "./Image", "dtb_filepath": "./rk3568_limit_zone1.dtb", - "kernel_load_paddr": "0x40080000", - "dtb_load_paddr": "0x40000000", - "entry_point": "0x40080000", + "kernel_load_paddr": "0x50400000", + "dtb_load_paddr": "0x50000000", + "entry_point": "0x50400000", "arch_config": { "gic_version": "v3", "gicd_base": "0xfd400000", @@ -44,5 +44,6 @@ "gicr_size": "0xc0000", "gits_base": "0x0", "gits_size": "0x0" - } + }, + "pci_config": [] } diff --git a/platform/aarch64/rk3568/configs/virtio.json b/platform/aarch64/rk3568/configs/virtio.json index 2ee0fa216..82c461793 100644 --- a/platform/aarch64/rk3568/configs/virtio.json +++ b/platform/aarch64/rk3568/configs/virtio.json @@ -4,9 +4,9 @@ "id": 1, "memory_region": [ { - "zone0_ipa": "0x40000000", - "zonex_ipa": "0x40000000", - "size": "0x20000000" + "zone0_ipa": "0x50000000", + "zonex_ipa": "0x50000000", + "size": "0x25000000" } ], "devices": [ diff --git a/platform/aarch64/rk3568/image/dts/rk3568_limit_zone0.dts b/platform/aarch64/rk3568/image/dts/rk3568_limit_zone0.dts index 420426e81..0eac654e0 100644 --- a/platform/aarch64/rk3568/image/dts/rk3568_limit_zone0.dts +++ b/platform/aarch64/rk3568/image/dts/rk3568_limit_zone0.dts @@ -16,6 +16,7 @@ mmc1 = "/dwmmc@fe2b0000"; mmc2 = "/dwmmc@fe2c0000"; mmc3 = "/dwmmc@fe000000"; + ethernet1 = "/ethernet@fe010000"; }; syscon@fdc50000 { @@ -140,47 +141,47 @@ }; - // pcie@fe260000 { - // power-domains = <0x22 0x0f>; - // #address-cells = <0x03>; - // phy-names = "pcie-phy"; - // bus-range = <0x00 0x0f>; - // clock-names = "aclk_mst\0aclk_slv\0aclk_dbi\0pclk\0aux"; - // reg-names = "pcie-dbi\0pcie-apb"; - // num-ob-windows = <0x02>; - // resets = <0x20 0xa1>; - // interrupts = <0x00 0x4b 0x04 0x00 0x4a 0x04 0x00 0x49 0x04 0x00 0x48 0x04 0x00 0x47 0x04>; - // clocks = <0x20 0x81 0x20 0x82 0x20 0x83 0x20 0x84 0x20 0x85>; - // interrupt-map = <0x00 0x00 0x00 0x01 0xac 0x00 0x00 0x00 0x00 0x02 0xac 0x01 0x00 0x00 0x00 0x03 0xac 0x02 0x00 0x00 0x00 0x04 0xac 0x03>; - // #size-cells = <0x02>; - // max-link-speed = <0x02>; - // device_type = "pci"; - // interrupt-map-mask = <0x00 0x00 0x00 0x07>; - // reset-gpios = <0x83 0x11 0x00>; - // num-lanes = <0x01>; - // compatible = "rockchip,rk3568-pcie\0snps,dw-pcie"; - // ranges = <0x800 0x00 0xf4000000 0x00 0xf4000000 0x00 0x100000 0x81000000 0x00 0xf4100000 0x00 0xf4100000 0x00 0x100000 0x82000000 0x00 0xf4200000 0x00 0xf4200000 0x00 0x1e00000 0xc3000000 0x03 0x00 0x03 0x00 0x00 0x40000000>; - // msi-map = <0x00 0xad 0x00 0x1000>; - // #interrupt-cells = <0x01>; - // status = "okay"; - // interrupt-names = "sys\0pmc\0msg\0legacy\0err"; - // phys = <0x24 0x02>; - // num-viewport = <0x08>; - // reg = <0x03 0xc0000000 0x00 0x400000 0x00 0xfe260000 0x00 0x10000>; - // linux,pci-domain = <0x00>; - // phandle = <0x19d>; - // reset-names = "pipe"; - // num-ib-windows = <0x06>; - - // legacy-interrupt-controller { - // #address-cells = <0x00>; - // interrupts = <0x00 0x48 0x01>; - // interrupt-parent = <0x01>; - // #interrupt-cells = <0x01>; - // phandle = <0xac>; - // interrupt-controller; - // }; - // }; + pcie@fe260000 { + power-domains = <0x22 0x0f>; + #address-cells = <0x03>; + phy-names = "pcie-phy"; + bus-range = <0x00 0x0f>; + clock-names = "aclk_mst\0aclk_slv\0aclk_dbi\0pclk\0aux"; + reg-names = "pcie-dbi\0pcie-apb"; + num-ob-windows = <0x02>; + resets = <0x20 0xa1>; + interrupts = <0x00 0x4b 0x04 0x00 0x4a 0x04 0x00 0x49 0x04 0x00 0x48 0x04 0x00 0x47 0x04>; + clocks = <0x20 0x81 0x20 0x82 0x20 0x83 0x20 0x84 0x20 0x85>; + interrupt-map = <0x00 0x00 0x00 0x01 0xac 0x00 0x00 0x00 0x00 0x02 0xac 0x01 0x00 0x00 0x00 0x03 0xac 0x02 0x00 0x00 0x00 0x04 0xac 0x03>; + #size-cells = <0x02>; + max-link-speed = <0x02>; + device_type = "pci"; + interrupt-map-mask = <0x00 0x00 0x00 0x07>; + reset-gpios = <0x83 0x11 0x00>; + num-lanes = <0x01>; + compatible = "rockchip,rk3568-pcie\0snps,dw-pcie"; + ranges = <0x800 0x00 0xf4000000 0x00 0xf4000000 0x00 0x100000 0x81000000 0x00 0xf4100000 0x00 0xf4100000 0x00 0x100000 0x82000000 0x00 0xf4200000 0x00 0xf4200000 0x00 0x1e00000 0xc3000000 0x03 0x00 0x03 0x00 0x00 0x40000000>; + msi-map = <0x00 0xad 0x00 0x1000>; + #interrupt-cells = <0x01>; + status = "okay"; + interrupt-names = "sys\0pmc\0msg\0legacy\0err"; + phys = <0x24 0x02>; + num-viewport = <0x08>; + reg = <0x03 0xc0000000 0x00 0x400000 0x00 0xfe260000 0x00 0x10000>; + linux,pci-domain = <0x00>; + phandle = <0x19d>; + reset-names = "pipe"; + num-ib-windows = <0x06>; + + legacy-interrupt-controller { + #address-cells = <0x00>; + interrupts = <0x00 0x48 0x01>; + interrupt-parent = <0x01>; + #interrupt-cells = <0x01>; + phandle = <0xac>; + interrupt-controller; + }; + }; syscon@fdcb8000 { compatible = "rockchip,pcie30-phy-grf\0syscon"; @@ -259,48 +260,48 @@ }; }; - // pcie@fe280000 { - // power-domains = <0x22 0x0f>; - // vpcie3v3-supply = <0xb0>; - // #address-cells = <0x03>; - // phy-names = "pcie-phy"; - // bus-range = <0x20 0x2f>; - // clock-names = "aclk_mst\0aclk_slv\0aclk_dbi\0pclk\0aux"; - // reg-names = "pcie-dbi\0pcie-apb"; - // num-ob-windows = <0x02>; - // resets = <0x20 0xc1>; - // interrupts = <0x00 0xa5 0x04 0x00 0xa4 0x04 0x00 0xa3 0x04 0x00 0xa2 0x04 0x00 0xa1 0x04>; - // clocks = <0x20 0x8f 0x20 0x90 0x20 0x91 0x20 0x92 0x20 0x93>; - // interrupt-map = <0x00 0x00 0x00 0x01 0xb1 0x00 0x00 0x00 0x00 0x02 0xb1 0x01 0x00 0x00 0x00 0x03 0xb1 0x02 0x00 0x00 0x00 0x04 0xb1 0x03>; - // #size-cells = <0x02>; - // max-link-speed = <0x03>; - // device_type = "pci"; - // interrupt-map-mask = <0x00 0x00 0x00 0x07>; - // reset-gpios = <0xb2 0x1e 0x00>; - // num-lanes = <0x02>; - // compatible = "rockchip,rk3568-pcie\0snps,dw-pcie"; - // ranges = <0x800 0x00 0xf0000000 0x00 0xf0000000 0x00 0x100000 0x81000000 0x00 0xf0100000 0x00 0xf0100000 0x00 0x100000 0x82000000 0x00 0xf0200000 0x00 0xf0200000 0x00 0x1e00000 0xc3000000 0x03 0x80000000 0x03 0x80000000 0x00 0x40000000>; - // msi-map = <0x2000 0xad 0x2000 0x1000>; - // #interrupt-cells = <0x01>; - // status = "okay"; - // interrupt-names = "sys\0pmc\0msg\0legacy\0err"; - // phys = <0xaf>; - // num-viewport = <0x08>; - // reg = <0x03 0xc0800000 0x00 0x400000 0x00 0xfe280000 0x00 0x10000>; - // linux,pci-domain = <0x02>; - // phandle = <0x19f>; - // reset-names = "pipe"; - // num-ib-windows = <0x06>; - - // legacy-interrupt-controller { - // #address-cells = <0x00>; - // interrupts = <0x00 0xa2 0x01>; - // interrupt-parent = <0x01>; - // #interrupt-cells = <0x01>; - // phandle = <0xb1>; - // interrupt-controller; - // }; - // }; + pcie@fe280000 { + power-domains = <0x22 0x0f>; + vpcie3v3-supply = <0xb0>; + #address-cells = <0x03>; + phy-names = "pcie-phy"; + bus-range = <0x20 0x2f>; + clock-names = "aclk_mst\0aclk_slv\0aclk_dbi\0pclk\0aux"; + reg-names = "pcie-dbi\0pcie-apb"; + num-ob-windows = <0x02>; + resets = <0x20 0xc1>; + interrupts = <0x00 0xa5 0x04 0x00 0xa4 0x04 0x00 0xa3 0x04 0x00 0xa2 0x04 0x00 0xa1 0x04>; + clocks = <0x20 0x8f 0x20 0x90 0x20 0x91 0x20 0x92 0x20 0x93>; + interrupt-map = <0x00 0x00 0x00 0x01 0xb1 0x00 0x00 0x00 0x00 0x02 0xb1 0x01 0x00 0x00 0x00 0x03 0xb1 0x02 0x00 0x00 0x00 0x04 0xb1 0x03>; + #size-cells = <0x02>; + max-link-speed = <0x03>; + device_type = "pci"; + interrupt-map-mask = <0x00 0x00 0x00 0x07>; + reset-gpios = <0xb2 0x1e 0x00>; + num-lanes = <0x02>; + compatible = "rockchip,rk3568-pcie\0snps,dw-pcie"; + ranges = <0x800 0x00 0xf0000000 0x00 0xf0000000 0x00 0x100000 0x81000000 0x00 0xf0100000 0x00 0xf0100000 0x00 0x100000 0x82000000 0x00 0xf0200000 0x00 0xf0200000 0x00 0x1e00000 0xc3000000 0x03 0x80000000 0x03 0x80000000 0x00 0x40000000>; + msi-map = <0x2000 0xad 0x2000 0x1000>; + #interrupt-cells = <0x01>; + status = "okay"; + interrupt-names = "sys\0pmc\0msg\0legacy\0err"; + phys = <0xaf>; + num-viewport = <0x08>; + reg = <0x03 0xc0800000 0x00 0x400000 0x00 0xfe280000 0x00 0x10000>; + linux,pci-domain = <0x02>; + phandle = <0x19f>; + reset-names = "pipe"; + num-ib-windows = <0x06>; + + legacy-interrupt-controller { + #address-cells = <0x00>; + interrupts = <0x00 0xa2 0x01>; + interrupt-parent = <0x01>; + #interrupt-cells = <0x01>; + phandle = <0xb1>; + interrupt-controller; + }; + }; sdhci@fe310000 { clock-names = "core\0bus\0axi\0block\0timer"; @@ -391,7 +392,83 @@ max-frequency = <0x8f0d180>; reset-names = "reset"; }; - + + syscon@fda00000 { + compatible = "rockchip,rk3568-xpcs\0syscon"; + status = "okay"; + reg = <0x00 0xfda00000 0x00 0x200000>; + phandle = <0x161>; + }; + + ethernet@fe010000 { + pinctrl-names = "default"; + phy-mode = "rgmii"; + snps,mixed-burst; + snps,mtl-rx-config = <0x81>; + snps,reset-active-low; + pinctrl-0 = <0x84 0x85 0x86 0x87 0x88>; + clock-names = "stmmaceth\0mac_clk_rx\0mac_clk_tx\0clk_mac_refout\0aclk_mac\0pclk_mac\0clk_mac_speed\0ptp_ref\0pclk_xpcs\0clk_xpcs_eee"; + assigned-clocks = <0x20 0x189 0x20 0x186>; + assigned-clock-parents = <0x20 0x187 0x20 0xc5>; + snps,mtl-tx-config = <0x82>; + local-mac-address = [2a fd 45 b0 3b 1a]; + assigned-clock-rates = <0x00 0x7735940>; + resets = <0x20 0xec>; + interrupts = <0x00 0x20 0x04 0x00 0x1d 0x04>; + clocks = <0x20 0x186 0x20 0x189 0x20 0x189 0x20 0xc7 0x20 0xc3 0x20 0xc4 0x20 0x189 0x20 0xc8 0x20 0xac 0x20 0xab>; + clock_in_out = "output"; + snps,tso; + compatible = "rockchip,rk3568-gmac\0snps,dwmac-4.20a"; + status = "okay"; + rockchip,grf = <0x34>; + interrupt-names = "macirq\0eth_wake_irq"; + snps,reset-gpio = <0x83 0x08 0x01>; + reg = <0x00 0xfe010000 0x00 0x10000>; + rx_delay = <0x26>; + phandle = <0x7f>; + phy-handle = <0x89>; + reset-names = "stmmaceth"; + tx_delay = <0x4f>; + snps,axi-config = <0x80>; + snps,reset-delays-us = <0x00 0x4e20 0x186a0>; + + mdio { + #address-cells = <0x01>; + #size-cells = <0x00>; + compatible = "snps,dwmac-mdio"; + phandle = <0x18a>; + + phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x00>; + phandle = <0x89>; + }; + }; + + tx-queues-config { + phandle = <0x82>; + snps,tx-queues-to-use = <0x01>; + + queue0 { + }; + }; + + stmmac-axi-config { + snps,wr_osr_lmt = <0x04>; + phandle = <0x80>; + snps,blen = <0x00 0x00 0x00 0x00 0x10 0x08 0x04>; + snps,rd_osr_lmt = <0x08>; + }; + + rx-queues-config { + snps,rx-queues-to-use = <0x01>; + phandle = <0x81>; + + queue0 { + }; + }; + }; + memory { device_type = "memory"; reg = <0x00 0x200000 0x00 0x8200000 0x00 0x9400000 0x00 0xe6c00000 0x01 0xf0000000 0x00 0x10000000>; @@ -652,13 +729,13 @@ phandle = <0x01>; interrupt-controller; - // interrupt-controller@fd440000 { - // msi-controller; - // compatible = "arm,gic-v3-its"; - // reg = <0x00 0xfd440000 0x00 0x20000>; - // phandle = <0xad>; - // #msi-cells = <0x01>; - // }; + interrupt-controller@fd440000 { + msi-controller; + compatible = "arm,gic-v3-its"; + reg = <0x00 0xfd440000 0x00 0x20000>; + phandle = <0xad>; + #msi-cells = <0x01>; + }; }; @@ -1650,6 +1727,6 @@ hvisor_virtio_device { compatible = "hvisor"; interrupt-parent = <0x01>; - interrupts = <0x00 0x20 0x01>; + interrupts = <0x00 0x26 0x01>; }; -}; \ No newline at end of file +}; diff --git a/platform/aarch64/rk3568/image/dts/rk3568_limit_zone1.dts b/platform/aarch64/rk3568/image/dts/rk3568_limit_zone1.dts index 97e392aba..31ea801c0 100644 --- a/platform/aarch64/rk3568/image/dts/rk3568_limit_zone1.dts +++ b/platform/aarch64/rk3568/image/dts/rk3568_limit_zone1.dts @@ -16,7 +16,7 @@ memory { device_type = "memory"; - reg = <0x00 0x40000000 0x00 0x20000000>; + reg = <0x00 0x50000000 0x00 0x25000000>; }; reserved-memory { @@ -416,7 +416,7 @@ chosen { - bootargs = "clk_ignore_unused rw rootwait earlycon=uart8250,mmio32,0xfe660000 console=hvc0 root=/dev/vda"; + bootargs = "clk_ignore_unused rw rootwait earlycon=hvc0 console=hvc0 root=/dev/vda"; // bootargs = "clk_ignore_unused rw rootwait earlycon=uart8250,mmio32,0xfe660000 console=ttyFIQ0 root=/dev/vda"; // bootargs = "clk_ignore_unused earlycon=virtio,mmio,0xff9e0000 console=hvc0 root=/dev/vda rootwait rw"; phandle = <0x1dd>; diff --git a/platform/aarch64/rk3568/kconfig/defconfig b/platform/aarch64/rk3568/kconfig/defconfig new file mode 100644 index 000000000..04cc741de --- /dev/null +++ b/platform/aarch64/rk3568/kconfig/defconfig @@ -0,0 +1,8 @@ +CONFIG_ARCH_AARCH64=y +CONFIG_IRQ_GICV3=y +CONFIG_NO_PCIE_BAR_REALLOC=y +CONFIG_PCI=y +CONFIG_PCIE_DWC=y +CONFIG_UART_16550=y +CONFIG_PCI_INIT_DELAY=y + diff --git a/platform/aarch64/rk3568/scripts/boot_zone1.sh b/platform/aarch64/rk3568/scripts/boot_zone1.sh new file mode 100644 index 000000000..dad724f1c --- /dev/null +++ b/platform/aarch64/rk3568/scripts/boot_zone1.sh @@ -0,0 +1,10 @@ +#!/bin/bash + +insmod hvisor.ko 2>/dev/null || true +mount -t proc proc /proc 2>/dev/null || true +mount -t sysfs sysfs /sys 2>/dev/null || true +rm -f nohup.out +mkdir -p /dev/pts +mount -t devpts devpts /dev/pts 2>/dev/null || true +nohup ./hvisor virtio start virtio.json & +./hvisor zone start linux2.json diff --git a/platform/aarch64/rk3568/scripts/uboot_cmd b/platform/aarch64/rk3568/scripts/uboot_cmd new file mode 100644 index 000000000..cbbb1f06b --- /dev/null +++ b/platform/aarch64/rk3568/scripts/uboot_cmd @@ -0,0 +1 @@ +pci enum;setenv serverip 192.168.1.181; setenv ipaddr 192.168.1.240; setenv loadaddr 0x60800000; setenv fdt_addr 0xa0000000; setenv zone0_kernel_addr 0x00280000; tftp ${loadaddr} ${serverip}:hvisor.bin; tftp ${fdt_addr} ${serverip}:rk3568_limit_zone0.dtb; tftp ${zone0_kernel_addr} ${serverip}:Image; bootm ${loadaddr} - ${fdt_addr}; diff --git a/platform/aarch64/rk3588/board.rs b/platform/aarch64/rk3588/board.rs index 4634691a8..f64567fd4 100644 --- a/platform/aarch64/rk3588/board.rs +++ b/platform/aarch64/rk3588/board.rs @@ -16,7 +16,7 @@ use crate::{ arch::{ mmu::MemoryType, - zone::{GicConfig, Gicv3Config, HvArchZoneConfig}, + zone::{GicConfig, Gicv3Config, HvArchZoneConfig, UefiConfig}, }, config::*, pci::vpci_dev::VpciDevType, @@ -49,6 +49,9 @@ pub static BOARD_MPIDR_MAPPINGS: [u64; BOARD_NCPUS] = [ 0x700, // cpu7 ]; +/// Early boot cache invalidate mask (per CPU): bit0->L1(D), bit1->L2, bit2->L3. +pub static BOARD_EARLY_CACHE_INVALIDATE_MASKS: [u64; BOARD_NCPUS] = [0b111; BOARD_NCPUS]; + /// The physical memory layout of the board. /// Each address should align to 2M (0x200000). /// Addresses must be in ascending order. @@ -193,6 +196,7 @@ pub const ROOT_ARCH_ZONE_CONFIG: HvArchZoneConfig = HvArchZoneConfig { gits_base: 0x8080000, gits_size: 0x20000, }), + uefi_config: UefiConfig::NoUefi }; pub const ROOT_PCI_CONFIG: HvPciConfig = HvPciConfig { @@ -215,6 +219,6 @@ pub const ROOT_PCI_CONFIG: HvPciConfig = HvPciConfig { pub const ROOT_ZONE_IVC_CONFIG: [HvIvcConfig; 0] = []; pub const ROOT_PCI_DEVS: [HvPciDevConfig; 2] = [ - pci_dev!(0x0, 0x0, 0x0, 0x0, VpciDevType::Physical), - pci_dev!(0x0, 0x0, 0x1, 0x0, VpciDevType::Physical), + pci_dev!(0x0, 0x0, 0x0, 0x0 => 0x0, 0x0, 0x0, VpciDevType::Physical), + pci_dev!(0x0, 0x0, 0x1, 0x0 => 0x0, 0x1, 0x0, VpciDevType::Physical), ]; diff --git a/platform/aarch64/rk3588/cargo/features b/platform/aarch64/rk3588/cargo/features deleted file mode 100644 index afa594897..000000000 --- a/platform/aarch64/rk3588/cargo/features +++ /dev/null @@ -1,2 +0,0 @@ -gicv3 -uart_16550 diff --git a/platform/aarch64/rk3588/configs/zone1-linux.json b/platform/aarch64/rk3588/configs/zone1-linux.json index e579f678e..72057fada 100644 --- a/platform/aarch64/rk3588/configs/zone1-linux.json +++ b/platform/aarch64/rk3588/configs/zone1-linux.json @@ -45,6 +45,6 @@ "gicr_size": "0x100000", "gits_base": "0x0", "gits_size": "0x0" - } + }, + "pci_config": [] } - diff --git a/platform/aarch64/rk3588/kconfig/defconfig b/platform/aarch64/rk3588/kconfig/defconfig new file mode 100644 index 000000000..242faa328 --- /dev/null +++ b/platform/aarch64/rk3588/kconfig/defconfig @@ -0,0 +1,3 @@ +CONFIG_ARCH_AARCH64=y +CONFIG_IRQ_GICV3=y +CONFIG_UART_16550=y diff --git a/platform/aarch64/sysoul_x3300-scmi/README.md b/platform/aarch64/sysoul_x3300-scmi/README.md new file mode 100644 index 000000000..925ef6efd --- /dev/null +++ b/platform/aarch64/sysoul_x3300-scmi/README.md @@ -0,0 +1,102 @@ +# sysoul_x3300-scmi — RK3588 Linux Multi-Zone (NPU + GPU + VOP/HDMI) + +## Overview + +The `sysoul_x3300-scmi` platform is the **Linux / VirtIO-SCMI variant** of +the `sysoul_x3300` platform (the original Android configuration stays in +`platform/aarch64/sysoul_x3300`). It targets the same **Rockchip RK3588** +SoC board with a multi-zone Linux deployment: + +- **Zone 0 (root)**: runs the root Linux, the `hvisor.ko` driver and + `hvisor-tool`, which provide the VirtIO-SCMI back-end, virtio console, + block and network devices for the non-root zones. +- **Zone 1**: dedicated to the **NPU** (Cortex-A76 cores 6, 7). +- **Zone 2**: dedicated to the **GPU + VOP + HDMI display** (cores 4, 5). + +## Zone Layout + +| Zone | CPUs | Devices | SCMI resources | +|------|------|---------|----------------| +| **Zone 1 (npu)** | 6, 7 | RKNPU, virtio-blk/net/console | clocks 0-7, resets 0-5, power 0-2 | +| **Zone 2 (gpu)** | 4, 5 | Mali GPU, VOP2, HDMI0, HD-PHY, VOP IOMMU | clocks 8-11, power 3 | + +## Configurations (`configs/`) + +| File | Purpose | +|------|---------| +| `zones-npu-gpu-virtio.json` | Launch Zone 1 (NPU) and Zone 2 (GPU) simultaneously | +| `zone1-linux-npu.json` | NPU zone (Zone 1) | +| `zone2-linux-gpu-hdmi.json` | GPU + VOP + HDMI display zone (Zone 2, 2 GB RAM) | + +## Device Trees (`image/dts/`) + +| File | Purpose | +|------|---------| +| `sysoul_iron.dts` | Board-level device tree (used by u-boot and the root zone) | +| `zone0.dts` | Root zone; declares the `hvisor_virtio_device` node listing the SCMI-exposed clocks/resets/power domains | +| `zone1-linux-npu.dts` | NPU zone: NPU + reserved DMA pool | +| `zone2-linux-gpu-hdmi.dts` | GPU + display zone: GPU, VOP2, HDMI0, hdmiphy, VOP IOMMU | + +## Zone 1: NPU Passthrough + +| Resource | Details | +|----------|---------| +| MMIO | `0xfdab0000` + `0xfdac0000` + `0xfdad0000` (3 × 64 KB) | +| IRQs (INTID) | 0x8e, 0x8f, 0x90 | +| SCMI | clocks 0-7, resets 0-5, power domains 0-2 | +| DMA | Reserved memory pool at `0x38000000` (64 MB, shared-dma-pool, no-IOMMU mode) | + +The NPU uses a `shared-dma-pool` reserved region instead of the +`rockchip,iommu-v2` IOMMU. + +## Zone 2: GPU + VOP + HDMI Passthrough + +| Resource | Details | +|----------|---------| +| GPU MMIO | `0xfb000000` (2 MB), GPU GRF `0xfd5a0000`, PVTM `0xfdb30000` | +| GPU IRQs (INTID) | JOB=0x7e, MMU=0x7d, GPU=0x7c | +| GPU SCMI | clocks 8-11, power domain 3 | +| RAM | 2 GB at `0x58000000` – `0xd8000000` (IOVAs == PAs via `dma-ranges`) | +| VOP2 | `0xfdd90000`, VOP IOMMU `0xfdd97e00` (passthrough, translated) | +| HDMI | HDMI0 TX `0xfde80000`, HD-PHY `0xfed60000`, plus sys/ioc GRF | + +The display pipeline (VOP2 + HDMI0 + hdptx-phy) is fully passed through and +**translated by the VOP IOMMU**, with the display clocks (including +`hdmi0_phy_pll`) delivered through VirtIO-SCMI. The zone2 DTS keeps +`hdmiphy0` disabled on the root side so the clock is not touched by zone0. + +### Display notes (verified on hardware) + +- The vop2 `plane-mask` of the display zone is `0x3cf` (all 12 windows + assigned to VP0). u-boot leaves stale VOP windows enabled (e.g. Esmart1/3 + pointing at its logo buffer); the vop2 driver only disables windows that + belong to the driven VP's plane mask, and only when the mode changes. + Assigning every window to VP0 lets any mode switch disable all of them, + otherwise stale windows keep faulting through the IOMMU and the screen + stays green. +- Do **not** set `iommu.passthrough=1` for this zone: the VOP IOMMU must + translate the front buffers, and passthrough leaves the iommu group + domain in a state that breaks re-attach after a mode switch. +- glmark2 runs fullscreen at 4K60 directly after boot (no pre-mode-switch + needed): `glmark2-es2-drm`. + +## Build & Deploy + +```bash +make all BID=aarch64/sysoul_x3300-scmi +``` + +Compile the device trees with `dtc` (see `image/dts/Makefile`), then boot +via u-boot: load `hvisor.bin` with `bootm`, which starts the root zone; +the zones are launched by `hvisor-tool` on the root zone using the JSON +configs above (adjust `kernel_filepath` / `dtb_filepath` to the deployed +file names). + +## Verification + +- **Zone 1 (NPU)**: check `rknpu` probe in the zone kernel and run an NPU + workload (e.g. rknn-toolkit-lite). +- **Zone 2 (GPU/display)**: `glmark2-es2-drm` should report 4K60 FPS with + no `Page fault` / `POST_BUF_EMPTY` in dmesg; `modetest -M rockchip -s + @:` mode switches should complete without + `-EBUSY` or `rk_iommu_force_reset` timeouts. diff --git a/platform/aarch64/sysoul_x3300-scmi/board.rs b/platform/aarch64/sysoul_x3300-scmi/board.rs new file mode 100644 index 000000000..cb75bec37 --- /dev/null +++ b/platform/aarch64/sysoul_x3300-scmi/board.rs @@ -0,0 +1,503 @@ +// Copyright (c) 2025 Syswonder +// hvisor is licensed under Mulan PSL v2. +// You can use this software according to the terms and conditions of the Mulan PSL v2. +// You may obtain a copy of Mulan PSL v2 at: +// http://license.coscl.org.cn/MulanPSL2 +// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR +// FIT FOR A PARTICULAR PURPOSE. +// See the Mulan PSL v2 for more details. +// +// Syswonder Website: +// https://www.syswonder.org +// +// Authors: +// + +use crate::pci_dev; +use crate::{ + arch::{ + mmu::MemoryType, + zone::{GicConfig, Gicv3Config, HvArchZoneConfig, UefiConfig}, + }, + config::*, + pci::vpci_dev::VpciDevType, +}; + +pub const BOARD_NAME: &str = "sysoul-x3300"; + +pub const BOARD_NCPUS: usize = 8; +pub const BOARD_UART_BASE: u64 = 0xfeb5_0000; + +#[rustfmt::skip] +pub static BOARD_MPIDR_MAPPINGS: [u64; BOARD_NCPUS] = [ + 0x000, // cpu0 + 0x100, // cpu1 + 0x200, // cpu2 + 0x300, // cpu3 + 0x400, // cpu4 + 0x500, // cpu5 + 0x600, // cpu6 + 0x700, // cpu7 +]; + +/// Early boot cache invalidate mask (per CPU): bit0->L1(D), bit1->L2, bit2->L3. +pub static BOARD_EARLY_CACHE_INVALIDATE_MASKS: [u64; BOARD_NCPUS] = [0b111; BOARD_NCPUS]; + +/// The physical memory layout of the board. +/// Each address should align to 2M (0x20_0000). +/// Addresses must be in ascending order. +#[rustfmt::skip] +pub const BOARD_PHYSMEM_LIST: &[(u64, u64, MemoryType)] = &[ + // ( start, end, type) + ( 0x0000_0000, 0x0020_0000, MemoryType::Device), // Includes low-address SRAM, marked as Device + ( 0x0020_0000, 0x0840_0000, MemoryType::Normal), + ( 0x0940_0000, 0xf000_0000, MemoryType::Normal), + ( 0xf000_0000, 0x1_0000_0000, MemoryType::Device), // Dense device region, marked as Device. + (0x1_0000_0000, 0x3_fc00_0000, MemoryType::Normal), + // (0x3_fc50_0000, 0x3_fff0_0000, MemoryType::Normal), + (0x3_fc40_0000, 0x4_0000_0000, MemoryType::Normal), // aligned to 2 MiB + (0x4_f000_0000, 0x5_0000_0000, MemoryType::Normal), +]; + +pub const ROOT_ZONE_DTB_ADDR: u64 = 0x2000_0000; +pub const ROOT_ZONE_KERNEL_ADDR: u64 = 0x2040_0000; +pub const ROOT_ZONE_ENTRY: u64 = 0x2040_0000; +pub const ROOT_ZONE_CPUS: u64 = (1 << 2) - 1; + +pub const ROOT_ZONE_NAME: &str = "root-linux"; + +pub const IRQ_WAKEUP_VIRTIO_DEVICE: usize = 32 + 0x20; +pub const ROOT_ZONE_MEMORY_REGIONS: &[HvConfigMemoryRegion] = &[ + // /proc/iomem System RAM + HvConfigMemoryRegion { + mem_type: MEM_TYPE_RAM, + physical_start: 0x0020_0000, + virtual_start: 0x0020_0000, + size: 0x0820_0000, + }, + // HvConfigMemoryRegion { + // mem_type: MEM_TYPE_RAM, + // physical_start: 0x0940_0000, + // virtual_start: 0x0940_0000, + // size: 0xe6c0_0000, + // }, + HvConfigMemoryRegion { + mem_type: MEM_TYPE_RAM, + physical_start: 0x0940_0000, + virtual_start: 0x0940_0000, + size: 0x06c0_0000, + }, + HvConfigMemoryRegion { + mem_type: MEM_TYPE_RAM, + physical_start: 0x1000_0000, + virtual_start: 0x1000_0000, + size: 0x1000_0000, + }, + HvConfigMemoryRegion { + mem_type: MEM_TYPE_RAM, + physical_start: 0x2000_0000, + virtual_start: 0x2000_0000, + size: 0x2000_0000, + }, // zone0 kernel/dtb area + // Zone1 RAM: 0x3000_0000 - 0x4000_0000 (assigned to zone1) + HvConfigMemoryRegion { + mem_type: MEM_TYPE_RAM, + physical_start: 0x4000_0000, + virtual_start: 0x4000_0000, + size: 0xb000_0000, + }, + // Zone1 RAM (large block) + Zone0 RAM + HvConfigMemoryRegion { + mem_type: MEM_TYPE_RAM, + physical_start: 0x1_0000_0000, + virtual_start: 0x1_0000_0000, + size: 0x2_fc00_0000, + }, + HvConfigMemoryRegion { + mem_type: MEM_TYPE_RAM, + physical_start: 0x3_fc50_0000, + virtual_start: 0x3_fc50_0000, + size: 0x03a0_0000, + }, + HvConfigMemoryRegion { + mem_type: MEM_TYPE_RAM, + physical_start: 0x4_f000_0000, + virtual_start: 0x4_f000_0000, + size: 0x1000_0000, + }, + // Ramoops + HvConfigMemoryRegion { + mem_type: MEM_TYPE_RAM, + physical_start: 0x0011_0000, + virtual_start: 0x0011_0000, + size: 0x000f_0000, + }, + // /proc/iomem Devices I/O + // GPU region (0xfb00_0000-0xfb20_0000) moved to zone1 + // HvConfigMemoryRegion { + // mem_type: MEM_TYPE_IO, + // physical_start: 0xfb00_0000, + // virtual_start: 0xfb00_0000, + // size: 0x0020_0000, + // }, + HvConfigMemoryRegion { + mem_type: MEM_TYPE_IO, + physical_start: 0xfc00_0000, + virtual_start: 0xfc00_0000, + size: 0x15a_4000, // fc000000..fd5a4000 + }, + // VOP-GRF: keep in root zone for DDR MCU access + HvConfigMemoryRegion { + mem_type: MEM_TYPE_IO, + physical_start: 0xfd5a_4000, + virtual_start: 0xfd5a_4000, + size: 0x2000, // fd5a4000..fd5a6000 + }, + HvConfigMemoryRegion { + mem_type: MEM_TYPE_IO, + physical_start: 0xfd5a_6000, + virtual_start: 0xfd5a_6000, + size: 0x7ea_000, // fd5a6000..fdd90000 + }, + // VOP: keep in root zone for DDR MCU line-flag synchronization + HvConfigMemoryRegion { + mem_type: MEM_TYPE_IO, + physical_start: 0xfdd9_0000, + virtual_start: 0xfdd9_0000, + size: 0x8000, // fdd90000..fdd98000 + }, + HvConfigMemoryRegion { + mem_type: MEM_TYPE_IO, + physical_start: 0xfdd9_8000, + virtual_start: 0xfdd9_8000, + size: 0x26_8000, // fdd98000..fe000000 + }, + HvConfigMemoryRegion { + mem_type: MEM_TYPE_IO, + physical_start: 0xfe00_0000, + virtual_start: 0xfe00_0000, + size: 0x0060_0000, + }, + HvConfigMemoryRegion { + mem_type: MEM_TYPE_IO, + physical_start: 0xfea0_0000, + virtual_start: 0xfea0_0000, + size: 0x0050_0000, + }, + // SRAM and Other Devices + HvConfigMemoryRegion { + mem_type: MEM_TYPE_IO, + physical_start: 0x0010_f000, + virtual_start: 0x0010_f000, + // size: 0x0100, // 10f000.sram + size: 0x1000, // aligned with page size + }, + HvConfigMemoryRegion { + mem_type: MEM_TYPE_IO, + physical_start: 0xff00_1000, + virtual_start: 0xff00_1000, + size: 0x000e_e000, //ff001000.sram + }, + // Unknown Region, maybe we should ask vendor for help + HvConfigMemoryRegion { + mem_type: MEM_TYPE_IO, + physical_start: 0x0010_0000, + virtual_start: 0x0010_0000, + size: 0xf000, + }, + // Unknown Region, maybe we should ask vendor for help + HvConfigMemoryRegion { + mem_type: MEM_TYPE_IO, + physical_start: 0xa_0000_0000, + virtual_start: 0xa_0000_0000, + size: 0x1_0000_0000, + }, +]; + +pub const ROOT_ZONE_IRQS_BITMAP: &[BitmapWord] = &get_irqs_bitmap(&[ + 0x27, // arm-pmu + 0x69, // dmc + 0x2d, // timer + 0x2e, // timer + 0x2b, // timer + 0x2a, // timer + // GPU IRQs moved to zone1: + // 0x7e, // gpu@fb000000 + // 0x7d, // gpu@fb000000 + // 0x7c, // gpu@fb000000 + 0xfc, // usb@fc000000 + 0xf7, // usb@fc800000 + 0xf8, // usb@fc840000 + 0xfa, // usb@fc880000 + 0xfb, // usb@fc8c0000 + 0x191, // iommu@fc900000 + 0x193, // iommu@fc900000 + 0x196, // iommu@fc900000 + 0x18f, // iommu@fc900000 + 0x19d, // iommu@fcb00000 + 0x19f, // iommu@fcb00000 + 0x1a2, // iommu@fcb00000 + 0x19b, // iommu@fcb00000 + 0xfe, // usb@fcd00000 + 0x1a9, // usb2-phy@0 + 0x1a7, // usb2-phy@8000 + 0x1a8, // usb2-phy@c000 + 0x15d, // i2c@fd880000 + 0x16b, // serial@fd890000 + 0x178, // pwm@fd8b0000 + 0x178, // pwm@fd8b0010 + 0x178, // pwm@fd8b0020 + 0x178, // pwm@fd8b0030 + 0x179, // pwm@fd8b0030 + // NPU IRQs moved to zone1: + // 0x8e, // npu@fdab0000 + // 0x8f, // npu@fdab0000 + // 0x90, // npu@fdab0000 + // 0x8e, // iommu@fdab9000 + // 0x8f, // iommu@fdab9000 + // 0x90, // iommu@fdab9000 + 0x98, // vepu@fdb50000 + 0x97, // vdpu@fdb50400 + 0x96, // iommu@fdb50800 + 0x97, // avsd-plus@fdb51000 + 0x92, // rga@fdb60000 + 0x92, // iommu@fdb60f00 + 0x93, // rga@fdb70000 + 0x93, // iommu@fdb70f00 + 0x94, // rga@fdb80000 + 0xa1, // jpegd@fdb90000 + 0xa2, // iommu@fdb90480 + 0x9a, // jpege-core@fdba0000 + 0x99, // iommu@fdba0800 + 0x9c, // jpege-core@fdba4000 + 0x9b, // iommu@fdba4800 + 0x9e, // jpege-core@fdba8000 + 0x9d, // iommu@fdba8800 + 0xa0, // jpege-core@fdbac000 + 0x9f, // iommu@fdbac800 + 0x95, // iep@fdbb0000 + 0x95, // iommu@fdbb0800 + 0x85, // rkvenc-core@fdbd0000 + 0x83, // iommu@fdbdf000 + 0x84, // iommu@fdbdf000 + 0x88, // rkvenc-core@fdbe0000 + 0x86, // iommu@fdbef000 + 0x87, // iommu@fdbef000 + 0x7f, // rkvdec-core@fdc38000 + 0x80, // iommu@fdc38700 + 0x81, // rkvdec-core@fdc48000 + 0x82, // iommu@fdc48700 + 0x8c, // av1d@fdc70000 + 0x8b, // av1d@fdc70000 + 0x8a, // av1d@fdc70000 + 0x8d, // iommu@fdca0000 + 0xa7, // rkisp-unite@fdcb0000 + 0xa9, // rkisp-unite@fdcb0000 + 0xaa, // rkisp-unite@fdcb0000 + 0xa3, // rkisp@fdcb0000 + 0xa5, // rkisp@fdcb0000 + 0xa6, // rkisp@fdcb0000 + 0xa4, // rkisp-unite-mmu@fdcb7f00 + 0xa8, // rkisp-unite-mmu@fdcb7f00 + 0xa4, // iommu@fdcb7f00 + 0xa7, // rkisp@fdcc0000 + 0xa9, // rkisp@fdcc0000 + 0xaa, // rkisp@fdcc0000 + 0xa8, // iommu@fdcc7f00 + 0xab, // rkispp@fdcd0000 + 0xac, // iommu@fdcd0f00 + 0xad, // rkispp@fdcd8000 + 0xae, // iommu@fdcd8f00 + 0xbb, // rkcif@fdce0000 + 0x91, // iommu@fdce0800 + 0xaf, // mipi0-csi2@fdd10000 + 0xb0, // mipi0-csi2@fdd10000 + 0xb1, // mipi1-csi2@fdd20000 + 0xb2, // mipi1-csi2@fdd20000 + 0xb3, // mipi2-csi2@fdd30000 + 0xb4, // mipi2-csi2@fdd30000 + 0xb5, // mipi3-csi2@fdd40000 + 0xb6, // mipi3-csi2@fdd40000 + // 0xbc, // vop@fdd90000 — moved to zone1 + // 0xbc, // iommu@fdd97e00 — moved to zone1 + 0xe3, // spdif-tx@fddb0000 + 0xd8, // i2s@fddc0000 + 0xe4, // spdif-tx@fdde0000 + 0xd9, // i2s@fddf0000 + 0xdd, // i2s@fddfc000 + 0xe7, // spdif-rx@fde08000 + 0xc7, // dsi@fde20000 + 0xc8, // dsi@fde30000 + 0xbf, // hdcp@fde40000 + 0xc1, // dp@fde50000 + 0xc0, // hdcp@fde70000 + // 0xc9, // hdmi@fde80000 — moved to zone1 + // 0xca, // hdmi@fde80000 — moved to zone1 + // 0xcb, // hdmi@fde80000 — moved to zone1 + // 0xcc, // hdmi@fde80000 — moved to zone1 + // 0x188, // hdmi@fde80000 — moved to zone1 + 0xc3, // edp@fdec0000 + 0x118, // pcie@fe180000 + 0x117, // pcie@fe180000 + 0x116, // pcie@fe180000 + 0x115, // pcie@fe180000 + 0x114, // pcie@fe180000 + 0x115, // legacy-interrupt-controller + 0x11d, // pcie@fe190000 + 0x11c, // pcie@fe190000 + 0x11b, // pcie@fe190000 + 0x11a, // pcie@fe190000 + 0x119, // pcie@fe190000 + 0x11a, // legacy-interrupt-controller + 0x10a, // ethernet@fe1c0000 + 0x109, // ethernet@fe1c0000 + 0x131, // sata@fe210000 + 0x133, // sata@fe230000 + 0xee, // spi@fe2b0000 + 0xeb, // mmc@fe2c0000 + 0xec, // mmc@fe2d0000 + 0xed, // mmc@fe2e0000 + 0xf1, // crypto@fe370000 + 0x1b0, // rng@fe378000 + 0xd4, // i2s@fe470000 + 0xd5, // i2s@fe480000 + 0xd6, // i2s@fe490000 + 0xd7, // i2s@fe4a0000 + 0xea, // vad@fe4d0000 + 0xe1, // spdif-tx@fe4e0000 + 0xe2, // spdif-tx@fe4f0000 + 0x29, // interrupt-controller@fe600000 + 0x76, // dma-controller@fea10000 + 0x77, // dma-controller@fea10000 + 0x78, // dma-controller@fea30000 + 0x79, // dma-controller@fea30000 + 0x175, // can@fea50000 + 0x176, // can@fea60000 + 0x177, // can@fea70000 + 0x75, // decompress@fea80000 + 0x15e, // i2c@fea90000 + 0x15f, // i2c@feaa0000 + 0x160, // i2c@feab0000 + 0x161, // i2c@feac0000 + 0x162, // i2c@fead0000 + 0x141, // timer@feae0000 + 0x15b, // watchdog@feaf0000 + 0x166, // spi@feb00000 + 0x167, // spi@feb10000 + 0x168, // spi@feb20000 + 0x169, // spi@feb30000 + 0x16c, // serial@feb40000 + 0x16d, // serial@feb50000 + 0x16e, // serial@feb60000 + 0x16f, // serial@feb70000 + 0x170, // serial@feb80000 + 0x171, // serial@feb90000 + 0x172, // serial@feba0000 + 0x173, // serial@febb0000 + 0x174, // serial@febc0000 + 0x17a, // pwm@febd0000 + 0x17a, // pwm@febd0010 + 0x17a, // pwm@febd0020 + 0x17a, // pwm@febd0030 + 0x17b, // pwm@febd0030 + 0x17c, // pwm@febe0000 + 0x17c, // pwm@febe0010 + 0x17c, // pwm@febe0020 + 0x17c, // pwm@febe0030 + 0x17d, // pwm@febe0030 + 0x17e, // pwm@febf0000 + 0x17e, // pwm@febf0010 + 0x17e, // pwm@febf0020 + 0x17e, // pwm@febf0030 + 0x17f, // pwm@febf0030 + 0x1ad, // tsadc@fec00000 + 0x1ae, // saradc@fec10000 + 0x5d, // mailbox@fec60000 + 0x5e, // mailbox@fec60000 + 0x5f, // mailbox@fec60000 + 0x60, // mailbox@fec60000 + 0x65, // mailbox@fec70000 + 0x66, // mailbox@fec70000 + 0x67, // mailbox@fec70000 + 0x68, // mailbox@fec70000 + 0x163, // i2c@fec80000 + 0x164, // i2c@fec90000 + 0x165, // i2c@feca0000 + 0x16a, // spi@fecb0000 + 0x6d, // mailbox@fece0000 + 0x6e, // mailbox@fece0000 + 0x6f, // mailbox@fece0000 + 0x70, // mailbox@fece0000 + 0x7a, // dma-controller@fed10000 + 0x7b, // dma-controller@fed10000 + 0x135, // gpio@fd8a0000 + 0x136, // gpio@fec20000 + 0x137, // gpio@fec30000 + 0x138, // gpio@fec40000 + 0x139, // gpio@fec50000 + 0xfd, // usb@fc400000 + 0x1aa, // usb2-phy@4000 + 0xb7, // mipi4-csi2@fdd50000 + 0xb8, // mipi4-csi2@fdd50000 + 0xb9, // mipi5-csi2@fdd60000 + 0xba, // mipi5-csi2@fdd60000 + 0xe6, // spdif-tx@fddb8000 + 0xdc, // i2s@fddc8000 + 0xe5, // spdif-tx@fdde8000 + 0xda, // i2s@fddf4000 + 0xdb, // i2s@fddf8000 + 0xde, // i2s@fde00000 + 0xe8, // spdif-rx@fde10000 + 0xe9, // spdif-rx@fde18000 + 0xc2, // dp@fde60000 + // 0xcd, // hdmi@fdea0000 — moved to zone1 + // 0xce, // hdmi@fdea0000 — moved to zone1 + // 0xcf, // hdmi@fdea0000 — moved to zone1 + // 0xd0, // hdmi@fdea0000 — moved to zone1 + // 0x189, // hdmi@fdea0000 — moved to zone1 + 0xc4, // edp@fded0000 + 0xd1, // hdmirx-controller@fdee0000 + 0x1d4, // hdmirx-controller@fdee0000 + 0xd3, // hdmirx-controller@fdee0000 + 0x127, // pcie@fe150000 + 0x126, // pcie@fe150000 + 0x125, // pcie@fe150000 + 0x124, // pcie@fe150000 + 0x123, // pcie@fe150000 + 0x124, // legacy-interrupt-controller + 0x122, // pcie@fe160000 + 0x121, // pcie@fe160000 + 0x120, // pcie@fe160000 + 0x11f, // pcie@fe160000 + 0x11e, // pcie@fe160000 + 0x11f, // legacy-interrupt-controller + 0x113, // pcie@fe170000 + 0x112, // pcie@fe170000 + 0x111, // pcie@fe170000 + 0x110, // pcie@fe170000 + 0x10f, // pcie@fe170000 + 0x110, // legacy-interrupt-controller + 0x103, // ethernet@fe1b0000 + 0x102, // ethernet@fe1b0000 + 0x132, // sata@fe220000 + 0x1c7, // fiq-debugger + 0x40, // hvisor_virtio_device +]); + +pub const ROOT_ARCH_ZONE_CONFIG: HvArchZoneConfig = HvArchZoneConfig { + is_aarch32: 0, + uefi_config: UefiConfig::NoUefi, + gic_config: GicConfig::Gicv3(Gicv3Config { + gicd_base: 0xfe60_0000, + gicd_size: 0x0001_0000, + gicr_base: 0xfe68_0000, + gicr_size: 0x0010_0000, + gits_base: 0x0, + gits_size: 0x0, + }), +}; + +pub const ROOT_ZONE_IVC_CONFIG: [HvIvcConfig; 0] = []; + +pub const ROOT_PCI_DEVS: [HvPciDevConfig; 0] = []; diff --git a/platform/aarch64/sysoul_x3300-scmi/cargo/config.template.toml b/platform/aarch64/sysoul_x3300-scmi/cargo/config.template.toml new file mode 100644 index 000000000..85e2f56c7 --- /dev/null +++ b/platform/aarch64/sysoul_x3300-scmi/cargo/config.template.toml @@ -0,0 +1,7 @@ +[target.aarch64-unknown-none] +runner = "platform/__ARCH__/__BOARD__/test/runner.sh" +rustflags = [ + "-Clink-arg=-Tplatform/__ARCH__/__BOARD__/linker.ld", + "-Ctarget-feature=+a72,+v8a,+strict-align,-neon,-fp-armv8", + "-Cforce-frame-pointers=yes", +] \ No newline at end of file diff --git a/platform/aarch64/sysoul_x3300-scmi/configs/zone1-linux-npu.json b/platform/aarch64/sysoul_x3300-scmi/configs/zone1-linux-npu.json new file mode 100644 index 000000000..0bdd11420 --- /dev/null +++ b/platform/aarch64/sysoul_x3300-scmi/configs/zone1-linux-npu.json @@ -0,0 +1,104 @@ +{ + "arch": "arm64", + "name": "zone1-npu", + "zone_id": 1, + "cpus": [ + 6, + 7 + ], + "memory_regions": [ + { + "type": "io", + "physical_start": "0x00100000", + "virtual_start": "0x00100000", + "size": "0xf000" + }, + { + "type": "ram", + "physical_start": "0x30000000", + "virtual_start": "0x30000000", + "size": "0x10000000" + }, + { + "type": "ram", + "physical_start": "0x100000000", + "virtual_start": "0x100000000", + "size": "0x1fc000000" + }, + { + "type": "virtio", + "physical_start": "0xff9c0000", + "virtual_start": "0xff9c0000", + "size": "0x1000" + }, + { + "type": "virtio", + "physical_start": "0xff9d0000", + "virtual_start": "0xff9d0000", + "size": "0x1000" + }, + { + "type": "virtio", + "physical_start": "0xff9e0000", + "virtual_start": "0xff9e0000", + "size": "0x1000" + }, + { + "type": "virtio", + "physical_start": "0xffa00000", + "virtual_start": "0xffa00000", + "size": "0x1000" + }, + { + "type": "io", + "physical_start": "0xfdab0000", + "virtual_start": "0xfdab0000", + "size": "0x10000" + }, + { + "type": "io", + "physical_start": "0xfdac0000", + "virtual_start": "0xfdac0000", + "size": "0x10000" + }, + { + "type": "io", + "physical_start": "0xfdad0000", + "virtual_start": "0xfdad0000", + "size": "0x10000" + }, + { + "type": "io", + "physical_start": "0xfd588000", + "virtual_start": "0xfd588000", + "size": "0x1000" + } + ], + "interrupts": [ + "0x44", + "0x41", + "0x42", + "0x43", + "0x45", + "0x8e", + "0x8f", + "0x90" + ], + "ivc_configs": [], + "kernel_filepath": "./202605-Image", + "dtb_filepath": "./202608-sysoul_iron_zone1-linux-npu.dtb", + "kernel_load_paddr": "0x30400000", + "dtb_load_paddr": "0x30000000", + "entry_point": "0x30400000", + "kernel_args": "", + "arch_config": { + "gic_version": "v3", + "gicd_base": "0xfe600000", + "gicd_size": "0x10000", + "gicr_base": "0xfe680000", + "gicr_size": "0x100000", + "gits_base": "0x0", + "gits_size": "0x0" + }, + "pci_config": [] +} \ No newline at end of file diff --git a/platform/aarch64/sysoul_x3300-scmi/configs/zone2-linux-gpu-hdmi.json b/platform/aarch64/sysoul_x3300-scmi/configs/zone2-linux-gpu-hdmi.json new file mode 100644 index 000000000..015a354a9 --- /dev/null +++ b/platform/aarch64/sysoul_x3300-scmi/configs/zone2-linux-gpu-hdmi.json @@ -0,0 +1,151 @@ +{ + "arch": "arm64", + "name": "zone2-gpu-hdmi", + "zone_id": 2, + "cpus": [ + 4, + 5 + ], + "memory_regions": [ + { + "type": "io", + "physical_start": "0x00100000", + "virtual_start": "0x00100000", + "size": "0xf000" + }, + { + "type": "ram", + "physical_start": "0x58000000", + "virtual_start": "0x58000000", + "size": "0x80000000" + }, + { + "type": "io", + "physical_start": "0xfb000000", + "virtual_start": "0xfb000000", + "size": "0x200000" + }, + { + "type": "io", + "physical_start": "0xfd5a0000", + "virtual_start": "0xfd5a0000", + "size": "0x1000" + }, + { + "type": "io", + "physical_start": "0xfdb30000", + "virtual_start": "0xfdb30000", + "size": "0x1000" + }, + { + "type": "io", + "physical_start": "0xfdd90000", + "virtual_start": "0xfdd90000", + "size": "0x10000" + }, + { + "type": "io", + "physical_start": "0xfde80000", + "virtual_start": "0xfde80000", + "size": "0x20000" + }, + { + "type": "io", + "physical_start": "0xfed60000", + "virtual_start": "0xfed60000", + "size": "0x10000" + }, + { + "type": "io", + "physical_start": "0xfd5a8000", + "virtual_start": "0xfd5a8000", + "size": "0x1000" + }, + { + "type": "io", + "physical_start": "0xfd5a6000", + "virtual_start": "0xfd5a6000", + "size": "0x1000" + }, + { + "type": "io", + "physical_start": "0xfd5e0000", + "virtual_start": "0xfd5e0000", + "size": "0x1000" + }, + { + "type": "io", + "physical_start": "0xfd5f0000", + "virtual_start": "0xfd5f0000", + "size": "0x10000" + }, + { + "type": "io", + "physical_start": "0xfd58c000", + "virtual_start": "0xfd58c000", + "size": "0x1000" + }, + { + "type": "virtio", + "physical_start": "0xffa10000", + "virtual_start": "0xffa10000", + "size": "0x1000" + }, + { + "type": "virtio", + "physical_start": "0xffa20000", + "virtual_start": "0xffa20000", + "size": "0x1000" + }, + { + "type": "virtio", + "physical_start": "0xffa30000", + "virtual_start": "0xffa30000", + "size": "0x1000" + }, + { + "type": "virtio", + "physical_start": "0xffa50000", + "virtual_start": "0xffa50000", + "size": "0x1000" + }, + { + "type": "io", + "physical_start": "0xfd5a4000", + "virtual_start": "0xfd5a4000", + "size": "0x2000" + } + ], + "interrupts": [ + "0x66", + "0x67", + "0x68", + "0x69", + "0x7e", + "0x7d", + "0x7c", + "0xbc", + "0xc9", + "0xca", + "0xcb", + "0xcc", + "0x188" + ], + "ivc_configs": [], + "kernel_filepath": "./202605-Image", + "dtb_filepath": "./202608-sysoul_iron_zone2-linux-gpu-hdmi.dtb", + "kernel_load_paddr": "0x58400000", + "dtb_load_paddr": "0x58000000", + "entry_point": "0x58400000", + "kernel_args": "", + "arch_config": { + "gic_version": "v3", + "gicd_base": "0xfe600000", + "gicd_size": "0x10000", + "gicr_base": "0xfe680000", + "gicr_size": "0x100000", + "gits_base": "0x0", + "gits_size": "0x0" + }, + "pci_config": [] +} \ No newline at end of file diff --git a/platform/aarch64/sysoul_x3300-scmi/configs/zones-npu-gpu-virtio.json b/platform/aarch64/sysoul_x3300-scmi/configs/zones-npu-gpu-virtio.json new file mode 100644 index 000000000..cbb2102f3 --- /dev/null +++ b/platform/aarch64/sysoul_x3300-scmi/configs/zones-npu-gpu-virtio.json @@ -0,0 +1,180 @@ +{ + "zones": [ + { + "id": 1, + "memory_region": [ + { + "zone0_ipa": "0x30000000", + "zonex_ipa": "0x30000000", + "size": "0x10000000" + }, + { + "zone0_ipa": "0x100000000", + "zonex_ipa": "0x100000000", + "size": "0x1fc000000" + } + ], + "devices": [ + { + "type": "scmi", + "addr": "0xff9c0000", + "len": "0x200", + "irq": "0x44", + "status": "enable", + "clock_ids": [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7 + ], + "reset_ids": [ + 0, + 1, + 2, + 3, + 4, + 5 + ], + "power_ids": [ + 0, + 1, + 2 + ] + }, + { + "type": "blk", + "addr": "0xff9d0000", + "len": "0x200", + "irq": "0x41", + "img": "202605-rootfs.img", + "status": "enable" + }, + { + "type": "console", + "addr": "0xff9e0000", + "len": "0x200", + "irq": "0x42", + "status": "enable" + }, + { + "type": "net", + "addr": "0xffa00000", + "len": "0x200", + "irq": "0x45", + "tap": "tap0", + "mac": [ + "0x00", + "0x11", + "0x22", + "0x33", + "0x44", + "0x55" + ], + "status": "enable" + } + ] + }, + { + "id": 2, + "memory_region": [ + { + "zone0_ipa": "0x58000000", + "zonex_ipa": "0x58000000", + "size": "0x80000000" + } + ], + "devices": [ + { + "type": "scmi", + "addr": "0xffa10000", + "len": "0x200", + "irq": "0x66", + "status": "enable", + "clock_ids": [ + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29, + 35, + 36 + ], + "power_ids": [ + 3, + 4, + 5 + ], + "reset_ids": [ + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 16, + 17, + 18, + 19, + 20, + 21, + 22 + ] + }, + { + "type": "blk", + "addr": "0xffa20000", + "len": "0x200", + "irq": "0x67", + "img": "202605-rootfs-gpu.img", + "status": "enable" + }, + { + "type": "console", + "addr": "0xffa30000", + "len": "0x200", + "irq": "0x68", + "status": "enable" + }, + { + "type": "net", + "addr": "0xffa50000", + "len": "0x200", + "irq": "0x69", + "tap": "tap1", + "mac": [ + "0x00", + "0x11", + "0x22", + "0x33", + "0x44", + "0x66" + ], + "status": "enable" + } + ] + } + ] +} \ No newline at end of file diff --git a/platform/aarch64/sysoul_x3300-scmi/image/dts/Makefile b/platform/aarch64/sysoul_x3300-scmi/image/dts/Makefile new file mode 100644 index 000000000..2f795e7fe --- /dev/null +++ b/platform/aarch64/sysoul_x3300-scmi/image/dts/Makefile @@ -0,0 +1,8 @@ +DTS_FILES := $(wildcard *.dts) +DTB_FILES := $(DTS_FILES:.dts=.dtb) + +all: $(DTB_FILES) +%.dtb: %.dts + dtc -I dts -O dtb $< -o $@ +clean: + rm -f $(DTB_FILES) \ No newline at end of file diff --git a/platform/aarch64/sysoul_x3300-scmi/image/dts/sysoul_iron.dts b/platform/aarch64/sysoul_x3300-scmi/image/dts/sysoul_iron.dts new file mode 100644 index 000000000..367728f2d --- /dev/null +++ b/platform/aarch64/sysoul_x3300-scmi/image/dts/sysoul_iron.dts @@ -0,0 +1,6128 @@ +/dts-v1/; + +/ { + serial-number = "c377a354961ceca2"; + compatible = "rockchip,xiuos_rk3588\0rockchip,rk3588"; + interrupt-parent = <0x1>; + #address-cells = <0x2>; + #size-cells = <0x2>; + model = "Rockchip RK3588 XIUOS Board"; + + memory { + reg = <0x0 0x200000 0x0 0x8200000 0x0 0x9400000 0x0 0xe6c00000 0x1 0x0 0x2 0xfc000000 0x3 0xfc500000 0x0 0x3a00000 0x4 0xf0000000 0x0 0x10000000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; + device_type = "memory"; + }; + + aliases { + csi2dcphy0 = "/csi2-dcphy0"; + csi2dcphy1 = "/csi2-dcphy1"; + csi2dphy0 = "/csi2-dphy0"; + csi2dphy1 = "/csi2-dphy1"; + csi2dphy2 = "/csi2-dphy2"; + dsi0 = "/dsi@fde20000"; + dsi1 = "/dsi@fde30000"; + ethernet1 = "/ethernet@fe1c0000"; + gpio0 = "/pinctrl/gpio@fd8a0000"; + gpio1 = "/pinctrl/gpio@fec20000"; + gpio2 = "/pinctrl/gpio@fec30000"; + gpio3 = "/pinctrl/gpio@fec40000"; + gpio4 = "/pinctrl/gpio@fec50000"; + i2c0 = "/i2c@fd880000"; + i2c1 = "/i2c@fea90000"; + i2c2 = "/i2c@feaa0000"; + i2c3 = "/i2c@feab0000"; + i2c4 = "/i2c@feac0000"; + i2c5 = "/i2c@fead0000"; + i2c6 = "/i2c@fec80000"; + i2c7 = "/i2c@fec90000"; + i2c8 = "/i2c@feca0000"; + rkcif_mipi_lvds0 = "/rkcif-mipi-lvds"; + rkcif_mipi_lvds1 = "/rkcif-mipi-lvds1"; + rkcif_mipi_lvds2 = "/rkcif-mipi-lvds2"; + rkcif_mipi_lvds3 = "/rkcif-mipi-lvds3"; + rkvdec0 = "/rkvdec-core@fdc38000"; + rkvdec1 = "/rkvdec-core@fdc48000"; + rkvenc0 = "/rkvenc-core@fdbd0000"; + rkvenc1 = "/rkvenc-core@fdbe0000"; + jpege0 = "/jpege-core@fdba0000"; + jpege1 = "/jpege-core@fdba4000"; + jpege2 = "/jpege-core@fdba8000"; + jpege3 = "/jpege-core@fdbac000"; + serial0 = "/serial@fd890000"; + serial1 = "/serial@feb40000"; + serial2 = "/serial@feb50000"; + serial3 = "/serial@feb60000"; + serial4 = "/serial@feb70000"; + serial5 = "/serial@feb80000"; + serial6 = "/serial@feb90000"; + serial7 = "/serial@feba0000"; + serial8 = "/serial@febb0000"; + serial9 = "/serial@febc0000"; + spi0 = "/spi@feb00000"; + spi1 = "/spi@feb10000"; + spi2 = "/spi@feb20000"; + spi3 = "/spi@feb30000"; + spi4 = "/spi@fecb0000"; + spi5 = "/spi@fe2b0000"; + hdcp0 = "/hdcp@fde40000"; + hdcp1 = "/hdcp@fde70000"; + csi2dphy3 = "/csi2-dphy3"; + csi2dphy4 = "/csi2-dphy4"; + csi2dphy5 = "/csi2-dphy5"; + dp0 = "/dp@fde50000"; + dp1 = "/dp@fde60000"; + edp0 = "/edp@fdec0000"; + edp1 = "/edp@fded0000"; + ethernet0 = "/ethernet@fe1b0000"; + hdptx0 = "/phy@fed60000"; + hdptx1 = "/phy@fed70000"; + hdptxhdmi0 = "/hdmiphy@fed60000"; + hdptxhdmi1 = "/hdmiphy@fed70000"; + hdmi0 = "/hdmi@fde80000"; + hdmi1 = "/hdmi@fdea0000"; + hdmirx0 = "/hdmirx-controller@fdee0000"; + rkcif_mipi_lvds4 = "/rkcif-mipi-lvds4"; + rkcif_mipi_lvds5 = "/rkcif-mipi-lvds5"; + usbdp0 = "/phy@fed80000"; + usbdp1 = "/phy@fed90000"; + mmc0 = "/mmc@fe2e0000"; + mmc1 = "/mmc@fe2c0000"; + mmc2 = "/mmc@fe2d0000"; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <0x2>; + #size-cells = <0x2>; + ranges; + + spll { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <0x29d7ab80>; + clock-output-names = "spll"; + }; + + xin32k { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <0x8000>; + clock-output-names = "xin32k"; + }; + + xin24m { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <0x16e3600>; + clock-output-names = "xin24m"; + }; + + hclk_vo1@fd7c08ec { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x0 0xfd7c08ec 0x0 0x10>; + clock-names = "link"; + clocks = <0x2 0x264>; + #power-domain-cells = <0x1>; + #clock-cells = <0x0>; + phandle = <0x5>; + }; + + aclk_vdpu_low_pre@fd7c08b0 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x0 0xfd7c08b0 0x0 0x10>; + clock-names = "link"; + clocks = <0x2 0x1bc>; + #power-domain-cells = <0x1>; + #clock-cells = <0x0>; + }; + + hclk_vo0@fd7c08dc { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x0 0xfd7c08dc 0x0 0x10>; + clock-names = "link"; + clocks = <0x2 0x26d>; + #power-domain-cells = <0x1>; + #clock-cells = <0x0>; + phandle = <0x4>; + }; + + hclk_usb@fd7c08a8 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x0 0xfd7c08a8 0x0 0x10>; + clock-names = "link"; + clocks = <0x2 0x264>; + #power-domain-cells = <0x1>; + #clock-cells = <0x0>; + }; + + hclk_nvm@fd7c087c { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x0 0xfd7c087c 0x0 0x10>; + clock-names = "link"; + clocks = <0x2 0x141>; + #power-domain-cells = <0x1>; + #clock-cells = <0x0>; + phandle = <0x3>; + }; + + aclk_usb@fd7c08a8 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x0 0xfd7c08a8 0x0 0x10>; + clock-names = "link"; + clocks = <0x2 0x263>; + #power-domain-cells = <0x1>; + #clock-cells = <0x0>; + }; + + hclk_isp1_pre@fd7c0868 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x0 0xfd7c0868 0x0 0x10>; + clock-names = "link"; + clocks = <0x2 0x1e1>; + #power-domain-cells = <0x1>; + #clock-cells = <0x0>; + }; + + aclk_isp1_pre@fd7c0868 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x0 0xfd7c0868 0x0 0x10>; + clock-names = "link"; + clocks = <0x2 0x1e0>; + #power-domain-cells = <0x1>; + #clock-cells = <0x0>; + }; + + aclk_rkvdec0_pre@fd7c08a0 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x0 0xfd7c08a0 0x0 0x10>; + clock-names = "link"; + clocks = <0x2 0x1bc>; + #power-domain-cells = <0x1>; + #clock-cells = <0x0>; + }; + + hclk_rkvdec0_pre@fd7c08a0 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x0 0xfd7c08a0 0x0 0x10>; + clock-names = "link"; + clocks = <0x2 0x1be>; + #power-domain-cells = <0x1>; + #clock-cells = <0x0>; + }; + + aclk_rkvdec1_pre@fd7c08a4 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x0 0xfd7c08a4 0x0 0x10>; + clock-names = "link"; + clocks = <0x2 0x1bc>; + #power-domain-cells = <0x1>; + #clock-cells = <0x0>; + }; + + hclk_rkvdec1_pre@fd7c08a4 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x0 0xfd7c08a4 0x0 0x10>; + clock-names = "link"; + clocks = <0x2 0x1be>; + #power-domain-cells = <0x1>; + #clock-cells = <0x0>; + }; + + aclk_jpeg_decoder_pre@fd7c08b0 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x0 0xfd7c08b0 0x0 0x10>; + clock-names = "link"; + clocks = <0x2 0x1bc>; + #power-domain-cells = <0x1>; + #clock-cells = <0x0>; + }; + + aclk_rkvenc1_pre@fd7c08c0 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x0 0xfd7c08c0 0x0 0x10>; + clock-names = "link"; + clocks = <0x2 0x1c5>; + #power-domain-cells = <0x1>; + #clock-cells = <0x0>; + }; + + hclk_rkvenc1_pre@fd7c08c0 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x0 0xfd7c08c0 0x0 0x10>; + clock-names = "link"; + clocks = <0x2 0x1c4>; + #power-domain-cells = <0x1>; + #clock-cells = <0x0>; + }; + + aclk_hdcp0_pre@fd7c08dc { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x0 0xfd7c08dc 0x0 0x10>; + clock-names = "link"; + clocks = <0x2 0x26c>; + #power-domain-cells = <0x1>; + #clock-cells = <0x0>; + }; + + aclk_hdcp1_pre@fd7c08ec { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x0 0xfd7c08ec 0x0 0x10>; + clock-names = "link"; + clocks = <0x2 0x263>; + #power-domain-cells = <0x1>; + #clock-cells = <0x0>; + }; + + pclk_av1_pre@fd7c0910 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x0 0xfd7c0910 0x0 0x10>; + clock-names = "link"; + clocks = <0x2 0x1be>; + #power-domain-cells = <0x1>; + #clock-cells = <0x0>; + }; + + aclk_av1_pre@fd7c0910 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x0 0xfd7c0910 0x0 0x10>; + clock-names = "link"; + clocks = <0x2 0x1bc>; + #power-domain-cells = <0x1>; + #clock-cells = <0x0>; + }; + + hclk_sdio_pre@fd7c092c { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x0 0xfd7c092c 0x0 0x10>; + clock-names = "link"; + clocks = <0x3>; + #power-domain-cells = <0x1>; + #clock-cells = <0x0>; + }; + + pclk_vo0_grf@fd7c08dc { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x0 0xfd7c08dc 0x0 0x4>; + clocks = <0x4>; + clock-names = "link"; + #clock-cells = <0x0>; + phandle = <0x5f>; + }; + + pclk_vo1_grf@fd7c08ec { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x0 0xfd7c08ec 0x0 0x4>; + clocks = <0x5>; + clock-names = "link"; + #clock-cells = <0x0>; + phandle = <0x60>; + }; + + mclkin-i2s0 { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <0x0>; + clock-output-names = "i2s0_mclkin"; + }; + + mclkin-i2s1 { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <0x0>; + clock-output-names = "i2s1_mclkin"; + }; + + mclkin-i2s2 { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <0x0>; + clock-output-names = "i2s2_mclkin"; + }; + + mclkin-i2s3 { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <0x0>; + clock-output-names = "i2s3_mclkin"; + }; + + mclkout-i2s0@fd58c318 { + compatible = "rockchip,clk-out"; + reg = <0x0 0xfd58c318 0x0 0x4>; + clocks = <0x2 0x39>; + #clock-cells = <0x0>; + clock-output-names = "i2s0_mclkout_to_io"; + rockchip,bit-shift = <0x0>; + rockchip,bit-set-to-disable; + phandle = <0x139>; + }; + + mclkout-i2s1@fd58c318 { + compatible = "rockchip,clk-out"; + reg = <0x0 0xfd58c318 0x0 0x4>; + clocks = <0x2 0x291>; + #clock-cells = <0x0>; + clock-output-names = "i2s1_mclkout_to_io"; + rockchip,bit-shift = <0x1>; + rockchip,bit-set-to-disable; + }; + + mclkout-i2s2@fd58c318 { + compatible = "rockchip,clk-out"; + reg = <0x0 0xfd58c318 0x0 0x4>; + clocks = <0x2 0x28>; + #clock-cells = <0x0>; + clock-output-names = "i2s2_mclkout_to_io"; + rockchip,bit-shift = <0x2>; + rockchip,bit-set-to-disable; + }; + + mclkout-i2s3@fd58c318 { + compatible = "rockchip,clk-out"; + reg = <0x0 0xfd58c318 0x0 0x4>; + clocks = <0x2 0x2e>; + #clock-cells = <0x0>; + clock-output-names = "i2s3_mclkout_to_io"; + rockchip,bit-shift = <0x7>; + rockchip,bit-set-to-disable; + }; + }; + + cpus { + #address-cells = <0x1>; + #size-cells = <0x0>; + + cpu-map { + cluster0 { + core0 { + cpu = <0x6>; + }; + + core1 { + cpu = <0x7>; + }; + + core2 { + cpu = <0x8>; + }; + + core3 { + cpu = <0x9>; + }; + }; + + cluster1 { + core0 { + cpu = <0xa>; + }; + + core1 { + cpu = <0xb>; + }; + }; + + cluster2 { + core0 { + cpu = <0xc>; + }; + + core1 { + cpu = <0xd>; + }; + }; + }; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0>; + enable-method = "psci"; + capacity-dmips-mhz = <0x212>; + clocks = <0xe 0x0>; + operating-points-v2 = <0xf>; + cpu-idle-states = <0x10>; + i-cache-size = <0x8000>; + i-cache-line-size = <0x40>; + i-cache-sets = <0x80>; + d-cache-size = <0x8000>; + d-cache-line-size = <0x40>; + d-cache-sets = <0x80>; + next-level-cache = <0x11>; + #cooling-cells = <0x2>; + dynamic-power-coefficient = <0x64>; + cpu-supply = <0x12>; + mem-supply = <0x12>; + phandle = <0x6>; + }; + + cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x100>; + enable-method = "psci"; + capacity-dmips-mhz = <0x212>; + clocks = <0xe 0x0>; + operating-points-v2 = <0xf>; + cpu-idle-states = <0x10>; + i-cache-size = <0x8000>; + i-cache-line-size = <0x40>; + i-cache-sets = <0x80>; + d-cache-size = <0x8000>; + d-cache-line-size = <0x40>; + d-cache-sets = <0x80>; + next-level-cache = <0x13>; + phandle = <0x7>; + }; + + cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x200>; + enable-method = "psci"; + capacity-dmips-mhz = <0x212>; + clocks = <0xe 0x0>; + operating-points-v2 = <0xf>; + cpu-idle-states = <0x10>; + i-cache-size = <0x8000>; + i-cache-line-size = <0x40>; + i-cache-sets = <0x80>; + d-cache-size = <0x8000>; + d-cache-line-size = <0x40>; + d-cache-sets = <0x80>; + next-level-cache = <0x14>; + phandle = <0x8>; + }; + + cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x300>; + enable-method = "psci"; + capacity-dmips-mhz = <0x212>; + clocks = <0xe 0x0>; + operating-points-v2 = <0xf>; + cpu-idle-states = <0x10>; + i-cache-size = <0x8000>; + i-cache-line-size = <0x40>; + i-cache-sets = <0x80>; + d-cache-size = <0x8000>; + d-cache-line-size = <0x40>; + d-cache-sets = <0x80>; + next-level-cache = <0x15>; + phandle = <0x9>; + }; + + cpu@400 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x400>; + enable-method = "psci"; + capacity-dmips-mhz = <0x400>; + clocks = <0xe 0x2>; + operating-points-v2 = <0x16>; + cpu-idle-states = <0x10>; + i-cache-size = <0x10000>; + i-cache-line-size = <0x40>; + i-cache-sets = <0x100>; + d-cache-size = <0x10000>; + d-cache-line-size = <0x40>; + d-cache-sets = <0x100>; + next-level-cache = <0x17>; + #cooling-cells = <0x2>; + dynamic-power-coefficient = <0x12c>; + cpu-supply = <0x18>; + mem-supply = <0x18>; + phandle = <0xa>; + }; + + cpu@500 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x500>; + enable-method = "psci"; + capacity-dmips-mhz = <0x400>; + clocks = <0xe 0x2>; + operating-points-v2 = <0x16>; + cpu-idle-states = <0x10>; + i-cache-size = <0x10000>; + i-cache-line-size = <0x40>; + i-cache-sets = <0x100>; + d-cache-size = <0x10000>; + d-cache-line-size = <0x40>; + d-cache-sets = <0x100>; + next-level-cache = <0x19>; + phandle = <0xb>; + }; + + cpu@600 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x600>; + enable-method = "psci"; + capacity-dmips-mhz = <0x400>; + clocks = <0xe 0x3>; + operating-points-v2 = <0x1a>; + cpu-idle-states = <0x10>; + i-cache-size = <0x10000>; + i-cache-line-size = <0x40>; + i-cache-sets = <0x100>; + d-cache-size = <0x10000>; + d-cache-line-size = <0x40>; + d-cache-sets = <0x100>; + next-level-cache = <0x1b>; + #cooling-cells = <0x2>; + dynamic-power-coefficient = <0x12c>; + cpu-supply = <0x1c>; + mem-supply = <0x1c>; + phandle = <0xc>; + }; + + cpu@700 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x700>; + enable-method = "psci"; + capacity-dmips-mhz = <0x400>; + clocks = <0xe 0x3>; + operating-points-v2 = <0x1a>; + cpu-idle-states = <0x10>; + i-cache-size = <0x10000>; + i-cache-line-size = <0x40>; + i-cache-sets = <0x100>; + d-cache-size = <0x10000>; + d-cache-line-size = <0x40>; + d-cache-sets = <0x100>; + next-level-cache = <0x1d>; + phandle = <0xd>; + }; + + idle-states { + entry-method = "psci"; + + cpu-sleep { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x10000>; + entry-latency-us = <0x64>; + exit-latency-us = <0x78>; + min-residency-us = <0x3e8>; + phandle = <0x10>; + }; + }; + + l2-cache-l0 { + compatible = "cache"; + cache-size = <0x20000>; + cache-line-size = <0x40>; + cache-sets = <0x200>; + next-level-cache = <0x1e>; + phandle = <0x11>; + }; + + l2-cache-l1 { + compatible = "cache"; + cache-size = <0x20000>; + cache-line-size = <0x40>; + cache-sets = <0x200>; + next-level-cache = <0x1e>; + phandle = <0x13>; + }; + + l2-cache-l2 { + compatible = "cache"; + cache-size = <0x20000>; + cache-line-size = <0x40>; + cache-sets = <0x200>; + next-level-cache = <0x1e>; + phandle = <0x14>; + }; + + l2-cache-l3 { + compatible = "cache"; + cache-size = <0x20000>; + cache-line-size = <0x40>; + cache-sets = <0x200>; + next-level-cache = <0x1e>; + phandle = <0x15>; + }; + + l2-cache-b0 { + compatible = "cache"; + cache-size = <0x80000>; + cache-line-size = <0x40>; + cache-sets = <0x400>; + next-level-cache = <0x1e>; + phandle = <0x17>; + }; + + l2-cache-b1 { + compatible = "cache"; + cache-size = <0x80000>; + cache-line-size = <0x40>; + cache-sets = <0x400>; + next-level-cache = <0x1e>; + phandle = <0x19>; + }; + + l2-cache-b2 { + compatible = "cache"; + cache-size = <0x80000>; + cache-line-size = <0x40>; + cache-sets = <0x400>; + next-level-cache = <0x1e>; + phandle = <0x1b>; + }; + + l2-cache-b3 { + compatible = "cache"; + cache-size = <0x80000>; + cache-line-size = <0x40>; + cache-sets = <0x400>; + next-level-cache = <0x1e>; + phandle = <0x1d>; + }; + + l3-cache { + compatible = "cache"; + cache-size = <0x300000>; + cache-line-size = <0x40>; + cache-sets = <0x1000>; + phandle = <0x1e>; + }; + }; + + cluster0-opp-table { + compatible = "operating-points-v2"; + opp-shared; + nvmem-cells = <0x1f 0x20>; + nvmem-cell-names = "leakage\0specification_serial_number"; + rockchip,supported-hw; + rockchip,opp-shared-dsu; + rockchip,pvtm-voltage-sel = <0x0 0x582 0x0 0x583 0x59a 0x1 0x59b 0x5b2 0x2 0x5b3 0x5ca 0x3 0x5cb 0x5e2 0x4 0x5e3 0x5fa 0x5 0x5fb 0x270f 0x6>; + rockchip,pvtm-pvtpll; + rockchip,pvtm-offset = <0x64>; + rockchip,pvtm-sample-time = <0x44c>; + rockchip,pvtm-freq = <0x159b40>; + rockchip,pvtm-volt = <0xb71b0>; + rockchip,pvtm-ref-temp = <0x19>; + rockchip,pvtm-temp-prop = <0xf4 0xf4>; + rockchip,pvtm-thermal-zone = "soc-thermal"; + rockchip,grf = <0x21>; + rockchip,dsu-grf = <0x22>; + volt-mem-read-margin = <0xd0bd8 0x1 0xbac48 0x2 0xa4cb8 0x3 0x78d98 0x4>; + low-volt-mem-read-margin = <0x4>; + intermediate-threshold-freq = <0xf6180>; + rockchip,reboot-freq = <0x159b40>; + rockchip,temp-hysteresis = <0x1388>; + rockchip,low-temp = <0x2710>; + rockchip,low-temp-min-volt = <0xb71b0>; + rockchip,high-temp = <0x14c08>; + rockchip,high-temp-max-freq = <0x188940>; + phandle = <0xf>; + + opp-408000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = <0x0 0x18519600>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-600000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = <0x0 0x23c34600>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-816000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = <0x0 0x30a32c00>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-1008000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = <0x0 0x3c14dc00>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-1200000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = <0x0 0x47868c00>; + opp-microvolt = <0xadf34 0xadf34 0xe7ef0 0xadf34 0xadf34 0xe7ef0>; + opp-microvolt-L1 = <0xaae60 0xaae60 0xe7ef0 0xaae60 0xaae60 0xe7ef0>; + opp-microvolt-L2 = <0xaae60 0xaae60 0xe7ef0 0xaae60 0xaae60 0xe7ef0>; + opp-microvolt-L3 = <0xa7d8c 0xa7d8c 0xe7ef0 0xa7d8c 0xa7d8c 0xe7ef0>; + opp-microvolt-L4 = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>; + opp-microvolt-L5 = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>; + opp-microvolt-L6 = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-1416000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = <0x0 0x54667200>; + opp-microvolt = <0xba284 0xba284 0xe7ef0 0xba284 0xba284 0xe7ef0>; + opp-microvolt-L1 = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>; + opp-microvolt-L2 = <0xb40dc 0xb40dc 0xe7ef0 0xb40dc 0xb40dc 0xe7ef0>; + opp-microvolt-L3 = <0xb1008 0xb1008 0xe7ef0 0xb1008 0xb1008 0xe7ef0>; + opp-microvolt-L4 = <0xb1008 0xb1008 0xe7ef0 0xb1008 0xb1008 0xe7ef0>; + opp-microvolt-L5 = <0xadf34 0xadf34 0xe7ef0 0xadf34 0xadf34 0xe7ef0>; + opp-microvolt-L6 = <0xadf34 0xadf34 0xe7ef0 0xadf34 0xadf34 0xe7ef0>; + clock-latency-ns = <0x9c40>; + opp-suspend; + }; + + opp-1608000000 { + opp-supported-hw = <0xfb 0xffff>; + opp-hz = <0x0 0x5fd82200>; + opp-microvolt = <0xcf850 0xcf850 0xe7ef0 0xcf850 0xcf850 0xe7ef0>; + opp-microvolt-L1 = <0xcc77c 0xcc77c 0xe7ef0 0xcc77c 0xcc77c 0xe7ef0>; + opp-microvolt-L2 = <0xc96a8 0xc96a8 0xe7ef0 0xc96a8 0xc96a8 0xe7ef0>; + opp-microvolt-L3 = <0xc65d4 0xc65d4 0xe7ef0 0xc65d4 0xc65d4 0xe7ef0>; + opp-microvolt-L4 = <0xc3500 0xc3500 0xe7ef0 0xc3500 0xc3500 0xe7ef0>; + opp-microvolt-L5 = <0xc3500 0xc3500 0xe7ef0 0xc3500 0xc3500 0xe7ef0>; + opp-microvolt-L6 = <0xc042c 0xc042c 0xe7ef0 0xc042c 0xc042c 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-1704000000 { + opp-supported-hw = <0x2 0xffff>; + opp-hz = <0x0 0x6590fa00>; + opp-microvolt = <0xdbba0 0xdbba0 0xe7ef0 0xdbba0 0xdbba0 0xe7ef0>; + opp-microvolt-L1 = <0xd8acc 0xd8acc 0xe7ef0 0xd8acc 0xd8acc 0xe7ef0>; + opp-microvolt-L2 = <0xd59f8 0xd59f8 0xe7ef0 0xd59f8 0xd59f8 0xe7ef0>; + opp-microvolt-L3 = <0xd2924 0xd2924 0xe7ef0 0xd2924 0xd2924 0xe7ef0>; + opp-microvolt-L4 = <0xcf850 0xcf850 0xe7ef0 0xcf850 0xcf850 0xe7ef0>; + opp-microvolt-L5 = <0xcc77c 0xcc77c 0xe7ef0 0xcc77c 0xcc77c 0xe7ef0>; + opp-microvolt-L6 = <0xc96a8 0xc96a8 0xe7ef0 0xc96a8 0xc96a8 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-1800000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = <0x0 0x6b49d200>; + opp-microvolt = <0xe7ef0 0xe7ef0 0xe7ef0 0xe7ef0 0xe7ef0 0xe7ef0>; + opp-microvolt-L1 = <0xe4e1c 0xe4e1c 0xe7ef0 0xe4e1c 0xe4e1c 0xe7ef0>; + opp-microvolt-L2 = <0xe1d48 0xe1d48 0xe7ef0 0xe1d48 0xe1d48 0xe7ef0>; + opp-microvolt-L3 = <0xdec74 0xdec74 0xe7ef0 0xdec74 0xdec74 0xe7ef0>; + opp-microvolt-L4 = <0xdbba0 0xdbba0 0xe7ef0 0xdbba0 0xdbba0 0xe7ef0>; + opp-microvolt-L5 = <0xd8acc 0xd8acc 0xe7ef0 0xd8acc 0xd8acc 0xe7ef0>; + opp-microvolt-L6 = <0xd59f8 0xd59f8 0xe7ef0 0xd59f8 0xd59f8 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + }; + + cluster1-opp-table { + compatible = "operating-points-v2"; + opp-shared; + nvmem-cells = <0x23 0x20>; + nvmem-cell-names = "leakage\0specification_serial_number"; + rockchip,supported-hw; + rockchip,pvtm-voltage-sel = <0x0 0x63b 0x0 0x63c 0x64f 0x1 0x650 0x668 0x2 0x669 0x68b 0x3 0x68c 0x6ae 0x4 0x6af 0x6cf 0x5 0x6d0 0x6f0 0x6 0x6f1 0x270f 0x7>; + rockchip,pvtm-pvtpll; + rockchip,pvtm-offset = <0x18>; + rockchip,pvtm-sample-time = <0x44c>; + rockchip,pvtm-freq = <0x188940>; + rockchip,pvtm-volt = <0xb71b0>; + rockchip,pvtm-ref-temp = <0x19>; + rockchip,pvtm-temp-prop = <0x10e 0x10e>; + rockchip,pvtm-thermal-zone = "soc-thermal"; + rockchip,pvtm-low-len-sel = <0x3>; + rockchip,grf = <0x24>; + volt-mem-read-margin = <0xd0bd8 0x1 0xbac48 0x2 0xa4cb8 0x3 0x78d98 0x4>; + low-volt-mem-read-margin = <0x4>; + intermediate-threshold-freq = <0xf6180>; + rockchip,idle-threshold-freq = <0x21b100>; + rockchip,reboot-freq = <0x1b7740>; + rockchip,temp-hysteresis = <0x1388>; + rockchip,low-temp = <0x2710>; + rockchip,low-temp-min-volt = <0xb71b0>; + rockchip,high-temp = <0x14c08>; + rockchip,high-temp-max-freq = <0x21b100>; + phandle = <0x16>; + + opp-408000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = <0x0 0x18519600>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>; + clock-latency-ns = <0x9c40>; + opp-suspend; + }; + + opp-600000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = <0x0 0x23c34600>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-816000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = <0x0 0x30a32c00>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-1008000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = <0x0 0x3c14dc00>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-1200000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = <0x0 0x47868c00>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-1416000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = <0x0 0x54667200>; + opp-microvolt = <0xb1008 0xb1008 0xf4240 0xb1008 0xb1008 0xf4240>; + opp-microvolt-L2 = <0xadf34 0xadf34 0xf4240 0xadf34 0xadf34 0xf4240>; + opp-microvolt-L3 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>; + opp-microvolt-L4 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>; + opp-microvolt-L5 = <0xa7d8c 0xa7d8c 0xf4240 0xa7d8c 0xa7d8c 0xf4240>; + opp-microvolt-L6 = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>; + opp-microvolt-L7 = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-1608000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = <0x0 0x5fd82200>; + opp-microvolt = <0xba284 0xba284 0xf4240 0xba284 0xba284 0xf4240>; + opp-microvolt-L2 = <0xb71b0 0xb71b0 0xf4240 0xb71b0 0xb71b0 0xf4240>; + opp-microvolt-L3 = <0xb40dc 0xb40dc 0xf4240 0xb40dc 0xb40dc 0xf4240>; + opp-microvolt-L4 = <0xb1008 0xb1008 0xf4240 0xb1008 0xb1008 0xf4240>; + opp-microvolt-L5 = <0xadf34 0xadf34 0xf4240 0xadf34 0xadf34 0xf4240>; + opp-microvolt-L6 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>; + opp-microvolt-L7 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-1800000000 { + opp-supported-hw = <0xfb 0xffff>; + opp-hz = <0x0 0x6b49d200>; + opp-microvolt = <0xcf850 0xcf850 0xf4240 0xcf850 0xcf850 0xf4240>; + opp-microvolt-L1 = <0xcc77c 0xcc77c 0xf4240 0xcc77c 0xcc77c 0xf4240>; + opp-microvolt-L2 = <0xc96a8 0xc96a8 0xf4240 0xc96a8 0xc96a8 0xf4240>; + opp-microvolt-L3 = <0xc65d4 0xc65d4 0xf4240 0xc65d4 0xc65d4 0xf4240>; + opp-microvolt-L4 = <0xc3500 0xc3500 0xf4240 0xc3500 0xc3500 0xf4240>; + opp-microvolt-L5 = <0xc042c 0xc042c 0xf4240 0xc042c 0xc042c 0xf4240>; + opp-microvolt-L6 = <0xbd358 0xbd358 0xf4240 0xbd358 0xbd358 0xf4240>; + opp-microvolt-L7 = <0xba284 0xba284 0xf4240 0xba284 0xba284 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-2016000000 { + opp-supported-hw = <0xfb 0xffff>; + opp-hz = <0x0 0x7829b800>; + opp-microvolt = <0xe1d48 0xe1d48 0xf4240 0xe1d48 0xe1d48 0xf4240>; + opp-microvolt-L1 = <0xdec74 0xdec74 0xf4240 0xdec74 0xdec74 0xf4240>; + opp-microvolt-L2 = <0xdbba0 0xdbba0 0xf4240 0xdbba0 0xdbba0 0xf4240>; + opp-microvolt-L3 = <0xd8acc 0xd8acc 0xf4240 0xd8acc 0xd8acc 0xf4240>; + opp-microvolt-L4 = <0xd59f8 0xd59f8 0xf4240 0xd59f8 0xd59f8 0xf4240>; + opp-microvolt-L5 = <0xd2924 0xd2924 0xf4240 0xd2924 0xd2924 0xf4240>; + opp-microvolt-L6 = <0xcf850 0xcf850 0xf4240 0xcf850 0xcf850 0xf4240>; + opp-microvolt-L7 = <0xcc77c 0xcc77c 0xf4240 0xcc77c 0xcc77c 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-2208000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = <0x0 0x839b6800>; + opp-microvolt = <0xf116c 0xf116c 0xf4240 0xf116c 0xf116c 0xf4240>; + opp-microvolt-L1 = <0xee098 0xee098 0xf4240 0xee098 0xee098 0xf4240>; + opp-microvolt-L2 = <0xeafc4 0xeafc4 0xf4240 0xeafc4 0xeafc4 0xf4240>; + opp-microvolt-L3 = <0xe7ef0 0xe7ef0 0xf4240 0xe7ef0 0xe7ef0 0xf4240>; + opp-microvolt-L4 = <0xeafc4 0xeafc4 0xf4240 0xeafc4 0xeafc4 0xf4240>; + opp-microvolt-L5 = <0xe7ef0 0xe7ef0 0xf4240 0xe7ef0 0xe7ef0 0xf4240>; + opp-microvolt-L6 = <0xe1d48 0xe1d48 0xf4240 0xe1d48 0xe1d48 0xf4240>; + opp-microvolt-L7 = <0xdec74 0xdec74 0xf4240 0xdec74 0xdec74 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-2256000000 { + opp-supported-hw = <0xf9 0x13>; + opp-hz = <0x0 0x8677d400>; + opp-microvolt = <0xf4240 0xf4240 0xf4240 0xf4240 0xf4240 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-2304000000 { + opp-supported-hw = <0xf9 0x24>; + opp-hz = <0x0 0x89544000>; + opp-microvolt = <0xf4240 0xf4240 0xf4240 0xf4240 0xf4240 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-2352000000 { + opp-supported-hw = <0xf9 0x48>; + opp-hz = <0x0 0x8c30ac00>; + opp-microvolt = <0xf4240 0xf4240 0xf4240 0xf4240 0xf4240 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-2400000000 { + opp-supported-hw = <0xf9 0x80>; + opp-hz = <0x0 0x8f0d1800>; + opp-microvolt = <0xf4240 0xf4240 0xf4240 0xf4240 0xf4240 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + }; + + cluster2-opp-table { + compatible = "operating-points-v2"; + opp-shared; + nvmem-cells = <0x25 0x20>; + nvmem-cell-names = "leakage\0specification_serial_number"; + rockchip,supported-hw; + rockchip,pvtm-voltage-sel = <0x0 0x63b 0x0 0x63c 0x64f 0x1 0x650 0x668 0x2 0x669 0x68b 0x3 0x68c 0x6ae 0x4 0x6af 0x6cf 0x5 0x6d0 0x6f0 0x6 0x6f1 0x270f 0x7>; + rockchip,pvtm-pvtpll; + rockchip,pvtm-offset = <0x18>; + rockchip,pvtm-sample-time = <0x44c>; + rockchip,pvtm-freq = <0x188940>; + rockchip,pvtm-volt = <0xb71b0>; + rockchip,pvtm-ref-temp = <0x19>; + rockchip,pvtm-temp-prop = <0x10e 0x10e>; + rockchip,pvtm-thermal-zone = "soc-thermal"; + rockchip,pvtm-low-len-sel = <0x3>; + rockchip,grf = <0x26>; + volt-mem-read-margin = <0xd0bd8 0x1 0xbac48 0x2 0xa4cb8 0x3 0x78d98 0x4>; + low-volt-mem-read-margin = <0x4>; + intermediate-threshold-freq = <0xf6180>; + rockchip,idle-threshold-freq = <0x21b100>; + rockchip,reboot-freq = <0x1b7740>; + rockchip,temp-hysteresis = <0x1388>; + rockchip,low-temp = <0x2710>; + rockchip,low-temp-min-volt = <0xb71b0>; + rockchip,high-temp = <0x14c08>; + rockchip,high-temp-max-freq = <0x21b100>; + phandle = <0x1a>; + + opp-408000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = <0x0 0x18519600>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>; + clock-latency-ns = <0x9c40>; + opp-suspend; + }; + + opp-600000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = <0x0 0x23c34600>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-816000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = <0x0 0x30a32c00>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-1008000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = <0x0 0x3c14dc00>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-1200000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = <0x0 0x47868c00>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-1416000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = <0x0 0x54667200>; + opp-microvolt = <0xb1008 0xb1008 0xf4240 0xb1008 0xb1008 0xf4240>; + opp-microvolt-L2 = <0xadf34 0xadf34 0xf4240 0xadf34 0xadf34 0xf4240>; + opp-microvolt-L3 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>; + opp-microvolt-L4 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>; + opp-microvolt-L5 = <0xa7d8c 0xa7d8c 0xf4240 0xa7d8c 0xa7d8c 0xf4240>; + opp-microvolt-L6 = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>; + opp-microvolt-L7 = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-1608000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = <0x0 0x5fd82200>; + opp-microvolt = <0xba284 0xba284 0xf4240 0xba284 0xba284 0xf4240>; + opp-microvolt-L2 = <0xb71b0 0xb71b0 0xf4240 0xb71b0 0xb71b0 0xf4240>; + opp-microvolt-L3 = <0xb40dc 0xb40dc 0xf4240 0xb40dc 0xb40dc 0xf4240>; + opp-microvolt-L4 = <0xb1008 0xb1008 0xf4240 0xb1008 0xb1008 0xf4240>; + opp-microvolt-L5 = <0xadf34 0xadf34 0xf4240 0xadf34 0xadf34 0xf4240>; + opp-microvolt-L6 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>; + opp-microvolt-L7 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-1800000000 { + opp-supported-hw = <0xfb 0xffff>; + opp-hz = <0x0 0x6b49d200>; + opp-microvolt = <0xcf850 0xcf850 0xf4240 0xcf850 0xcf850 0xf4240>; + opp-microvolt-L1 = <0xcc77c 0xcc77c 0xf4240 0xcc77c 0xcc77c 0xf4240>; + opp-microvolt-L2 = <0xc96a8 0xc96a8 0xf4240 0xc96a8 0xc96a8 0xf4240>; + opp-microvolt-L3 = <0xc65d4 0xc65d4 0xf4240 0xc65d4 0xc65d4 0xf4240>; + opp-microvolt-L4 = <0xc3500 0xc3500 0xf4240 0xc3500 0xc3500 0xf4240>; + opp-microvolt-L5 = <0xc042c 0xc042c 0xf4240 0xc042c 0xc042c 0xf4240>; + opp-microvolt-L6 = <0xbd358 0xbd358 0xf4240 0xbd358 0xbd358 0xf4240>; + opp-microvolt-L7 = <0xba284 0xba284 0xf4240 0xba284 0xba284 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-2016000000 { + opp-supported-hw = <0xfb 0xffff>; + opp-hz = <0x0 0x7829b800>; + opp-microvolt = <0xe1d48 0xe1d48 0xf4240 0xe1d48 0xe1d48 0xf4240>; + opp-microvolt-L1 = <0xdec74 0xdec74 0xf4240 0xdec74 0xdec74 0xf4240>; + opp-microvolt-L2 = <0xdbba0 0xdbba0 0xf4240 0xdbba0 0xdbba0 0xf4240>; + opp-microvolt-L3 = <0xd8acc 0xd8acc 0xf4240 0xd8acc 0xd8acc 0xf4240>; + opp-microvolt-L4 = <0xd59f8 0xd59f8 0xf4240 0xd59f8 0xd59f8 0xf4240>; + opp-microvolt-L5 = <0xd2924 0xd2924 0xf4240 0xd2924 0xd2924 0xf4240>; + opp-microvolt-L6 = <0xcf850 0xcf850 0xf4240 0xcf850 0xcf850 0xf4240>; + opp-microvolt-L7 = <0xcc77c 0xcc77c 0xf4240 0xcc77c 0xcc77c 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-2208000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = <0x0 0x839b6800>; + opp-microvolt = <0xf116c 0xf116c 0xf4240 0xf116c 0xf116c 0xf4240>; + opp-microvolt-L3 = <0xee098 0xee098 0xf4240 0xee098 0xee098 0xf4240>; + opp-microvolt-L4 = <0xeafc4 0xeafc4 0xf4240 0xeafc4 0xeafc4 0xf4240>; + opp-microvolt-L5 = <0xe7ef0 0xe7ef0 0xf4240 0xe7ef0 0xe7ef0 0xf4240>; + opp-microvolt-L6 = <0xe1d48 0xe1d48 0xf4240 0xe1d48 0xe1d48 0xf4240>; + opp-microvolt-L7 = <0xdec74 0xdec74 0xf4240 0xdec74 0xdec74 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-2256000000 { + opp-supported-hw = <0xf9 0x13>; + opp-hz = <0x0 0x8677d400>; + opp-microvolt = <0xf4240 0xf4240 0xf4240 0xf4240 0xf4240 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-2304000000 { + opp-supported-hw = <0xf9 0x24>; + opp-hz = <0x0 0x89544000>; + opp-microvolt = <0xf4240 0xf4240 0xf4240 0xf4240 0xf4240 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-2352000000 { + opp-supported-hw = <0xf9 0x48>; + opp-hz = <0x0 0x8c30ac00>; + opp-microvolt = <0xf4240 0xf4240 0xf4240 0xf4240 0xf4240 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-2400000000 { + opp-supported-hw = <0xf9 0x80>; + opp-hz = <0x0 0x8f0d1800>; + opp-microvolt = <0xf4240 0xf4240 0xf4240 0xf4240 0xf4240 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + }; + + arm-pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <0x1 0x7 0x8>; + interrupt-affinity = <0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd>; + }; + + cpuinfo { + compatible = "rockchip,cpuinfo"; + nvmem-cells = <0x27 0x28 0x29>; + nvmem-cell-names = "id\0cpu-version\0cpu-code"; + }; + + csi2-dphy0 { + compatible = "rockchip,rk3568-csi2-dphy"; + rockchip,hw = <0x2c>; + status = "okay"; + + ports { + #address-cells = <0x1>; + #size-cells = <0x0>; + + port@0 { + reg = <0x0>; + #address-cells = <0x1>; + #size-cells = <0x0>; + + endpoint@1 { + reg = <0x1>; + remote-endpoint = <0x2d>; + data-lanes = <0x1 0x2 0x3 0x4>; + phandle = <0x13f>; + }; + }; + + port@1 { + reg = <0x1>; + #address-cells = <0x1>; + #size-cells = <0x0>; + + endpoint@0 { + reg = <0x0>; + remote-endpoint = <0x2e>; + phandle = <0xbd>; + }; + }; + }; + }; + + display-subsystem { + compatible = "rockchip,display-subsystem"; + ports = <0x2f>; + memory-region = <0x30>; + memory-region-names = "drm-logo"; + + route { + route-dsi0 { + overscan,bottom_margin = <0x64>; + overscan,top_margin = <0x64>; + overscan,right_margin = <0x64>; + overscan,left_margin = <0x64>; + video,aspect_ratio = <0x0>; + video,flags = <0xa>; + video,vrefresh = <0x4b>; + video,crtc_vsync_end = <0x265>; + video,crtc_hsync_end = <0x4aa>; + video,vdisplay = <0x258>; + video,hdisplay = <0x400>; + video,clock = <0xfde8>; + logo,ymirror = <0x0>; + logo,bpp = <0x10>; + logo,height = <0x10e>; + logo,width = <0x28e>; + logo,offset = <0x61000>; + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <0x32>; + }; + + route-hdmi0 { + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <0x35>; + }; + }; + }; + + dmc { + compatible = "rockchip,rk3588-dmc"; + interrupts = <0x0 0x49 0x4>; + interrupt-names = "complete"; + devfreq-events = <0x39>; + clocks = <0xe 0x4>; + clock-names = "dmc_clk"; + operating-points-v2 = <0x3a>; + upthreshold = <0x28>; + downdifferential = <0x14>; + system-status-level = <0x1 0x4 0x8 0x8 0x2 0x1 0x10 0x4 0x10000 0x4 0x80000 0x4 0x1000 0x8 0x4000 0x8 0x2000 0x8 0xc00 0x8 0x40000 0x8>; + auto-freq-en = <0x1>; + status = "okay"; + center-supply = <0x3b>; + mem-supply = <0x3c>; + }; + + dmc-opp-table { + compatible = "operating-points-v2"; + nvmem-cells = <0x3d>; + nvmem-cell-names = "leakage"; + rockchip,leakage-voltage-sel = <0x1 0x1f 0x0 0x20 0x2c 0x1 0x2d 0x39 0x2 0x3a 0xfe 0x3>; + rockchip,temp-hysteresis = <0x1388>; + rockchip,low-temp = <0x2710>; + rockchip,low-temp-min-volt = <0xb71b0>; + phandle = <0x3a>; + + opp-528000000 { + opp-hz = <0x0 0x1f78a400>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xd59f8 0xb1008 0xb1008 0xb71b0>; + opp-microvolt-L1 = <0xa4cb8 0xa4cb8 0xd59f8 0xaae60 0xaae60 0xb71b0>; + opp-microvolt-L2 = <0xa4cb8 0xa4cb8 0xd59f8 0xa7d8c 0xa7d8c 0xb71b0>; + opp-microvolt-L3 = <0xa4cb8 0xa4cb8 0xd59f8 0xa4cb8 0xa4cb8 0xb71b0>; + }; + + opp-1068000000 { + opp-hz = <0x0 0x3fa86300>; + opp-microvolt = <0xb1008 0xb1008 0xd59f8 0xb40dc 0xb40dc 0xb71b0>; + opp-microvolt-L1 = <0xaae60 0xaae60 0xd59f8 0xadf34 0xadf34 0xb71b0>; + opp-microvolt-L2 = <0xa4cb8 0xa4cb8 0xd59f8 0xaae60 0xaae60 0xb71b0>; + opp-microvolt-L3 = <0xa4cb8 0xa4cb8 0xd59f8 0xa7d8c 0xa7d8c 0xb71b0>; + }; + + opp-1560000000 { + opp-hz = <0x0 0x5cfbb600>; + opp-microvolt = <0xc3500 0xc3500 0xd59f8 0xb71b0 0xb71b0 0xb71b0>; + opp-microvolt-L1 = <0xbd358 0xbd358 0xd59f8 0xb1008 0xb1008 0xb71b0>; + opp-microvolt-L2 = <0xb71b0 0xb71b0 0xd59f8 0xadf34 0xadf34 0xb71b0>; + opp-microvolt-L3 = <0xb1008 0xb1008 0xd59f8 0xaae60 0xaae60 0xb71b0>; + }; + + opp-2750000000 { + opp-hz = <0x0 0xa3e9ab80>; + opp-microvolt = <0xd59f8 0xd59f8 0xd59f8 0xb71b0 0xb71b0 0xb71b0>; + opp-microvolt-L1 = <0xcf850 0xcf850 0xd59f8 0xb71b0 0xb71b0 0xb71b0>; + opp-microvolt-L2 = <0xcc77c 0xcc77c 0xd59f8 0xb1008 0xb1008 0xb71b0>; + opp-microvolt-L3 = <0xc96a8 0xc8320 0xd59f8 0xaae60 0xaae60 0xb71b0>; + }; + }; + + firmware { + scmi { + compatible = "arm,scmi-smc"; + shmem = <0x3e>; + arm,smc-id = <0x82000010>; + #address-cells = <0x1>; + #size-cells = <0x0>; + + protocol@14 { + reg = <0x14>; + #clock-cells = <0x1>; + assigned-clocks = <0xe 0x0 0xe 0x2 0xe 0x3>; + assigned-clock-rates = <0x30a32c00 0x30a32c00 0x30a32c00>; + phandle = <0xe>; + }; + + protocol@16 { + reg = <0x16>; + #reset-cells = <0x1>; + phandle = <0x10d>; + }; + }; + + sdei { + compatible = "arm,sdei-1.0"; + method = "smc"; + }; + + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; + + jpege-ccu { + compatible = "rockchip,vpu-jpege-ccu"; + status = "okay"; + phandle = <0xa6>; + }; + + mpp-srv { + compatible = "rockchip,mpp-service"; + rockchip,taskqueue-count = <0xc>; + rockchip,resetgroup-count = <0x1>; + status = "okay"; + phandle = <0xa1>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + rkcif-mipi-lvds2 { + compatible = "rockchip,rkcif-mipi-lvds"; + rockchip,hw = <0x3f>; + iommus = <0x40>; + status = "okay"; + phandle = <0x45>; + + port { + endpoint { + remote-endpoint = <0x44>; + phandle = <0xbe>; + }; + }; + }; + + rkcif-mipi-lvds2-sditf { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <0x45>; + status = "okay"; + + port { + endpoint { + remote-endpoint = <0x46>; + phandle = <0x49>; + }; + }; + }; + + rkisp0-vir0 { + compatible = "rockchip,rkisp-vir"; + rockchip,hw = <0x48>; + status = "okay"; + + port { + #address-cells = <0x1>; + #size-cells = <0x0>; + + endpoint@0 { + reg = <0x0>; + remote-endpoint = <0x49>; + phandle = <0x46>; + }; + }; + }; + + rkvenc-ccu { + compatible = "rockchip,rkv-encoder-v2-ccu"; + status = "okay"; + phandle = <0xac>; + }; + + rockchip-suspend { + compatible = "rockchip,pm-rk3588"; + status = "okay"; + rockchip,sleep-debug-en = <0x1>; + rockchip,sleep-mode-config = <0x5000604>; + rockchip,wakeup-config = <0x100>; + }; + + rockchip-system-monitor { + compatible = "rockchip,system-monitor"; + rockchip,thermal-zone = "soc-thermal"; + }; + + thermal-zones { + soc-thermal { + polling-delay-passive = <0x14>; + polling-delay = <0x3e8>; + sustainable-power = <0x834>; + thermal-sensors = <0x4d 0x0>; + + trips { + trip-point-0 { + temperature = <0x124f8>; + hysteresis = <0x7d0>; + type = "passive"; + }; + + trip-point-1 { + temperature = <0x14c08>; + hysteresis = <0x7d0>; + type = "passive"; + phandle = <0x4e>; + }; + + soc-crit { + temperature = <0x1c138>; + hysteresis = <0x7d0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <0x4e>; + cooling-device = <0x6 0xffffffff 0xffffffff>; + contribution = <0x400>; + }; + + map1 { + trip = <0x4e>; + cooling-device = <0xa 0xffffffff 0xffffffff>; + contribution = <0x400>; + }; + + map2 { + trip = <0x4e>; + cooling-device = <0xc 0xffffffff 0xffffffff>; + contribution = <0x400>; + }; + + map3 { + trip = <0x4e>; + cooling-device = <0x4f 0xffffffff 0xffffffff>; + contribution = <0x400>; + }; + }; + }; + + bigcore0-thermal { + polling-delay-passive = <0x14>; + polling-delay = <0x3e8>; + thermal-sensors = <0x4d 0x1>; + }; + + bigcore1-thermal { + polling-delay-passive = <0x14>; + polling-delay = <0x3e8>; + thermal-sensors = <0x4d 0x2>; + }; + + littlecore-thermal { + polling-delay-passive = <0x14>; + polling-delay = <0x3e8>; + thermal-sensors = <0x4d 0x3>; + }; + + center-thermal { + polling-delay-passive = <0x14>; + polling-delay = <0x3e8>; + thermal-sensors = <0x4d 0x4>; + }; + + gpu-thermal { + polling-delay-passive = <0x14>; + polling-delay = <0x3e8>; + thermal-sensors = <0x4d 0x5>; + }; + + npu-thermal { + polling-delay-passive = <0x14>; + polling-delay = <0x3e8>; + thermal-sensors = <0x4d 0x6>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <0x1 0xd 0xf04 0x1 0xe 0xf04 0x1 0xb 0xf04 0x1 0xa 0xf04>; + }; + + sram@10f000 { + compatible = "mmio-sram"; + reg = <0x0 0x10f000 0x0 0x100>; + #address-cells = <0x1>; + #size-cells = <0x1>; + ranges = <0x0 0x0 0x10f000 0x100>; + + sram@0 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x100>; + phandle = <0x3e>; + }; + }; + + gpu@fb000000 { + compatible = "arm,mali-bifrost"; + reg = <0x0 0xfb000000 0x0 0x200000>; + interrupts = <0x0 0x5e 0x4 0x0 0x5d 0x4 0x0 0x5c 0x4>; + interrupt-names = "GPU\0MMU\0JOB"; + clocks = <0xe 0x5 0x2 0x115 0x2 0x116 0x2 0x114>; + clock-names = "clk_mali\0clk_gpu_coregroup\0clk_gpu_stacks\0clk_gpu"; + assigned-clocks = <0xe 0x5>; + assigned-clock-rates = <0xbebc200>; + power-domains = <0x50 0xc>; + operating-points-v2 = <0x51>; + #cooling-cells = <0x2>; + dynamic-power-coefficient = <0xba6>; + upthreshold = <0x1e>; + downdifferential = <0xa>; + status = "okay"; + mali-supply = <0x52>; + mem-supply = <0x52>; + phandle = <0x4f>; + }; + + gpu-opp-table { + compatible = "operating-points-v2"; + nvmem-cells = <0x53 0x20>; + nvmem-cell-names = "leakage\0specification_serial_number"; + rockchip,supported-hw; + rockchip,pvtm-voltage-sel = <0x0 0x32f 0x0 0x330 0x343 0x1 0x344 0x35c 0x2 0x35d 0x375 0x3 0x376 0x38e 0x4 0x38f 0x270f 0x5>; + rockchip,pvtm-pvtpll; + rockchip,pvtm-offset = <0x1c>; + rockchip,pvtm-sample-time = <0x44c>; + rockchip,pvtm-freq = <0xc3500>; + rockchip,pvtm-volt = <0xb71b0>; + rockchip,pvtm-ref-temp = <0x19>; + rockchip,pvtm-temp-prop = <0xffffff79 0xffffff79>; + rockchip,pvtm-thermal-zone = "gpu-thermal"; + clocks = <0x2 0x114>; + clock-names = "clk"; + rockchip,grf = <0x54>; + volt-mem-read-margin = <0xd0bd8 0x1 0xbac48 0x2 0xa4cb8 0x3 0x78d98 0x4>; + low-volt-mem-read-margin = <0x4>; + intermediate-threshold-freq = <0x61a80>; + rockchip,temp-hysteresis = <0x1388>; + rockchip,low-temp = <0x2710>; + rockchip,low-temp-min-volt = <0xb71b0>; + rockchip,high-temp = <0x14c08>; + rockchip,high-temp-max-freq = <0xc3500>; + phandle = <0x51>; + + opp-300000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = <0x0 0x11e1a300>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + }; + + opp-400000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = <0x0 0x17d78400>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + }; + + opp-500000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = <0x0 0x1dcd6500>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + }; + + opp-600000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = <0x0 0x23c34600>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + }; + + opp-700000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = <0x0 0x29b92700>; + opp-microvolt = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>; + opp-microvolt-L2 = <0xa7d8c 0xa7d8c 0xcf850 0xa7d8c 0xa7d8c 0xcf850>; + opp-microvolt-L3 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L4 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L5 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + }; + + opp-800000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = <0x0 0x2faf0800>; + opp-microvolt = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>; + opp-microvolt-L1 = <0xb40dc 0xb40dc 0xcf850 0xb40dc 0xb40dc 0xcf850>; + opp-microvolt-L2 = <0xb1008 0xb1008 0xcf850 0xb1008 0xb1008 0xcf850>; + opp-microvolt-L3 = <0xadf34 0xadf34 0xcf850 0xadf34 0xadf34 0xcf850>; + opp-microvolt-L4 = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>; + opp-microvolt-L5 = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>; + }; + + opp-900000000 { + opp-supported-hw = <0xfb 0xffff>; + opp-hz = <0x0 0x35a4e900>; + opp-microvolt = <0xc3500 0xc3500 0xcf850 0xc3500 0xc3500 0xcf850>; + opp-microvolt-L1 = <0xc042c 0xc042c 0xcf850 0xc042c 0xc042c 0xcf850>; + opp-microvolt-L2 = <0xbd358 0xbd358 0xcf850 0xbd358 0xbd358 0xcf850>; + opp-microvolt-L3 = <0xba284 0xba284 0xcf850 0xba284 0xba284 0xcf850>; + opp-microvolt-L4 = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>; + opp-microvolt-L5 = <0xb40dc 0xb40dc 0xcf850 0xb40dc 0xb40dc 0xcf850>; + }; + + opp-1000000000 { + opp-supported-hw = <0xfb 0xffff>; + opp-hz = <0x0 0x3b9aca00>; + opp-microvolt = <0xcf850 0xcf850 0xcf850 0xcf850 0xcf850 0xcf850>; + opp-microvolt-L1 = <0xcc77c 0xcc77c 0xcf850 0xcc77c 0xcc77c 0xcf850>; + opp-microvolt-L2 = <0xc96a8 0xc96a8 0xcf850 0xc96a8 0xc96a8 0xcf850>; + opp-microvolt-L3 = <0xc65d4 0xc65d4 0xcf850 0xc65d4 0xc65d4 0xcf850>; + opp-microvolt-L4 = <0xc3500 0xc3500 0xcf850 0xc3500 0xc3500 0xcf850>; + opp-microvolt-L5 = <0xc042c 0xc042c 0xcf850 0xc042c 0xc042c 0xcf850>; + }; + }; + + usbdrd3_0 { + compatible = "rockchip,rk3588-dwc3\0rockchip,rk3399-dwc3"; + clocks = <0x2 0x1a3 0x2 0x1a2 0x2 0x1a1>; + clock-names = "ref\0suspend\0bus"; + #address-cells = <0x2>; + #size-cells = <0x2>; + ranges; + status = "okay"; + + usb@fc000000 { + compatible = "snps,dwc3"; + reg = <0x0 0xfc000000 0x0 0x400000>; + interrupts = <0x0 0xdc 0x4>; + power-domains = <0x50 0x1f>; + resets = <0x2 0x2a4>; + reset-names = "usb3-otg"; + dr_mode = "otg"; + phys = <0x55 0x56>; + phy-names = "usb2-phy\0usb3-phy"; + phy_type = "utmi_wide"; + snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + snps,parkmode-disable-ss-quirk; + quirk-skip-phy-init; + status = "okay"; + }; + }; + + usb@fc800000 { + compatible = "rockchip,rk3588-ehci\0generic-ehci"; + reg = <0x0 0xfc800000 0x0 0x40000>; + interrupts = <0x0 0xd7 0x4>; + clocks = <0x2 0x19d 0x2 0x19e 0x57>; + clock-names = "usbhost\0arbiter\0utmi"; + companion = <0x58>; + phys = <0x59>; + phy-names = "usb2-phy"; + power-domains = <0x50 0x1f>; + status = "okay"; + }; + + usb@fc840000 { + compatible = "generic-ohci"; + reg = <0x0 0xfc840000 0x0 0x40000>; + interrupts = <0x0 0xd8 0x4>; + clocks = <0x2 0x19d 0x2 0x19e 0x57>; + clock-names = "usbhost\0arbiter\0utmi"; + phys = <0x59>; + phy-names = "usb2-phy"; + power-domains = <0x50 0x1f>; + status = "okay"; + phandle = <0x58>; + }; + + usb@fc880000 { + compatible = "rockchip,rk3588-ehci\0generic-ehci"; + reg = <0x0 0xfc880000 0x0 0x40000>; + interrupts = <0x0 0xda 0x4>; + clocks = <0x2 0x19f 0x2 0x1a0 0x5a>; + clock-names = "usbhost\0arbiter\0utmi"; + companion = <0x5b>; + phys = <0x5c>; + phy-names = "usb2-phy"; + power-domains = <0x50 0x1f>; + status = "okay"; + }; + + usb@fc8c0000 { + compatible = "generic-ohci"; + reg = <0x0 0xfc8c0000 0x0 0x40000>; + interrupts = <0x0 0xdb 0x4>; + clocks = <0x2 0x19f 0x2 0x1a0 0x5a>; + clock-names = "usbhost\0arbiter\0utmi"; + phys = <0x5c>; + phy-names = "usb2-phy"; + power-domains = <0x50 0x1f>; + status = "okay"; + phandle = <0x5b>; + }; + + usbhost3_0 { + compatible = "rockchip,rk3588-dwc3\0rockchip,rk3399-dwc3"; + clocks = <0x2 0x179 0x2 0x178 0x2 0x177 0x2 0x17a 0x2 0x166 0x2 0x181>; + clock-names = "ref\0suspend\0bus\0utmi\0php\0pipe"; + #address-cells = <0x2>; + #size-cells = <0x2>; + ranges; + status = "okay"; + + usb@fcd00000 { + compatible = "snps,dwc3"; + reg = <0x0 0xfcd00000 0x0 0x400000>; + interrupts = <0x0 0xde 0x4>; + resets = <0x2 0x237>; + reset-names = "usb3-host"; + dr_mode = "host"; + phys = <0x5d 0x4>; + phy-names = "usb3-phy"; + phy_type = "utmi_wide"; + snps,dis_enblslpm_quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + snps,dis_rxdet_inp3_quirk; + snps,parkmode-disable-ss-quirk; + status = "okay"; + }; + }; + + syscon@fd588000 { + compatible = "rockchip,rk3588-pmu0-grf\0syscon\0simple-mfd"; + reg = <0x0 0xfd588000 0x0 0x2000>; + + reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x80>; + mode-bootloader = <0x5242c301>; + mode-charge = <0x5242c30b>; + mode-fastboot = <0x5242c309>; + mode-loader = <0x5242c301>; + mode-normal = <0x5242c300>; + mode-recovery = <0x5242c303>; + mode-ums = <0x5242c30c>; + mode-panic = <0x5242c307>; + mode-watchdog = <0x5242c308>; + mode-quiescent = <0x5242c30e>; + }; + }; + + syscon@fd58a000 { + compatible = "rockchip,rk3588-pmu1-grf\0syscon"; + reg = <0x0 0xfd58a000 0x0 0x2000>; + phandle = <0xf7>; + }; + + syscon@fd58c000 { + compatible = "rockchip,rk3588-sys-grf\0syscon\0simple-mfd"; + reg = <0x0 0xfd58c000 0x0 0x1000>; + phandle = <0xb1>; + }; + + syscon@fd590000 { + compatible = "rockchip,rk3588-bigcore0-grf\0syscon"; + reg = <0x0 0xfd590000 0x0 0x100>; + phandle = <0x24>; + }; + + syscon@fd592000 { + compatible = "rockchip,rk3588-bigcore1-grf\0syscon"; + reg = <0x0 0xfd592000 0x0 0x100>; + phandle = <0x26>; + }; + + syscon@fd594000 { + compatible = "rockchip,rk3588-litcore-grf\0syscon"; + reg = <0x0 0xfd594000 0x0 0x100>; + phandle = <0x21>; + }; + + syscon@fd598000 { + compatible = "rockchip,rk3588-dsu-grf\0syscon"; + reg = <0x0 0xfd598000 0x0 0x100>; + phandle = <0x22>; + }; + + syscon@fd5a0000 { + compatible = "rockchip,rk3588-gpu-grf\0syscon"; + reg = <0x0 0xfd5a0000 0x0 0x100>; + phandle = <0x54>; + }; + + syscon@fd5a2000 { + compatible = "rockchip,rk3588-npu-grf\0syscon"; + reg = <0x0 0xfd5a2000 0x0 0x100>; + phandle = <0x9f>; + }; + + syscon@fd5a4000 { + compatible = "rockchip,rk3588-vop-grf\0syscon"; + reg = <0x0 0xfd5a4000 0x0 0x2000>; + phandle = <0xc0>; + }; + + syscon@fd5a6000 { + compatible = "rockchip,rk3588-vo-grf\0syscon"; + reg = <0x0 0xfd5a6000 0x0 0x2000>; + clocks = <0x5f>; + phandle = <0xe7>; + }; + + syscon@fd5a8000 { + compatible = "rockchip,rk3588-vo-grf\0syscon"; + reg = <0x0 0xfd5a8000 0x0 0x100>; + clocks = <0x60>; + phandle = <0xc1>; + }; + + syscon@fd5ac000 { + compatible = "rockchip,rk3588-usb-grf\0syscon"; + reg = <0x0 0xfd5ac000 0x0 0x4000>; + phandle = <0x61>; + }; + + syscon@fd5b0000 { + compatible = "rockchip,rk3588-php-grf\0syscon"; + reg = <0x0 0xfd5b0000 0x0 0x1000>; + phandle = <0x63>; + }; + + syscon@fd5b4000 { + compatible = "rockchip,mipi-dphy-grf\0syscon"; + reg = <0x0 0xfd5b4000 0x0 0x1000>; + phandle = <0x178>; + }; + + syscon@fd5b5000 { + compatible = "rockchip,mipi-dphy-grf\0syscon"; + reg = <0x0 0xfd5b5000 0x0 0x1000>; + phandle = <0x1af>; + }; + + syscon@fd5bc000 { + compatible = "rockchip,pipe-phy-grf\0syscon"; + reg = <0x0 0xfd5bc000 0x0 0x100>; + phandle = <0x179>; + }; + + syscon@fd5c4000 { + compatible = "rockchip,pipe-phy-grf\0syscon"; + reg = <0x0 0xfd5c4000 0x0 0x100>; + phandle = <0x17a>; + }; + + syscon@fd5c8000 { + compatible = "rockchip,rk3588-usbdpphy-grf\0syscon"; + reg = <0x0 0xfd5c8000 0x0 0x4000>; + phandle = <0x174>; + }; + + syscon@fd5d0000 { + compatible = "rockchip,rk3588-usb2phy-grf\0syscon\0simple-mfd"; + reg = <0x0 0xfd5d0000 0x0 0x4000>; + #address-cells = <0x1>; + #size-cells = <0x1>; + phandle = <0x173>; + + usb2-phy@0 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0x0 0x10>; + interrupts = <0x0 0x189 0x4>; + resets = <0x2 0xc0047 0x2 0x488>; + reset-names = "phy\0apb"; + clocks = <0x2 0x2b5>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy0"; + #clock-cells = <0x0>; + rockchip,usbctrl-grf = <0x61>; + status = "okay"; + phandle = <0x175>; + + otg-port { + #phy-cells = <0x0>; + status = "okay"; + phandle = <0x55>; + }; + }; + }; + + syscon@fd5d8000 { + compatible = "rockchip,rk3588-usb2phy-grf\0syscon\0simple-mfd"; + reg = <0x0 0xfd5d8000 0x0 0x4000>; + #address-cells = <0x1>; + #size-cells = <0x1>; + + usb2-phy@8000 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0x8000 0x10>; + interrupts = <0x0 0x187 0x4>; + resets = <0x2 0xc0049 0x2 0x48a>; + reset-names = "phy\0apb"; + clocks = <0x2 0x2b5>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy2"; + #clock-cells = <0x0>; + status = "okay"; + phandle = <0x57>; + + host-port { + #phy-cells = <0x0>; + status = "okay"; + phandle = <0x59>; + }; + }; + }; + + syscon@fd5dc000 { + compatible = "rockchip,rk3588-usb2phy-grf\0syscon\0simple-mfd"; + reg = <0x0 0xfd5dc000 0x0 0x4000>; + #address-cells = <0x1>; + #size-cells = <0x1>; + + usb2-phy@c000 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0xc000 0x10>; + interrupts = <0x0 0x188 0x4>; + resets = <0x2 0xc004a 0x2 0x48b>; + reset-names = "phy\0apb"; + clocks = <0x2 0x2b5>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy3"; + #clock-cells = <0x0>; + status = "okay"; + phandle = <0x5a>; + + host-port { + #phy-cells = <0x0>; + status = "okay"; + phy-supply = <0x62>; + phandle = <0x5c>; + }; + }; + }; + + syscon@fd5e0000 { + compatible = "rockchip,rk3588-hdptxphy-grf\0syscon"; + reg = <0x0 0xfd5e0000 0x0 0x100>; + phandle = <0x172>; + }; + + syscon@fd5e8000 { + compatible = "rockchip,mipi-dcphy-grf\0syscon"; + reg = <0x0 0xfd5e8000 0x0 0x4000>; + phandle = <0x176>; + }; + + syscon@fd5ec000 { + compatible = "rockchip,mipi-dcphy-grf\0syscon"; + reg = <0x0 0xfd5ec000 0x0 0x4000>; + phandle = <0x177>; + }; + + syscon@fd5f0000 { + compatible = "rockchip,rk3588-ioc\0syscon"; + reg = <0x0 0xfd5f0000 0x0 0x10000>; + phandle = <0x17b>; + }; + + clock-controller@fd7c0000 { + compatible = "rockchip,rk3588-cru"; + rockchip,grf = <0x63>; + reg = <0x0 0xfd7c0000 0x0 0x5c000>; + #clock-cells = <0x1>; + #reset-cells = <0x1>; + assigned-clocks = <0x2 0x9 0x2 0x5 0x2 0x8 0x2 0x7 0x2 0xd8 0x2 0xda 0x2 0xd9 0x2 0x10e 0x2 0x10f 0x2 0x110 0x2 0x299 0x2 0x29a 0x2 0x7b 0x2 0xec 0x2 0x114 0x2 0x208 0x2 0x20e>; + assigned-clock-rates = <0x4190ab00 0x2ee00000 0x32a9f880 0x46cf7100 0x29d7ab80 0x17d78400 0x1dcd6500 0x2cb41780 0x5f5e100 0x17d78400 0x5f5e100 0xbebc200 0x165a0bc0 0x8f0d180 0xbebc200 0xb71b00 0xb71b00>; + phandle = <0x2>; + }; + + i2c@fd880000 { + compatible = "rockchip,rk3588-i2c\0rockchip,rk3399-i2c"; + reg = <0x0 0xfd880000 0x0 0x1000>; + clocks = <0x2 0x287 0x2 0x286>; + clock-names = "i2c\0pclk"; + interrupts = <0x0 0x13d 0x4>; + pinctrl-names = "default"; + pinctrl-0 = <0x64>; + #address-cells = <0x1>; + #size-cells = <0x0>; + status = "okay"; + + rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <0x65>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big0_s0"; + regulator-min-microvolt = <0x86470>; + regulator-max-microvolt = <0x100590>; + regulator-ramp-delay = <0x8fc>; + rockchip,suspend-voltage-selector = <0x1>; + regulator-boot-on; + regulator-always-on; + phandle = <0x18>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk8603@43 { + compatible = "rockchip,rk8603"; + reg = <0x43>; + vin-supply = <0x65>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big1_s0"; + regulator-min-microvolt = <0x86470>; + regulator-max-microvolt = <0x100590>; + regulator-ramp-delay = <0x8fc>; + rockchip,suspend-voltage-selector = <0x1>; + regulator-boot-on; + regulator-always-on; + phandle = <0x1c>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + serial@fd890000 { + compatible = "rockchip,rk3588-uart\0snps,dw-apb-uart"; + reg = <0x0 0xfd890000 0x0 0x100>; + interrupts = <0x0 0x14b 0x4>; + clocks = <0x2 0x2ae 0x2 0x2af>; + clock-names = "baudclk\0apb_pclk"; + reg-shift = <0x2>; + reg-io-width = <0x4>; + dmas = <0x66 0x6 0x66 0x7>; + pinctrl-names = "default"; + pinctrl-0 = <0x67>; + status = "okay"; + }; + + pwm@fd8b0010 { + compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm"; + reg = <0x0 0xfd8b0010 0x0 0x10>; + interrupts = <0x0 0x158 0x4>; + #pwm-cells = <0x3>; + pinctrl-names = "active"; + pinctrl-0 = <0x69>; + clocks = <0x2 0x2a5 0x2 0x2a4>; + clock-names = "pwm\0pclk"; + status = "okay"; + phandle = <0x1b3>; + }; + + power-management@fd8d8000 { + compatible = "rockchip,rk3588-pmu\0syscon\0simple-mfd"; + reg = <0x0 0xfd8d8000 0x0 0x400>; + phandle = <0xc2>; + + power-controller { + compatible = "rockchip,rk3588-power-controller"; + #power-domain-cells = <0x1>; + #address-cells = <0x1>; + #size-cells = <0x0>; + status = "okay"; + phandle = <0x50>; + + power-domain@8 { + reg = <0x8>; + #address-cells = <0x1>; + #size-cells = <0x0>; + + power-domain@9 { + reg = <0x9>; + #address-cells = <0x1>; + #size-cells = <0x0>; + clocks = <0x2 0x12f 0x2 0x131 0x2 0x130 0x2 0x126>; + pm_qos = <0x6c 0x6d 0x6e>; + + power-domain@10 { + reg = <0xa>; + clocks = <0x2 0x12f 0x2 0x131 0x2 0x130>; + pm_qos = <0x6f>; + }; + + power-domain@11 { + reg = <0xb>; + clocks = <0x2 0x12f 0x2 0x131 0x2 0x130>; + pm_qos = <0x70>; + }; + }; + }; + + power-domain@12 { + reg = <0xc>; + clocks = <0x2 0x114 0x2 0x115 0x2 0x116>; + pm_qos = <0x71 0x72 0x73 0x74>; + }; + + power-domain@13 { + reg = <0xd>; + #address-cells = <0x1>; + #size-cells = <0x0>; + + power-domain@14 { + reg = <0xe>; + clocks = <0x2 0x18f 0x2 0x1be 0x2 0x1bc 0x2 0x190 0x2 0x18e>; + pm_qos = <0x75>; + }; + + power-domain@15 { + reg = <0xf>; + clocks = <0x2 0x194 0x2 0x1be 0x2 0x1bc 0x2 0x195>; + pm_qos = <0x76>; + }; + + power-domain@16 { + reg = <0x10>; + #address-cells = <0x1>; + #size-cells = <0x0>; + clocks = <0x2 0x1c4 0x2 0x1c5>; + pm_qos = <0x77 0x78 0x79>; + + power-domain@17 { + reg = <0x11>; + clocks = <0x2 0x1c9 0x2 0x1c4 0x2 0x1c5 0x2 0x1ca>; + pm_qos = <0x7a 0x7b 0x7c>; + }; + }; + }; + + power-domain@21 { + reg = <0x15>; + #address-cells = <0x1>; + #size-cells = <0x0>; + clocks = <0x2 0x1be 0x2 0x1bd 0x2 0x1bc 0x2 0x1bf 0x2 0x1aa 0x2 0x1a9 0x2 0x1ac 0x2 0x1ad 0x2 0x1ae 0x2 0x1af 0x2 0x1b0 0x2 0x1b1 0x2 0x1b2 0x2 0x1b3 0x2 0x1b4 0x2 0x1b5 0x2 0x1b7 0x2 0x1b6>; + pm_qos = <0x7d 0x7e 0x7f 0x80 0x81 0x82 0x83 0x84>; + + power-domain@23 { + reg = <0x17>; + clocks = <0x2 0x4b 0x2 0x49 0x2 0x1be>; + pm_qos = <0x85>; + }; + + power-domain@14 { + reg = <0xe>; + clocks = <0x2 0x18f 0x2 0x1be 0x2 0x1bc 0x2 0x190>; + pm_qos = <0x75>; + }; + + power-domain@15 { + reg = <0xf>; + clocks = <0x2 0x194 0x2 0x1be 0x2 0x1bc>; + pm_qos = <0x76>; + }; + + power-domain@22 { + reg = <0x16>; + clocks = <0x2 0x1ba 0x2 0x1b9>; + pm_qos = <0x86>; + }; + }; + + power-domain@24 { + reg = <0x18>; + #address-cells = <0x1>; + #size-cells = <0x0>; + clocks = <0x2 0x26e 0x2 0x26d 0x2 0x270>; + pm_qos = <0x87 0x88>; + + power-domain@25 { + reg = <0x19>; + clocks = <0x2 0x1f6 0x2 0x1f7 0x2 0x1f5 0x2 0x1f3 0x2 0x1ee 0x2 0x1ed 0x2 0x26d>; + pm_qos = <0x89>; + }; + }; + + power-domain@26 { + reg = <0x1a>; + clocks = <0x2 0x22e 0x2 0x22f 0x2 0x22d 0x2 0x218 0x2 0x217 0x2 0x22b 0x2 0x264>; + pm_qos = <0x8a 0x8b>; + }; + + power-domain@27 { + reg = <0x1b>; + #address-cells = <0x1>; + #size-cells = <0x0>; + clocks = <0x2 0x1e1 0x2 0x1e2 0x2 0x1df 0x2 0x1de 0x2 0x1e5 0x2 0x1e4>; + pm_qos = <0x8c 0x8d 0x8e 0x8f>; + + power-domain@28 { + reg = <0x1c>; + clocks = <0x2 0x121 0x2 0x120 0x2 0x1e1 0x2 0x1e2>; + pm_qos = <0x90 0x91>; + }; + + power-domain@29 { + reg = <0x1d>; + clocks = <0x2 0x1d6 0x2 0x1d5 0x2 0x1d9 0x2 0x1d8 0x2 0x1e2>; + pm_qos = <0x92 0x93>; + }; + }; + + power-domain@30 { + reg = <0x1e>; + clocks = <0x2 0x189 0x2 0x18a>; + pm_qos = <0x94>; + }; + + power-domain@31 { + reg = <0x1f>; + clocks = <0x2 0x166 0x2 0x19b 0x2 0x19c 0x2 0x19d 0x2 0x19e 0x2 0x19f 0x2 0x1a0>; + pm_qos = <0x95 0x96 0x97 0x98>; + }; + + power-domain@33 { + reg = <0x21>; + clocks = <0x2 0x166 0x2 0x169 0x2 0x16a>; + }; + + power-domain@34 { + reg = <0x22>; + clocks = <0x2 0x166 0x2 0x169 0x2 0x16a>; + }; + + power-domain@37 { + reg = <0x25>; + clocks = <0x2 0x199 0x2 0x140>; + pm_qos = <0x99>; + }; + + power-domain@38 { + reg = <0x26>; + clocks = <0x2 0x3c 0x2 0x3d>; + }; + + power-domain@40 { + reg = <0x28>; + pm_qos = <0x9a>; + }; + }; + }; + + pvtm@fda40000 { + compatible = "rockchip,rk3588-bigcore0-pvtm"; + reg = <0x0 0xfda40000 0x0 0x100>; + #address-cells = <0x1>; + #size-cells = <0x0>; + + pvtm@0 { + reg = <0x0>; + clocks = <0x2 0x2c6 0x2 0x15>; + clock-names = "clk\0pclk"; + }; + }; + + pvtm@fda50000 { + compatible = "rockchip,rk3588-bigcore1-pvtm"; + reg = <0x0 0xfda50000 0x0 0x100>; + #address-cells = <0x1>; + #size-cells = <0x0>; + + pvtm@1 { + reg = <0x1>; + clocks = <0x2 0x2c8 0x2 0x17>; + clock-names = "clk\0pclk"; + }; + }; + + pvtm@fda60000 { + compatible = "rockchip,rk3588-litcore-pvtm"; + reg = <0x0 0xfda60000 0x0 0x100>; + #address-cells = <0x1>; + #size-cells = <0x0>; + + pvtm@2 { + reg = <0x2>; + clocks = <0x2 0x2ca 0x2 0x1b>; + clock-names = "clk\0pclk"; + }; + }; + + pvtm@fdaf0000 { + compatible = "rockchip,rk3588-npu-pvtm"; + reg = <0x0 0xfdaf0000 0x0 0x100>; + #address-cells = <0x1>; + #size-cells = <0x0>; + + pvtm@3 { + reg = <0x3>; + clocks = <0x2 0x12b 0x2 0x129>; + clock-names = "clk\0pclk"; + resets = <0x2 0x1de 0x2 0x1dc>; + reset-names = "rts\0rst-p"; + }; + }; + + pvtm@fdb30000 { + compatible = "rockchip,rk3588-gpu-pvtm"; + reg = <0x0 0xfdb30000 0x0 0x100>; + #address-cells = <0x1>; + #size-cells = <0x0>; + + pvtm@4 { + reg = <0x4>; + clocks = <0x2 0x118>; + clock-names = "clk"; + resets = <0x2 0x430 0x2 0x42f>; + reset-names = "rts\0rst-p"; + }; + }; + + npu@fdab0000 { + compatible = "rockchip,rk3588-rknpu"; + reg = <0x0 0xfdab0000 0x0 0x10000 0x0 0xfdac0000 0x0 0x10000 0x0 0xfdad0000 0x0 0x10000>; + interrupts = <0x0 0x6e 0x4 0x0 0x6f 0x4 0x0 0x70 0x4>; + interrupt-names = "npu0_irq\0npu1_irq\0npu2_irq"; + clocks = <0xe 0x6 0x2 0x12d 0x2 0x122 0x2 0x124 0x2 0x12e 0x2 0x123 0x2 0x125 0x2 0x131>; + clock-names = "clk_npu\0aclk0\0aclk1\0aclk2\0hclk0\0hclk1\0hclk2\0pclk"; + assigned-clocks = <0xe 0x6>; + assigned-clock-rates = <0xbebc200>; + resets = <0x2 0x1e6 0x2 0x1b0 0x2 0x1c0 0x2 0x1e8 0x2 0x1b2 0x2 0x1c2>; + reset-names = "srst_a0\0srst_a1\0srst_a2\0srst_h0\0srst_h1\0srst_h2"; + power-domains = <0x50 0x9 0x50 0xa 0x50 0xb>; + power-domain-names = "npu0\0npu1\0npu2"; + operating-points-v2 = <0x9b>; + iommus = <0x9c>; + status = "okay"; + rknpu-supply = <0x9d>; + mem-supply = <0x9d>; + }; + + npu-opp-table { + compatible = "operating-points-v2"; + nvmem-cells = <0x9e 0x20>; + nvmem-cell-names = "leakage\0specification_serial_number"; + rockchip,supported-hw; + rockchip,pvtm-voltage-sel = <0x0 0x32f 0x0 0x330 0x343 0x1 0x344 0x35c 0x2 0x35d 0x375 0x3 0x376 0x38e 0x4 0x38f 0x270f 0x5>; + rockchip,pvtm-pvtpll; + rockchip,pvtm-offset = <0x50>; + rockchip,pvtm-sample-time = <0x44c>; + rockchip,pvtm-freq = <0xc3500>; + rockchip,pvtm-volt = <0xb71b0>; + rockchip,pvtm-ref-temp = <0x19>; + rockchip,pvtm-temp-prop = <0xffffff8f 0xffffff8f>; + rockchip,pvtm-thermal-zone = "npu-thermal"; + clocks = <0x2 0x12a>; + clock-names = "pclk"; + rockchip,grf = <0x9f>; + volt-mem-read-margin = <0xd0bd8 0x1 0xbac48 0x2 0xa4cb8 0x3 0x78d98 0x4>; + low-volt-read-margin = <0x4>; + intermediate-threshold-freq = <0x7a120>; + rockchip,init-freq = <0xf4240>; + rockchip,temp-hysteresis = <0x1388>; + rockchip,low-temp = <0x2710>; + rockchip,low-temp-min-volt = <0xb71b0>; + rockchip,high-temp = <0x14c08>; + rockchip,high-temp-max-freq = <0xc3500>; + phandle = <0x9b>; + + opp-300000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = <0x0 0x11e1a300>; + opp-microvolt = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>; + opp-microvolt-L1 = <0xa7d8c 0xa7d8c 0xcf850 0xa7d8c 0xa7d8c 0xcf850>; + opp-microvolt-L2 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L3 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L4 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L5 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + }; + + opp-400000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = <0x0 0x17d78400>; + opp-microvolt = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>; + opp-microvolt-L1 = <0xa7d8c 0xa7d8c 0xcf850 0xa7d8c 0xa7d8c 0xcf850>; + opp-microvolt-L2 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L3 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L4 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L5 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + }; + + opp-500000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = <0x0 0x1dcd6500>; + opp-microvolt = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>; + opp-microvolt-L1 = <0xa7d8c 0xa7d8c 0xcf850 0xa7d8c 0xa7d8c 0xcf850>; + opp-microvolt-L2 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L3 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L4 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L5 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + }; + + opp-600000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = <0x0 0x23c34600>; + opp-microvolt = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>; + opp-microvolt-L1 = <0xa7d8c 0xa7d8c 0xcf850 0xa7d8c 0xa7d8c 0xcf850>; + opp-microvolt-L2 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L3 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L4 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L5 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + }; + + opp-700000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = <0x0 0x29b92700>; + opp-microvolt = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>; + opp-microvolt-L3 = <0xa7d8c 0xa7d8c 0xcf850 0xa7d8c 0xa7d8c 0xcf850>; + opp-microvolt-L4 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L5 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + }; + + opp-800000000 { + opp-supported-hw = <0xff 0xffff>; + opp-hz = <0x0 0x2faf0800>; + opp-microvolt = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>; + opp-microvolt-L2 = <0xb40dc 0xb40dc 0xcf850 0xb40dc 0xb40dc 0xcf850>; + opp-microvolt-L3 = <0xb1008 0xb1008 0xcf850 0xb1008 0xb1008 0xcf850>; + opp-microvolt-L4 = <0xadf34 0xadf34 0xcf850 0xadf34 0xadf34 0xcf850>; + opp-microvolt-L5 = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>; + }; + + opp-900000000 { + opp-supported-hw = <0xfb 0xffff>; + opp-hz = <0x0 0x35a4e900>; + opp-microvolt = <0xc3500 0xc3500 0xcf850 0xc3500 0xc3500 0xcf850>; + opp-microvolt-L1 = <0xc042c 0xc042c 0xcf850 0xc042c 0xc042c 0xcf850>; + opp-microvolt-L2 = <0xbd358 0xbd358 0xcf850 0xbd358 0xbd358 0xcf850>; + opp-microvolt-L3 = <0xba284 0xba284 0xcf850 0xba284 0xba284 0xcf850>; + opp-microvolt-L4 = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>; + opp-microvolt-L5 = <0xb40dc 0xb40dc 0xcf850 0xb40dc 0xb40dc 0xcf850>; + }; + + opp-1000000000 { + opp-supported-hw = <0xfb 0xffff>; + opp-hz = <0x0 0x3b9aca00>; + opp-microvolt = <0xcf850 0xcf850 0xcf850 0xcf850 0xcf850 0xcf850>; + opp-microvolt-L1 = <0xcc77c 0xcc77c 0xcf850 0xcc77c 0xcc77c 0xcf850>; + opp-microvolt-L2 = <0xc96a8 0xc96a8 0xcf850 0xc96a8 0xc96a8 0xcf850>; + opp-microvolt-L3 = <0xc65d4 0xc65d4 0xcf850 0xc65d4 0xc65d4 0xcf850>; + opp-microvolt-L4 = <0xc3500 0xc3500 0xcf850 0xc3500 0xc3500 0xcf850>; + opp-microvolt-L5 = <0xc042c 0xc042c 0xcf850 0xc042c 0xc042c 0xcf850>; + }; + }; + + iommu@fdab9000 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdab9000 0x0 0x100 0x0 0xfdaba000 0x0 0x100 0x0 0xfdaca000 0x0 0x100 0x0 0xfdada000 0x0 0x100>; + interrupts = <0x0 0x6e 0x4 0x0 0x6f 0x4 0x0 0x70 0x4>; + interrupt-names = "npu0_mmu\0npu1_mmu\0npu2_mmu"; + clocks = <0x2 0x12d 0x2 0x122 0x2 0x124 0x2 0x12e 0x2 0x123 0x2 0x125>; + clock-names = "aclk0\0aclk1\0aclk2\0iface0\0iface1\0iface2"; + #iommu-cells = <0x0>; + status = "okay"; + phandle = <0x9c>; + }; + + vepu@fdb50000 { + compatible = "rockchip,vpu-encoder-v2"; + reg = <0x0 0xfdb50000 0x0 0x400>; + interrupts = <0x0 0x78 0x4>; + interrupt-names = "irq_vepu"; + clocks = <0x2 0x1c0 0x2 0x1c1>; + clock-names = "aclk_vcodec\0hclk_vcodec"; + rockchip,normal-rates = <0x2367b880 0x0>; + assigned-clocks = <0x2 0x1c0>; + assigned-clock-rates = <0x2367b880>; + resets = <0x2 0x2c8 0x2 0x2c9>; + reset-names = "shared_video_a\0shared_video_h"; + rockchip,skip-pmu-idle-request; + rockchip,disable-auto-freq; + iommus = <0xa0>; + rockchip,srv = <0xa1>; + rockchip,taskqueue-node = <0x0>; + rockchip,resetgroup-node = <0x0>; + power-domains = <0x50 0x15>; + status = "okay"; + }; + + vdpu@fdb50400 { + compatible = "rockchip,vpu-decoder-v2"; + reg = <0x0 0xfdb50400 0x0 0x400>; + interrupts = <0x0 0x77 0x4>; + interrupt-names = "irq_vdpu"; + clocks = <0x2 0x1c0 0x2 0x1c1>; + clock-names = "aclk_vcodec\0hclk_vcodec"; + rockchip,normal-rates = <0x2367b880 0x0>; + assigned-clocks = <0x2 0x1c0>; + assigned-clock-rates = <0x2367b880>; + resets = <0x2 0x2c8 0x2 0x2c9>; + reset-names = "shared_video_a\0shared_video_h"; + rockchip,skip-pmu-idle-request; + rockchip,disable-auto-freq; + iommus = <0xa0>; + rockchip,srv = <0xa1>; + rockchip,taskqueue-node = <0x0>; + rockchip,resetgroup-node = <0x0>; + power-domains = <0x50 0x15>; + status = "okay"; + }; + + iommu@fdb50800 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdb50800 0x0 0x40>; + interrupts = <0x0 0x76 0x4>; + interrupt-names = "irq_vdpu_mmu"; + clocks = <0x2 0x1c0 0x2 0x1c1>; + clock-names = "aclk\0iface"; + power-domains = <0x50 0x15>; + #iommu-cells = <0x0>; + status = "okay"; + phandle = <0xa0>; + }; + + avsd-plus@fdb51000 { + compatible = "rockchip,avs-plus-decoder"; + reg = <0x0 0xfdb51000 0x0 0x200>; + interrupts = <0x0 0x77 0x4>; + interrupt-names = "irq_avsd"; + clocks = <0x2 0x1c0 0x2 0x1c1>; + clock-names = "aclk_vcodec\0hclk_vcodec"; + rockchip,normal-rates = <0x2367b880 0x0>; + assigned-clocks = <0x2 0x1c0>; + assigned-clock-rates = <0x2367b880>; + resets = <0x2 0x2c8 0x2 0x2c9>; + reset-names = "shared_video_a\0shared_video_h"; + rockchip,skip-pmu-idle-request; + rockchip,disable-auto-freq; + iommus = <0xa0>; + power-domains = <0x50 0x15>; + rockchip,srv = <0xa1>; + rockchip,taskqueue-node = <0x0>; + rockchip,resetgroup-node = <0x0>; + status = "okay"; + }; + + rga@fdb60000 { + compatible = "rockchip,rga3_core0"; + reg = <0x0 0xfdb60000 0x0 0x1000>; + interrupts = <0x0 0x72 0x4>; + interrupt-names = "rga3_core0_irq"; + clocks = <0x2 0x1ba 0x2 0x1b9 0x2 0x1bb>; + clock-names = "aclk_rga3_0\0hclk_rga3_0\0clk_rga3_0"; + power-domains = <0x50 0x16>; + iommus = <0xa2>; + status = "okay"; + }; + + iommu@fdb60f00 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdb60f00 0x0 0x100>; + interrupts = <0x0 0x72 0x4>; + interrupt-names = "rga3_0_mmu"; + clocks = <0x2 0x1ba 0x2 0x1b9>; + clock-names = "aclk\0iface"; + power-domains = <0x50 0x16>; + #iommu-cells = <0x0>; + status = "okay"; + phandle = <0xa2>; + }; + + rga@fdb70000 { + compatible = "rockchip,rga3_core1"; + reg = <0x0 0xfdb70000 0x0 0x1000>; + interrupts = <0x0 0x73 0x4>; + interrupt-names = "rga3_core1_irq"; + clocks = <0x2 0x18a 0x2 0x189 0x2 0x18b>; + clock-names = "aclk_rga3_1\0hclk_rga3_1\0clk_rga3_1"; + power-domains = <0x50 0x1e>; + iommus = <0xa3>; + status = "okay"; + }; + + iommu@fdb70f00 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdb70f00 0x0 0x100>; + interrupts = <0x0 0x73 0x4>; + interrupt-names = "rga3_1_mmu"; + clocks = <0x2 0x18a 0x2 0x189>; + clock-names = "aclk\0iface"; + power-domains = <0x50 0x1e>; + #iommu-cells = <0x0>; + status = "okay"; + phandle = <0xa3>; + }; + + rga@fdb80000 { + compatible = "rockchip,rga2_core0"; + reg = <0x0 0xfdb80000 0x0 0x1000>; + interrupts = <0x0 0x74 0x4>; + interrupt-names = "rga2_irq"; + clocks = <0x2 0x1b7 0x2 0x1b6 0x2 0x1b8>; + clock-names = "aclk_rga2\0hclk_rga2\0clk_rga2"; + power-domains = <0x50 0x15>; + status = "okay"; + }; + + jpegd@fdb90000 { + compatible = "rockchip,rkv-jpeg-decoder-v1"; + reg = <0x0 0xfdb90000 0x0 0x400>; + interrupts = <0x0 0x81 0x4>; + interrupt-names = "irq_jpegd"; + clocks = <0x2 0x1b4 0x2 0x1b5>; + clock-names = "aclk_vcodec\0hclk_vcodec"; + rockchip,normal-rates = <0x23c34600 0x0>; + assigned-clocks = <0x2 0x1b4>; + assigned-clock-rates = <0x23c34600>; + resets = <0x2 0x2d2 0x2 0x2d3>; + reset-names = "video_a\0video_h"; + rockchip,skip-pmu-idle-request; + iommus = <0xa4>; + rockchip,srv = <0xa1>; + rockchip,taskqueue-node = <0x1>; + power-domains = <0x50 0x15>; + status = "okay"; + }; + + iommu@fdb90480 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdb90480 0x0 0x40>; + interrupts = <0x0 0x82 0x4>; + interrupt-names = "irq_jpegd_mmu"; + clocks = <0x2 0x1b4 0x2 0x1b5>; + clock-names = "aclk\0iface"; + power-domains = <0x50 0x15>; + #iommu-cells = <0x0>; + status = "okay"; + phandle = <0xa4>; + }; + + jpege-core@fdba0000 { + compatible = "rockchip,vpu-jpege-core"; + reg = <0x0 0xfdba0000 0x0 0x400>; + interrupts = <0x0 0x7a 0x4>; + interrupt-names = "irq_jpege0"; + clocks = <0x2 0x1ac 0x2 0x1ad>; + clock-names = "aclk_vcodec\0hclk_vcodec"; + rockchip,normal-rates = <0x2367b880 0x0>; + assigned-clocks = <0x2 0x1ac>; + assigned-clock-rates = <0x2367b880>; + resets = <0x2 0x2ca 0x2 0x2cb>; + reset-names = "video_a\0video_h"; + rockchip,skip-pmu-idle-request; + rockchip,disable-auto-freq; + iommus = <0xa5>; + rockchip,srv = <0xa1>; + rockchip,taskqueue-node = <0x2>; + rockchip,ccu = <0xa6>; + power-domains = <0x50 0x15>; + status = "okay"; + }; + + iommu@fdba0800 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdba0800 0x0 0x40>; + interrupts = <0x0 0x79 0x4>; + interrupt-names = "irq_jpege0_mmu"; + clocks = <0x2 0x1ac 0x2 0x1ad>; + clock-names = "aclk\0iface"; + power-domains = <0x50 0x15>; + #iommu-cells = <0x0>; + status = "okay"; + phandle = <0xa5>; + }; + + jpege-core@fdba4000 { + compatible = "rockchip,vpu-jpege-core"; + reg = <0x0 0xfdba4000 0x0 0x400>; + interrupts = <0x0 0x7c 0x4>; + interrupt-names = "irq_jpege1"; + clocks = <0x2 0x1ae 0x2 0x1af>; + clock-names = "aclk_vcodec\0hclk_vcodec"; + rockchip,normal-rates = <0x2367b880 0x0>; + assigned-clocks = <0x2 0x1ae>; + assigned-clock-rates = <0x2367b880>; + resets = <0x2 0x2cc 0x2 0x2cd>; + reset-names = "video_a\0video_h"; + rockchip,skip-pmu-idle-request; + rockchip,disable-auto-freq; + iommus = <0xa7>; + rockchip,srv = <0xa1>; + rockchip,taskqueue-node = <0x2>; + rockchip,ccu = <0xa6>; + power-domains = <0x50 0x15>; + status = "okay"; + }; + + iommu@fdba4800 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdba4800 0x0 0x40>; + interrupts = <0x0 0x7b 0x4>; + interrupt-names = "irq_jpege1_mmu"; + clocks = <0x2 0x1ae 0x2 0x1af>; + clock-names = "aclk\0iface"; + power-domains = <0x50 0x15>; + #iommu-cells = <0x0>; + status = "okay"; + phandle = <0xa7>; + }; + + jpege-core@fdba8000 { + compatible = "rockchip,vpu-jpege-core"; + reg = <0x0 0xfdba8000 0x0 0x400>; + interrupts = <0x0 0x7e 0x4>; + interrupt-names = "irq_jpege2"; + clocks = <0x2 0x1b0 0x2 0x1b1>; + clock-names = "aclk_vcodec\0hclk_vcodec"; + rockchip,normal-rates = <0x2367b880 0x0>; + assigned-clocks = <0x2 0x1b0>; + assigned-clock-rates = <0x2367b880>; + resets = <0x2 0x2ce 0x2 0x2cf>; + reset-names = "video_a\0video_h"; + rockchip,skip-pmu-idle-request; + rockchip,disable-auto-freq; + iommus = <0xa8>; + rockchip,srv = <0xa1>; + rockchip,taskqueue-node = <0x2>; + rockchip,ccu = <0xa6>; + power-domains = <0x50 0x15>; + status = "okay"; + }; + + iommu@fdba8800 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdba8800 0x0 0x40>; + interrupts = <0x0 0x7d 0x4>; + interrupt-names = "irq_jpege2_mmu"; + clocks = <0x2 0x1b0 0x2 0x1b1>; + clock-names = "aclk\0iface"; + power-domains = <0x50 0x15>; + #iommu-cells = <0x0>; + status = "okay"; + phandle = <0xa8>; + }; + + jpege-core@fdbac000 { + compatible = "rockchip,vpu-jpege-core"; + reg = <0x0 0xfdbac000 0x0 0x400>; + interrupts = <0x0 0x80 0x4>; + interrupt-names = "irq_jpege3"; + clocks = <0x2 0x1b2 0x2 0x1b3>; + clock-names = "aclk_vcodec\0hclk_vcodec"; + rockchip,normal-rates = <0x2367b880 0x0>; + assigned-clocks = <0x2 0x1b2>; + assigned-clock-rates = <0x2367b880>; + resets = <0x2 0x2d0 0x2 0x2d1>; + reset-names = "video_a\0video_h"; + rockchip,skip-pmu-idle-request; + rockchip,disable-auto-freq; + iommus = <0xa9>; + rockchip,srv = <0xa1>; + rockchip,taskqueue-node = <0x2>; + rockchip,ccu = <0xa6>; + power-domains = <0x50 0x15>; + status = "okay"; + }; + + iommu@fdbac800 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdbac800 0x0 0x40>; + interrupts = <0x0 0x7f 0x4>; + interrupt-names = "irq_jpege3_mmu"; + clocks = <0x2 0x1b2 0x2 0x1b3>; + clock-names = "aclk\0iface"; + power-domains = <0x50 0x15>; + #iommu-cells = <0x0>; + status = "okay"; + phandle = <0xa9>; + }; + + iep@fdbb0000 { + compatible = "rockchip,iep-v2"; + reg = <0x0 0xfdbb0000 0x0 0x500>; + interrupts = <0x0 0x75 0x4>; + interrupt-names = "irq_iep"; + clocks = <0x2 0x1aa 0x2 0x1a9 0x2 0x1ab>; + clock-names = "aclk\0hclk\0sclk"; + rockchip,normal-rates = <0x2367b880 0x0>; + assigned-clocks = <0x2 0x1aa>; + assigned-clock-rates = <0x2367b880>; + resets = <0x2 0x2d5 0x2 0x2d4 0x2 0x2d6>; + reset-names = "rst_a\0rst_h\0rst_s"; + rockchip,skip-pmu-idle-request; + rockchip,disable-auto-freq; + power-domains = <0x50 0x15>; + rockchip,srv = <0xa1>; + rockchip,taskqueue-node = <0x6>; + iommus = <0xaa>; + status = "okay"; + }; + + iommu@fdbb0800 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdbb0800 0x0 0x100>; + interrupts = <0x0 0x75 0x4>; + interrupt-names = "irq_iep_mmu"; + clocks = <0x2 0x1aa 0x2 0x1a9>; + clock-names = "aclk\0iface"; + #iommu-cells = <0x0>; + power-domains = <0x50 0x15>; + status = "okay"; + phandle = <0xaa>; + }; + + rkvenc-core@fdbd0000 { + compatible = "rockchip,rkv-encoder-v2-core"; + reg = <0x0 0xfdbd0000 0x0 0x6000>; + interrupts = <0x0 0x65 0x4>; + interrupt-names = "irq_rkvenc0"; + clocks = <0x2 0x1c5 0x2 0x1c4 0x2 0x1c6>; + clock-names = "aclk_vcodec\0hclk_vcodec\0clk_core"; + rockchip,normal-rates = <0x23c34600 0x0 0x2faf0800>; + assigned-clocks = <0x2 0x1c5 0x2 0x1c6>; + assigned-clock-rates = <0x23c34600 0x2faf0800>; + resets = <0x2 0x2f5 0x2 0x2f4 0x2 0x2f6>; + reset-names = "video_a\0video_h\0video_core"; + rockchip,skip-pmu-idle-request; + iommus = <0xab>; + rockchip,srv = <0xa1>; + rockchip,ccu = <0xac>; + rockchip,taskqueue-node = <0x7>; + rockchip,task-capacity = <0x8>; + power-domains = <0x50 0x10>; + operating-points-v2 = <0xad>; + status = "okay"; + venc-supply = <0xae>; + mem-supply = <0xae>; + }; + + iommu@fdbdf000 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdbdf000 0x0 0x40 0x0 0xfdbdf040 0x0 0x40>; + interrupts = <0x0 0x63 0x4 0x0 0x64 0x4>; + interrupt-names = "irq_rkvenc0_mmu0\0irq_rkvenc0_mmu1"; + clocks = <0x2 0x1c5 0x2 0x1c4>; + clock-names = "aclk\0iface"; + rockchip,disable-mmu-reset; + rockchip,enable-cmd-retry; + rockchip,shootdown-entire; + #iommu-cells = <0x0>; + power-domains = <0x50 0x10>; + status = "okay"; + phandle = <0xab>; + }; + + rkvenc-core@fdbe0000 { + compatible = "rockchip,rkv-encoder-v2-core"; + reg = <0x0 0xfdbe0000 0x0 0x6000>; + interrupts = <0x0 0x68 0x4>; + interrupt-names = "irq_rkvenc1"; + clocks = <0x2 0x1ca 0x2 0x1c9 0x2 0x1cb>; + clock-names = "aclk_vcodec\0hclk_vcodec\0clk_core"; + rockchip,normal-rates = <0x23c34600 0x0 0x2faf0800>; + assigned-clocks = <0x2 0x1ca 0x2 0x1cb>; + assigned-clock-rates = <0x23c34600 0x2faf0800>; + resets = <0x2 0x305 0x2 0x304 0x2 0x306>; + reset-names = "video_a\0video_h\0video_core"; + rockchip,skip-pmu-idle-request; + iommus = <0xaf>; + rockchip,srv = <0xa1>; + rockchip,ccu = <0xac>; + rockchip,taskqueue-node = <0x7>; + rockchip,task-capacity = <0x8>; + power-domains = <0x50 0x11>; + operating-points-v2 = <0xad>; + status = "okay"; + venc-supply = <0xae>; + mem-supply = <0xae>; + }; + + iommu@fdbef000 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdbef000 0x0 0x40 0x0 0xfdbef040 0x0 0x40>; + interrupts = <0x0 0x66 0x4 0x0 0x67 0x4>; + interrupt-names = "irq_rkvenc1_mmu0\0irq_rkvenc1_mmu1"; + clocks = <0x2 0x1ca 0x2 0x1c9>; + lock-names = "aclk\0iface"; + rockchip,disable-mmu-reset; + rockchip,enable-cmd-retry; + rockchip,shootdown-entire; + #iommu-cells = <0x0>; + power-domains = <0x50 0x11>; + status = "okay"; + phandle = <0xaf>; + }; + + venc-opp-table { + compatible = "operating-points-v2"; + nvmem-cells = <0xb0>; + nvmem-cell-names = "leakage"; + rockchip,leakage-voltage-sel = <0x1 0x8 0x0 0x9 0x14 0x1 0x15 0xfe 0x2>; + rockchip,grf = <0xb1>; + volt-mem-read-margin = <0xd0bd8 0x1 0xbac48 0x2 0xa4cb8 0x3 0x78d98 0x4>; + phandle = <0xad>; + + opp-800000000 { + opp-hz = <0x0 0x2faf0800>; + opp-microvolt = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>; + opp-microvolt-L0 = <0xc3500 0xc3500 0xcf850 0xc3500 0xc3500 0xcf850>; + opp-microvolt-L1 = <0xbd358 0xbd358 0xcf850 0xbd358 0xbd358 0xcf850>; + opp-microvolt-L2 = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>; + }; + }; + + rkvdec-ccu@fdc30000 { + compatible = "rockchip,rkv-decoder-v2-ccu"; + reg = <0x0 0xfdc30000 0x0 0x100>; + reg-names = "ccu"; + clocks = <0x2 0x18e>; + clock-names = "aclk_ccu"; + assigned-clocks = <0x2 0x18e>; + assigned-clock-rates = <0x23c34600>; + resets = <0x2 0x282>; + reset-names = "video_ccu"; + rockchip,skip-pmu-idle-request; + rockchip,ccu-mode = <0x1>; + power-domains = <0x50 0xe>; + status = "okay"; + phandle = <0xb3>; + }; + + rkvdec-core@fdc38000 { + compatible = "rockchip,rkv-decoder-v2"; + reg = <0x0 0xfdc38100 0x0 0x400 0x0 0xfdc38000 0x0 0x100>; + reg-names = "regs\0link"; + interrupts = <0x0 0x5f 0x4>; + interrupt-names = "irq_rkvdec0"; + clocks = <0x2 0x190 0x2 0x18f 0x2 0x193 0x2 0x191 0x2 0x192>; + clock-names = "aclk_vcodec\0hclk_vcodec\0clk_core\0clk_cabac\0clk_hevc_cabac"; + rockchip,normal-rates = <0x2faf0800 0x0 0x23c34600 0x23c34600 0x3b9aca00>; + assigned-clocks = <0x2 0x190 0x2 0x193 0x2 0x191 0x2 0x192>; + assigned-clock-rates = <0x2faf0800 0x23c34600 0x23c34600 0x3b9aca00>; + resets = <0x2 0x284 0x2 0x283 0x2 0x289 0x2 0x287 0x2 0x288>; + reset-names = "video_a\0video_h\0video_core\0video_cabac\0video_hevc_cabac"; + rockchip,skip-pmu-idle-request; + iommus = <0xb2>; + rockchip,srv = <0xa1>; + rockchip,ccu = <0xb3>; + rockchip,core-mask = <0x10001>; + rockchip,task-capacity = <0x10>; + rockchip,taskqueue-node = <0x9>; + rockchip,sram = <0xb4>; + rockchip,rcb-iova = <0xfff00000 0x100000>; + rockchip,rcb-info = <0x88 0x6000 0x89 0xc000 0x8d 0x16000 0x8c 0xc000 0x8b 0x2c000 0x85 0xc000 0x86 0x2000 0x87 0x1100 0x8a 0x3300 0x8e 0x47300>; + rockchip,rcb-min-width = <0x200>; + power-domains = <0x50 0xe>; + status = "okay"; + }; + + iommu@fdc38700 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdc38700 0x0 0x40 0x0 0xfdc38740 0x0 0x40>; + interrupts = <0x0 0x60 0x4>; + interrupt-names = "irq_rkvdec0_mmu"; + clocks = <0x2 0x190 0x2 0x18f>; + clock-names = "aclk\0iface"; + rockchip,disable-mmu-reset; + rockchip,enable-cmd-retry; + rockchip,shootdown-entire; + rockchip,master-handle-irq; + #iommu-cells = <0x0>; + power-domains = <0x50 0xe>; + status = "okay"; + phandle = <0xb2>; + }; + + rkvdec-core@fdc48000 { + compatible = "rockchip,rkv-decoder-v2"; + reg = <0x0 0xfdc48100 0x0 0x400 0x0 0xfdc48000 0x0 0x100>; + reg-names = "regs\0link"; + interrupts = <0x0 0x61 0x4>; + interrupt-names = "irq_rkvdec1"; + clocks = <0x2 0x195 0x2 0x194 0x2 0x198 0x2 0x196 0x2 0x197>; + clock-names = "aclk_vcodec\0hclk_vcodec\0clk_core\0clk_cabac\0clk_hevc_cabac"; + rockchip,normal-rates = <0x2faf0800 0x0 0x23c34600 0x23c34600 0x3b9aca00>; + assigned-clocks = <0x2 0x195 0x2 0x198 0x2 0x196 0x2 0x197>; + assigned-clock-rates = <0x2faf0800 0x23c34600 0x23c34600 0x3b9aca00>; + resets = <0x2 0x293 0x2 0x292 0x2 0x298 0x2 0x296 0x2 0x297>; + reset-names = "video_a\0video_h\0video_core\0video_cabac\0video_hevc_cabac"; + rockchip,skip-pmu-idle-request; + iommus = <0xb5>; + rockchip,srv = <0xa1>; + rockchip,ccu = <0xb3>; + rockchip,core-mask = <0x20002>; + rockchip,task-capacity = <0x10>; + rockchip,taskqueue-node = <0x9>; + rockchip,sram = <0xb6>; + rockchip,rcb-iova = <0xffe00000 0x100000>; + rockchip,rcb-info = <0x88 0x6000 0x89 0xc000 0x8d 0x16000 0x8c 0xc000 0x8b 0x2c000 0x85 0xc000 0x86 0x2000 0x87 0x1100 0x8a 0x3300 0x8e 0x47300>; + rockchip,rcb-min-width = <0x200>; + power-domains = <0x50 0xf>; + status = "okay"; + }; + + iommu@fdc48700 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdc48700 0x0 0x40 0x0 0xfdc48740 0x0 0x40>; + interrupts = <0x0 0x62 0x4>; + interrupt-names = "irq_rkvdec1_mmu"; + clocks = <0x2 0x195 0x2 0x194>; + clock-names = "aclk\0iface"; + rockchip,disable-mmu-reset; + rockchip,enable-cmd-retry; + rockchip,shootdown-entire; + rockchip,master-handle-irq; + #iommu-cells = <0x0>; + power-domains = <0x50 0xf>; + status = "okay"; + phandle = <0xb5>; + }; + + iommu@fdca0000 { + compatible = "rockchip,iommu-av1"; + reg = <0x0 0xfdca0000 0x0 0x600>; + interrupts = <0x0 0x6d 0x4>; + interrupt-names = "irq_av1d_mmu"; + clocks = <0x2 0x49 0x2 0x4b>; + clock-names = "aclk\0iface"; + #iommu-cells = <0x0>; + power-domains = <0x50 0x17>; + status = "okay"; + phandle = <0xb7>; + }; + + rkisp@fdcb0000 { + compatible = "rockchip,rk3588-rkisp"; + reg = <0x0 0xfdcb0000 0x0 0x7f00>; + interrupts = <0x0 0x83 0x4 0x0 0x85 0x4 0x0 0x86 0x4>; + interrupt-names = "isp_irq\0mi_irq\0mipi_irq"; + clocks = <0x2 0x1de 0x2 0x1df 0x2 0x1db 0x2 0x1dc 0x2 0x1dd>; + clock-names = "aclk_isp\0hclk_isp\0clk_isp_core\0clk_isp_core_marvin\0clk_isp_core_vicap"; + power-domains = <0x50 0x1b>; + iommus = <0xb9>; + status = "okay"; + phandle = <0x48>; + }; + + iommu@fdcb7f00 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdcb7f00 0x0 0x100>; + interrupts = <0x0 0x84 0x4>; + interrupt-names = "isp0_mmu"; + clocks = <0x2 0x1de 0x2 0x1df>; + clock-names = "aclk\0iface"; + power-domains = <0x50 0x1b>; + #iommu-cells = <0x0>; + rockchip,disable-mmu-reset; + status = "okay"; + phandle = <0xb9>; + }; + + rkcif@fdce0000 { + compatible = "rockchip,rk3588-cif"; + reg = <0x0 0xfdce0000 0x0 0x800>; + reg-names = "cif_regs"; + interrupts = <0x0 0x9b 0x4>; + interrupt-names = "cif-intr"; + clocks = <0x2 0x1e4 0x2 0x1e5 0x2 0x1e3 0x2 0x1cd 0x2 0x1ce>; + clock-names = "aclk_cif\0hclk_cif\0dclk_cif\0iclk_host0\0iclk_host1"; + resets = <0x2 0x317 0x2 0x318 0x2 0x316 0x2 0x334 0x2 0x335 0x2 0x336 0x2 0x337 0x2 0x338 0x2 0x339>; + reset-names = "rst_cif_a\0rst_cif_h\0rst_cif_d\0rst_cif_host0\0rst_cif_host1\0rst_cif_host2\0rst_cif_host3\0rst_cif_host4\0rst_cif_host5"; + assigned-clocks = <0x2 0x1e3>; + assigned-clock-rates = <0x23c34600>; + power-domains = <0x50 0x1b>; + rockchip,grf = <0xb1>; + iommus = <0x40>; + status = "okay"; + phandle = <0x3f>; + }; + + iommu@fdce0800 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdce0800 0x0 0x100 0x0 0xfdce0900 0x0 0x100>; + interrupts = <0x0 0x71 0x4>; + interrupt-names = "cif_mmu"; + clocks = <0x2 0x1e4 0x2 0x1e5>; + clock-names = "aclk\0iface"; + power-domains = <0x50 0x1b>; + rockchip,disable-mmu-reset; + #iommu-cells = <0x0>; + status = "okay"; + phandle = <0x40>; + }; + + mipi2-csi2@fdd30000 { + compatible = "rockchip,rk3588-mipi-csi2"; + reg = <0x0 0xfdd30000 0x0 0x10000>; + reg-names = "csihost_regs"; + interrupts = <0x0 0x93 0x4 0x0 0x94 0x4>; + interrupt-names = "csi-intr1\0csi-intr2"; + clocks = <0x2 0x1d1>; + clock-names = "pclk_csi2host"; + resets = <0x2 0x326>; + reset-names = "srst_csihost_p"; + status = "okay"; + + ports { + #address-cells = <0x1>; + #size-cells = <0x0>; + + port@0 { + reg = <0x0>; + #address-cells = <0x1>; + #size-cells = <0x0>; + + endpoint@1 { + reg = <0x1>; + remote-endpoint = <0xbd>; + phandle = <0x2e>; + }; + }; + + port@1 { + reg = <0x1>; + #address-cells = <0x1>; + #size-cells = <0x0>; + + endpoint@0 { + reg = <0x0>; + remote-endpoint = <0xbe>; + phandle = <0x44>; + }; + }; + }; + }; + + vop@fdd90000 { + compatible = "rockchip,rk3588-vop"; + reg = <0x0 0xfdd90000 0x0 0x4200 0x0 0xfdd95000 0x0 0x1000>; + reg-names = "regs\0gamma_lut"; + interrupts = <0x0 0x9c 0x4>; + clocks = <0x2 0x270 0x2 0x26f 0x2 0x274 0x2 0x275 0x2 0x276 0x2 0x277 0x2 0x26e 0x2 0x271 0x2 0x272 0x2 0x273>; + clock-names = "aclk_vop\0hclk_vop\0dclk_vp0\0dclk_vp1\0dclk_vp2\0dclk_vp3\0pclk_vop\0dclk_src_vp0\0dclk_src_vp1\0dclk_src_vp2"; + assigned-clocks = <0x2 0x270>; + assigned-clock-rates = <0x2faf0800>; + resets = <0x2 0x349 0x2 0x348 0x2 0x34d 0x2 0x350 0x2 0x351 0x2 0x352>; + reset-names = "axi\0ahb\0dclk_vp0\0dclk_vp1\0dclk_vp2\0dclk_vp3"; + iommus = <0xbf>; + power-domains = <0x50 0x18>; + rockchip,grf = <0xb1>; + rockchip,vop-grf = <0xc0>; + rockchip,vo1-grf = <0xc1>; + rockchip,pmu = <0xc2>; + status = "okay"; + + ports { + #address-cells = <0x1>; + #size-cells = <0x0>; + phandle = <0x2f>; + + port@0 { + #address-cells = <0x1>; + #size-cells = <0x0>; + reg = <0x0>; + rockchip,plane-mask = <0x5>; + rockchip,primary-plane = <0x2>; + + endpoint@0 { + reg = <0x0>; + remote-endpoint = <0xc3>; + phandle = <0xe9>; + }; + + endpoint@1 { + reg = <0x1>; + remote-endpoint = <0xc4>; + phandle = <0xf5>; + }; + + endpoint@2 { + reg = <0x2>; + remote-endpoint = <0xc5>; + phandle = <0x35>; + }; + + endpoint@3 { + reg = <0x3>; + remote-endpoint = <0xc6>; + phandle = <0x18c>; + }; + + endpoint@4 { + reg = <0x4>; + remote-endpoint = <0xc7>; + phandle = <0x197>; + }; + + endpoint@5 { + reg = <0x5>; + remote-endpoint = <0xc8>; + phandle = <0x194>; + }; + }; + + port@1 { + #address-cells = <0x1>; + #size-cells = <0x0>; + reg = <0x1>; + rockchip,plane-mask = <0xa>; + rockchip,primary-plane = <0x3>; + + endpoint@0 { + reg = <0x0>; + remote-endpoint = <0xc9>; + phandle = <0x31>; + }; + + endpoint@1 { + reg = <0x1>; + remote-endpoint = <0xca>; + phandle = <0xf6>; + }; + + endpoint@2 { + reg = <0x2>; + remote-endpoint = <0xcb>; + phandle = <0xf2>; + }; + + endpoint@3 { + reg = <0x3>; + remote-endpoint = <0xcc>; + phandle = <0x37>; + }; + + endpoint@4 { + reg = <0x4>; + remote-endpoint = <0xcd>; + phandle = <0x198>; + }; + + endpoint@5 { + reg = <0x5>; + remote-endpoint = <0xce>; + phandle = <0x38>; + }; + }; + + port@2 { + #address-cells = <0x1>; + #size-cells = <0x0>; + reg = <0x2>; + assigned-clocks = <0x2 0x273>; + assigned-clock-parents = <0x2 0x4>; + rockchip,plane-mask = <0x140>; + rockchip,primary-plane = <0x8>; + + endpoint@0 { + reg = <0x0>; + remote-endpoint = <0xcf>; + phandle = <0xea>; + }; + + endpoint@1 { + reg = <0x1>; + remote-endpoint = <0xd0>; + phandle = <0x34>; + }; + + endpoint@2 { + reg = <0x2>; + remote-endpoint = <0xd1>; + phandle = <0xf3>; + }; + + endpoint@3 { + reg = <0x3>; + remote-endpoint = <0xd2>; + phandle = <0xdc>; + }; + + endpoint@4 { + reg = <0x4>; + remote-endpoint = <0xd3>; + phandle = <0xe3>; + }; + + endpoint@5 { + reg = <0x5>; + remote-endpoint = <0xd4>; + phandle = <0x18d>; + }; + + endpoint@6 { + reg = <0x6>; + remote-endpoint = <0xd5>; + phandle = <0x199>; + }; + + endpoint@7 { + reg = <0x7>; + remote-endpoint = <0xd6>; + phandle = <0x195>; + }; + }; + + port@3 { + #address-cells = <0x1>; + #size-cells = <0x0>; + reg = <0x3>; + rockchip,plane-mask = <0x280>; + rockchip,primary-plane = <0x9>; + + endpoint@0 { + reg = <0x0>; + remote-endpoint = <0xd7>; + phandle = <0x32>; + }; + + endpoint@1 { + reg = <0x1>; + remote-endpoint = <0xd8>; + phandle = <0x33>; + }; + + endpoint@2 { + reg = <0x2>; + remote-endpoint = <0xd9>; + phandle = <0x36>; + }; + }; + }; + }; + + iommu@fdd97e00 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdd97e00 0x0 0x100 0x0 0xfdd97f00 0x0 0x100>; + interrupts = <0x0 0x9c 0x4>; + interrupt-names = "vop_mmu"; + clocks = <0x2 0x270 0x2 0x26f>; + clock-names = "aclk\0iface"; + #iommu-cells = <0x0>; + rockchip,disable-device-link-resume; + rockchip,shootdown-entire; + status = "okay"; + phandle = <0xbf>; + }; + + dsi@fde20000 { + compatible = "rockchip,rk3588-mipi-dsi2"; + reg = <0x0 0xfde20000 0x0 0x10000>; + interrupts = <0x0 0xa7 0x4>; + clocks = <0x2 0x278 0x2 0x27a>; + clock-names = "pclk\0sys_clk"; + resets = <0x2 0x354>; + reset-names = "apb"; + power-domains = <0x50 0x18>; + phys = <0x2a>; + phy-names = "dcphy"; + rockchip,grf = <0xc0>; + #address-cells = <0x1>; + #size-cells = <0x0>; + status = "okay"; + + ports { + #address-cells = <0x1>; + #size-cells = <0x0>; + + port@0 { + reg = <0x0>; + #address-cells = <0x1>; + #size-cells = <0x0>; + + endpoint@1 { + reg = <0x1>; + remote-endpoint = <0x32>; + status = "okay"; + phandle = <0xd7>; + }; + }; + + port@1 { + reg = <0x1>; + + endpoint { + remote-endpoint = <0xdd>; + phandle = <0xe2>; + }; + }; + }; + + panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0x0>; + backlight = <0xde>; + reset-delay-ms = <0xa>; + enable-delay-ms = <0xa>; + prepare-delay-ms = <0xa>; + unprepare-delay-ms = <0xa>; + disable-delay-ms = <0x3c>; + dsi,flags = <0xa03>; + dsi,format = <0x0>; + dsi,lanes = <0x4>; + panel-init-sequence = [13 00 02 80 ac 13 00 02 81 b8 13 00 02 82 09 13 00 02 83 78 13 00 02 84 7f 13 00 02 85 bb 13 00 02 86 70]; + panel-exit-sequence = <0x5000128 0x5000110>; + power-supply = <0xdf>; + pinctrl-names = "default"; + pinctrl-0 = <0xe0>; + + display-timings { + native-mode = <0xe1>; + + timing0 { + clock-frequency = <0x3dfd240>; + hactive = <0x400>; + vactive = <0x258>; + hfront-porch = <0xa0>; + hsync-len = <0xa>; + hback-porch = <0xa0>; + vfront-porch = <0xc>; + vsync-len = <0x1>; + vback-porch = <0x17>; + hsync-active = <0x0>; + vsync-active = <0x0>; + de-active = <0x0>; + pixelclk-active = <0x0>; + phandle = <0xe1>; + }; + }; + + ports { + #address-cells = <0x1>; + #size-cells = <0x0>; + + port@0 { + reg = <0x0>; + + endpoint { + remote-endpoint = <0xe2>; + phandle = <0xdd>; + }; + }; + }; + }; + }; + + hdmi@fde80000 { + compatible = "rockchip,rk3588-dw-hdmi"; + reg = <0x0 0xfde80000 0x0 0x20000>; + interrupts = <0x0 0xa9 0x4 0x0 0xaa 0x4 0x0 0xab 0x4 0x0 0xac 0x4 0x0 0x168 0x4>; + clocks = <0x2 0x221 0x2 0x265 0x2 0x222 0x2 0x223 0x2 0x246 0x2 0x274 0x2 0x275 0x2 0x276 0x2 0x277 0x5 0xeb>; + clock-names = "pclk\0hpd\0earc\0hdmitx_ref\0aud\0dclk_vp0\0dclk_vp1\0dclk_vp2\0dclk_vp3\0hclk_vo1\0link_clk"; + resets = <0x2 0x3d0 0x2 0x49c>; + reset-names = "ref\0hdp"; + power-domains = <0x50 0x1a>; + pinctrl-names = "default"; + pinctrl-0 = <0xec 0xed 0xee 0xef>; + reg-io-width = <0x4>; + rockchip,grf = <0xb1>; + rockchip,vo1_grf = <0xc1>; + phys = <0xf0>; + phy-names = "hdmi"; + #sound-dai-cells = <0x0>; + status = "okay"; + enable-gpios = <0xf1 0x9 0x0>; + phandle = <0x1b5>; + + ports { + #address-cells = <0x1>; + #size-cells = <0x0>; + + port@0 { + reg = <0x0>; + #address-cells = <0x1>; + #size-cells = <0x0>; + + endpoint@0 { + reg = <0x0>; + remote-endpoint = <0x35>; + status = "okay"; + phandle = <0xc5>; + }; + }; + }; + }; + + qos@fdf35000 { + compatible = "syscon"; + reg = <0x0 0xfdf35000 0x0 0x20>; + phandle = <0x71>; + }; + + qos@fdf35200 { + compatible = "syscon"; + reg = <0x0 0xfdf35200 0x0 0x20>; + phandle = <0x72>; + }; + + qos@fdf35400 { + compatible = "syscon"; + reg = <0x0 0xfdf35400 0x0 0x20>; + phandle = <0x73>; + }; + + qos@fdf35600 { + compatible = "syscon"; + reg = <0x0 0xfdf35600 0x0 0x20>; + phandle = <0x74>; + }; + + qos@fdf36000 { + compatible = "syscon"; + reg = <0x0 0xfdf36000 0x0 0x20>; + phandle = <0x94>; + }; + + qos@fdf39000 { + compatible = "syscon"; + reg = <0x0 0xfdf39000 0x0 0x20>; + phandle = <0x99>; + }; + + qos@fdf3d800 { + compatible = "syscon"; + reg = <0x0 0xfdf3d800 0x0 0x20>; + phandle = <0x9a>; + }; + + qos@fdf3e000 { + compatible = "syscon"; + reg = <0x0 0xfdf3e000 0x0 0x20>; + phandle = <0x96>; + }; + + qos@fdf3e200 { + compatible = "syscon"; + reg = <0x0 0xfdf3e200 0x0 0x20>; + phandle = <0x95>; + }; + + qos@fdf3e400 { + compatible = "syscon"; + reg = <0x0 0xfdf3e400 0x0 0x20>; + phandle = <0x97>; + }; + + qos@fdf3e600 { + compatible = "syscon"; + reg = <0x0 0xfdf3e600 0x0 0x20>; + phandle = <0x98>; + }; + + qos@fdf40000 { + compatible = "syscon"; + reg = <0x0 0xfdf40000 0x0 0x20>; + phandle = <0x92>; + }; + + qos@fdf40200 { + compatible = "syscon"; + reg = <0x0 0xfdf40200 0x0 0x20>; + phandle = <0x93>; + }; + + qos@fdf40400 { + compatible = "syscon"; + reg = <0x0 0xfdf40400 0x0 0x20>; + phandle = <0x8c>; + }; + + qos@fdf40500 { + compatible = "syscon"; + reg = <0x0 0xfdf40500 0x0 0x20>; + phandle = <0x8d>; + }; + + qos@fdf40600 { + compatible = "syscon"; + reg = <0x0 0xfdf40600 0x0 0x20>; + phandle = <0x8e>; + }; + + qos@fdf40800 { + compatible = "syscon"; + reg = <0x0 0xfdf40800 0x0 0x20>; + phandle = <0x8f>; + }; + + qos@fdf41000 { + compatible = "syscon"; + reg = <0x0 0xfdf41000 0x0 0x20>; + phandle = <0x90>; + }; + + qos@fdf41100 { + compatible = "syscon"; + reg = <0x0 0xfdf41100 0x0 0x20>; + phandle = <0x91>; + }; + + qos@fdf60000 { + compatible = "syscon"; + reg = <0x0 0xfdf60000 0x0 0x20>; + phandle = <0x77>; + }; + + qos@fdf60200 { + compatible = "syscon"; + reg = <0x0 0xfdf60200 0x0 0x20>; + phandle = <0x78>; + }; + + qos@fdf60400 { + compatible = "syscon"; + reg = <0x0 0xfdf60400 0x0 0x20>; + phandle = <0x79>; + }; + + qos@fdf61000 { + compatible = "syscon"; + reg = <0x0 0xfdf61000 0x0 0x20>; + phandle = <0x7a>; + }; + + qos@fdf61200 { + compatible = "syscon"; + reg = <0x0 0xfdf61200 0x0 0x20>; + phandle = <0x7b>; + }; + + qos@fdf61400 { + compatible = "syscon"; + reg = <0x0 0xfdf61400 0x0 0x20>; + phandle = <0x7c>; + }; + + qos@fdf62000 { + compatible = "syscon"; + reg = <0x0 0xfdf62000 0x0 0x20>; + phandle = <0x75>; + }; + + qos@fdf63000 { + compatible = "syscon"; + reg = <0x0 0xfdf63000 0x0 0x20>; + phandle = <0x76>; + }; + + qos@fdf64000 { + compatible = "syscon"; + reg = <0x0 0xfdf64000 0x0 0x20>; + phandle = <0x85>; + }; + + qos@fdf66000 { + compatible = "syscon"; + reg = <0x0 0xfdf66000 0x0 0x20>; + phandle = <0x7d>; + }; + + qos@fdf66200 { + compatible = "syscon"; + reg = <0x0 0xfdf66200 0x0 0x20>; + phandle = <0x7e>; + }; + + qos@fdf66400 { + compatible = "syscon"; + reg = <0x0 0xfdf66400 0x0 0x20>; + phandle = <0x7f>; + }; + + qos@fdf66600 { + compatible = "syscon"; + reg = <0x0 0xfdf66600 0x0 0x20>; + phandle = <0x80>; + }; + + qos@fdf66800 { + compatible = "syscon"; + reg = <0x0 0xfdf66800 0x0 0x20>; + phandle = <0x81>; + }; + + qos@fdf66a00 { + compatible = "syscon"; + reg = <0x0 0xfdf66a00 0x0 0x20>; + phandle = <0x82>; + }; + + qos@fdf66c00 { + compatible = "syscon"; + reg = <0x0 0xfdf66c00 0x0 0x20>; + phandle = <0x83>; + }; + + qos@fdf66e00 { + compatible = "syscon"; + reg = <0x0 0xfdf66e00 0x0 0x20>; + phandle = <0x84>; + }; + + qos@fdf67000 { + compatible = "syscon"; + reg = <0x0 0xfdf67000 0x0 0x20>; + phandle = <0x86>; + }; + + qos@fdf67200 { + compatible = "syscon"; + reg = <0x0 0xfdf67200 0x0 0x20>; + }; + + qos@fdf70000 { + compatible = "syscon"; + reg = <0x0 0xfdf70000 0x0 0x20>; + phandle = <0x6f>; + }; + + qos@fdf71000 { + compatible = "syscon"; + reg = <0x0 0xfdf71000 0x0 0x20>; + phandle = <0x70>; + }; + + qos@fdf72000 { + compatible = "syscon"; + reg = <0x0 0xfdf72000 0x0 0x20>; + phandle = <0x6c>; + }; + + qos@fdf72200 { + compatible = "syscon"; + reg = <0x0 0xfdf72200 0x0 0x20>; + phandle = <0x6d>; + }; + + qos@fdf72400 { + compatible = "syscon"; + reg = <0x0 0xfdf72400 0x0 0x20>; + phandle = <0x6e>; + }; + + qos@fdf80000 { + compatible = "syscon"; + reg = <0x0 0xfdf80000 0x0 0x20>; + phandle = <0x89>; + }; + + qos@fdf81000 { + compatible = "syscon"; + reg = <0x0 0xfdf81000 0x0 0x20>; + phandle = <0x8a>; + }; + + qos@fdf81200 { + compatible = "syscon"; + reg = <0x0 0xfdf81200 0x0 0x20>; + phandle = <0x8b>; + }; + + qos@fdf82000 { + compatible = "syscon"; + reg = <0x0 0xfdf82000 0x0 0x20>; + phandle = <0x87>; + }; + + qos@fdf82200 { + compatible = "syscon"; + reg = <0x0 0xfdf82200 0x0 0x20>; + phandle = <0x88>; + }; + + dfi@fe060000 { + compatible = "rockchip,rk3588-dfi"; + reg = <0x0 0xfe060000 0x0 0x10000>; + rockchip,pmu_grf = <0xf7>; + status = "okay"; + phandle = <0x39>; + }; + + ethernet@fe1c0000 { + local-mac-address = [46 ae fd 14 a7 64]; + compatible = "rockchip,rk3588-gmac\0snps,dwmac-4.20a"; + reg = <0x0 0xfe1c0000 0x0 0x10000>; + interrupts = <0x0 0xea 0x4 0x0 0xe9 0x4>; + interrupt-names = "macirq\0eth_wake_irq"; + rockchip,grf = <0xb1>; + rockchip,php_grf = <0x63>; + clocks = <0x2 0x144 0x2 0x145 0x2 0x168 0x2 0x16d 0x2 0x143>; + clock-names = "stmmaceth\0clk_mac_ref\0pclk_mac\0aclk_mac\0ptp_ref"; + resets = <0x2 0x20b>; + reset-names = "stmmaceth"; + power-domains = <0x50 0x21>; + snps,mixed-burst; + snps,tso; + snps,axi-config = <0xfc>; + snps,mtl-rx-config = <0xfd>; + snps,mtl-tx-config = <0xfe>; + status = "okay"; + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + snps,reset-gpio = <0xff 0xf 0x1>; + snps,reset-active-low; + snps,reset-delays-us = <0x0 0x4e20 0x186a0>; + pinctrl-names = "default"; + pinctrl-0 = <0x100 0x101 0x102 0x103 0x104>; + tx_delay = <0x44>; + phy-handle = <0x105>; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <0x1>; + #size-cells = <0x0>; + + phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + phandle = <0x105>; + }; + }; + + stmmac-axi-config { + snps,wr_osr_lmt = <0x4>; + snps,rd_osr_lmt = <0x8>; + snps,blen = <0x0 0x0 0x0 0x0 0x10 0x8 0x4>; + phandle = <0xfc>; + }; + + rx-queues-config { + snps,rx-queues-to-use = <0x2>; + phandle = <0xfd>; + + queue0 { + }; + + queue1 { + }; + }; + + tx-queues-config { + snps,tx-queues-to-use = <0x2>; + phandle = <0xfe>; + + queue0 { + }; + + queue1 { + }; + }; + }; + + mmc@fe2c0000 { + compatible = "rockchip,rk3588-dw-mshc\0rockchip,rk3288-dw-mshc"; + reg = <0x0 0xfe2c0000 0x0 0x4000>; + interrupts = <0x0 0xcb 0x4>; + clocks = <0xe 0x17 0xe 0x9 0x2 0x2c2 0x2 0x2c3>; + clock-names = "biu\0ciu\0ciu-drive\0ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <0x8f0d180>; + pinctrl-names = "default"; + pinctrl-0 = <0x106 0x107 0x108 0x109>; + power-domains = <0x50 0x28>; + status = "okay"; + no-sdio; + no-mmc; + bus-width = <0x4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vqmmc-supply = <0x10a>; + vmmc-supply = <0x10b>; + }; + + mmc@fe2e0000 { + compatible = "rockchip,rk3588-dwcmshc\0rockchip,dwcmshc-sdhci"; + reg = <0x0 0xfe2e0000 0x0 0x10000>; + interrupts = <0x0 0xcd 0x4>; + assigned-clocks = <0x2 0x13b 0x2 0x13c 0x2 0x13a>; + assigned-clock-rates = <0xbebc200 0x16e3600 0xbebc200>; + clocks = <0x2 0x13a 0x2 0x138 0x2 0x139 0x2 0x13b 0x2 0x13c>; + clock-names = "core\0bus\0axi\0block\0timer"; + resets = <0x2 0x1f6 0x2 0x1f4 0x2 0x1f5 0x2 0x1f7 0x2 0x1f8>; + reset-names = "core\0bus\0axi\0block\0timer"; + max-frequency = <0xbebc200>; + status = "okay"; + bus-width = <0x8>; + no-sdio; + no-sd; + non-removable; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + full-pwr-cycle-in-suspend; + }; + + rng@fe378000 { + compatible = "rockchip,trngv1"; + reg = <0x0 0xfe378000 0x0 0x200>; + interrupts = <0x0 0x190 0x4>; + clocks = <0xe 0xc>; + clock-names = "hclk_trng"; + resets = <0x10d 0x30>; + reset-names = "reset"; + status = "okay"; + }; + + i2s@fe470000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfe470000 0x0 0x1000>; + interrupts = <0x0 0xb4 0x4>; + clocks = <0x2 0x33 0x2 0x37 0x2 0x30>; + clock-names = "mclk_tx\0mclk_rx\0hclk"; + assigned-clocks = <0x2 0x31 0x2 0x35>; + assigned-clock-parents = <0x2 0x5 0x2 0x5>; + dmas = <0x66 0x0 0x66 0x1>; + dma-names = "tx\0rx"; + power-domains = <0x50 0x26>; + resets = <0x2 0x77 0x2 0x7a>; + reset-names = "tx-m\0rx-m"; + rockchip,clk-trcm = <0x1>; + pinctrl-names = "default"; + pinctrl-0 = <0x10e 0x10f 0x110 0x111>; + #sound-dai-cells = <0x0>; + status = "okay"; + phandle = <0x1c8>; + }; + + hwspinlock@fe5a0000 { + compatible = "rockchip,hwspinlock"; + reg = <0x0 0xfe5a0000 0x0 0x100>; + #hwlock-cells = <0x1>; + }; + + interrupt-controller@fe600000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <0x3>; + #address-cells = <0x2>; + #size-cells = <0x2>; + ranges; + interrupt-controller; + reg = <0x0 0xfe600000 0x0 0x10000 0x0 0xfe680000 0x0 0x100000>; + interrupts = <0x1 0x9 0x4>; + phandle = <0x1>; + + msi-controller@fe640000 { + compatible = "arm,gic-v3-its"; + msi-controller; + #msi-cells = <0x1>; + reg = <0x0 0xfe640000 0x0 0x20000>; + phandle = <0xf9>; + }; + + msi-controller@fe660000 { + compatible = "arm,gic-v3-its"; + msi-controller; + #msi-cells = <0x1>; + reg = <0x0 0xfe660000 0x0 0x20000>; + phandle = <0x19c>; + }; + }; + + dma-controller@fea10000 { + compatible = "arm,pl330\0arm,primecell"; + reg = <0x0 0xfea10000 0x0 0x4000>; + interrupts = <0x0 0x56 0x4 0x0 0x57 0x4>; + clocks = <0x2 0x78>; + clock-names = "apb_pclk"; + #dma-cells = <0x1>; + arm,pl330-periph-burst; + phandle = <0x66>; + }; + + dma-controller@fea30000 { + compatible = "arm,pl330\0arm,primecell"; + reg = <0x0 0xfea30000 0x0 0x4000>; + interrupts = <0x0 0x58 0x4 0x0 0x59 0x4>; + clocks = <0x2 0x79>; + clock-names = "apb_pclk"; + #dma-cells = <0x1>; + arm,pl330-periph-burst; + phandle = <0xda>; + }; + + i2c@fea90000 { + compatible = "rockchip,rk3588-i2c\0rockchip,rk3399-i2c"; + reg = <0x0 0xfea90000 0x0 0x1000>; + clocks = <0x2 0x8d 0x2 0x85>; + clock-names = "i2c\0pclk"; + interrupts = <0x0 0x13e 0x4>; + pinctrl-names = "default"; + pinctrl-0 = <0x136>; + #address-cells = <0x1>; + #size-cells = <0x0>; + status = "okay"; + + rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <0x65>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_npu_s0"; + regulator-min-microvolt = <0x86470>; + regulator-max-microvolt = <0xe7ef0>; + regulator-ramp-delay = <0x8fc>; + rockchip,suspend-voltage-selector = <0x1>; + regulator-boot-on; + regulator-always-on; + phandle = <0x9d>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + i2c@feab0000 { + compatible = "rockchip,rk3588-i2c\0rockchip,rk3399-i2c"; + reg = <0x0 0xfeab0000 0x0 0x1000>; + clocks = <0x2 0x8f 0x2 0x87>; + clock-names = "i2c\0pclk"; + interrupts = <0x0 0x140 0x4>; + pinctrl-names = "default"; + pinctrl-0 = <0x138>; + #address-cells = <0x1>; + #size-cells = <0x0>; + status = "okay"; + + es8311@19 { + status = "okay"; + compatible = "everest,es8311"; + reg = <0x19>; + #sound-dai-cells = <0x0>; + adc-pga-gain = <0x6>; + adc-volume = <0xbf>; + dac-volume = <0xbf>; + aec-mode = "adc left, adc right"; + clocks = <0x139>; + clock-names = "mclk"; + assigned-clocks = <0x139>; + assigned-clock-rates = <0xbb8000>; + pinctrl-names = "default"; + pinctrl-0 = <0x13a>; + phandle = <0x1c9>; + }; + }; + + i2c@feac0000 { + compatible = "rockchip,rk3588-i2c\0rockchip,rk3399-i2c"; + reg = <0x0 0xfeac0000 0x0 0x1000>; + clocks = <0x2 0x90 0x2 0x88>; + clock-names = "i2c\0pclk"; + interrupts = <0x0 0x141 0x4>; + pinctrl-names = "default"; + pinctrl-0 = <0x13b>; + #address-cells = <0x1>; + #size-cells = <0x0>; + status = "okay"; + + imx415@36 { + compatible = "sony,imx415"; + reg = <0x36>; + clocks = <0x2 0x100>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <0x13c>; + power-domains = <0x50 0x1b>; + reset-gpios = <0x13d 0x16 0x1>; + avdd-supply = <0x13e>; + rockchip,camera-module-index = <0x0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT2022-PX1"; + rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20"; + + port { + endpoint { + remote-endpoint = <0x13f>; + data-lanes = <0x1 0x2 0x3 0x4>; + phandle = <0x2d>; + }; + }; + }; + + gt9xx@14 { + compatible = "goodix,gt9xx"; + reg = <0x14>; + pinctrl-names = "default"; + pinctrl-0 = <0x140>; + touch-gpio = <0x141 0x0 0x8>; + reset-gpio = <0x141 0x1 0x0>; + max-x = <0x400>; + max-y = <0x258>; + tp-size = <0x38f>; + status = "okay"; + }; + }; + + timer@feae0000 { + compatible = "rockchip,rk3588-timer\0rockchip,rk3288-timer"; + reg = <0x0 0xfeae0000 0x0 0x20>; + interrupts = <0x0 0x121 0x4>; + clocks = <0x2 0x5c 0x2 0x5f>; + clock-names = "pclk\0timer"; + }; + + watchdog@feaf0000 { + compatible = "snps,dw-wdt"; + reg = <0x0 0xfeaf0000 0x0 0x100>; + clocks = <0x2 0x6c 0x2 0x6b>; + clock-names = "tclk\0pclk"; + interrupts = <0x0 0x13b 0x4>; + status = "okay"; + }; + + spi@feb00000 { + compatible = "rockchip,rk3066-spi"; + reg = <0x0 0xfeb00000 0x0 0x1000>; + interrupts = <0x0 0x146 0x4>; + #address-cells = <0x1>; + #size-cells = <0x0>; + clocks = <0x2 0xa3 0x2 0x9e>; + clock-names = "spiclk\0apb_pclk"; + dmas = <0x66 0xe 0x66 0xf>; + dma-names = "tx\0rx"; + pinctrl-names = "default"; + pinctrl-0 = <0x143 0x144>; + num-cs = <0x1>; + status = "okay"; + max-freq = <0x2faf080>; + + spidev@0 { + compatible = "rockchip,spidev"; + status = "okay"; + reg = <0x0>; + spi-max-frequency = <0x2faf080>; + }; + }; + + spi@feb20000 { + compatible = "rockchip,rk3066-spi"; + reg = <0x0 0xfeb20000 0x0 0x1000>; + interrupts = <0x0 0x148 0x4>; + #address-cells = <0x1>; + #size-cells = <0x0>; + clocks = <0x2 0xa5 0x2 0xa0>; + clock-names = "spiclk\0apb_pclk"; + dmas = <0xda 0xf 0xda 0x10>; + dma-names = "tx\0rx"; + pinctrl-names = "default"; + pinctrl-0 = <0x148 0x149>; + num-cs = <0x1>; + status = "okay"; + assigned-clocks = <0x2 0xa5>; + assigned-clock-rates = <0xbebc200>; + + rk806single@0 { + compatible = "rockchip,rk806"; + spi-max-frequency = <0xf4240>; + reg = <0x0>; + interrupt-parent = <0x13d>; + interrupts = <0x7 0x8>; + pinctrl-names = "default\0pmic-power-off"; + pinctrl-0 = <0x14a 0x14b 0x14c 0x14d>; + pinctrl-1 = <0x14e>; + low_voltage_threshold = <0xbb8>; + shutdown_voltage_threshold = <0xa8c>; + shutdown_temperture_threshold = <0xa0>; + hotdie_temperture_threshold = <0x73>; + pmic-reset-func = <0x1>; + vcc1-supply = <0x65>; + vcc2-supply = <0x65>; + vcc3-supply = <0x65>; + vcc4-supply = <0x65>; + vcc5-supply = <0x65>; + vcc6-supply = <0x65>; + vcc7-supply = <0x65>; + vcc8-supply = <0x65>; + vcc9-supply = <0x65>; + vcc10-supply = <0x65>; + vcc11-supply = <0x14f>; + vcc12-supply = <0x65>; + vcc13-supply = <0x150>; + vcc14-supply = <0x150>; + vcca-supply = <0x65>; + + pwrkey { + status = "okay"; + }; + + pinctrl_rk806 { + gpio-controller; + #gpio-cells = <0x2>; + + rk806_dvs1_null { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + phandle = <0x14b>; + }; + + rk806_dvs1_slp { + pins = "gpio_pwrctrl1"; + function = "pin_fun1"; + }; + + rk806_dvs1_pwrdn { + pins = "gpio_pwrctrl1"; + function = "pin_fun2"; + phandle = <0x14e>; + }; + + rk806_dvs1_rst { + pins = "gpio_pwrctrl1"; + function = "pin_fun3"; + }; + + rk806_dvs2_null { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + phandle = <0x14c>; + }; + + rk806_dvs2_slp { + pins = "gpio_pwrctrl2"; + function = "pin_fun1"; + }; + + rk806_dvs2_pwrdn { + pins = "gpio_pwrctrl2"; + function = "pin_fun2"; + }; + + rk806_dvs2_rst { + pins = "gpio_pwrctrl2"; + function = "pin_fun3"; + }; + + rk806_dvs2_dvs { + pins = "gpio_pwrctrl2"; + function = "pin_fun4"; + }; + + rk806_dvs2_gpio { + pins = "gpio_pwrctrl2"; + function = "pin_fun5"; + }; + + rk806_dvs3_null { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + phandle = <0x14d>; + }; + + rk806_dvs3_slp { + pins = "gpio_pwrctrl3"; + function = "pin_fun1"; + }; + + rk806_dvs3_pwrdn { + pins = "gpio_pwrctrl3"; + function = "pin_fun2"; + }; + + rk806_dvs3_rst { + pins = "gpio_pwrctrl3"; + function = "pin_fun3"; + }; + + rk806_dvs3_dvs { + pins = "gpio_pwrctrl3"; + function = "pin_fun4"; + }; + + rk806_dvs3_gpio { + pins = "gpio_pwrctrl3"; + function = "pin_fun5"; + }; + }; + + regulators { + DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x86470>; + regulator-max-microvolt = <0xe7ef0>; + regulator-ramp-delay = <0x30d4>; + regulator-name = "vdd_gpu_s0"; + regulator-enable-ramp-delay = <0x190>; + phandle = <0x52>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x86470>; + regulator-max-microvolt = <0xe7ef0>; + regulator-ramp-delay = <0x30d4>; + regulator-name = "vdd_cpu_lit_s0"; + phandle = <0x12>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0xa4cb8>; + regulator-max-microvolt = <0xb71b0>; + regulator-ramp-delay = <0x30d4>; + regulator-name = "vdd_log_s0"; + phandle = <0x3c>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <0xb71b0>; + }; + }; + + DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x86470>; + regulator-max-microvolt = <0xe7ef0>; + regulator-init-microvolt = <0xb71b0>; + regulator-ramp-delay = <0x30d4>; + regulator-name = "vdd_vdenc_s0"; + phandle = <0xae>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + DCDC_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0xa4cb8>; + regulator-max-microvolt = <0xdbba0>; + regulator-ramp-delay = <0x30d4>; + regulator-name = "vdd_ddr_s0"; + phandle = <0x3b>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <0xcf850>; + }; + }; + + DCDC_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd2_ddr_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + DCDC_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x1e8480>; + regulator-max-microvolt = <0x1e8480>; + regulator-name = "vdd_2v0_pldo_s3"; + phandle = <0x14f>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <0x1e8480>; + }; + }; + + DCDC_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x325aa0>; + regulator-max-microvolt = <0x325aa0>; + regulator-name = "vcc_3v3_s3"; + phandle = <0x1c6>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <0x325aa0>; + }; + }; + + DCDC_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vddq_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + DCDC_REG10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x1b7740>; + regulator-max-microvolt = <0x1b7740>; + regulator-name = "vcc_1v8_s3"; + phandle = <0x1c7>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <0x1b7740>; + }; + }; + + PLDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x1b7740>; + regulator-max-microvolt = <0x1b7740>; + regulator-name = "avcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + PLDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x1b7740>; + regulator-max-microvolt = <0x1b7740>; + regulator-name = "vcc_1v8_s0"; + phandle = <0x16b>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <0x1b7740>; + }; + }; + + PLDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x124f80>; + regulator-max-microvolt = <0x124f80>; + regulator-name = "avdd_1v2_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + PLDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x325aa0>; + regulator-max-microvolt = <0x325aa0>; + regulator-name = "vcc_3v3_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + PLDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x1b7740>; + regulator-max-microvolt = <0x325aa0>; + regulator-name = "vccio_sd_s0"; + phandle = <0x10a>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + PLDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x1b7740>; + regulator-max-microvolt = <0x1b7740>; + regulator-name = "pldo6_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <0x1b7740>; + }; + }; + + NLDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0xb71b0>; + regulator-max-microvolt = <0xb71b0>; + regulator-name = "vdd_0v75_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <0xb71b0>; + }; + }; + + NLDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0xcf850>; + regulator-max-microvolt = <0xcf850>; + regulator-name = "vdd_ddr_pll_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <0xcf850>; + }; + }; + + NLDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0xcc77c>; + regulator-max-microvolt = <0xcc77c>; + regulator-name = "avdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + NLDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0xcf850>; + regulator-max-microvolt = <0xcf850>; + regulator-name = "vdd_0v85_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + NLDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0xb71b0>; + regulator-max-microvolt = <0xb71b0>; + regulator-name = "vdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + }; + + serial@feb60000 { + compatible = "rockchip,rk3588-uart\0snps,dw-apb-uart"; + reg = <0x0 0xfeb60000 0x0 0x100>; + interrupts = <0x0 0x14e 0x4>; + clocks = <0x2 0xbf 0x2 0xad>; + clock-names = "baudclk\0apb_pclk"; + reg-shift = <0x2>; + reg-io-width = <0x4>; + dmas = <0x66 0xc 0x66 0xd>; + pinctrl-names = "default"; + pinctrl-0 = <0x156>; + status = "okay"; + }; + + serial@feb70000 { + compatible = "rockchip,rk3588-uart\0snps,dw-apb-uart"; + reg = <0x0 0xfeb70000 0x0 0x100>; + interrupts = <0x0 0x14f 0x4>; + clocks = <0x2 0xc3 0x2 0xae>; + clock-names = "baudclk\0apb_pclk"; + reg-shift = <0x2>; + reg-io-width = <0x4>; + dmas = <0xda 0x9 0xda 0xa>; + pinctrl-names = "default"; + pinctrl-0 = <0x157>; + status = "okay"; + }; + + serial@feba0000 { + compatible = "rockchip,rk3588-uart\0snps,dw-apb-uart"; + reg = <0x0 0xfeba0000 0x0 0x100>; + interrupts = <0x0 0x152 0x4>; + clocks = <0x2 0xcf 0x2 0xb1>; + clock-names = "baudclk\0apb_pclk"; + reg-shift = <0x2>; + reg-io-width = <0x4>; + dmas = <0xdb 0x7 0xdb 0x8>; + pinctrl-names = "default"; + pinctrl-0 = <0x15a>; + status = "okay"; + }; + + tsadc@fec00000 { + compatible = "rockchip,rk3588-tsadc"; + reg = <0x0 0xfec00000 0x0 0x400>; + interrupts = <0x0 0x18d 0x4>; + clocks = <0x2 0xaa 0x2 0xa9>; + clock-names = "tsadc\0apb_pclk"; + assigned-clocks = <0x2 0xaa>; + assigned-clock-rates = <0x1e8480>; + resets = <0x2 0xc1 0x2 0xc0>; + reset-names = "tsadc\0tsadc-apb"; + #thermal-sensor-cells = <0x1>; + rockchip,hw-tshut-temp = <0x1d4c0>; + rockchip,hw-tshut-mode = <0x0>; + rockchip,hw-tshut-polarity = <0x0>; + pinctrl-names = "gpio\0otpout"; + pinctrl-0 = <0x169>; + pinctrl-1 = <0x16a>; + status = "okay"; + phandle = <0x4d>; + }; + + saradc@fec10000 { + compatible = "rockchip,rk3588-saradc"; + reg = <0x0 0xfec10000 0x0 0x10000>; + interrupts = <0x0 0x18e 0x4>; + #io-channel-cells = <0x1>; + clocks = <0x2 0x9d 0x2 0x9c>; + clock-names = "saradc\0apb_pclk"; + resets = <0x2 0xbe>; + reset-names = "saradc-apb"; + status = "okay"; + vref-supply = <0x16b>; + phandle = <0x1b2>; + }; + + otp@fecc0000 { + compatible = "rockchip,rk3588-otp"; + reg = <0x0 0xfecc0000 0x0 0x400>; + #address-cells = <0x1>; + #size-cells = <0x1>; + clocks = <0x2 0x96 0x2 0x95 0x2 0x97 0x2 0x99>; + clock-names = "otpc\0apb\0arb\0phy"; + resets = <0x2 0x12a 0x2 0x129 0x2 0x12b>; + reset-names = "otpc\0apb\0arb"; + + cpu-code@2 { + reg = <0x2 0x2>; + phandle = <0x29>; + }; + + specification-serial-number@6 { + reg = <0x6 0x1>; + bits = <0x0 0x5>; + phandle = <0x20>; + }; + + id@7 { + reg = <0x7 0x10>; + phandle = <0x27>; + }; + + cpu-version@1c { + reg = <0x1c 0x1>; + bits = <0x3 0x3>; + phandle = <0x28>; + }; + + cpub0-leakage@17 { + reg = <0x17 0x1>; + phandle = <0x23>; + }; + + cpub1-leakage@18 { + reg = <0x18 0x1>; + phandle = <0x25>; + }; + + cpul-leakage@19 { + reg = <0x19 0x1>; + phandle = <0x1f>; + }; + + log-leakage@1a { + reg = <0x1a 0x1>; + phandle = <0x3d>; + }; + + gpu-leakage@1b { + reg = <0x1b 0x1>; + phandle = <0x53>; + }; + + npu-leakage@28 { + reg = <0x28 0x1>; + phandle = <0x9e>; + }; + + codec-leakage@29 { + reg = <0x29 0x1>; + phandle = <0xb0>; + }; + }; + + dma-controller@fed10000 { + compatible = "arm,pl330\0arm,primecell"; + reg = <0x0 0xfed10000 0x0 0x4000>; + interrupts = <0x0 0x5a 0x4 0x0 0x5b 0x4>; + clocks = <0x2 0x7a>; + clock-names = "apb_pclk"; + #dma-cells = <0x1>; + arm,pl330-periph-burst; + phandle = <0xdb>; + }; + + hdmiphy@fed60000 { + compatible = "rockchip,rk3588-hdptx-phy-hdmi"; + reg = <0x0 0xfed60000 0x0 0x2000>; + clocks = <0x2 0x2b5 0x2 0x267>; + clock-names = "ref\0apb"; + resets = <0x2 0x48e 0x2 0x485 0x2 0xc003b 0x2 0xc003c 0x2 0xc003d 0x2 0x48c 0x2 0x48d>; + reset-names = "phy\0apb\0init\0cmn\0lane\0ropll\0lcpll"; + rockchip,grf = <0x172>; + #phy-cells = <0x0>; + status = "okay"; + phandle = <0xf0>; + + clk-port { + #clock-cells = <0x0>; + status = "okay"; + phandle = <0xeb>; + }; + }; + + phy@fed80000 { + compatible = "rockchip,rk3588-usbdp-phy"; + reg = <0x0 0xfed80000 0x0 0x10000>; + rockchip,u2phy-grf = <0x173>; + rockchip,usb-grf = <0x61>; + rockchip,usbdpphy-grf = <0x174>; + rockchip,vo-grf = <0xe7>; + clocks = <0x2 0x2b6 0x2 0x27f 0x2 0x269 0x175>; + clock-names = "refclk\0immortal\0pclk\0utmi"; + resets = <0x2 0x28 0x2 0x29 0x2 0x2a 0x2 0x2b 0x2 0x482>; + reset-names = "init\0cmn\0lane\0pcs_apb\0pma_apb"; + status = "okay"; + + dp-port { + #phy-cells = <0x0>; + status = "okay"; + phandle = <0xe8>; + }; + + u3-port { + #phy-cells = <0x0>; + status = "okay"; + phandle = <0x56>; + }; + }; + + phy@feda0000 { + compatible = "rockchip,rk3588-mipi-dcphy"; + reg = <0x0 0xfeda0000 0x0 0x10000>; + rockchip,grf = <0x176>; + clocks = <0x2 0x108 0x2 0x2b6>; + clock-names = "pclk\0ref"; + resets = <0x2 0xc0043 0x2 0x3e 0x2 0x3f 0x2 0xc0044>; + reset-names = "m_phy\0apb\0grf\0s_phy"; + #phy-cells = <0x0>; + status = "okay"; + phandle = <0x2a>; + }; + + csi2-dphy0-hw@fedc0000 { + compatible = "rockchip,rk3588-csi2-dphy-hw"; + reg = <0x0 0xfedc0000 0x0 0x8000>; + clocks = <0x2 0x10c>; + clock-names = "pclk"; + resets = <0x2 0x17 0x2 0x16>; + reset-names = "srst_csiphy0\0srst_p_csiphy0"; + rockchip,grf = <0x178>; + rockchip,sys_grf = <0xb1>; + status = "okay"; + phandle = <0x2c>; + }; + + phy@fee20000 { + compatible = "rockchip,rk3588-naneng-combphy"; + reg = <0x0 0xfee20000 0x0 0x100>; + #phy-cells = <0x1>; + clocks = <0x2 0x2bf 0x2 0x187 0x2 0x166>; + clock-names = "refclk\0apbclk\0phpclk"; + assigned-clocks = <0x2 0x2bf>; + assigned-clock-rates = <0x5f5e100>; + resets = <0x2 0x20007 0x2 0x4d8>; + reset-names = "combphy-apb\0combphy"; + rockchip,pipe-grf = <0x63>; + rockchip,pipe-phy-grf = <0x17a>; + rockchip,pcie1ln-sel-bits = <0x100 0x1 0x1 0x0>; + status = "okay"; + phandle = <0x5d>; + }; + + sram@ff001000 { + compatible = "mmio-sram"; + reg = <0x0 0xff001000 0x0 0xef000>; + #address-cells = <0x1>; + #size-cells = <0x1>; + ranges = <0x0 0x0 0xff001000 0xef000>; + + rkvdec-sram@0 { + reg = <0x0 0x78000>; + phandle = <0xb4>; + }; + + rkvdec-sram@78000 { + reg = <0x78000 0x77000>; + phandle = <0xb6>; + }; + }; + + pinctrl { + compatible = "rockchip,rk3588-pinctrl"; + rockchip,grf = <0x17b>; + #address-cells = <0x2>; + #size-cells = <0x2>; + ranges; + phandle = <0x17c>; + + gpio@fd8a0000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfd8a0000 0x0 0x100>; + interrupts = <0x0 0x115 0x4>; + clocks = <0x2 0x284 0x2 0x285>; + gpio-controller; + #gpio-cells = <0x2>; + gpio-ranges = <0x17c 0x0 0x0 0x20>; + interrupt-controller; + #interrupt-cells = <0x2>; + phandle = <0x13d>; + }; + + gpio@fec20000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfec20000 0x0 0x100>; + interrupts = <0x0 0x116 0x4>; + clocks = <0x2 0x7d 0x2 0x7e>; + gpio-controller; + #gpio-cells = <0x2>; + gpio-ranges = <0x17c 0x0 0x20 0x20>; + interrupt-controller; + #interrupt-cells = <0x2>; + phandle = <0x141>; + }; + + gpio@fec30000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfec30000 0x0 0x100>; + interrupts = <0x0 0x117 0x4>; + clocks = <0x2 0x7f 0x2 0x80>; + gpio-controller; + #gpio-cells = <0x2>; + gpio-ranges = <0x17c 0x0 0x40 0x20>; + interrupt-controller; + #interrupt-cells = <0x2>; + phandle = <0x1a4>; + }; + + gpio@fec40000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfec40000 0x0 0x100>; + interrupts = <0x0 0x118 0x4>; + clocks = <0x2 0x81 0x2 0x82>; + gpio-controller; + #gpio-cells = <0x2>; + gpio-ranges = <0x17c 0x0 0x60 0x20>; + interrupt-controller; + #interrupt-cells = <0x2>; + phandle = <0xff>; + }; + + gpio@fec50000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfec50000 0x0 0x100>; + interrupts = <0x0 0x119 0x4>; + clocks = <0x2 0x83 0x2 0x84>; + gpio-controller; + #gpio-cells = <0x2>; + gpio-ranges = <0x17c 0x0 0x80 0x20>; + interrupt-controller; + #interrupt-cells = <0x2>; + phandle = <0xf1>; + }; + + pcfg-pull-up { + bias-pull-up; + phandle = <0x182>; + }; + + pcfg-pull-none { + bias-disable; + phandle = <0x17d>; + }; + + pcfg-pull-none-drv-level-2 { + bias-disable; + drive-strength = <0x2>; + phandle = <0x185>; + }; + + pcfg-pull-up-drv-level-1 { + bias-pull-up; + drive-strength = <0x1>; + phandle = <0x184>; + }; + + pcfg-pull-up-drv-level-2 { + bias-pull-up; + drive-strength = <0x2>; + phandle = <0x17e>; + }; + + pcfg-pull-up-drv-level-6 { + bias-pull-up; + drive-strength = <0x6>; + phandle = <0x183>; + }; + + pcfg-pull-none-smt { + bias-disable; + input-schmitt-enable; + phandle = <0x181>; + }; + + pcfg-pull-none-drv-level-1-smt { + bias-disable; + drive-strength = <0x1>; + input-schmitt-enable; + phandle = <0x180>; + }; + + pcfg-pull-none-drv-level-5-smt { + bias-disable; + drive-strength = <0x5>; + input-schmitt-enable; + phandle = <0x17f>; + }; + + auddsm { + auddsm-pins { + rockchip,pins = <0x3 0x1 0x4 0x17d 0x3 0x2 0x4 0x17d 0x3 0x3 0x4 0x17d 0x3 0x4 0x4 0x17d>; + phandle = <0x132>; + }; + }; + + bt1120 { + bt1120-pins { + rockchip,pins = <0x4 0x8 0x2 0x17d 0x4 0x0 0x2 0x17d 0x4 0x1 0x2 0x17d 0x4 0x2 0x2 0x17d 0x4 0x3 0x2 0x17d 0x4 0x4 0x2 0x17d 0x4 0x5 0x2 0x17d 0x4 0x6 0x2 0x17d 0x4 0x7 0x2 0x17d 0x4 0xa 0x2 0x17d 0x4 0xb 0x2 0x17d 0x4 0xc 0x2 0x17d 0x4 0xd 0x2 0x17d 0x4 0xe 0x2 0x17d 0x4 0xf 0x2 0x17d 0x4 0x10 0x2 0x17d 0x4 0x11 0x2 0x17d>; + phandle = <0x5e>; + }; + }; + + can0 { + can0m0-pins { + rockchip,pins = <0x0 0x10 0xb 0x17d 0x0 0xf 0xb 0x17d>; + phandle = <0x133>; + }; + }; + + can1 { + can1m0-pins { + rockchip,pins = <0x3 0xd 0x9 0x17d 0x3 0xe 0x9 0x17d>; + phandle = <0x134>; + }; + }; + + can2 { + can2m0-pins { + rockchip,pins = <0x3 0x14 0x9 0x17d 0x3 0x15 0x9 0x17d>; + phandle = <0x135>; + }; + }; + + gmac1 { + gmac1-miim { + rockchip,pins = <0x3 0x12 0x1 0x17d 0x3 0x13 0x1 0x17d>; + phandle = <0x100>; + }; + + gmac1-rx-bus2 { + rockchip,pins = <0x3 0x7 0x1 0x17d 0x3 0x8 0x1 0x17d 0x3 0x9 0x1 0x17d>; + phandle = <0x102>; + }; + + gmac1-tx-bus2 { + rockchip,pins = <0x3 0xb 0x1 0x17d 0x3 0xc 0x1 0x17d 0x3 0xd 0x1 0x17d>; + phandle = <0x101>; + }; + + gmac1-rgmii-clk { + rockchip,pins = <0x3 0x5 0x1 0x17d 0x3 0x4 0x1 0x17d>; + phandle = <0x103>; + }; + + gmac1-rgmii-bus { + rockchip,pins = <0x3 0x2 0x1 0x17d 0x3 0x3 0x1 0x17d 0x3 0x0 0x1 0x17d 0x3 0x1 0x1 0x17d>; + phandle = <0x104>; + }; + }; + + hdmi { + hdmim0-tx0-cec { + rockchip,pins = <0x4 0x11 0x5 0x17d>; + phandle = <0xec>; + }; + + hdmim0-tx0-hpd { + rockchip,pins = <0x1 0x5 0x5 0x17d>; + phandle = <0xed>; + }; + + hdmim0-tx0-scl { + rockchip,pins = <0x4 0xf 0x5 0x17f>; + phandle = <0xee>; + }; + + hdmim0-tx0-sda { + rockchip,pins = <0x4 0x10 0x5 0x180>; + phandle = <0xef>; + }; + + hdmim0-tx1-hpd { + rockchip,pins = <0x1 0x6 0x5 0x17d>; + phandle = <0x190>; + }; + + hdmim1-rx { + rockchip,pins = <0x3 0x19 0x5 0x17d 0x3 0x1a 0x5 0x181 0x3 0x1b 0x5 0x181 0x3 0x1c 0x5 0x17d>; + phandle = <0x19a>; + }; + + hdmim1-tx1-scl { + rockchip,pins = <0x3 0x16 0x5 0x17f>; + phandle = <0x191>; + }; + + hdmim1-tx1-sda { + rockchip,pins = <0x3 0x15 0x5 0x180>; + phandle = <0x192>; + }; + + hdmim2-tx1-cec { + rockchip,pins = <0x3 0x14 0x5 0x17d>; + phandle = <0x18f>; + }; + }; + + i2c0 { + i2c0m2-xfer { + rockchip,pins = <0x0 0x19 0x3 0x181 0x0 0x1a 0x3 0x181>; + phandle = <0x64>; + }; + }; + + i2c1 { + i2c1m2-xfer { + rockchip,pins = <0x0 0x1c 0x9 0x181 0x0 0x1d 0x9 0x181>; + phandle = <0x136>; + }; + }; + + i2c2 { + i2c2m0-xfer { + rockchip,pins = <0x0 0xf 0x9 0x181 0x0 0x10 0x9 0x181>; + phandle = <0x137>; + }; + }; + + i2c3 { + i2c3m0-xfer { + rockchip,pins = <0x1 0x11 0x9 0x181 0x1 0x10 0x9 0x181>; + phandle = <0x138>; + }; + }; + + i2c4 { + i2c4m3-xfer { + rockchip,pins = <0x1 0x3 0x9 0x181 0x1 0x2 0x9 0x181>; + phandle = <0x13b>; + }; + }; + + i2c5 { + i2c5m0-xfer { + rockchip,pins = <0x3 0x17 0x9 0x181 0x3 0x18 0x9 0x181>; + phandle = <0x142>; + }; + }; + + i2c6 { + i2c6m0-xfer { + rockchip,pins = <0x0 0x18 0x9 0x181 0x0 0x17 0x9 0x181>; + phandle = <0x16c>; + }; + }; + + i2c7 { + i2c7m0-xfer { + rockchip,pins = <0x1 0x18 0x9 0x181 0x1 0x19 0x9 0x181>; + phandle = <0x16d>; + }; + }; + + i2c8 { + i2c8m0-xfer { + rockchip,pins = <0x4 0x1a 0x9 0x181 0x4 0x1b 0x9 0x181>; + phandle = <0x16e>; + }; + }; + + i2s0 { + i2s0-lrck { + rockchip,pins = <0x1 0x15 0x1 0x17d>; + phandle = <0x10e>; + }; + + i2s0-mclk { + rockchip,pins = <0x1 0x12 0x1 0x17d>; + phandle = <0x13a>; + }; + + i2s0-sclk { + rockchip,pins = <0x1 0x13 0x1 0x17d>; + phandle = <0x10f>; + }; + + i2s0-sdi0 { + rockchip,pins = <0x1 0x1c 0x2 0x17d>; + phandle = <0x110>; + }; + + i2s0-sdo0 { + rockchip,pins = <0x1 0x17 0x1 0x17d>; + phandle = <0x111>; + }; + }; + + i2s1 { + i2s1m0-lrck { + rockchip,pins = <0x4 0x2 0x3 0x17d>; + phandle = <0x112>; + }; + + i2s1m0-sclk { + rockchip,pins = <0x4 0x1 0x3 0x17d>; + phandle = <0x113>; + }; + + i2s1m0-sdi0 { + rockchip,pins = <0x4 0x5 0x3 0x17d>; + phandle = <0x114>; + }; + + i2s1m0-sdi1 { + rockchip,pins = <0x4 0x6 0x3 0x17d>; + phandle = <0x115>; + }; + + i2s1m0-sdi2 { + rockchip,pins = <0x4 0x7 0x3 0x17d>; + phandle = <0x116>; + }; + + i2s1m0-sdi3 { + rockchip,pins = <0x4 0x8 0x3 0x17d>; + phandle = <0x117>; + }; + + i2s1m0-sdo0 { + rockchip,pins = <0x4 0x9 0x3 0x17d>; + phandle = <0x118>; + }; + + i2s1m0-sdo1 { + rockchip,pins = <0x4 0xa 0x3 0x17d>; + phandle = <0x119>; + }; + + i2s1m0-sdo2 { + rockchip,pins = <0x4 0xb 0x3 0x17d>; + phandle = <0x11a>; + }; + + i2s1m0-sdo3 { + rockchip,pins = <0x4 0xc 0x3 0x17d>; + phandle = <0x11b>; + }; + }; + + i2s2 { + i2s2m1-lrck { + rockchip,pins = <0x3 0xe 0x3 0x17d>; + phandle = <0x11c>; + }; + + i2s2m1-sclk { + rockchip,pins = <0x3 0xd 0x3 0x17d>; + phandle = <0x11d>; + }; + + i2s2m1-sdi { + rockchip,pins = <0x3 0xa 0x3 0x17d>; + phandle = <0x11e>; + }; + + i2s2m1-sdo { + rockchip,pins = <0x3 0xb 0x3 0x17d>; + phandle = <0x11f>; + }; + }; + + i2s3 { + i2s3-lrck { + rockchip,pins = <0x3 0x2 0x3 0x17d>; + phandle = <0x120>; + }; + + i2s3-sclk { + rockchip,pins = <0x3 0x1 0x3 0x17d>; + phandle = <0x121>; + }; + + i2s3-sdi { + rockchip,pins = <0x3 0x4 0x3 0x17d>; + phandle = <0x122>; + }; + + i2s3-sdo { + rockchip,pins = <0x3 0x3 0x3 0x17d>; + phandle = <0x123>; + }; + }; + + mipi { + mipim0-camera1-clk { + rockchip,pins = <0x1 0xe 0x2 0x17d>; + phandle = <0x13c>; + }; + }; + + pdm0 { + pdm0m0-clk { + rockchip,pins = <0x1 0x16 0x3 0x17d>; + phandle = <0x124>; + }; + + pdm0m0-clk1 { + rockchip,pins = <0x1 0x14 0x3 0x17d>; + phandle = <0x125>; + }; + + pdm0m0-sdi0 { + rockchip,pins = <0x1 0x1d 0x3 0x17d>; + phandle = <0x126>; + }; + + pdm0m0-sdi1 { + rockchip,pins = <0x1 0x19 0x3 0x17d>; + phandle = <0x127>; + }; + + pdm0m0-sdi2 { + rockchip,pins = <0x1 0x1a 0x3 0x17d>; + phandle = <0x128>; + }; + + pdm0m0-sdi3 { + rockchip,pins = <0x1 0x1b 0x3 0x17d>; + phandle = <0x129>; + }; + }; + + pdm1 { + pdm1m0-clk { + rockchip,pins = <0x4 0x1d 0x2 0x17d>; + phandle = <0x12a>; + }; + + pdm1m0-clk1 { + rockchip,pins = <0x4 0x1c 0x2 0x17d>; + phandle = <0x12b>; + }; + + pdm1m0-sdi0 { + rockchip,pins = <0x4 0x1b 0x2 0x17d>; + phandle = <0x12c>; + }; + + pdm1m0-sdi1 { + rockchip,pins = <0x4 0x1a 0x2 0x17d>; + phandle = <0x12d>; + }; + + pdm1m0-sdi2 { + rockchip,pins = <0x4 0x19 0x2 0x17d>; + phandle = <0x12e>; + }; + + pdm1m0-sdi3 { + rockchip,pins = <0x4 0x18 0x2 0x17d>; + phandle = <0x12f>; + }; + }; + + pmic { + pmic-pins { + rockchip,pins = <0x0 0x7 0x0 0x182 0x0 0x2 0x1 0x17d 0x0 0x3 0x1 0x17d 0x0 0x11 0x1 0x17d 0x0 0x12 0x1 0x17d 0x0 0x13 0x1 0x17d 0x0 0x1e 0x1 0x17d>; + phandle = <0x14a>; + }; + }; + + pwm0 { + pwm0m0-pins { + rockchip,pins = <0x0 0xf 0x3 0x17d>; + phandle = <0x68>; + }; + }; + + pwm1 { + pwm1m0-pins { + rockchip,pins = <0x0 0x10 0x3 0x17d>; + phandle = <0x69>; + }; + }; + + pwm2 { + pwm2m0-pins { + rockchip,pins = <0x0 0x14 0x3 0x17d>; + phandle = <0x6a>; + }; + }; + + pwm3 { + pwm3m0-pins { + rockchip,pins = <0x0 0x1c 0x3 0x17d>; + phandle = <0x6b>; + }; + }; + + pwm4 { + pwm4m0-pins { + rockchip,pins = <0x0 0x15 0xb 0x17d>; + phandle = <0x15d>; + }; + }; + + pwm5 { + pwm5m0-pins { + rockchip,pins = <0x0 0x9 0x3 0x17d>; + phandle = <0x15e>; + }; + }; + + pwm6 { + pwm6m0-pins { + rockchip,pins = <0x0 0x17 0xb 0x17d>; + phandle = <0x15f>; + }; + }; + + pwm7 { + pwm7m0-pins { + rockchip,pins = <0x0 0x18 0xb 0x17d>; + phandle = <0x160>; + }; + }; + + pwm8 { + pwm8m0-pins { + rockchip,pins = <0x3 0x7 0xb 0x17d>; + phandle = <0x161>; + }; + }; + + pwm9 { + pwm9m0-pins { + rockchip,pins = <0x3 0x8 0xb 0x17d>; + phandle = <0x162>; + }; + }; + + pwm10 { + pwm10m0-pins { + rockchip,pins = <0x3 0x0 0xb 0x17d>; + phandle = <0x163>; + }; + }; + + pwm11 { + pwm11m0-pins { + rockchip,pins = <0x3 0x1 0xb 0x17d>; + phandle = <0x164>; + }; + }; + + pwm12 { + pwm12m0-pins { + rockchip,pins = <0x3 0xd 0xb 0x17d>; + phandle = <0x165>; + }; + }; + + pwm13 { + pwm13m0-pins { + rockchip,pins = <0x3 0xe 0xb 0x17d>; + phandle = <0x166>; + }; + }; + + pwm14 { + pwm14m0-pins { + rockchip,pins = <0x3 0x12 0xb 0x17d>; + phandle = <0x167>; + }; + }; + + pwm15 { + pwm15m0-pins { + rockchip,pins = <0x3 0x13 0xb 0x17d>; + phandle = <0x168>; + }; + }; + + sdio { + sdiom1-pins { + rockchip,pins = <0x3 0x5 0x2 0x17d 0x3 0x4 0x2 0x182 0x3 0x0 0x2 0x182 0x3 0x1 0x2 0x182 0x3 0x2 0x2 0x182 0x3 0x3 0x2 0x182>; + phandle = <0x10c>; + }; + }; + + sdmmc { + sdmmc-bus4 { + rockchip,pins = <0x4 0x18 0x1 0x17e 0x4 0x19 0x1 0x17e 0x4 0x1a 0x1 0x17e 0x4 0x1b 0x1 0x17e>; + phandle = <0x109>; + }; + + sdmmc-clk { + rockchip,pins = <0x4 0x1d 0x1 0x17e>; + phandle = <0x106>; + }; + + sdmmc-cmd { + rockchip,pins = <0x4 0x1c 0x1 0x17e>; + phandle = <0x107>; + }; + + sdmmc-det { + rockchip,pins = <0x0 0x4 0x1 0x182>; + phandle = <0x108>; + }; + + sd-s0-pwr { + rockchip,pins = <0x0 0xf 0x0 0x182>; + phandle = <0x1c5>; + }; + }; + + spdif0 { + spdif0m0-tx { + rockchip,pins = <0x1 0xe 0x3 0x17d>; + phandle = <0x130>; + }; + }; + + spdif1 { + spdif1m0-tx { + rockchip,pins = <0x1 0xf 0x3 0x17d>; + phandle = <0x131>; + }; + }; + + spi0 { + spi0m3-pins { + rockchip,pins = <0x3 0x1b 0x8 0x183 0x3 0x19 0x8 0x183 0x3 0x1a 0x8 0x183>; + phandle = <0x144>; + }; + + spi0m3-cs0 { + rockchip,pins = <0x3 0x1c 0x8 0x183>; + phandle = <0x143>; + }; + }; + + spi1 { + spi1m1-pins { + rockchip,pins = <0x3 0x11 0x8 0x183 0x3 0x10 0x8 0x183 0x3 0xf 0x8 0x183>; + phandle = <0x147>; + }; + + spi1m1-cs0 { + rockchip,pins = <0x3 0x12 0x8 0x183>; + phandle = <0x145>; + }; + + spi1m1-cs1 { + rockchip,pins = <0x3 0x13 0x8 0x183>; + phandle = <0x146>; + }; + }; + + spi2 { + spi2m2-pins { + rockchip,pins = <0x0 0x5 0x1 0x184 0x0 0xb 0x1 0x184 0x0 0x6 0x1 0x184>; + phandle = <0x149>; + }; + + spi2m2-cs0 { + rockchip,pins = <0x0 0x9 0x1 0x184>; + phandle = <0x148>; + }; + }; + + spi3 { + spi3m1-pins { + rockchip,pins = <0x4 0xf 0x8 0x183 0x4 0xd 0x8 0x183 0x4 0xe 0x8 0x183>; + phandle = <0x153>; + }; + + spi3m1-cs0 { + rockchip,pins = <0x4 0x10 0x8 0x183>; + phandle = <0x151>; + }; + + spi3m1-cs1 { + rockchip,pins = <0x4 0x11 0x8 0x183>; + phandle = <0x152>; + }; + }; + + spi4 { + spi4m0-pins { + rockchip,pins = <0x1 0x12 0x8 0x183 0x1 0x10 0x8 0x183 0x1 0x11 0x8 0x183>; + phandle = <0x171>; + }; + + spi4m0-cs0 { + rockchip,pins = <0x1 0x13 0x8 0x183>; + phandle = <0x16f>; + }; + + spi4m0-cs1 { + rockchip,pins = <0x1 0x14 0x8 0x183>; + phandle = <0x170>; + }; + }; + + tsadc { + tsadc-shut { + rockchip,pins = <0x0 0x1 0x2 0x17d>; + phandle = <0x16a>; + }; + }; + + uart0 { + uart0m2-xfer { + rockchip,pins = <0x4 0x4 0xa 0x182 0x4 0x3 0xa 0x182>; + phandle = <0x67>; + }; + }; + + uart1 { + uart1m1-xfer { + rockchip,pins = <0x1 0xf 0xa 0x182 0x1 0xe 0xa 0x182>; + phandle = <0x154>; + }; + }; + + uart2 { + uart2m0-xfer { + rockchip,pins = <0x0 0xe 0xa 0x182 0x0 0xd 0xa 0x182>; + phandle = <0x1c2>; + }; + + uart2m1-xfer { + rockchip,pins = <0x4 0x19 0xa 0x182 0x4 0x18 0xa 0x182>; + phandle = <0x155>; + }; + }; + + uart3 { + uart3m2-xfer { + rockchip,pins = <0x4 0x6 0xa 0x182 0x4 0x5 0xa 0x182>; + phandle = <0x156>; + }; + }; + + uart4 { + uart4m2-xfer { + rockchip,pins = <0x1 0xa 0xa 0x182 0x1 0xb 0xa 0x182>; + phandle = <0x157>; + }; + }; + + uart5 { + uart5m1-xfer { + rockchip,pins = <0x3 0x15 0xa 0x182 0x3 0x14 0xa 0x182>; + phandle = <0x158>; + }; + }; + + uart6 { + uart6m1-xfer { + rockchip,pins = <0x1 0x0 0xa 0x182 0x1 0x1 0xa 0x182>; + phandle = <0x159>; + }; + }; + + uart7 { + uart7m2-xfer { + rockchip,pins = <0x1 0xc 0xa 0x182 0x1 0xd 0xa 0x182>; + phandle = <0x15a>; + }; + }; + + uart8 { + uart8m1-xfer { + rockchip,pins = <0x3 0x3 0xa 0x182 0x3 0x2 0xa 0x182>; + phandle = <0x15b>; + }; + }; + + uart9 { + uart9m1-xfer { + rockchip,pins = <0x4 0xd 0xa 0x182 0x4 0xc 0xa 0x182>; + phandle = <0x15c>; + }; + }; + + gpio-func { + tsadc-gpio-func { + rockchip,pins = <0x0 0x1 0x0 0x17d>; + phandle = <0x169>; + }; + }; + + gmac0 { + gmac0-miim { + rockchip,pins = <0x4 0x14 0x1 0x17d 0x4 0x15 0x1 0x17d>; + phandle = <0x1a5>; + }; + + gmac0-rx-bus2 { + rockchip,pins = <0x2 0x11 0x1 0x17d 0x2 0x12 0x1 0x17d 0x4 0x12 0x1 0x17d>; + phandle = <0x1a7>; + }; + + gmac0-tx-bus2 { + rockchip,pins = <0x2 0xe 0x1 0x17d 0x2 0xf 0x1 0x17d 0x2 0x10 0x1 0x17d>; + phandle = <0x1a6>; + }; + + gmac0-rgmii-clk { + rockchip,pins = <0x2 0x8 0x1 0x17d 0x2 0xb 0x1 0x17d>; + phandle = <0x1a8>; + }; + + gmac0-rgmii-bus { + rockchip,pins = <0x2 0x6 0x1 0x17d 0x2 0x7 0x1 0x17d 0x2 0x9 0x1 0x17d 0x2 0xa 0x1 0x17d>; + phandle = <0x1a9>; + }; + }; + + cam { + mipidphy0-pwr { + rockchip,pins = <0x1 0x1a 0x0 0x17d>; + phandle = <0x1c3>; + }; + }; + + lcd { + lcd-rst-gpio { + rockchip,pins = <0x2 0xc 0x0 0x17d>; + phandle = <0xe0>; + }; + }; + + touch { + touch-gpio { + rockchip,pins = <0x1 0x1 0x0 0x182 0x1 0x0 0x0 0x17d>; + phandle = <0x140>; + }; + }; + }; + + usbdrd3_1 { + compatible = "rockchip,rk3588-dwc3\0rockchip,rk3399-dwc3"; + clocks = <0x2 0x1a6 0x2 0x1a5 0x2 0x1a4>; + clock-names = "ref\0suspend\0bus"; + #address-cells = <0x2>; + #size-cells = <0x2>; + ranges; + status = "okay"; + + usb@fc400000 { + compatible = "snps,dwc3"; + reg = <0x0 0xfc400000 0x0 0x400000>; + interrupts = <0x0 0xdd 0x4>; + power-domains = <0x50 0x1f>; + resets = <0x2 0x2a7>; + reset-names = "usb3-otg"; + dr_mode = "host"; + phys = <0x189 0x18a>; + phy-names = "usb2-phy\0usb3-phy"; + phy_type = "utmi_wide"; + snps,dis_enblslpm_quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + snps,parkmode-disable-ss-quirk; + status = "okay"; + }; + }; + + syscon@fd5b8000 { + compatible = "rockchip,pcie30-phy-grf\0syscon"; + reg = <0x0 0xfd5b8000 0x0 0x10000>; + phandle = <0x1b1>; + }; + + syscon@fd5c0000 { + compatible = "rockchip,pipe-phy-grf\0syscon"; + reg = <0x0 0xfd5c0000 0x0 0x100>; + phandle = <0x1b0>; + }; + + syscon@fd5cc000 { + compatible = "rockchip,rk3588-usbdpphy-grf\0syscon"; + reg = <0x0 0xfd5cc000 0x0 0x4000>; + phandle = <0x1ad>; + }; + + syscon@fd5d4000 { + compatible = "rockchip,rk3588-usb2phy-grf\0syscon\0simple-mfd"; + reg = <0x0 0xfd5d4000 0x0 0x4000>; + #address-cells = <0x1>; + #size-cells = <0x1>; + phandle = <0x1ac>; + + usb2-phy@4000 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0x4000 0x10>; + interrupts = <0x0 0x18a 0x4>; + resets = <0x2 0xc0048 0x2 0x489>; + reset-names = "phy\0apb"; + clocks = <0x2 0x2b5>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy1"; + #clock-cells = <0x0>; + rockchip,usbctrl-grf = <0x61>; + status = "okay"; + phandle = <0x1ae>; + + otg-port { + #phy-cells = <0x0>; + status = "okay"; + phandle = <0x189>; + }; + }; + }; + + syscon@fd5e4000 { + compatible = "rockchip,rk3588-hdptxphy-grf\0syscon"; + reg = <0x0 0xfd5e4000 0x0 0x100>; + phandle = <0x1ab>; + }; + + ethernet@fe1b0000 { + local-mac-address = [42 ae fd 14 a7 64]; + compatible = "rockchip,rk3588-gmac\0snps,dwmac-4.20a"; + reg = <0x0 0xfe1b0000 0x0 0x10000>; + interrupts = <0x0 0xe3 0x4 0x0 0xe2 0x4>; + interrupt-names = "macirq\0eth_wake_irq"; + rockchip,grf = <0xb1>; + rockchip,php_grf = <0x63>; + clocks = <0x2 0x144 0x2 0x145 0x2 0x167 0x2 0x16c 0x2 0x142>; + clock-names = "stmmaceth\0clk_mac_ref\0pclk_mac\0aclk_mac\0ptp_ref"; + resets = <0x2 0x20a>; + reset-names = "stmmaceth"; + power-domains = <0x50 0x21>; + snps,mixed-burst; + snps,tso; + snps,axi-config = <0x1a1>; + snps,mtl-rx-config = <0x1a2>; + snps,mtl-tx-config = <0x1a3>; + status = "okay"; + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + snps,reset-gpio = <0x1a4 0xb 0x1>; + snps,reset-active-low; + snps,reset-delays-us = <0x0 0x4e20 0x186a0>; + pinctrl-names = "default"; + pinctrl-0 = <0x1a5 0x1a6 0x1a7 0x1a8 0x1a9>; + tx_delay = <0x44>; + phy-handle = <0x1aa>; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <0x1>; + #size-cells = <0x0>; + + phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + phandle = <0x1aa>; + }; + }; + + stmmac-axi-config { + snps,wr_osr_lmt = <0x4>; + snps,rd_osr_lmt = <0x8>; + snps,blen = <0x0 0x0 0x0 0x0 0x10 0x8 0x4>; + phandle = <0x1a1>; + }; + + rx-queues-config { + snps,rx-queues-to-use = <0x2>; + phandle = <0x1a2>; + + queue0 { + }; + + queue1 { + }; + }; + + tx-queues-config { + snps,tx-queues-to-use = <0x2>; + phandle = <0x1a3>; + + queue0 { + }; + + queue1 { + }; + }; + }; + + phy@fed90000 { + compatible = "rockchip,rk3588-usbdp-phy"; + reg = <0x0 0xfed90000 0x0 0x10000>; + rockchip,u2phy-grf = <0x1ac>; + rockchip,usb-grf = <0x61>; + rockchip,usbdpphy-grf = <0x1ad>; + rockchip,vo-grf = <0xe7>; + clocks = <0x2 0x2b6 0x2 0x280 0x2 0x26a 0x1ae>; + clock-names = "refclk\0immortal\0pclk\0utmi"; + resets = <0x2 0x2f 0x2 0x30 0x2 0x31 0x2 0x32 0x2 0x484>; + reset-names = "init\0cmn\0lane\0pcs_apb\0pma_apb"; + status = "okay"; + + dp-port { + #phy-cells = <0x0>; + status = "okay"; + phandle = <0x18b>; + }; + + u3-port { + #phy-cells = <0x0>; + status = "okay"; + phandle = <0x18a>; + }; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <0x1b2 0x1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <0x1b7740>; + poll-interval = <0x64>; + + vol-up-key { + label = "volume up"; + linux,code = <0x73>; + press-threshold-microvolt = <0x4268>; + }; + + vol-down-key { + label = "volume down"; + linux,code = <0x72>; + press-threshold-microvolt = <0x65ce8>; + }; + + menu-key { + label = "menu"; + linux,code = <0x8b>; + press-threshold-microvolt = <0xd9490>; + }; + + back-key { + label = "back"; + linux,code = <0x9e>; + press-threshold-microvolt = <0x12d838>; + }; + }; + + backlight { + compatible = "pwm-backlight"; + brightness-levels = <0x0 0x14 0x14 0x15 0x15 0x16 0x16 0x17 0x17 0x18 0x18 0x19 0x19 0x1a 0x1a 0x1b 0x1b 0x1c 0x1c 0x1d 0x1d 0x1e 0x1e 0x1f 0x1f 0x20 0x20 0x21 0x21 0x22 0x22 0x23 0x23 0x24 0x24 0x25 0x25 0x26 0x26 0x27 0x28 0x29 0x2a 0x2b 0x2c 0x2d 0x2e 0x2f 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3a 0x3b 0x3c 0x3d 0x3e 0x3f 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4a 0x4b 0x4c 0x4d 0x4e 0x4f 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5a 0x5b 0x5c 0x5d 0x5e 0x5f 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6a 0x6b 0x6c 0x6d 0x6e 0x6f 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7a 0x7b 0x7c 0x7d 0x7e 0x7f 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9a 0x9b 0x9c 0x9d 0x9e 0x9f 0xa0 0xa1 0xa2 0xa3 0xa4 0xa5 0xa6 0xa7 0xa8 0xa9 0xaa 0xab 0xac 0xad 0xae 0xaf 0xb0 0xb1 0xb2 0xb3 0xb4 0xb5 0xb6 0xb7 0xb8 0xb9 0xba 0xbb 0xbc 0xbd 0xbe 0xbf 0xc0 0xc1 0xc2 0xc3 0xc4 0xc5 0xc6 0xc7 0xc8 0xc9 0xca 0xcb 0xcc 0xcd 0xce 0xcf 0xd0 0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 0xd7 0xd8 0xd9 0xda 0xdb 0xdc 0xdd 0xde 0xdf 0xe0 0xe1 0xe2 0xe3 0xe4 0xe5 0xe6 0xe7 0xe8 0xe9 0xea 0xeb 0xec 0xed 0xee 0xef 0xf0 0xf1 0xf2 0xf3 0xf4 0xf5 0xf6 0xf7 0xf8 0xf9 0xfa 0xfb 0xfc 0xfd 0xfe 0xff>; + default-brightness-level = <0xc8>; + pwms = <0x1b3 0x0 0x61a8 0x0>; + status = "okay"; + phandle = <0xde>; + }; + + hdmi0-sound { + status = "okay"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <0x80>; + rockchip,card-name = "rockchip-hdmi0"; + rockchip,cpu = <0x1b4>; + rockchip,codec = <0x1b5>; + rockchip,jack-det; + }; + + leds { + compatible = "gpio-leds"; + + work { + gpios = <0xff 0xf 0x0>; + linux,default-trigger = "heartbeat"; + }; + }; + + test-power { + status = "okay"; + }; + + vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0xb71b00>; + regulator-max-microvolt = <0xb71b00>; + phandle = <0x1c0>; + }; + + vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x4c4b40>; + regulator-max-microvolt = <0x4c4b40>; + vin-supply = <0x1c0>; + phandle = <0x65>; + }; + + vcc5v0-usbdcin { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usbdcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x4c4b40>; + regulator-max-microvolt = <0x4c4b40>; + vin-supply = <0x1c0>; + phandle = <0x1c1>; + }; + + vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x4c4b40>; + regulator-max-microvolt = <0x4c4b40>; + vin-supply = <0x1c1>; + phandle = <0x1c4>; + }; + + chosen { + bootargs = "storagemedia=emmc androidboot.storagemedia=emmc androidboot.mode=normal androidboot.verifiedbootstate=orange ro rootwait earlycon=uart8250,mmio32,0xfeb50000 console=ttyFIQ0 irqchip.gicv3_pseudo_nmi=0 root=PARTLABEL=rootfs rootfstype=ext4 overlayroot=device:dev=PARTLABEL=userdata,fstype=ext4,mkfs=1 coherent_pool=1m systemd.gpt_auto=0 cgroup_enable=memory swapaccount=1 rockchip_pm_domains.always_on=1"; + }; + + cspmu@fd10c000 { + compatible = "rockchip,cspmu"; + reg = <0x0 0xfd10c000 0x0 0x1000 0x0 0xfd10d000 0x0 0x1000 0x0 0xfd10e000 0x0 0x1000 0x0 0xfd10f000 0x0 0x1000 0x0 0xfd12c000 0x0 0x1000 0x0 0xfd12d000 0x0 0x1000 0x0 0xfd12e000 0x0 0x1000 0x0 0xfd12f000 0x0 0x1000>; + }; + + debug@fd104000 { + compatible = "rockchip,debug"; + reg = <0x0 0xfd104000 0x0 0x1000 0x0 0xfd105000 0x0 0x1000 0x0 0xfd106000 0x0 0x1000 0x0 0xfd107000 0x0 0x1000 0x0 0xfd124000 0x0 0x1000 0x0 0xfd125000 0x0 0x1000 0x0 0xfd126000 0x0 0x1000 0x0 0xfd127000 0x0 0x1000>; + }; + + fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <0x2>; + rockchip,wake-irq = <0x0>; + rockchip,irq-mode-enable = <0x1>; + rockchip,baudrate = <0x16e360>; + interrupts = <0x0 0x1a7 0x8>; + pinctrl-names = "default"; + pinctrl-0 = <0x1c2>; + status = "okay"; + }; + + reserved-memory { + #address-cells = <0x2>; + #size-cells = <0x2>; + ranges; + + cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x800000>; + linux,cma-default; + }; + + drm-logo@00000000 { + compatible = "rockchip,drm-logo"; + reg = <0x0 0xedf00000 0x0 0xb8000>; + phandle = <0x30>; + }; + + drm-cubic-lut@00000000 { + compatible = "rockchip,drm-cubic-lut"; + reg = <0x0 0x0 0x0 0x0>; + }; + + ramoops@110000 { + compatible = "ramoops"; + reg = <0x0 0x110000 0x0 0xf0000>; + record-size = <0x20000>; + console-size = <0x80000>; + ftrace-size = <0x0>; + pmsg-size = <0x50000>; + }; + }; + + vcc-mipidcphy0-regulator { + compatible = "regulator-fixed"; + gpio = <0x141 0x1a 0x0>; + pinctrl-names = "default"; + pinctrl-0 = <0x1c3>; + regulator-name = "vcc_mipidphy0"; + enable-active-high; + phandle = <0x13e>; + }; + + vcc5v0-host { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <0x4c4b40>; + regulator-max-microvolt = <0x4c4b40>; + enable-active-high; + gpio = <0xf1 0x1 0x0>; + vin-supply = <0x1c4>; + pinctrl-names = "default"; + phandle = <0x62>; + }; + + vcc-3v3-sd-s0-regulator { + compatible = "regulator-fixed"; + enable-active-low; + gpio = <0x13d 0xf 0x1>; + pinctrl-names = "default"; + pinctrl-0 = <0x1c5>; + regulator-always-on; + regulator-max-microvolt = <0x2dc6c0>; + regulator-min-microvolt = <0x2dc6c0>; + regulator-name = "vcc_3v3_sd_s0"; + vin-supply = <0x1c6>; + phandle = <0x10b>; + }; + + vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x10c8e0>; + regulator-max-microvolt = <0x10c8e0>; + vin-supply = <0x65>; + phandle = <0x150>; + }; + + vcc3v3-lcd0-n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd0_n"; + regulator-boot-on; + enable-active-high; + gpio = <0x1a4 0x15 0x0>; + vin-supply = <0x1c7>; + phandle = <0xdf>; + }; + + i2s0-sound { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <0x100>; + simple-audio-card,name = "rockchip,es8311"; + + simple-audio-card,dai-link@0 { + format = "i2s"; + + cpu { + sound-dai = <0x1c8>; + }; + + codec { + sound-dai = <0x1c9>; + }; + }; + }; +}; diff --git a/platform/aarch64/sysoul_x3300-scmi/image/dts/zone0.dts b/platform/aarch64/sysoul_x3300-scmi/image/dts/zone0.dts new file mode 100644 index 000000000..7eec33cb7 --- /dev/null +++ b/platform/aarch64/sysoul_x3300-scmi/image/dts/zone0.dts @@ -0,0 +1,14132 @@ +/dts-v1/; + +/ { + serial-number = "c377a354961ceca2"; + compatible = "rockchip,rk3588-evb7-v11\0rockchip,rk3588"; + interrupt-parent = <0x01>; + #address-cells = <0x02>; + #size-cells = <0x02>; + model = "Rockchip RK3588 EVB7 V11 Board"; + + memory { + reg = <0x00 0x200000 0x00 0x8200000 + 0x00 0x9400000 0x00 0xe6c00000 + 0x01 0x00 0x02 0xfc000000 + 0x03 0xfc500000 0x00 0x3a00000 + 0x04 0xf0000000 0x00 0x10000000 + 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>; + device_type = "memory"; + }; + + aliases { + csi2dcphy0 = "/csi2-dcphy0"; + csi2dcphy1 = "/csi2-dcphy1"; + csi2dphy0 = "/csi2-dphy0"; + csi2dphy1 = "/csi2-dphy1"; + csi2dphy2 = "/csi2-dphy2"; + csi2dphy3 = "/csi2-dphy3"; + csi2dphy4 = "/csi2-dphy4"; + csi2dphy5 = "/csi2-dphy5"; + dsi0 = "/dsi@fde20000"; + dsi1 = "/dsi@fde30000"; + ethernet1 = "/ethernet@fe1c0000"; + gpio0 = "/pinctrl/gpio@fd8a0000"; + gpio1 = "/pinctrl/gpio@fec20000"; + gpio2 = "/pinctrl/gpio@fec30000"; + gpio3 = "/pinctrl/gpio@fec40000"; + gpio4 = "/pinctrl/gpio@fec50000"; + i2c0 = "/i2c@fd880000"; + i2c1 = "/i2c@fea90000"; + i2c2 = "/i2c@feaa0000"; + i2c3 = "/i2c@feab0000"; + i2c4 = "/i2c@feac0000"; + i2c5 = "/i2c@fead0000"; + i2c6 = "/i2c@fec80000"; + i2c7 = "/i2c@fec90000"; + i2c8 = "/i2c@feca0000"; + rkcif_mipi_lvds0 = "/rkcif-mipi-lvds"; + rkcif_mipi_lvds1 = "/rkcif-mipi-lvds1"; + rkcif_mipi_lvds2 = "/rkcif-mipi-lvds2"; + rkcif_mipi_lvds3 = "/rkcif-mipi-lvds3"; + rkcif_mipi_lvds4 = "/rkcif-mipi-lvds4"; + rkcif_mipi_lvds5 = "/rkcif-mipi-lvds5"; + rkvdec0 = "/rkvdec-core@fdc38000"; + rkvdec1 = "/rkvdec-core@fdc48000"; + rkvenc0 = "/rkvenc-core@fdbd0000"; + rkvenc1 = "/rkvenc-core@fdbe0000"; + jpege0 = "/jpege-core@fdba0000"; + jpege1 = "/jpege-core@fdba4000"; + jpege2 = "/jpege-core@fdba8000"; + jpege3 = "/jpege-core@fdbac000"; + serial0 = "/serial@fd890000"; + serial1 = "/serial@feb40000"; + serial2 = "/serial@feb50000"; + serial3 = "/serial@feb60000"; + serial4 = "/serial@feb70000"; + serial5 = "/serial@feb80000"; + serial6 = "/serial@feb90000"; + serial7 = "/serial@feba0000"; + serial8 = "/serial@febb0000"; + serial9 = "/serial@febc0000"; + spi0 = "/spi@feb00000"; + spi1 = "/spi@feb10000"; + spi2 = "/spi@feb20000"; + spi3 = "/spi@feb30000"; + spi4 = "/spi@fecb0000"; + spi5 = "/spi@fe2b0000"; + hdcp0 = "/hdcp@fde40000"; + hdcp1 = "/hdcp@fde70000"; + dp0 = "/dp@fde50000"; + dp1 = "/dp@fde60000"; + edp0 = "/edp@fdec0000"; + edp1 = "/edp@fded0000"; + ethernet0 = "/ethernet@fe1b0000"; + hdptx0 = "/phy@fed60000"; + hdptx1 = "/phy@fed70000"; + hdptxhdmi0 = "/hdmiphy@fed60000"; + hdptxhdmi1 = "/hdmiphy@fed70000"; + hdmi0 = "/hdmi@fde80000"; + hdmi1 = "/hdmi@fdea0000"; + hdmirx0 = "/hdmirx-controller@fdee0000"; + usbdp0 = "/phy@fed80000"; + usbdp1 = "/phy@fed90000"; + mmc0 = "/mmc@fe2e0000"; + mmc1 = "/mmc@fe2c0000"; + mmc2 = "/mmc@fe2d0000"; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <0x02>; + #size-cells = <0x02>; + ranges; + + spll { + compatible = "fixed-clock"; + #clock-cells = <0x00>; + clock-frequency = <0x29d7ab80>; + clock-output-names = "spll"; + phandle = <0x20c>; + }; + + xin32k { + compatible = "fixed-clock"; + #clock-cells = <0x00>; + clock-frequency = <0x8000>; + clock-output-names = "xin32k"; + phandle = <0x20d>; + }; + + xin24m { + compatible = "fixed-clock"; + #clock-cells = <0x00>; + clock-frequency = <0x16e3600>; + clock-output-names = "xin24m"; + phandle = <0x20e>; + }; + + hclk_vo1@fd7c08ec { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x00 0xfd7c08ec 0x00 0x10>; + clock-names = "link"; + clocks = <0x02 0x264>; + #power-domain-cells = <0x01>; + #clock-cells = <0x00>; + phandle = <0x05>; + }; + + aclk_vdpu_low_pre@fd7c08b0 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x00 0xfd7c08b0 0x00 0x10>; + clock-names = "link"; + clocks = <0x02 0x1bc>; + #power-domain-cells = <0x01>; + #clock-cells = <0x00>; + phandle = <0x20f>; + }; + + hclk_vo0@fd7c08dc { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x00 0xfd7c08dc 0x00 0x10>; + clock-names = "link"; + clocks = <0x02 0x26d>; + #power-domain-cells = <0x01>; + #clock-cells = <0x00>; + phandle = <0x04>; + }; + + hclk_usb@fd7c08a8 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x00 0xfd7c08a8 0x00 0x10>; + clock-names = "link"; + clocks = <0x02 0x264>; + #power-domain-cells = <0x01>; + #clock-cells = <0x00>; + phandle = <0x210>; + }; + + hclk_nvm@fd7c087c { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x00 0xfd7c087c 0x00 0x10>; + clock-names = "link"; + clocks = <0x02 0x141>; + #power-domain-cells = <0x01>; + #clock-cells = <0x00>; + phandle = <0x03>; + }; + + aclk_usb@fd7c08a8 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x00 0xfd7c08a8 0x00 0x10>; + clock-names = "link"; + clocks = <0x02 0x263>; + #power-domain-cells = <0x01>; + #clock-cells = <0x00>; + phandle = <0x6b>; + }; + + hclk_isp1_pre@fd7c0868 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x00 0xfd7c0868 0x00 0x10>; + clock-names = "link"; + clocks = <0x02 0x1e1>; + #power-domain-cells = <0x01>; + #clock-cells = <0x00>; + phandle = <0x211>; + }; + + aclk_isp1_pre@fd7c0868 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x00 0xfd7c0868 0x00 0x10>; + clock-names = "link"; + clocks = <0x02 0x1e0>; + #power-domain-cells = <0x01>; + #clock-cells = <0x00>; + phandle = <0x212>; + }; + + aclk_rkvdec0_pre@fd7c08a0 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x00 0xfd7c08a0 0x00 0x10>; + clock-names = "link"; + clocks = <0x02 0x1bc>; + #power-domain-cells = <0x01>; + #clock-cells = <0x00>; + phandle = <0x213>; + }; + + hclk_rkvdec0_pre@fd7c08a0 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x00 0xfd7c08a0 0x00 0x10>; + clock-names = "link"; + clocks = <0x02 0x1be>; + #power-domain-cells = <0x01>; + #clock-cells = <0x00>; + phandle = <0x214>; + }; + + aclk_rkvdec1_pre@fd7c08a4 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x00 0xfd7c08a4 0x00 0x10>; + clock-names = "link"; + clocks = <0x02 0x1bc>; + #power-domain-cells = <0x01>; + #clock-cells = <0x00>; + phandle = <0x215>; + }; + + hclk_rkvdec1_pre@fd7c08a4 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x00 0xfd7c08a4 0x00 0x10>; + clock-names = "link"; + clocks = <0x02 0x1be>; + #power-domain-cells = <0x01>; + #clock-cells = <0x00>; + phandle = <0x216>; + }; + + aclk_jpeg_decoder_pre@fd7c08b0 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x00 0xfd7c08b0 0x00 0x10>; + clock-names = "link"; + clocks = <0x02 0x1bc>; + #power-domain-cells = <0x01>; + #clock-cells = <0x00>; + phandle = <0x217>; + }; + + aclk_rkvenc1_pre@fd7c08c0 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x00 0xfd7c08c0 0x00 0x10>; + clock-names = "link"; + clocks = <0x02 0x1c5>; + #power-domain-cells = <0x01>; + #clock-cells = <0x00>; + phandle = <0x218>; + }; + + hclk_rkvenc1_pre@fd7c08c0 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x00 0xfd7c08c0 0x00 0x10>; + clock-names = "link"; + clocks = <0x02 0x1c4>; + #power-domain-cells = <0x01>; + #clock-cells = <0x00>; + phandle = <0x219>; + }; + + aclk_hdcp0_pre@fd7c08dc { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x00 0xfd7c08dc 0x00 0x10>; + clock-names = "link"; + clocks = <0x02 0x26c>; + #power-domain-cells = <0x01>; + #clock-cells = <0x00>; + phandle = <0x21a>; + }; + + aclk_hdcp1_pre@fd7c08ec { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x00 0xfd7c08ec 0x00 0x10>; + clock-names = "link"; + clocks = <0x02 0x263>; + #power-domain-cells = <0x01>; + #clock-cells = <0x00>; + phandle = <0x21b>; + }; + + pclk_av1_pre@fd7c0910 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x00 0xfd7c0910 0x00 0x10>; + clock-names = "link"; + clocks = <0x02 0x1be>; + #power-domain-cells = <0x01>; + #clock-cells = <0x00>; + phandle = <0x21c>; + }; + + aclk_av1_pre@fd7c0910 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x00 0xfd7c0910 0x00 0x10>; + clock-names = "link"; + clocks = <0x02 0x1bc>; + #power-domain-cells = <0x01>; + #clock-cells = <0x00>; + phandle = <0x21d>; + }; + + hclk_sdio_pre@fd7c092c { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x00 0xfd7c092c 0x00 0x10>; + clock-names = "link"; + clocks = <0x03>; + #power-domain-cells = <0x01>; + #clock-cells = <0x00>; + phandle = <0x21e>; + }; + + pclk_vo0_grf@fd7c08dc { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x00 0xfd7c08dc 0x00 0x04>; + clocks = <0x04>; + clock-names = "link"; + #clock-cells = <0x00>; + phandle = <0x73>; + }; + + pclk_vo1_grf@fd7c08ec { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x00 0xfd7c08ec 0x00 0x04>; + clocks = <0x05>; + clock-names = "link"; + #clock-cells = <0x00>; + phandle = <0x74>; + }; + + mclkin-i2s0 { + compatible = "fixed-clock"; + #clock-cells = <0x00>; + clock-frequency = <0x00>; + clock-output-names = "i2s0_mclkin"; + phandle = <0x21f>; + }; + + mclkin-i2s1 { + compatible = "fixed-clock"; + #clock-cells = <0x00>; + clock-frequency = <0x00>; + clock-output-names = "i2s1_mclkin"; + phandle = <0x220>; + }; + + mclkin-i2s2 { + compatible = "fixed-clock"; + #clock-cells = <0x00>; + clock-frequency = <0x00>; + clock-output-names = "i2s2_mclkin"; + phandle = <0x221>; + }; + + mclkin-i2s3 { + compatible = "fixed-clock"; + #clock-cells = <0x00>; + clock-frequency = <0x00>; + clock-output-names = "i2s3_mclkin"; + phandle = <0x222>; + }; + + mclkout-i2s0@fd58c318 { + compatible = "rockchip,clk-out"; + reg = <0x00 0xfd58c318 0x00 0x04>; + clocks = <0x02 0x39>; + #clock-cells = <0x00>; + clock-output-names = "i2s0_mclkout_to_io"; + power-domains = <0x06 0x26>; + rockchip,bit-shift = <0x00>; + rockchip,bit-set-to-disable; + phandle = <0x197>; + }; + + mclkout-i2s1@fd58c318 { + compatible = "rockchip,clk-out"; + reg = <0x00 0xfd58c318 0x00 0x04>; + clocks = <0x02 0x291>; + #clock-cells = <0x00>; + clock-output-names = "i2s1_mclkout_to_io"; + rockchip,bit-shift = <0x01>; + rockchip,bit-set-to-disable; + phandle = <0x223>; + }; + + mclkout-i2s1@fd58a000 { + compatible = "rockchip,clk-out"; + reg = <0x00 0xfd58a000 0x00 0x04>; + clocks = <0x02 0x291>; + #clock-cells = <0x00>; + clock-output-names = "i2s1m1_mclkout_to_io"; + rockchip,bit-shift = <0x06>; + phandle = <0x224>; + }; + + mclkout-i2s2@fd58c318 { + compatible = "rockchip,clk-out"; + reg = <0x00 0xfd58c318 0x00 0x04>; + clocks = <0x02 0x28>; + #clock-cells = <0x00>; + clock-output-names = "i2s2_mclkout_to_io"; + power-domains = <0x06 0x26>; + rockchip,bit-shift = <0x02>; + rockchip,bit-set-to-disable; + phandle = <0x225>; + }; + + mclkout-i2s3@fd58c318 { + compatible = "rockchip,clk-out"; + reg = <0x00 0xfd58c318 0x00 0x04>; + clocks = <0x02 0x2e>; + #clock-cells = <0x00>; + clock-output-names = "i2s3_mclkout_to_io"; + power-domains = <0x06 0x26>; + rockchip,bit-shift = <0x07>; + rockchip,bit-set-to-disable; + phandle = <0x226>; + }; + }; + + cpus { + #address-cells = <0x01>; + #size-cells = <0x00>; + + cpu-map { + + cluster0 { + + core0 { + cpu = <0x07>; + }; + + core1 { + cpu = <0x08>; + }; + + core2 { + cpu = <0x09>; + }; + + core3 { + cpu = <0x0a>; + }; + }; + + cluster1 { + + core0 { + cpu = <0x0b>; + }; + + core1 { + cpu = <0x0c>; + }; + }; + + cluster2 { + + core0 { + cpu = <0x0d>; + }; + + core1 { + cpu = <0x0e>; + }; + }; + }; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x00>; + enable-method = "psci"; + capacity-dmips-mhz = <0x212>; + clocks = <0x0f 0x00>; + operating-points-v2 = <0x10>; + cpu-idle-states = <0x11>; + i-cache-size = <0x8000>; + i-cache-line-size = <0x40>; + i-cache-sets = <0x80>; + d-cache-size = <0x8000>; + d-cache-line-size = <0x40>; + d-cache-sets = <0x80>; + next-level-cache = <0x12>; + #cooling-cells = <0x02>; + dynamic-power-coefficient = <0x64>; + cpu-supply = <0x13>; + mem-supply = <0x13>; + phandle = <0x07>; + }; + + cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x100>; + enable-method = "psci"; + capacity-dmips-mhz = <0x212>; + clocks = <0x0f 0x00>; + operating-points-v2 = <0x10>; + cpu-idle-states = <0x11>; + i-cache-size = <0x8000>; + i-cache-line-size = <0x40>; + i-cache-sets = <0x80>; + d-cache-size = <0x8000>; + d-cache-line-size = <0x40>; + d-cache-sets = <0x80>; + next-level-cache = <0x14>; + phandle = <0x08>; + }; + + // cpu@200 { + // device_type = "cpu"; + // compatible = "arm,cortex-a55"; + // reg = <0x200>; + // enable-method = "psci"; + // capacity-dmips-mhz = <0x212>; + // clocks = <0x0f 0x00>; + // operating-points-v2 = <0x10>; + // cpu-idle-states = <0x11>; + // i-cache-size = <0x8000>; + // i-cache-line-size = <0x40>; + // i-cache-sets = <0x80>; + // d-cache-size = <0x8000>; + // d-cache-line-size = <0x40>; + // d-cache-sets = <0x80>; + // next-level-cache = <0x15>; + // phandle = <0x09>; + // }; + + // cpu@300 { + // device_type = "cpu"; + // compatible = "arm,cortex-a55"; + // reg = <0x300>; + // enable-method = "psci"; + // capacity-dmips-mhz = <0x212>; + // clocks = <0x0f 0x00>; + // operating-points-v2 = <0x10>; + // cpu-idle-states = <0x11>; + // i-cache-size = <0x8000>; + // i-cache-line-size = <0x40>; + // i-cache-sets = <0x80>; + // d-cache-size = <0x8000>; + // d-cache-line-size = <0x40>; + // d-cache-sets = <0x80>; + // next-level-cache = <0x16>; + // phandle = <0x0a>; + // }; + + // cpu@400 { + // device_type = "cpu"; + // compatible = "arm,cortex-a76"; + // reg = <0x400>; + // enable-method = "psci"; + // capacity-dmips-mhz = <0x400>; + // clocks = <0x0f 0x02>; + // operating-points-v2 = <0x17>; + // cpu-idle-states = <0x11>; + // i-cache-size = <0x10000>; + // i-cache-line-size = <0x40>; + // i-cache-sets = <0x100>; + // d-cache-size = <0x10000>; + // d-cache-line-size = <0x40>; + // d-cache-sets = <0x100>; + // next-level-cache = <0x18>; + // #cooling-cells = <0x02>; + // dynamic-power-coefficient = <0x12c>; + // cpu-supply = <0x19>; + // mem-supply = <0x19>; + // phandle = <0x0b>; + // }; + + // cpu@500 { + // device_type = "cpu"; + // compatible = "arm,cortex-a76"; + // reg = <0x500>; + // enable-method = "psci"; + // capacity-dmips-mhz = <0x400>; + // clocks = <0x0f 0x02>; + // operating-points-v2 = <0x17>; + // cpu-idle-states = <0x11>; + // i-cache-size = <0x10000>; + // i-cache-line-size = <0x40>; + // i-cache-sets = <0x100>; + // d-cache-size = <0x10000>; + // d-cache-line-size = <0x40>; + // d-cache-sets = <0x100>; + // next-level-cache = <0x1a>; + // phandle = <0x0c>; + // }; + + // cpu@600 { + // device_type = "cpu"; + // compatible = "arm,cortex-a76"; + // reg = <0x600>; + // enable-method = "psci"; + // capacity-dmips-mhz = <0x400>; + // clocks = <0x0f 0x03>; + // operating-points-v2 = <0x1b>; + // cpu-idle-states = <0x11>; + // i-cache-size = <0x10000>; + // i-cache-line-size = <0x40>; + // i-cache-sets = <0x100>; + // d-cache-size = <0x10000>; + // d-cache-line-size = <0x40>; + // d-cache-sets = <0x100>; + // next-level-cache = <0x1c>; + // #cooling-cells = <0x02>; + // dynamic-power-coefficient = <0x12c>; + // cpu-supply = <0x1d>; + // mem-supply = <0x1d>; + // phandle = <0x0d>; + // }; + + // cpu@700 { + // device_type = "cpu"; + // compatible = "arm,cortex-a76"; + // reg = <0x700>; + // enable-method = "psci"; + // capacity-dmips-mhz = <0x400>; + // clocks = <0x0f 0x03>; + // operating-points-v2 = <0x1b>; + // cpu-idle-states = <0x11>; + // i-cache-size = <0x10000>; + // i-cache-line-size = <0x40>; + // i-cache-sets = <0x100>; + // d-cache-size = <0x10000>; + // d-cache-line-size = <0x40>; + // d-cache-sets = <0x100>; + // next-level-cache = <0x1e>; + // phandle = <0x0e>; + // }; + + idle-states { + entry-method = "psci"; + + cpu-sleep { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x10000>; + entry-latency-us = <0x64>; + exit-latency-us = <0x78>; + min-residency-us = <0x3e8>; + phandle = <0x11>; + }; + }; + + l2-cache-l0 { + compatible = "cache"; + cache-size = <0x20000>; + cache-line-size = <0x40>; + cache-sets = <0x200>; + next-level-cache = <0x1f>; + phandle = <0x12>; + }; + + l2-cache-l1 { + compatible = "cache"; + cache-size = <0x20000>; + cache-line-size = <0x40>; + cache-sets = <0x200>; + next-level-cache = <0x1f>; + phandle = <0x14>; + }; + + l2-cache-l2 { + compatible = "cache"; + cache-size = <0x20000>; + cache-line-size = <0x40>; + cache-sets = <0x200>; + next-level-cache = <0x1f>; + phandle = <0x15>; + }; + + l2-cache-l3 { + compatible = "cache"; + cache-size = <0x20000>; + cache-line-size = <0x40>; + cache-sets = <0x200>; + next-level-cache = <0x1f>; + phandle = <0x16>; + }; + + l2-cache-b0 { + compatible = "cache"; + cache-size = <0x80000>; + cache-line-size = <0x40>; + cache-sets = <0x400>; + next-level-cache = <0x1f>; + phandle = <0x18>; + }; + + l2-cache-b1 { + compatible = "cache"; + cache-size = <0x80000>; + cache-line-size = <0x40>; + cache-sets = <0x400>; + next-level-cache = <0x1f>; + phandle = <0x1a>; + }; + + l2-cache-b2 { + compatible = "cache"; + cache-size = <0x80000>; + cache-line-size = <0x40>; + cache-sets = <0x400>; + next-level-cache = <0x1f>; + phandle = <0x1c>; + }; + + l2-cache-b3 { + compatible = "cache"; + cache-size = <0x80000>; + cache-line-size = <0x40>; + cache-sets = <0x400>; + next-level-cache = <0x1f>; + phandle = <0x1e>; + }; + + l3-cache { + compatible = "cache"; + cache-size = <0x300000>; + cache-line-size = <0x40>; + cache-sets = <0x1000>; + phandle = <0x1f>; + }; + }; + + cluster0-opp-table { + compatible = "operating-points-v2"; + opp-shared; + nvmem-cells = <0x20 0x21 0x22 0x23>; + nvmem-cell-names = "leakage\0opp-info\0specification_serial_number\0customer_demand"; + rockchip,supported-hw; + rockchip,opp-shared-dsu; + rockchip,pvtm-hw = <0x06>; + rockchip,pvtm-voltage-sel-hw = <0x00 0x555 0x00 0x556 0x56b 0x01 0x56c 0x581 0x02 0x582 0x597 0x03 0x598 0x5ad 0x04 0x5ae 0x5c3 0x05 0x5c4 0x270f 0x06>; + rockchip,pvtm-voltage-sel-B4 = <0x00 0x532 0x00 0x533 0x555 0x01 0x556 0x56e 0x02 0x56f 0x582 0x03 0x583 0x59a 0x04 0x59b 0x5b2 0x05 0x5b3 0x5ca 0x06 0x5cb 0x5e2 0x07 0x5e3 0x5fa 0x08 0x5fb 0x270f 0x09>; + rockchip,pvtm-voltage-sel = <0x00 0x582 0x00 0x583 0x59a 0x01 0x59b 0x5b2 0x02 0x5b3 0x5ca 0x03 0x5cb 0x5e2 0x04 0x5e3 0x5fa 0x05 0x5fb 0x270f 0x06>; + rockchip,pvtm-pvtpll; + rockchip,pvtm-offset = <0x64>; + rockchip,pvtm-sample-time = <0x44c>; + rockchip,pvtm-freq = <0x159b40>; + rockchip,pvtm-volt = <0xb71b0>; + rockchip,pvtm-ref-temp = <0x19>; + rockchip,pvtm-temp-prop = <0xf4 0xf4>; + rockchip,pvtm-thermal-zone = "soc-thermal"; + rockchip,grf = <0x24>; + rockchip,dsu-grf = <0x25>; + volt-mem-read-margin = <0xd0bd8 0x01 0xbac48 0x02 0xa4cb8 0x03 0x78d98 0x04>; + low-volt-mem-read-margin = <0x04>; + intermediate-threshold-freq = <0xf6180>; + rockchip,reboot-freq = <0x159b40>; + rockchip,temp-hysteresis = <0x1388>; + rockchip,low-temp = <0x3a98>; + rockchip,low-temp-min-volt = "\0\f5"; + rockchip,high-temp = <0x14c08>; + rockchip,high-temp-max-freq = <0x188940>; + phandle = <0x10>; + + opp-408000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x18519600>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-600000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x23c34600>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-816000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x30a32c00>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-1008000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x3c14dc00>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-1200000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x47868c00>; + opp-microvolt = <0xadf34 0xadf34 0xe7ef0 0xadf34 0xadf34 0xe7ef0>; + opp-microvolt-L1 = <0xaae60 0xaae60 0xe7ef0 0xaae60 0xaae60 0xe7ef0>; + opp-microvolt-L2 = <0xaae60 0xaae60 0xe7ef0 0xaae60 0xaae60 0xe7ef0>; + opp-microvolt-L3 = <0xa7d8c 0xa7d8c 0xe7ef0 0xa7d8c 0xa7d8c 0xe7ef0>; + opp-microvolt-L4 = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>; + opp-microvolt-L5 = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>; + opp-microvolt-L6 = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-1416000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x54667200>; + opp-microvolt = <0xba284 0xba284 0xe7ef0 0xba284 0xba284 0xe7ef0>; + opp-microvolt-L1 = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>; + opp-microvolt-L2 = <0xb40dc 0xb40dc 0xe7ef0 0xb40dc 0xb40dc 0xe7ef0>; + opp-microvolt-L3 = <0xb1008 0xb1008 0xe7ef0 0xb1008 0xb1008 0xe7ef0>; + opp-microvolt-L4 = <0xb1008 0xb1008 0xe7ef0 0xb1008 0xb1008 0xe7ef0>; + opp-microvolt-L5 = <0xadf34 0xadf34 0xe7ef0 0xadf34 0xadf34 0xe7ef0>; + opp-microvolt-L6 = <0xadf34 0xadf34 0xe7ef0 0xadf34 0xadf34 0xe7ef0>; + clock-latency-ns = <0x9c40>; + opp-suspend; + }; + + opp-1608000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x5fd82200>; + opp-microvolt = <0xcf850 0xcf850 0xe7ef0 0xcf850 0xcf850 0xe7ef0>; + opp-microvolt-L1 = <0xcc77c 0xcc77c 0xe7ef0 0xcc77c 0xcc77c 0xe7ef0>; + opp-microvolt-L2 = <0xc96a8 0xc96a8 0xe7ef0 0xc96a8 0xc96a8 0xe7ef0>; + opp-microvolt-L3 = <0xc65d4 0xc65d4 0xe7ef0 0xc65d4 0xc65d4 0xe7ef0>; + opp-microvolt-L4 = <0xc3500 0xc3500 0xe7ef0 0xc3500 0xc3500 0xe7ef0>; + opp-microvolt-L5 = <0xc3500 0xc3500 0xe7ef0 0xc3500 0xc3500 0xe7ef0>; + opp-microvolt-L6 = <0xc042c 0xc042c 0xe7ef0 0xc042c 0xc042c 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-1800000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x6b49d200>; + opp-microvolt = <0xe7ef0 0xe7ef0 0xe7ef0 0xe7ef0 0xe7ef0 0xe7ef0>; + opp-microvolt-L1 = <0xe4e1c 0xe4e1c 0xe7ef0 0xe4e1c 0xe4e1c 0xe7ef0>; + opp-microvolt-L2 = <0xe1d48 0xe1d48 0xe7ef0 0xe1d48 0xe1d48 0xe7ef0>; + opp-microvolt-L3 = <0xdec74 0xdec74 0xe7ef0 0xdec74 0xdec74 0xe7ef0>; + opp-microvolt-L4 = <0xdbba0 0xdbba0 0xe7ef0 0xdbba0 0xdbba0 0xe7ef0>; + opp-microvolt-L5 = <0xd8acc 0xd8acc 0xe7ef0 0xd8acc 0xd8acc 0xe7ef0>; + opp-microvolt-L6 = <0xd59f8 0xd59f8 0xe7ef0 0xd59f8 0xd59f8 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-b-408000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x18519600>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>; + opp-microvolt-L0 = <0xadf34 0xadf34 0xe7ef0 0xadf34 0xadf34 0xe7ef0>; + opp-microvolt-L1 = <0xaae60 0xaae60 0xe7ef0 0xaae60 0xaae60 0xe7ef0>; + opp-microvolt-L2 = <0xa7d8c 0xa7d8c 0xe7ef0 0xa7d8c 0xa7d8c 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-b-600000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x23c34600>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>; + opp-microvolt-L0 = <0xadf34 0xadf34 0xe7ef0 0xadf34 0xadf34 0xe7ef0>; + opp-microvolt-L1 = <0xaae60 0xaae60 0xe7ef0 0xaae60 0xaae60 0xe7ef0>; + opp-microvolt-L2 = <0xa7d8c 0xa7d8c 0xe7ef0 0xa7d8c 0xa7d8c 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-b-816000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x30a32c00>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>; + opp-microvolt-L0 = <0xadf34 0xadf34 0xe7ef0 0xadf34 0xadf34 0xe7ef0>; + opp-microvolt-L1 = <0xaae60 0xaae60 0xe7ef0 0xaae60 0xaae60 0xe7ef0>; + opp-microvolt-L2 = <0xa7d8c 0xa7d8c 0xe7ef0 0xa7d8c 0xa7d8c 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-b-1008000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x3c14dc00>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>; + opp-microvolt-L0 = <0xadf34 0xadf34 0xe7ef0 0xadf34 0xadf34 0xe7ef0>; + opp-microvolt-L1 = <0xaae60 0xaae60 0xe7ef0 0xaae60 0xaae60 0xe7ef0>; + opp-microvolt-L2 = <0xa7d8c 0xa7d8c 0xe7ef0 0xa7d8c 0xa7d8c 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-b-1200000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x47868c00>; + opp-microvolt = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>; + opp-microvolt-L1 = <0xb40dc 0xb40dc 0xe7ef0 0xb40dc 0xb40dc 0xe7ef0>; + opp-microvolt-L2 = <0xb1008 0xb1008 0xe7ef0 0xb1008 0xb1008 0xe7ef0>; + opp-microvolt-L3 = <0xadf34 0xadf34 0xe7ef0 0xadf34 0xadf34 0xe7ef0>; + opp-microvolt-L4 = <0xaae60 0xaae60 0xe7ef0 0xaae60 0xaae60 0xe7ef0>; + opp-microvolt-L5 = <0xaae60 0xaae60 0xe7ef0 0xaae60 0xaae60 0xe7ef0>; + opp-microvolt-L6 = <0xa7d8c 0xa7d8c 0xe7ef0 0xa7d8c 0xa7d8c 0xe7ef0>; + opp-microvolt-L7 = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>; + opp-microvolt-L8 = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>; + opp-microvolt-L9 = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-b-1416000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x54667200>; + opp-microvolt = <0xc3500 0xc3500 0xe7ef0 0xc3500 0xc3500 0xe7ef0>; + opp-microvolt-L1 = <0xc042c 0xc042c 0xe7ef0 0xc042c 0xc042c 0xe7ef0>; + opp-microvolt-L2 = <0xbd358 0xbd358 0xe7ef0 0xbd358 0xbd358 0xe7ef0>; + opp-microvolt-L3 = <0xba284 0xba284 0xe7ef0 0xba284 0xba284 0xe7ef0>; + opp-microvolt-L4 = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>; + opp-microvolt-L5 = <0xb40dc 0xb40dc 0xe7ef0 0xb40dc 0xb40dc 0xe7ef0>; + opp-microvolt-L6 = <0xb1008 0xb1008 0xe7ef0 0xb1008 0xb1008 0xe7ef0>; + opp-microvolt-L7 = <0xb1008 0xb1008 0xe7ef0 0xb1008 0xb1008 0xe7ef0>; + opp-microvolt-L8 = <0xadf34 0xadf34 0xe7ef0 0xadf34 0xadf34 0xe7ef0>; + opp-microvolt-L9 = <0xadf34 0xadf34 0xe7ef0 0xadf34 0xadf34 0xe7ef0>; + clock-latency-ns = <0x9c40>; + opp-suspend; + }; + + opp-b-1608000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x5fd82200>; + opp-microvolt = <0xd8acc 0xd8acc 0xe7ef0 0xd8acc 0xd8acc 0xe7ef0>; + opp-microvolt-L1 = <0xd59f8 0xd59f8 0xe7ef0 0xd59f8 0xd59f8 0xe7ef0>; + opp-microvolt-L2 = <0xd2924 0xd2924 0xe7ef0 0xd2924 0xd2924 0xe7ef0>; + opp-microvolt-L3 = <0xcf850 0xcf850 0xe7ef0 0xcf850 0xcf850 0xe7ef0>; + opp-microvolt-L4 = <0xcc77c 0xcc77c 0xe7ef0 0xcc77c 0xcc77c 0xe7ef0>; + opp-microvolt-L5 = <0xc96a8 0xc96a8 0xe7ef0 0xc96a8 0xc96a8 0xe7ef0>; + opp-microvolt-L6 = <0xc65d4 0xc65d4 0xe7ef0 0xc65d4 0xc65d4 0xe7ef0>; + opp-microvolt-L7 = <0xc3500 0xc3500 0xe7ef0 0xc3500 0xc3500 0xe7ef0>; + opp-microvolt-L8 = <0xc3500 0xc3500 0xe7ef0 0xc3500 0xc3500 0xe7ef0>; + opp-microvolt-L9 = <0xc042c 0xc042c 0xe7ef0 0xc042c 0xc042c 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-j-m-408000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x18519600>; + opp-microvolt = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-j-m-600000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x23c34600>; + opp-microvolt = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-j-m-816000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x30a32c00>; + opp-microvolt = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-j-m-1008000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x3c14dc00>; + opp-microvolt = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-j-m-1200000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x47868c00>; + opp-microvolt = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-j-1296000000 { + opp-supported-hw = <0x04 0xffff>; + opp-hz = <0x00 0x4d3f6400>; + opp-microvolt = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>; + opp-microvolt-L0 = <0xbd358 0xbd358 0xe7ef0 0xbd358 0xbd358 0xe7ef0>; + opp-microvolt-L1 = <0xba284 0xba284 0xe7ef0 0xba284 0xba284 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-j-m-1416000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x54667200>; + opp-microvolt = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>; + opp-microvolt-L0 = <0xc042c 0xc042c 0xe7ef0 0xc042c 0xc042c 0xe7ef0>; + opp-microvolt-L1 = <0xbd358 0xbd358 0xe7ef0 0xbd358 0xbd358 0xe7ef0>; + opp-microvolt-L2 = <0xba284 0xba284 0xe7ef0 0xba284 0xba284 0xe7ef0>; + clock-latency-ns = <0x9c40>; + opp-suspend; + }; + + opp-j-m-1608000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x5fd82200>; + opp-microvolt = <0xd8acc 0xd8acc 0xe7ef0 0xd8acc 0xd8acc 0xe7ef0>; + opp-microvolt-L1 = <0xd59f8 0xd59f8 0xe7ef0 0xd59f8 0xd59f8 0xe7ef0>; + opp-microvolt-L2 = <0xd2924 0xd2924 0xe7ef0 0xd2924 0xd2924 0xe7ef0>; + opp-microvolt-L3 = <0xcf850 0xcf850 0xe7ef0 0xcf850 0xcf850 0xe7ef0>; + opp-microvolt-L4 = <0xcc77c 0xcc77c 0xe7ef0 0xcc77c 0xcc77c 0xe7ef0>; + opp-microvolt-L5 = <0xc96a8 0xc96a8 0xe7ef0 0xc96a8 0xc96a8 0xe7ef0>; + opp-microvolt-L6 = <0xc65d4 0xc65d4 0xe7ef0 0xc65d4 0xc65d4 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-j-m-1704000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x6590fa00>; + opp-microvolt = <0xe4e1c 0xe4e1c 0xe7ef0 0xe4e1c 0xe4e1c 0xe7ef0>; + opp-microvolt-L1 = <0xe1d48 0xe1d48 0xe7ef0 0xe1d48 0xe1d48 0xe7ef0>; + opp-microvolt-L2 = <0xdec74 0xdec74 0xe7ef0 0xdec74 0xdec74 0xe7ef0>; + opp-microvolt-L3 = <0xdbba0 0xdbba0 0xe7ef0 0xdbba0 0xdbba0 0xe7ef0>; + opp-microvolt-L4 = <0xd8acc 0xd8acc 0xe7ef0 0xd8acc 0xd8acc 0xe7ef0>; + opp-microvolt-L5 = <0xd59f8 0xd59f8 0xe7ef0 0xd59f8 0xd59f8 0xe7ef0>; + opp-microvolt-L6 = <0xd2924 0xd2924 0xe7ef0 0xd2924 0xd2924 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + }; + + cluster1-opp-table { + compatible = "operating-points-v2"; + opp-shared; + nvmem-cells = <0x26 0x27 0x22 0x23>; + nvmem-cell-names = "leakage\0opp-info\0specification_serial_number\0customer_demand"; + rockchip,supported-hw; + rockchip,pvtm-hw = <0x06>; + rockchip,pvtm-voltage-sel-hw = <0x00 0x603 0x00 0x604 0x61c 0x01 0x61d 0x635 0x02 0x636 0x64e 0x03 0x64f 0x66c 0x04 0x66d 0x68a 0x05 0x68b 0x6a8 0x06 0x6a9 0x270f 0x07>; + rockchip,pvtm-voltage-sel-B4 = <0x00 0x5f5 0x00 0x5f6 0x609 0x01 0x60a 0x61d 0x02 0x61e 0x63b 0x03 0x63c 0x64f 0x04 0x650 0x668 0x05 0x669 0x68b 0x06 0x68c 0x6ae 0x07 0x6af 0x6cf 0x08 0x6d0 0x6f0 0x09 0x6f1 0x270f 0x0a>; + rockchip,pvtm-voltage-sel = <0x00 0x63b 0x00 0x63c 0x64f 0x01 0x650 0x668 0x02 0x669 0x68b 0x03 0x68c 0x6ae 0x04 0x6af 0x6cf 0x05 0x6d0 0x6f0 0x06 0x6f1 0x270f 0x07>; + rockchip,pvtm-pvtpll; + rockchip,pvtm-offset = <0x18>; + rockchip,pvtm-sample-time = <0x44c>; + rockchip,pvtm-freq = <0x188940>; + rockchip,pvtm-volt = <0xb71b0>; + rockchip,pvtm-ref-temp = <0x19>; + rockchip,pvtm-temp-prop = <0x10e 0x10e>; + rockchip,pvtm-thermal-zone = "soc-thermal"; + rockchip,pvtm-low-len-sel = <0x03>; + rockchip,grf = <0x28>; + volt-mem-read-margin = <0xd0bd8 0x01 0xbac48 0x02 0xa4cb8 0x03 0x78d98 0x04>; + low-volt-mem-read-margin = <0x04>; + intermediate-threshold-freq = <0xf6180>; + rockchip,idle-threshold-freq = <0x21b100>; + rockchip,reboot-freq = <0x1b7740>; + rockchip,temp-hysteresis = <0x1388>; + rockchip,low-temp = <0x3a98>; + rockchip,low-temp-min-volt = "\0\f5"; + rockchip,high-temp = <0x14c08>; + rockchip,high-temp-max-freq = <0x21b100>; + phandle = <0x17>; + + opp-408000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x18519600>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>; + clock-latency-ns = <0x9c40>; + opp-suspend; + }; + + opp-600000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x23c34600>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-816000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x30a32c00>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-1008000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x3c14dc00>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-1200000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x47868c00>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-1416000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x54667200>; + opp-microvolt = <0xb1008 0xb1008 0xf4240 0xb1008 0xb1008 0xf4240>; + opp-microvolt-L2 = <0xadf34 0xadf34 0xf4240 0xadf34 0xadf34 0xf4240>; + opp-microvolt-L3 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>; + opp-microvolt-L4 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>; + opp-microvolt-L5 = <0xa7d8c 0xa7d8c 0xf4240 0xa7d8c 0xa7d8c 0xf4240>; + opp-microvolt-L6 = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>; + opp-microvolt-L7 = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-1608000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x5fd82200>; + opp-microvolt = <0xba284 0xba284 0xf4240 0xba284 0xba284 0xf4240>; + opp-microvolt-L2 = <0xb71b0 0xb71b0 0xf4240 0xb71b0 0xb71b0 0xf4240>; + opp-microvolt-L3 = <0xb40dc 0xb40dc 0xf4240 0xb40dc 0xb40dc 0xf4240>; + opp-microvolt-L4 = <0xb1008 0xb1008 0xf4240 0xb1008 0xb1008 0xf4240>; + opp-microvolt-L5 = <0xadf34 0xadf34 0xf4240 0xadf34 0xadf34 0xf4240>; + opp-microvolt-L6 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>; + opp-microvolt-L7 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-1800000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x6b49d200>; + opp-microvolt = <0xcf850 0xcf850 0xf4240 0xcf850 0xcf850 0xf4240>; + opp-microvolt-L1 = <0xcc77c 0xcc77c 0xf4240 0xcc77c 0xcc77c 0xf4240>; + opp-microvolt-L2 = <0xc96a8 0xc96a8 0xf4240 0xc96a8 0xc96a8 0xf4240>; + opp-microvolt-L3 = <0xc65d4 0xc65d4 0xf4240 0xc65d4 0xc65d4 0xf4240>; + opp-microvolt-L4 = <0xc3500 0xc3500 0xf4240 0xc3500 0xc3500 0xf4240>; + opp-microvolt-L5 = <0xc042c 0xc042c 0xf4240 0xc042c 0xc042c 0xf4240>; + opp-microvolt-L6 = <0xbd358 0xbd358 0xf4240 0xbd358 0xbd358 0xf4240>; + opp-microvolt-L7 = <0xba284 0xba284 0xf4240 0xba284 0xba284 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-2016000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x7829b800>; + opp-microvolt = <0xe1d48 0xe1d48 0xf4240 0xe1d48 0xe1d48 0xf4240>; + opp-microvolt-L1 = <0xdec74 0xdec74 0xf4240 0xdec74 0xdec74 0xf4240>; + opp-microvolt-L2 = <0xdbba0 0xdbba0 0xf4240 0xdbba0 0xdbba0 0xf4240>; + opp-microvolt-L3 = <0xd8acc 0xd8acc 0xf4240 0xd8acc 0xd8acc 0xf4240>; + opp-microvolt-L4 = <0xd59f8 0xd59f8 0xf4240 0xd59f8 0xd59f8 0xf4240>; + opp-microvolt-L5 = <0xd2924 0xd2924 0xf4240 0xd2924 0xd2924 0xf4240>; + opp-microvolt-L6 = <0xcf850 0xcf850 0xf4240 0xcf850 0xcf850 0xf4240>; + opp-microvolt-L7 = <0xcc77c 0xcc77c 0xf4240 0xcc77c 0xcc77c 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-2208000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x839b6800>; + opp-microvolt = <0xf116c 0xf116c 0xf4240 0xf116c 0xf116c 0xf4240>; + opp-microvolt-L1 = <0xee098 0xee098 0xf4240 0xee098 0xee098 0xf4240>; + opp-microvolt-L2 = <0xeafc4 0xeafc4 0xf4240 0xeafc4 0xeafc4 0xf4240>; + opp-microvolt-L3 = <0xe7ef0 0xe7ef0 0xf4240 0xe7ef0 0xe7ef0 0xf4240>; + opp-microvolt-L4 = <0xeafc4 0xeafc4 0xf4240 0xeafc4 0xeafc4 0xf4240>; + opp-microvolt-L5 = <0xe7ef0 0xe7ef0 0xf4240 0xe7ef0 0xe7ef0 0xf4240>; + opp-microvolt-L6 = <0xe1d48 0xe1d48 0xf4240 0xe1d48 0xe1d48 0xf4240>; + opp-microvolt-L7 = <0xdec74 0xdec74 0xf4240 0xdec74 0xdec74 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-2256000000 { + opp-supported-hw = <0xe9 0x13>; + opp-hz = <0x00 0x8677d400>; + opp-microvolt = <0xf4240 0xf4240 0xf4240 0xf4240 0xf4240 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-2304000000 { + opp-supported-hw = <0xe9 0x24>; + opp-hz = <0x00 0x89544000>; + opp-microvolt = <0xf4240 0xf4240 0xf4240 0xf4240 0xf4240 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-2352000000 { + opp-supported-hw = <0xe9 0x48>; + opp-hz = <0x00 0x8c30ac00>; + opp-microvolt = <0xf4240 0xf4240 0xf4240 0xf4240 0xf4240 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-2400000000 { + opp-supported-hw = <0xe9 0x80>; + opp-hz = <0x00 0x8f0d1800>; + opp-microvolt = <0xf4240 0xf4240 0xf4240 0xf4240 0xf4240 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-b-408000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x18519600>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>; + opp-microvolt-L0 = <0xadf34 0xadf34 0xe7ef0 0xadf34 0xadf34 0xe7ef0>; + opp-microvolt-L1 = <0xaae60 0xaae60 0xe7ef0 0xaae60 0xaae60 0xe7ef0>; + opp-microvolt-L2 = <0xa7d8c 0xa7d8c 0xe7ef0 0xa7d8c 0xa7d8c 0xe7ef0>; + clock-latency-ns = <0x9c40>; + opp-suspend; + }; + + opp-b-600000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x23c34600>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>; + opp-microvolt-L0 = <0xadf34 0xadf34 0xe7ef0 0xadf34 0xadf34 0xe7ef0>; + opp-microvolt-L1 = <0xaae60 0xaae60 0xe7ef0 0xaae60 0xaae60 0xe7ef0>; + opp-microvolt-L2 = <0xa7d8c 0xa7d8c 0xe7ef0 0xa7d8c 0xa7d8c 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-b-816000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x30a32c00>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>; + opp-microvolt-L0 = <0xadf34 0xadf34 0xe7ef0 0xadf34 0xadf34 0xe7ef0>; + opp-microvolt-L1 = <0xaae60 0xaae60 0xe7ef0 0xaae60 0xaae60 0xe7ef0>; + opp-microvolt-L2 = <0xa7d8c 0xa7d8c 0xe7ef0 0xa7d8c 0xa7d8c 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-b-1008000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x3c14dc00>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>; + opp-microvolt-L0 = <0xadf34 0xadf34 0xe7ef0 0xadf34 0xadf34 0xe7ef0>; + opp-microvolt-L1 = <0xaae60 0xaae60 0xe7ef0 0xaae60 0xaae60 0xe7ef0>; + opp-microvolt-L2 = <0xa7d8c 0xa7d8c 0xe7ef0 0xa7d8c 0xa7d8c 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-b-1200000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x47868c00>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>; + opp-microvolt-L0 = <0xadf34 0xadf34 0xe7ef0 0xadf34 0xadf34 0xe7ef0>; + opp-microvolt-L1 = <0xaae60 0xaae60 0xe7ef0 0xaae60 0xaae60 0xe7ef0>; + opp-microvolt-L2 = <0xa7d8c 0xa7d8c 0xe7ef0 0xa7d8c 0xa7d8c 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-b-1416000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x54667200>; + opp-microvolt = <0xb71b0 0xb71b0 0xf4240 0xb71b0 0xb71b0 0xf4240>; + opp-microvolt-L1 = <0xb40dc 0xb40dc 0xf4240 0xb40dc 0xb40dc 0xf4240>; + opp-microvolt-L2 = <0xb40dc 0xb40dc 0xf4240 0xb40dc 0xb40dc 0xf4240>; + opp-microvolt-L3 = <0xb1008 0xb1008 0xf4240 0xb1008 0xb1008 0xf4240>; + opp-microvolt-L4 = <0xb1008 0xb1008 0xf4240 0xb1008 0xb1008 0xf4240>; + opp-microvolt-L5 = <0xadf34 0xadf34 0xf4240 0xadf34 0xadf34 0xf4240>; + opp-microvolt-L6 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>; + opp-microvolt-L7 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>; + opp-microvolt-L8 = <0xa7d8c 0xa7d8c 0xf4240 0xa7d8c 0xa7d8c 0xf4240>; + opp-microvolt-L9 = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>; + opp-microvolt-L10 = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-b-1608000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x5fd82200>; + opp-microvolt = <0xc3500 0xc3500 0xf4240 0xc3500 0xc3500 0xf4240>; + opp-microvolt-L1 = <0xc042c 0xc042c 0xf4240 0xc042c 0xc042c 0xf4240>; + opp-microvolt-L2 = <0xbd358 0xbd358 0xf4240 0xbd358 0xbd358 0xf4240>; + opp-microvolt-L3 = <0xba284 0xba284 0xf4240 0xba284 0xba284 0xf4240>; + opp-microvolt-L4 = <0xba284 0xba284 0xf4240 0xba284 0xba284 0xf4240>; + opp-microvolt-L5 = <0xb71b0 0xb71b0 0xf4240 0xb71b0 0xb71b0 0xf4240>; + opp-microvolt-L6 = <0xb40dc 0xb40dc 0xf4240 0xb40dc 0xb40dc 0xf4240>; + opp-microvolt-L7 = <0xb1008 0xb1008 0xf4240 0xb1008 0xb1008 0xf4240>; + opp-microvolt-L8 = <0xadf34 0xadf34 0xf4240 0xadf34 0xadf34 0xf4240>; + opp-microvolt-L9 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>; + opp-microvolt-L10 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-b-1800000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x6b49d200>; + opp-microvolt = <0xd59f8 0xd59f8 0xf4240 0xd59f8 0xd59f8 0xf4240>; + opp-microvolt-L1 = <0xd59f8 0xd59f8 0xf4240 0xd59f8 0xd59f8 0xf4240>; + opp-microvolt-L2 = <0xd2924 0xd2924 0xf4240 0xd2924 0xd2924 0xf4240>; + opp-microvolt-L3 = <0xcf850 0xcf850 0xf4240 0xcf850 0xcf850 0xf4240>; + opp-microvolt-L4 = <0xcc77c 0xcc77c 0xf4240 0xcc77c 0xcc77c 0xf4240>; + opp-microvolt-L5 = <0xc96a8 0xc96a8 0xf4240 0xc96a8 0xc96a8 0xf4240>; + opp-microvolt-L6 = <0xc65d4 0xc65d4 0xf4240 0xc65d4 0xc65d4 0xf4240>; + opp-microvolt-L7 = <0xc3500 0xc3500 0xf4240 0xc3500 0xc3500 0xf4240>; + opp-microvolt-L8 = <0xc042c 0xc042c 0xf4240 0xc042c 0xc042c 0xf4240>; + opp-microvolt-L9 = <0xbd358 0xbd358 0xf4240 0xbd358 0xbd358 0xf4240>; + opp-microvolt-L10 = <0xba284 0xba284 0xf4240 0xba284 0xba284 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-b-2016000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x7829b800>; + opp-microvolt = <0xeafc4 0xeafc4 0xf4240 0xeafc4 0xeafc4 0xf4240>; + opp-microvolt-L1 = <0xe7ef0 0xe7ef0 0xf4240 0xe7ef0 0xe7ef0 0xf4240>; + opp-microvolt-L2 = <0xe4e1c 0xe4e1c 0xf4240 0xe4e1c 0xe4e1c 0xf4240>; + opp-microvolt-L3 = <0xe1d48 0xe1d48 0xf4240 0xe1d48 0xe1d48 0xf4240>; + opp-microvolt-L4 = <0xdec74 0xdec74 0xf4240 0xdec74 0xdec74 0xf4240>; + opp-microvolt-L5 = <0xdbba0 0xdbba0 0xf4240 0xdbba0 0xdbba0 0xf4240>; + opp-microvolt-L6 = <0xd8acc 0xd8acc 0xf4240 0xd8acc 0xd8acc 0xf4240>; + opp-microvolt-L7 = <0xd59f8 0xd59f8 0xf4240 0xd59f8 0xd59f8 0xf4240>; + opp-microvolt-L8 = <0xd2924 0xd2924 0xf4240 0xd2924 0xd2924 0xf4240>; + opp-microvolt-L9 = <0xcf850 0xcf850 0xf4240 0xcf850 0xcf850 0xf4240>; + opp-microvolt-L10 = <0xcc77c 0xcc77c 0xf4240 0xcc77c 0xcc77c 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-j-m-408000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x18519600>; + opp-microvolt = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-j-m-600000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x23c34600>; + opp-microvolt = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-j-m-816000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x30a32c00>; + opp-microvolt = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-j-m-1008000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x3c14dc00>; + opp-microvolt = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-j-m-1200000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x47868c00>; + opp-microvolt = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-j-m-1416000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x54667200>; + opp-microvolt = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>; + opp-microvolt-L0 = <0xba284 0xba284 0xe7ef0 0xba284 0xba284 0xe7ef0>; + clock-latency-ns = <0x9c40>; + opp-suspend; + }; + + opp-j-m-1608000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x5fd82200>; + opp-microvolt = <0xc042c 0xc042c 0xe7ef0 0xc042c 0xc042c 0xe7ef0>; + opp-microvolt-L2 = <0xbd358 0xbd358 0xe7ef0 0xbd358 0xbd358 0xe7ef0>; + opp-microvolt-L3 = <0xba284 0xba284 0xe7ef0 0xba284 0xba284 0xe7ef0>; + opp-microvolt-L4 = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>; + opp-microvolt-L5 = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>; + opp-microvolt-L6 = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>; + opp-microvolt-L7 = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-j-m-1800000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x6b49d200>; + opp-microvolt = <0xd59f8 0xd59f8 0xe7ef0 0xd59f8 0xd59f8 0xe7ef0>; + opp-microvolt-L1 = <0xd2924 0xd2924 0xe7ef0 0xd2924 0xd2924 0xe7ef0>; + opp-microvolt-L2 = <0xcf850 0xcf850 0xe7ef0 0xcf850 0xcf850 0xe7ef0>; + opp-microvolt-L3 = <0xcc77c 0xcc77c 0xe7ef0 0xcc77c 0xcc77c 0xe7ef0>; + opp-microvolt-L4 = <0xc96a8 0xc96a8 0xe7ef0 0xc96a8 0xc96a8 0xe7ef0>; + opp-microvolt-L5 = <0xc65d4 0xc65d4 0xe7ef0 0xc65d4 0xc65d4 0xe7ef0>; + opp-microvolt-L6 = <0xc3500 0xc3500 0xe7ef0 0xc3500 0xc3500 0xe7ef0>; + opp-microvolt-L7 = <0xc042c 0xc042c 0xe7ef0 0xc042c 0xc042c 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-j-m-2016000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x7829b800>; + opp-microvolt = <0xe7ef0 0xe7ef0 0xe7ef0 0xe7ef0 0xe7ef0 0xe7ef0>; + opp-microvolt-L1 = <0xe7ef0 0xe7ef0 0xe7ef0 0xe7ef0 0xe7ef0 0xe7ef0>; + opp-microvolt-L2 = <0xe4e1c 0xe4e1c 0xe7ef0 0xe4e1c 0xe4e1c 0xe7ef0>; + opp-microvolt-L3 = <0xe1d48 0xe1d48 0xe7ef0 0xe1d48 0xe1d48 0xe7ef0>; + opp-microvolt-L4 = <0xdec74 0xdec74 0xe7ef0 0xdec74 0xdec74 0xe7ef0>; + opp-microvolt-L5 = <0xdbba0 0xdbba0 0xe7ef0 0xdbba0 0xdbba0 0xe7ef0>; + opp-microvolt-L6 = <0xd8acc 0xd8acc 0xe7ef0 0xd8acc 0xd8acc 0xe7ef0>; + opp-microvolt-L7 = <0xd59f8 0xd59f8 0xe7ef0 0xd59f8 0xd59f8 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + }; + + cluster2-opp-table { + compatible = "operating-points-v2"; + opp-shared; + nvmem-cells = <0x29 0x2a 0x22 0x23>; + nvmem-cell-names = "leakage\0opp-info\0specification_serial_number\0customer_demand"; + rockchip,supported-hw; + rockchip,pvtm-hw = <0x06>; + rockchip,pvtm-voltage-sel-hw = <0x00 0x603 0x00 0x604 0x61c 0x01 0x61d 0x635 0x02 0x636 0x64e 0x03 0x64f 0x66c 0x04 0x66d 0x68a 0x05 0x68b 0x6a8 0x06 0x6a9 0x270f 0x07>; + rockchip,pvtm-voltage-sel-B4 = <0x00 0x5f5 0x00 0x5f6 0x609 0x01 0x60a 0x61d 0x02 0x61e 0x63b 0x03 0x63c 0x64f 0x04 0x650 0x668 0x05 0x669 0x68b 0x06 0x68c 0x6ae 0x07 0x6af 0x6cf 0x08 0x6d0 0x6f0 0x09 0x6f1 0x270f 0x0a>; + rockchip,pvtm-voltage-sel = <0x00 0x63b 0x00 0x63c 0x64f 0x01 0x650 0x668 0x02 0x669 0x68b 0x03 0x68c 0x6ae 0x04 0x6af 0x6cf 0x05 0x6d0 0x6f0 0x06 0x6f1 0x270f 0x07>; + rockchip,pvtm-pvtpll; + rockchip,pvtm-offset = <0x18>; + rockchip,pvtm-sample-time = <0x44c>; + rockchip,pvtm-freq = <0x188940>; + rockchip,pvtm-volt = <0xb71b0>; + rockchip,pvtm-ref-temp = <0x19>; + rockchip,pvtm-temp-prop = <0x10e 0x10e>; + rockchip,pvtm-thermal-zone = "soc-thermal"; + rockchip,pvtm-low-len-sel = <0x03>; + rockchip,grf = <0x2b>; + volt-mem-read-margin = <0xd0bd8 0x01 0xbac48 0x02 0xa4cb8 0x03 0x78d98 0x04>; + low-volt-mem-read-margin = <0x04>; + intermediate-threshold-freq = <0xf6180>; + rockchip,idle-threshold-freq = <0x21b100>; + rockchip,reboot-freq = <0x1b7740>; + rockchip,temp-hysteresis = <0x1388>; + rockchip,low-temp = <0x3a98>; + rockchip,low-temp-min-volt = "\0\f5"; + rockchip,high-temp = <0x14c08>; + rockchip,high-temp-max-freq = <0x21b100>; + phandle = <0x1b>; + + opp-408000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x18519600>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>; + clock-latency-ns = <0x9c40>; + opp-suspend; + }; + + opp-600000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x23c34600>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-816000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x30a32c00>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-1008000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x3c14dc00>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-1200000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x47868c00>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-1416000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x54667200>; + opp-microvolt = <0xb1008 0xb1008 0xf4240 0xb1008 0xb1008 0xf4240>; + opp-microvolt-L2 = <0xadf34 0xadf34 0xf4240 0xadf34 0xadf34 0xf4240>; + opp-microvolt-L3 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>; + opp-microvolt-L4 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>; + opp-microvolt-L5 = <0xa7d8c 0xa7d8c 0xf4240 0xa7d8c 0xa7d8c 0xf4240>; + opp-microvolt-L6 = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>; + opp-microvolt-L7 = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-1608000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x5fd82200>; + opp-microvolt = <0xba284 0xba284 0xf4240 0xba284 0xba284 0xf4240>; + opp-microvolt-L2 = <0xb71b0 0xb71b0 0xf4240 0xb71b0 0xb71b0 0xf4240>; + opp-microvolt-L3 = <0xb40dc 0xb40dc 0xf4240 0xb40dc 0xb40dc 0xf4240>; + opp-microvolt-L4 = <0xb1008 0xb1008 0xf4240 0xb1008 0xb1008 0xf4240>; + opp-microvolt-L5 = <0xadf34 0xadf34 0xf4240 0xadf34 0xadf34 0xf4240>; + opp-microvolt-L6 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>; + opp-microvolt-L7 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-1800000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x6b49d200>; + opp-microvolt = <0xcf850 0xcf850 0xf4240 0xcf850 0xcf850 0xf4240>; + opp-microvolt-L1 = <0xcc77c 0xcc77c 0xf4240 0xcc77c 0xcc77c 0xf4240>; + opp-microvolt-L2 = <0xc96a8 0xc96a8 0xf4240 0xc96a8 0xc96a8 0xf4240>; + opp-microvolt-L3 = <0xc65d4 0xc65d4 0xf4240 0xc65d4 0xc65d4 0xf4240>; + opp-microvolt-L4 = <0xc3500 0xc3500 0xf4240 0xc3500 0xc3500 0xf4240>; + opp-microvolt-L5 = <0xc042c 0xc042c 0xf4240 0xc042c 0xc042c 0xf4240>; + opp-microvolt-L6 = <0xbd358 0xbd358 0xf4240 0xbd358 0xbd358 0xf4240>; + opp-microvolt-L7 = <0xba284 0xba284 0xf4240 0xba284 0xba284 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-2016000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x7829b800>; + opp-microvolt = <0xe1d48 0xe1d48 0xf4240 0xe1d48 0xe1d48 0xf4240>; + opp-microvolt-L1 = <0xdec74 0xdec74 0xf4240 0xdec74 0xdec74 0xf4240>; + opp-microvolt-L2 = <0xdbba0 0xdbba0 0xf4240 0xdbba0 0xdbba0 0xf4240>; + opp-microvolt-L3 = <0xd8acc 0xd8acc 0xf4240 0xd8acc 0xd8acc 0xf4240>; + opp-microvolt-L4 = <0xd59f8 0xd59f8 0xf4240 0xd59f8 0xd59f8 0xf4240>; + opp-microvolt-L5 = <0xd2924 0xd2924 0xf4240 0xd2924 0xd2924 0xf4240>; + opp-microvolt-L6 = <0xcf850 0xcf850 0xf4240 0xcf850 0xcf850 0xf4240>; + opp-microvolt-L7 = <0xcc77c 0xcc77c 0xf4240 0xcc77c 0xcc77c 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-2208000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x839b6800>; + opp-microvolt = <0xf116c 0xf116c 0xf4240 0xf116c 0xf116c 0xf4240>; + opp-microvolt-L3 = <0xee098 0xee098 0xf4240 0xee098 0xee098 0xf4240>; + opp-microvolt-L4 = <0xeafc4 0xeafc4 0xf4240 0xeafc4 0xeafc4 0xf4240>; + opp-microvolt-L5 = <0xe7ef0 0xe7ef0 0xf4240 0xe7ef0 0xe7ef0 0xf4240>; + opp-microvolt-L6 = <0xe1d48 0xe1d48 0xf4240 0xe1d48 0xe1d48 0xf4240>; + opp-microvolt-L7 = <0xdec74 0xdec74 0xf4240 0xdec74 0xdec74 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-2256000000 { + opp-supported-hw = <0xe9 0x13>; + opp-hz = <0x00 0x8677d400>; + opp-microvolt = <0xf4240 0xf4240 0xf4240 0xf4240 0xf4240 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-2304000000 { + opp-supported-hw = <0xe9 0x24>; + opp-hz = <0x00 0x89544000>; + opp-microvolt = <0xf4240 0xf4240 0xf4240 0xf4240 0xf4240 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-2352000000 { + opp-supported-hw = <0xe9 0x48>; + opp-hz = <0x00 0x8c30ac00>; + opp-microvolt = <0xf4240 0xf4240 0xf4240 0xf4240 0xf4240 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-2400000000 { + opp-supported-hw = <0xe9 0x80>; + opp-hz = <0x00 0x8f0d1800>; + opp-microvolt = <0xf4240 0xf4240 0xf4240 0xf4240 0xf4240 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-b-408000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x18519600>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>; + opp-microvolt-L0 = <0xadf34 0xadf34 0xe7ef0 0xadf34 0xadf34 0xe7ef0>; + opp-microvolt-L1 = <0xaae60 0xaae60 0xe7ef0 0xaae60 0xaae60 0xe7ef0>; + opp-microvolt-L2 = <0xa7d8c 0xa7d8c 0xe7ef0 0xa7d8c 0xa7d8c 0xe7ef0>; + clock-latency-ns = <0x9c40>; + opp-suspend; + }; + + opp-b-600000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x23c34600>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>; + opp-microvolt-L0 = <0xadf34 0xadf34 0xe7ef0 0xadf34 0xadf34 0xe7ef0>; + opp-microvolt-L1 = <0xaae60 0xaae60 0xe7ef0 0xaae60 0xaae60 0xe7ef0>; + opp-microvolt-L2 = <0xa7d8c 0xa7d8c 0xe7ef0 0xa7d8c 0xa7d8c 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-b-816000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x30a32c00>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>; + opp-microvolt-L0 = <0xadf34 0xadf34 0xe7ef0 0xadf34 0xadf34 0xe7ef0>; + opp-microvolt-L1 = <0xaae60 0xaae60 0xe7ef0 0xaae60 0xaae60 0xe7ef0>; + opp-microvolt-L2 = <0xa7d8c 0xa7d8c 0xe7ef0 0xa7d8c 0xa7d8c 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-b-1008000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x3c14dc00>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>; + opp-microvolt-L0 = <0xadf34 0xadf34 0xe7ef0 0xadf34 0xadf34 0xe7ef0>; + opp-microvolt-L1 = <0xaae60 0xaae60 0xe7ef0 0xaae60 0xaae60 0xe7ef0>; + opp-microvolt-L2 = <0xa7d8c 0xa7d8c 0xe7ef0 0xa7d8c 0xa7d8c 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-b-1200000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x47868c00>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xe7ef0 0xa4cb8 0xa4cb8 0xe7ef0>; + opp-microvolt-L0 = <0xadf34 0xadf34 0xe7ef0 0xadf34 0xadf34 0xe7ef0>; + opp-microvolt-L1 = <0xaae60 0xaae60 0xe7ef0 0xaae60 0xaae60 0xe7ef0>; + opp-microvolt-L2 = <0xa7d8c 0xa7d8c 0xe7ef0 0xa7d8c 0xa7d8c 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-b-1416000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x54667200>; + opp-microvolt = <0xb71b0 0xb71b0 0xf4240 0xb71b0 0xb71b0 0xf4240>; + opp-microvolt-L1 = <0xb40dc 0xb40dc 0xf4240 0xb40dc 0xb40dc 0xf4240>; + opp-microvolt-L2 = <0xb40dc 0xb40dc 0xf4240 0xb40dc 0xb40dc 0xf4240>; + opp-microvolt-L3 = <0xb1008 0xb1008 0xf4240 0xb1008 0xb1008 0xf4240>; + opp-microvolt-L4 = <0xb1008 0xb1008 0xf4240 0xb1008 0xb1008 0xf4240>; + opp-microvolt-L5 = <0xadf34 0xadf34 0xf4240 0xadf34 0xadf34 0xf4240>; + opp-microvolt-L6 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>; + opp-microvolt-L7 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>; + opp-microvolt-L8 = <0xa7d8c 0xa7d8c 0xf4240 0xa7d8c 0xa7d8c 0xf4240>; + opp-microvolt-L9 = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>; + opp-microvolt-L10 = <0xa4cb8 0xa4cb8 0xf4240 0xa4cb8 0xa4cb8 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-b-1608000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x5fd82200>; + opp-microvolt = <0xc3500 0xc3500 0xf4240 0xc3500 0xc3500 0xf4240>; + opp-microvolt-L1 = <0xc042c 0xc042c 0xf4240 0xc042c 0xc042c 0xf4240>; + opp-microvolt-L2 = <0xbd358 0xbd358 0xf4240 0xbd358 0xbd358 0xf4240>; + opp-microvolt-L3 = <0xba284 0xba284 0xf4240 0xba284 0xba284 0xf4240>; + opp-microvolt-L4 = <0xba284 0xba284 0xf4240 0xba284 0xba284 0xf4240>; + opp-microvolt-L5 = <0xb71b0 0xb71b0 0xf4240 0xb71b0 0xb71b0 0xf4240>; + opp-microvolt-L6 = <0xb40dc 0xb40dc 0xf4240 0xb40dc 0xb40dc 0xf4240>; + opp-microvolt-L7 = <0xb1008 0xb1008 0xf4240 0xb1008 0xb1008 0xf4240>; + opp-microvolt-L8 = <0xadf34 0xadf34 0xf4240 0xadf34 0xadf34 0xf4240>; + opp-microvolt-L9 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>; + opp-microvolt-L10 = <0xaae60 0xaae60 0xf4240 0xaae60 0xaae60 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-b-1800000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x6b49d200>; + opp-microvolt = <0xd59f8 0xd59f8 0xf4240 0xd59f8 0xd59f8 0xf4240>; + opp-microvolt-L1 = <0xd59f8 0xd59f8 0xf4240 0xd59f8 0xd59f8 0xf4240>; + opp-microvolt-L2 = <0xd2924 0xd2924 0xf4240 0xd2924 0xd2924 0xf4240>; + opp-microvolt-L3 = <0xcf850 0xcf850 0xf4240 0xcf850 0xcf850 0xf4240>; + opp-microvolt-L4 = <0xcc77c 0xcc77c 0xf4240 0xcc77c 0xcc77c 0xf4240>; + opp-microvolt-L5 = <0xc96a8 0xc96a8 0xf4240 0xc96a8 0xc96a8 0xf4240>; + opp-microvolt-L6 = <0xc65d4 0xc65d4 0xf4240 0xc65d4 0xc65d4 0xf4240>; + opp-microvolt-L7 = <0xc3500 0xc3500 0xf4240 0xc3500 0xc3500 0xf4240>; + opp-microvolt-L8 = <0xc042c 0xc042c 0xf4240 0xc042c 0xc042c 0xf4240>; + opp-microvolt-L9 = <0xbd358 0xbd358 0xf4240 0xbd358 0xbd358 0xf4240>; + opp-microvolt-L10 = <0xba284 0xba284 0xf4240 0xba284 0xba284 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-b-2016000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x7829b800>; + opp-microvolt = <0xeafc4 0xeafc4 0xf4240 0xeafc4 0xeafc4 0xf4240>; + opp-microvolt-L1 = <0xe7ef0 0xe7ef0 0xf4240 0xe7ef0 0xe7ef0 0xf4240>; + opp-microvolt-L2 = <0xe4e1c 0xe4e1c 0xf4240 0xe4e1c 0xe4e1c 0xf4240>; + opp-microvolt-L3 = <0xe1d48 0xe1d48 0xf4240 0xe1d48 0xe1d48 0xf4240>; + opp-microvolt-L4 = <0xdec74 0xdec74 0xf4240 0xdec74 0xdec74 0xf4240>; + opp-microvolt-L5 = <0xdbba0 0xdbba0 0xf4240 0xdbba0 0xdbba0 0xf4240>; + opp-microvolt-L6 = <0xd8acc 0xd8acc 0xf4240 0xd8acc 0xd8acc 0xf4240>; + opp-microvolt-L7 = <0xd59f8 0xd59f8 0xf4240 0xd59f8 0xd59f8 0xf4240>; + opp-microvolt-L8 = <0xd2924 0xd2924 0xf4240 0xd2924 0xd2924 0xf4240>; + opp-microvolt-L9 = <0xcf850 0xcf850 0xf4240 0xcf850 0xcf850 0xf4240>; + opp-microvolt-L10 = <0xcc77c 0xcc77c 0xf4240 0xcc77c 0xcc77c 0xf4240>; + clock-latency-ns = <0x9c40>; + }; + + opp-j-m-408000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x18519600>; + opp-microvolt = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-j-m-600000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x23c34600>; + opp-microvolt = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-j-m-816000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x30a32c00>; + opp-microvolt = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-j-m-1008000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x3c14dc00>; + opp-microvolt = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-j-m-1200000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x47868c00>; + opp-microvolt = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-j-m-1416000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x54667200>; + opp-microvolt = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>; + opp-microvolt-L0 = <0xba284 0xba284 0xe7ef0 0xba284 0xba284 0xe7ef0>; + clock-latency-ns = <0x9c40>; + opp-suspend; + }; + + opp-j-m-1608000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x5fd82200>; + opp-microvolt = <0xc042c 0xc042c 0xe7ef0 0xc042c 0xc042c 0xe7ef0>; + opp-microvolt-L2 = <0xbd358 0xbd358 0xe7ef0 0xbd358 0xbd358 0xe7ef0>; + opp-microvolt-L3 = <0xba284 0xba284 0xe7ef0 0xba284 0xba284 0xe7ef0>; + opp-microvolt-L4 = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>; + opp-microvolt-L5 = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>; + opp-microvolt-L6 = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>; + opp-microvolt-L7 = <0xb71b0 0xb71b0 0xe7ef0 0xb71b0 0xb71b0 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-j-m-1800000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x6b49d200>; + opp-microvolt = <0xd59f8 0xd59f8 0xe7ef0 0xd59f8 0xd59f8 0xe7ef0>; + opp-microvolt-L1 = <0xd2924 0xd2924 0xe7ef0 0xd2924 0xd2924 0xe7ef0>; + opp-microvolt-L2 = <0xcf850 0xcf850 0xe7ef0 0xcf850 0xcf850 0xe7ef0>; + opp-microvolt-L3 = <0xcc77c 0xcc77c 0xe7ef0 0xcc77c 0xcc77c 0xe7ef0>; + opp-microvolt-L4 = <0xc96a8 0xc96a8 0xe7ef0 0xc96a8 0xc96a8 0xe7ef0>; + opp-microvolt-L5 = <0xc65d4 0xc65d4 0xe7ef0 0xc65d4 0xc65d4 0xe7ef0>; + opp-microvolt-L6 = <0xc3500 0xc3500 0xe7ef0 0xc3500 0xc3500 0xe7ef0>; + opp-microvolt-L7 = <0xc042c 0xc042c 0xe7ef0 0xc042c 0xc042c 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + + opp-j-m-2016000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x7829b800>; + opp-microvolt = <0xe7ef0 0xe7ef0 0xe7ef0 0xe7ef0 0xe7ef0 0xe7ef0>; + opp-microvolt-L1 = <0xe7ef0 0xe7ef0 0xe7ef0 0xe7ef0 0xe7ef0 0xe7ef0>; + opp-microvolt-L2 = <0xe4e1c 0xe4e1c 0xe7ef0 0xe4e1c 0xe4e1c 0xe7ef0>; + opp-microvolt-L3 = <0xe1d48 0xe1d48 0xe7ef0 0xe1d48 0xe1d48 0xe7ef0>; + opp-microvolt-L4 = <0xdec74 0xdec74 0xe7ef0 0xdec74 0xdec74 0xe7ef0>; + opp-microvolt-L5 = <0xdbba0 0xdbba0 0xe7ef0 0xdbba0 0xdbba0 0xe7ef0>; + opp-microvolt-L6 = <0xd8acc 0xd8acc 0xe7ef0 0xd8acc 0xd8acc 0xe7ef0>; + opp-microvolt-L7 = <0xd59f8 0xd59f8 0xe7ef0 0xd59f8 0xd59f8 0xe7ef0>; + clock-latency-ns = <0x9c40>; + }; + }; + + arm-pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <0x01 0x07 0x08>; + interrupt-affinity = <0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e>; + phandle = <0x227>; + }; + + cpuinfo { + compatible = "rockchip,cpuinfo"; + nvmem-cells = <0x2c 0x2d 0x2e>; + nvmem-cell-names = "id\0cpu-version\0cpu-code"; + }; + + csi2-dcphy0 { + compatible = "rockchip,rk3588-csi2-dphy"; + rockchip,hw = <0x2f 0x30>; + phys = <0x31 0x32>; + phy-names = "dcphy0\0dcphy1"; + status = "disabled"; + phandle = <0x228>; + }; + + csi2-dcphy1 { + compatible = "rockchip,rk3588-csi2-dphy"; + rockchip,hw = <0x2f 0x30>; + phys = <0x31 0x32>; + phy-names = "dcphy0\0dcphy1"; + status = "disabled"; + phandle = <0x229>; + }; + + csi2-dphy0 { + compatible = "rockchip,rk3588-csi2-dphy"; + rockchip,hw = <0x2f 0x30>; + phys = <0x31 0x32>; + phy-names = "dcphy0\0dcphy1"; + status = "okay"; + phandle = <0x22a>; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + #address-cells = <0x01>; + #size-cells = <0x00>; + + endpoint@1 { + reg = <0x01>; + remote-endpoint = <0x33>; + data-lanes = <0x01 0x02 0x03 0x04>; + phandle = <0x15c>; + }; + }; + + port@1 { + reg = <0x01>; + #address-cells = <0x01>; + #size-cells = <0x00>; + + endpoint@0 { + reg = <0x00>; + remote-endpoint = <0x34>; + phandle = <0x4e>; + }; + }; + }; + }; + + csi2-dphy1 { + compatible = "rockchip,rk3588-csi2-dphy"; + rockchip,hw = <0x2f 0x30>; + phys = <0x31 0x32>; + phy-names = "dcphy0\0dcphy1"; + status = "disabled"; + phandle = <0x22b>; + }; + + csi2-dphy2 { + compatible = "rockchip,rk3588-csi2-dphy"; + rockchip,hw = <0x2f 0x30>; + phys = <0x31 0x32>; + phy-names = "dcphy0\0dcphy1"; + status = "disabled"; + phandle = <0x22c>; + }; + + csi2-dphy3 { + compatible = "rockchip,rk3588-csi2-dphy"; + rockchip,hw = <0x2f 0x30>; + phys = <0x31 0x32>; + phy-names = "dcphy0\0dcphy1"; + status = "disabled"; + phandle = <0x22d>; + }; + + csi2-dphy4 { + compatible = "rockchip,rk3588-csi2-dphy"; + rockchip,hw = <0x2f 0x30>; + phys = <0x31 0x32>; + phy-names = "dcphy0\0dcphy1"; + status = "disabled"; + phandle = <0x22e>; + }; + + csi2-dphy5 { + compatible = "rockchip,rk3588-csi2-dphy"; + rockchip,hw = <0x2f 0x30>; + phys = <0x31 0x32>; + phy-names = "dcphy0\0dcphy1"; + status = "disabled"; + phandle = <0x22f>; + }; + + display-subsystem { + compatible = "rockchip,display-subsystem"; + ports = <0x35>; + clocks = <0x36 0x37>; + clock-names = "hdmi0_phy_pll\0hdmi1_phy_pll"; + memory-region = <0x38>; + memory-region-names = "drm-logo"; + phandle = <0x230>; + + route { + + route-dp0 { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <0x39>; + phandle = <0x231>; + }; + + route-dsi0 { + overscan,win_scale = <0x00>; + overscan,bottom_margin = <0x64>; + overscan,top_margin = <0x64>; + overscan,right_margin = <0x64>; + overscan,left_margin = <0x64>; + video,aspect_ratio = <0x00>; + video,flags = <0x0a>; + video,vrefresh = <0x3c>; + video,crtc_vsync_end = <0x791>; + video,crtc_hsync_end = <0x44b>; + video,vdisplay = <0x780>; + video,hdisplay = <0x438>; + video,clock = <0x203a0>; + logo,ymirror = <0x00>; + logo,bpp = <0x18>; + logo,height = <0x1f5>; + logo,width = <0x1f4>; + logo,offset = <0x228000>; + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <0x3a>; + phandle = <0x232>; + }; + + route-dsi1 { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <0x3b>; + phandle = <0x233>; + }; + + route-edp0 { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <0x3c>; + phandle = <0x234>; + }; + + route-edp1 { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + phandle = <0x235>; + }; + + route-hdmi0 { + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <0x3d>; + phandle = <0x236>; + }; + + route-rgb { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <0x3e>; + phandle = <0x237>; + }; + + route-dp1 { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <0x3f>; + phandle = <0x238>; + }; + + route-hdmi1 { + overscan,win_scale = <0x00>; + overscan,bottom_margin = <0x64>; + overscan,top_margin = <0x64>; + overscan,right_margin = <0x64>; + overscan,left_margin = <0x64>; + video,aspect_ratio = <0x02>; + video,flags = <0x05>; + video,vrefresh = <0x3c>; + video,crtc_vsync_end = <0x441>; + video,crtc_hsync_end = <0x804>; + video,vdisplay = <0x438>; + video,hdisplay = <0x780>; + video,clock = <0x24414>; + logo,ymirror = <0x00>; + logo,bpp = <0x18>; + logo,height = <0x1f5>; + logo,width = <0x1f4>; + logo,offset = <0x228000>; + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <0x40>; + phandle = <0x239>; + }; + }; + }; + + dmc { + compatible = "rockchip,rk3588-dmc"; + interrupts = <0x00 0x49 0x04>; + interrupt-names = "complete"; + devfreq-events = <0x41>; + clocks = <0x0f 0x04>; + clock-names = "dmc_clk"; + operating-points-v2 = <0x42>; + upthreshold = <0x28>; + downdifferential = <0x14>; + system-status-level = <0x01 0x04 0x08 0x08 0x02 0x01 0x10 0x04 0x10000 0x04 0x80000 0x04 0x1000 0x08 0x4000 0x08 0x2000 0x08 0xc00 0x08 0x40000 0x08 0x200000 0x08>; + auto-freq-en = <0x01>; + status = "okay"; + center-supply = <0x43>; + mem-supply = <0x44>; + phandle = <0x23a>; + }; + + dmc-opp-table { + compatible = "operating-points-v2"; + nvmem-cells = <0x45 0x46 0x22 0x23>; + nvmem-cell-names = "leakage\0opp-info\0specification_serial_number\0customer_demand"; + rockchip,supported-hw; + rockchip,leakage-voltage-sel = <0x01 0x1f 0x00 0x20 0x2c 0x01 0x2d 0x39 0x02 0x3a 0xfe 0x03>; + rockchip,temp-hysteresis = <0x1388>; + rockchip,low-temp = <0x3a98>; + rockchip,low-temp-min-volt = <0xb71b0>; + phandle = <0x42>; + + opp-528000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = <0x00 0x1f78a400>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xd59f8 0xb1008 0xb1008 0xc3500>; + opp-microvolt-L1 = <0xa4cb8 0xa4cb8 0xd59f8 0xaae60 0xaae60 0xc3500>; + opp-microvolt-L2 = <0xa4cb8 0xa4cb8 0xd59f8 0xa7d8c 0xa7d8c 0xc3500>; + opp-microvolt-L3 = <0xa4cb8 0xa4cb8 0xd59f8 0xa4cb8 0xa4cb8 0xc3500>; + }; + + opp-1068000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = <0x00 0x3fa86300>; + opp-microvolt = <0xb1008 0xb1008 0xd59f8 0xb40dc 0xb40dc 0xc3500>; + opp-microvolt-L1 = <0xaae60 0xaae60 0xd59f8 0xadf34 0xadf34 0xc3500>; + opp-microvolt-L2 = <0xa4cb8 0xa4cb8 0xd59f8 0xaae60 0xaae60 0xc3500>; + opp-microvolt-L3 = <0xa4cb8 0xa4cb8 0xd59f8 0xa7d8c 0xa7d8c 0xc3500>; + }; + + opp-1560000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = <0x00 0x5cfbb600>; + opp-microvolt = <0xc3500 0xc3500 0xd59f8 0xb71b0 0xb71b0 0xc3500>; + opp-microvolt-L1 = <0xbd358 0xbd358 0xd59f8 0xb1008 0xb1008 0xc3500>; + opp-microvolt-L2 = <0xb71b0 0xb71b0 0xd59f8 0xadf34 0xadf34 0xc3500>; + opp-microvolt-L3 = <0xb1008 0xb1008 0xd59f8 0xaae60 0xaae60 0xc3500>; + }; + + opp-2750000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0xa3e9ab80>; + opp-microvolt = <0xd59f8 0xd59f8 0xd59f8 0xb71b0 0xb71b0 0xc3500>; + opp-microvolt-L1 = <0xcf850 0xcf850 0xd59f8 0xb71b0 0xb71b0 0xc3500>; + opp-microvolt-L2 = <0xcc77c 0xcc77c 0xd59f8 0xb1008 0xb1008 0xc3500>; + opp-microvolt-L3 = <0xc96a8 0xc8320 0xd59f8 0xaae60 0xaae60 0xc3500>; + }; + + opp-b-1848000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x6e263e00>; + opp-microvolt = <0xd59f8 0xd59f8 0xd59f8 0xb71b0 0xb71b0 0xb71b0>; + opp-microvolt-L1 = <0xcf850 0xcf850 0xd59f8 0xb71b0 0xb71b0 0xb71b0>; + opp-microvolt-L2 = <0xcc77c 0xcc77c 0xd59f8 0xb1008 0xb1008 0xb71b0>; + opp-microvolt-L3 = <0xc96a8 0xc8320 0xd59f8 0xaae60 0xaae60 0xb71b0>; + }; + + opp-j-m-528000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x1f78a400>; + opp-microvolt = <0xb71b0 0xb71b0 0xd59f8 0xb71b0 0xb71b0 0xc3500>; + }; + + opp-j-m-1068000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x3fa86300>; + opp-microvolt = <0xb71b0 0xb71b0 0xd59f8 0xb71b0 0xb71b0 0xc3500>; + }; + + opp-j-m-1560000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x5cfbb600>; + opp-microvolt = <0xc3500 0xc3500 0xd59f8 0xb71b0 0xb71b0 0xc3500>; + opp-microvolt-L1 = <0xbd358 0xbd358 0xd59f8 0xb71b0 0xb71b0 0xc3500>; + opp-microvolt-L2 = <0xb71b0 0xb71b0 0xd59f8 0xb71b0 0xb71b0 0xc3500>; + opp-microvolt-L3 = <0xb71b0 0xb71b0 0xd59f8 0xb71b0 0xb71b0 0xc3500>; + }; + + opp-j-m-2750000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0xa3e9ab80>; + opp-microvolt = <0xd59f8 0xd59f8 0xd59f8 0xb71b0 0xb71b0 0xc3500>; + opp-microvolt-L1 = <0xcf850 0xcf850 0xd59f8 0xb71b0 0xb71b0 0xc3500>; + opp-microvolt-L2 = <0xcc77c 0xcc77c 0xd59f8 0xb71b0 0xb71b0 0xc3500>; + opp-microvolt-L3 = <0xc96a8 0xc8320 0xd59f8 0xb71b0 0xb71b0 0xc3500>; + }; + }; + + dmcdbg { + compatible = "rockchip,rk3588-dmcdbg"; + status = "disabled"; + phandle = <0x23b>; + }; + + firmware { + + scmi { + compatible = "arm,scmi-smc"; + shmem = <0x47>; + arm,smc-id = <0x82000010>; + #address-cells = <0x01>; + #size-cells = <0x00>; + phandle = <0x23c>; + + protocol@14 { + reg = <0x14>; + #clock-cells = <0x01>; + assigned-clocks = <0x0f 0x00 0x0f 0x02 0x0f 0x03>; + assigned-clock-rates = <0x30a32c00 0x30a32c00 0x30a32c00>; + phandle = <0x0f>; + }; + + protocol@16 { + reg = <0x16>; + #reset-cells = <0x01>; + phandle = <0x128>; + }; + }; + + sdei { + compatible = "arm,sdei-1.0"; + method = "smc"; + phandle = <0x23d>; + }; + + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + phandle = <0x23e>; + }; + }; + + jpege-ccu { + compatible = "rockchip,vpu-jpege-ccu"; + status = "okay"; + phandle = <0xbd>; + }; + + mipi-dcphy-dummy { + status = "disabled"; + phandle = <0x23f>; + }; + + mipi0-csi2 { + compatible = "rockchip,rk3588-mipi-csi2"; + rockchip,hw = <0x48 0x49 0x4a 0x4b 0x4c 0x4d>; + status = "disabled"; + phandle = <0x240>; + }; + + mipi1-csi2 { + compatible = "rockchip,rk3588-mipi-csi2"; + rockchip,hw = <0x48 0x49 0x4a 0x4b 0x4c 0x4d>; + status = "disabled"; + phandle = <0x241>; + }; + + mipi2-csi2 { + compatible = "rockchip,rk3588-mipi-csi2"; + rockchip,hw = <0x48 0x49 0x4a 0x4b 0x4c 0x4d>; + status = "okay"; + phandle = <0x242>; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + #address-cells = <0x01>; + #size-cells = <0x00>; + + endpoint@1 { + reg = <0x01>; + remote-endpoint = <0x4e>; + phandle = <0x34>; + }; + }; + + port@1 { + reg = <0x01>; + #address-cells = <0x01>; + #size-cells = <0x00>; + + endpoint@0 { + reg = <0x00>; + remote-endpoint = <0x4f>; + phandle = <0x54>; + }; + }; + }; + }; + + mipi3-csi2 { + compatible = "rockchip,rk3588-mipi-csi2"; + rockchip,hw = <0x48 0x49 0x4a 0x4b 0x4c 0x4d>; + status = "disabled"; + phandle = <0x243>; + }; + + mipi4-csi2 { + compatible = "rockchip,rk3588-mipi-csi2"; + rockchip,hw = <0x48 0x49 0x4a 0x4b 0x4c 0x4d>; + status = "disabled"; + phandle = <0x244>; + }; + + mipi5-csi2 { + compatible = "rockchip,rk3588-mipi-csi2"; + rockchip,hw = <0x48 0x49 0x4a 0x4b 0x4c 0x4d>; + status = "disabled"; + phandle = <0x245>; + }; + + mpp-srv { + compatible = "rockchip,mpp-service"; + rockchip,taskqueue-count = <0x0c>; + rockchip,resetgroup-count = <0x01>; + status = "okay"; + phandle = <0xb8>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + rkcif-dvp { + compatible = "rockchip,rkcif-dvp"; + rockchip,hw = <0x50>; + status = "disabled"; + phandle = <0x51>; + }; + + rkcif-dvp-sditf { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <0x51>; + status = "disabled"; + phandle = <0x246>; + }; + + rkcif-mipi-lvds { + compatible = "rockchip,rkcif-mipi-lvds"; + rockchip,hw = <0x50>; + status = "disabled"; + phandle = <0x52>; + }; + + rkcif-mipi-lvds-sditf { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <0x52>; + status = "disabled"; + phandle = <0x247>; + }; + + rkcif-mipi-lvds-sditf-vir1 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <0x52>; + status = "disabled"; + phandle = <0x248>; + }; + + rkcif-mipi-lvds-sditf-vir2 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <0x52>; + status = "disabled"; + phandle = <0x249>; + }; + + rkcif-mipi-lvds-sditf-vir3 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <0x52>; + status = "disabled"; + phandle = <0x24a>; + }; + + rkcif-mipi-lvds1 { + compatible = "rockchip,rkcif-mipi-lvds"; + rockchip,hw = <0x50>; + status = "disabled"; + phandle = <0x53>; + }; + + rkcif-mipi-lvds1-sditf { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <0x53>; + status = "disabled"; + phandle = <0x24b>; + }; + + rkcif-mipi-lvds1-sditf-vir1 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <0x53>; + status = "disabled"; + phandle = <0x24c>; + }; + + rkcif-mipi-lvds1-sditf-vir2 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <0x53>; + status = "disabled"; + phandle = <0x24d>; + }; + + rkcif-mipi-lvds1-sditf-vir3 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <0x53>; + status = "disabled"; + phandle = <0x24e>; + }; + + rkcif-mipi-lvds2 { + compatible = "rockchip,rkcif-mipi-lvds"; + rockchip,hw = <0x50>; + status = "okay"; + phandle = <0x55>; + + port { + + endpoint { + remote-endpoint = <0x54>; + phandle = <0x4f>; + }; + }; + }; + + rkcif-mipi-lvds2-sditf { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <0x55>; + status = "okay"; + phandle = <0x24f>; + + port { + + endpoint { + remote-endpoint = <0x56>; + phandle = <0x5b>; + }; + }; + }; + + rkcif-mipi-lvds2-sditf-vir1 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <0x55>; + status = "disabled"; + phandle = <0x250>; + }; + + rkcif-mipi-lvds2-sditf-vir2 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <0x55>; + status = "disabled"; + phandle = <0x251>; + }; + + rkcif-mipi-lvds2-sditf-vir3 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <0x55>; + status = "disabled"; + phandle = <0x252>; + }; + + rkcif-mipi-lvds3 { + compatible = "rockchip,rkcif-mipi-lvds"; + rockchip,hw = <0x50>; + status = "disabled"; + phandle = <0x57>; + }; + + rkcif-mipi-lvds3-sditf { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <0x57>; + status = "disabled"; + phandle = <0x253>; + }; + + rkcif-mipi-lvds3-sditf-vir1 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <0x57>; + status = "disabled"; + phandle = <0x254>; + }; + + rkcif-mipi-lvds3-sditf-vir2 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <0x57>; + status = "disabled"; + phandle = <0x255>; + }; + + rkcif-mipi-lvds3-sditf-vir3 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <0x57>; + status = "disabled"; + phandle = <0x256>; + }; + + rkcif-mipi-lvds4 { + compatible = "rockchip,rkcif-mipi-lvds"; + rockchip,hw = <0x50>; + status = "disabled"; + phandle = <0x58>; + }; + + rkcif-mipi-lvds4-sditf { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <0x58>; + status = "disabled"; + phandle = <0x257>; + }; + + rkcif-mipi-lvds4-sditf-vir1 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <0x58>; + status = "disabled"; + phandle = <0x258>; + }; + + rkcif-mipi-lvds4-sditf-vir2 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <0x58>; + status = "disabled"; + phandle = <0x259>; + }; + + rkcif-mipi-lvds4-sditf-vir3 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <0x58>; + status = "disabled"; + phandle = <0x25a>; + }; + + rkcif-mipi-lvds5 { + compatible = "rockchip,rkcif-mipi-lvds"; + rockchip,hw = <0x50>; + status = "disabled"; + phandle = <0x59>; + }; + + rkcif-mipi-lvds5-sditf { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <0x59>; + status = "disabled"; + phandle = <0x25b>; + }; + + rkcif-mipi-lvds5-sditf-vir1 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <0x59>; + status = "disabled"; + phandle = <0x25c>; + }; + + rkisp0-vir0 { + compatible = "rockchip,rkisp-vir"; + rockchip,hw = <0x5a>; + status = "okay"; + phandle = <0x25d>; + + port { + #address-cells = <0x01>; + #size-cells = <0x00>; + + endpoint@0 { + reg = <0x00>; + remote-endpoint = <0x5b>; + phandle = <0x56>; + }; + }; + }; + + rkisp0-vir1 { + compatible = "rockchip,rkisp-vir"; + rockchip,hw = <0x5a>; + status = "disabled"; + phandle = <0x25e>; + }; + + rkisp0-vir2 { + compatible = "rockchip,rkisp-vir"; + rockchip,hw = <0x5a>; + status = "disabled"; + phandle = <0x25f>; + }; + + rkisp0-vir3 { + compatible = "rockchip,rkisp-vir"; + rockchip,hw = <0x5a>; + status = "disabled"; + phandle = <0x260>; + }; + + rkisp1-vir0 { + compatible = "rockchip,rkisp-vir"; + rockchip,hw = <0x5c>; + status = "disabled"; + phandle = <0x261>; + }; + + rkisp1-vir1 { + compatible = "rockchip,rkisp-vir"; + rockchip,hw = <0x5c>; + status = "disabled"; + phandle = <0x262>; + }; + + rkisp1-vir2 { + compatible = "rockchip,rkisp-vir"; + rockchip,hw = <0x5c>; + status = "disabled"; + phandle = <0x263>; + }; + + rkisp1-vir3 { + compatible = "rockchip,rkisp-vir"; + rockchip,hw = <0x5c>; + status = "disabled"; + phandle = <0x264>; + }; + + rkispp0-vir0 { + compatible = "rockchip,rk3588-rkispp-vir"; + rockchip,hw = <0x5d>; + status = "disabled"; + phandle = <0x265>; + }; + + rkispp1-vir0 { + compatible = "rockchip,rk3588-rkispp-vir"; + rockchip,hw = <0x5e>; + status = "disabled"; + phandle = <0x266>; + }; + + rkvenc-ccu { + compatible = "rockchip,rkv-encoder-v2-ccu"; + status = "okay"; + phandle = <0xc3>; + }; + + rkvtunnel { + compatible = "rockchip,video-tunnel"; + status = "okay"; + phandle = <0x267>; + }; + + rockchip-suspend { + compatible = "rockchip,pm-rk3588"; + status = "okay"; + rockchip,sleep-debug-en = <0x01>; + rockchip,sleep-mode-config = <0x1000608>; + rockchip,wakeup-config = <0x100>; + power-domains = <0x06 0x1f>; + phandle = <0x268>; + }; + + rockchip-system-monitor { + compatible = "rockchip,system-monitor"; + rockchip,thermal-zone = "soc-thermal"; + phandle = <0x269>; + }; + + thermal-zones { + phandle = <0x26a>; + + soc-thermal { + polling-delay-passive = <0x14>; + polling-delay = <0x3e8>; + sustainable-power = <0x834>; + thermal-sensors = <0x5f 0x00>; + phandle = <0x26b>; + + trips { + + trip-point-0 { + temperature = <0x124f8>; + hysteresis = <0x7d0>; + type = "passive"; + phandle = <0x26c>; + }; + + trip-point-1 { + temperature = <0x14c08>; + hysteresis = <0x7d0>; + type = "passive"; + phandle = <0x60>; + }; + + soc-crit { + temperature = <0x1c138>; + hysteresis = <0x7d0>; + type = "critical"; + phandle = <0x26d>; + }; + }; + + cooling-maps { + + map0 { + trip = <0x60>; + cooling-device = <0x07 0xffffffff 0xffffffff>; + contribution = <0x400>; + }; + + map1 { + trip = <0x60>; + cooling-device = <0x0b 0xffffffff 0xffffffff>; + contribution = <0x400>; + }; + + map2 { + trip = <0x60>; + cooling-device = <0x0d 0xffffffff 0xffffffff>; + contribution = <0x400>; + }; + + map3 { + trip = <0x60>; + cooling-device = <0x61 0xffffffff 0xffffffff>; + contribution = <0x400>; + }; + }; + }; + + bigcore0-thermal { + polling-delay-passive = <0x14>; + polling-delay = <0x3e8>; + thermal-sensors = <0x5f 0x01>; + phandle = <0x26e>; + + trips { + + bigcore0-crit { + temperature = <0x1c138>; + hysteresis = <0x7d0>; + type = "critical"; + phandle = <0x26f>; + }; + }; + }; + + bigcore1-thermal { + polling-delay-passive = <0x14>; + polling-delay = <0x3e8>; + thermal-sensors = <0x5f 0x02>; + phandle = <0x270>; + + trips { + + bigcore1-crit { + temperature = <0x1c138>; + hysteresis = <0x7d0>; + type = "critical"; + phandle = <0x271>; + }; + }; + }; + + littlecore-thermal { + polling-delay-passive = <0x14>; + polling-delay = <0x3e8>; + thermal-sensors = <0x5f 0x03>; + phandle = <0x272>; + + trips { + + litcore-crit { + temperature = <0x1c138>; + hysteresis = <0x7d0>; + type = "critical"; + phandle = <0x273>; + }; + }; + }; + + center-thermal { + polling-delay-passive = <0x14>; + polling-delay = <0x3e8>; + thermal-sensors = <0x5f 0x04>; + phandle = <0x274>; + + trips { + + center-crit { + temperature = <0x1c138>; + hysteresis = <0x7d0>; + type = "critical"; + phandle = <0x275>; + }; + }; + }; + + gpu-thermal { + polling-delay-passive = <0x14>; + polling-delay = <0x3e8>; + thermal-sensors = <0x5f 0x05>; + phandle = <0x276>; + + trips { + + gpu-crit { + temperature = <0x1c138>; + hysteresis = <0x7d0>; + type = "critical"; + phandle = <0x277>; + }; + }; + }; + + npu-thermal { + polling-delay-passive = <0x14>; + polling-delay = <0x3e8>; + thermal-sensors = <0x5f 0x06>; + phandle = <0x278>; + + trips { + + npu-crit { + temperature = <0x1c138>; + hysteresis = <0x7d0>; + type = "critical"; + phandle = <0x279>; + }; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <0x01 0x0d 0xf04 0x01 0x0e 0xf04 0x01 0x0b 0xf04 0x01 0x0a 0xf04>; + }; + + sram@10f000 { + compatible = "mmio-sram"; + reg = <0x00 0x10f000 0x00 0x100>; + #address-cells = <0x01>; + #size-cells = <0x01>; + ranges = <0x00 0x00 0x10f000 0x100>; + + sram@0 { + compatible = "arm,scmi-shmem"; + reg = <0x00 0x100>; + phandle = <0x47>; + }; + }; + + gpu@fb000000 { + compatible = "arm,mali-valhall"; + reg = <0x00 0xfb000000 0x00 0x200000>; + interrupts = <0x00 0x5e 0x04 0x00 0x5d 0x04 0x00 0x5c 0x04>; + interrupt-names = "GPU\0MMU\0JOB"; + clocks = <0x0f 0x05 0x02 0x115 0x02 0x116 0x02 0x114>; + clock-names = "clk_mali\0clk_gpu_coregroup\0clk_gpu_stacks\0clk_gpu"; + assigned-clocks = <0x0f 0x05>; + assigned-clock-rates = <0xbebc200>; + power-domains = <0x06 0x0c>; + operating-points-v2 = <0x62>; + #cooling-cells = <0x02>; + dynamic-power-coefficient = <0xba6>; + upthreshold = <0x1e>; + downdifferential = <0x0a>; + status = "okay"; + mali-supply = <0x63>; + mem-supply = <0x63>; + phandle = <0x61>; + }; + + gpu-opp-table { + compatible = "operating-points-v2"; + nvmem-cells = <0x64 0x65 0x22 0x23>; + nvmem-cell-names = "leakage\0opp-info\0specification_serial_number\0customer_demand"; + rockchip,supported-hw; + rockchip,pvtm-hw = <0x04>; + rockchip,pvtm-voltage-sel-hw = <0x00 0x31f 0x00 0x320 0x333 0x01 0x334 0x34c 0x02 0x34d 0x365 0x03 0x366 0x37e 0x04 0x37f 0x270f 0x05>; + rockchip,pvtm-voltage-sel-B4 = <0x00 0x2f3 0x00 0x2f4 0x307 0x01 0x308 0x31b 0x02 0x31c 0x32f 0x03 0x330 0x343 0x04 0x344 0x35c 0x05 0x35d 0x375 0x06 0x376 0x38e 0x07 0x38f 0x270f 0x08>; + rockchip,pvtm-voltage-sel = <0x00 0x32f 0x00 0x330 0x343 0x01 0x344 0x35c 0x02 0x35d 0x375 0x03 0x376 0x38e 0x04 0x38f 0x270f 0x05>; + rockchip,pvtm-pvtpll; + rockchip,pvtm-offset = <0x1c>; + rockchip,pvtm-sample-time = <0x44c>; + rockchip,pvtm-freq = "\0\f5"; + rockchip,pvtm-volt = <0xb71b0>; + rockchip,pvtm-ref-temp = <0x19>; + rockchip,pvtm-temp-prop = <0xffffff79 0xffffff79>; + rockchip,pvtm-thermal-zone = "gpu-thermal"; + rockchip,opp-clocks = <0x02 0x114>; + rockchip,grf = <0x66>; + volt-mem-read-margin = <0xd0bd8 0x01 0xbac48 0x02 0xa4cb8 0x03 0x78d98 0x04>; + low-volt-mem-read-margin = <0x04>; + intermediate-threshold-freq = <0x61a80>; + rockchip,temp-hysteresis = <0x1388>; + rockchip,low-temp = <0x3a98>; + rockchip,low-temp-min-volt = <0xb71b0>; + rockchip,high-temp = <0x14c08>; + rockchip,high-temp-max-freq = "\0\f5"; + phandle = <0x62>; + + opp-300000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x11e1a300>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + }; + + opp-400000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x17d78400>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + }; + + opp-500000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x1dcd6500>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + }; + + opp-600000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x23c34600>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + }; + + opp-700000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x29b92700>; + opp-microvolt = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>; + opp-microvolt-L2 = <0xa7d8c 0xa7d8c 0xcf850 0xa7d8c 0xa7d8c 0xcf850>; + opp-microvolt-L3 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L4 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L5 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + }; + + opp-800000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x2faf0800>; + opp-microvolt = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>; + opp-microvolt-L1 = <0xb40dc 0xb40dc 0xcf850 0xb40dc 0xb40dc 0xcf850>; + opp-microvolt-L2 = <0xb1008 0xb1008 0xcf850 0xb1008 0xb1008 0xcf850>; + opp-microvolt-L3 = <0xadf34 0xadf34 0xcf850 0xadf34 0xadf34 0xcf850>; + opp-microvolt-L4 = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>; + opp-microvolt-L5 = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>; + }; + + opp-900000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x35a4e900>; + opp-microvolt = <0xc3500 0xc3500 0xcf850 0xc3500 0xc3500 0xcf850>; + opp-microvolt-L1 = <0xc042c 0xc042c 0xcf850 0xc042c 0xc042c 0xcf850>; + opp-microvolt-L2 = <0xbd358 0xbd358 0xcf850 0xbd358 0xbd358 0xcf850>; + opp-microvolt-L3 = <0xba284 0xba284 0xcf850 0xba284 0xba284 0xcf850>; + opp-microvolt-L4 = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>; + opp-microvolt-L5 = <0xb40dc 0xb40dc 0xcf850 0xb40dc 0xb40dc 0xcf850>; + }; + + opp-1000000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x3b9aca00>; + opp-microvolt = <0xcf850 0xcf850 0xcf850 0xcf850 0xcf850 0xcf850>; + opp-microvolt-L1 = <0xcc77c 0xcc77c 0xcf850 0xcc77c 0xcc77c 0xcf850>; + opp-microvolt-L2 = <0xc96a8 0xc96a8 0xcf850 0xc96a8 0xc96a8 0xcf850>; + opp-microvolt-L3 = <0xc65d4 0xc65d4 0xcf850 0xc65d4 0xc65d4 0xcf850>; + opp-microvolt-L4 = <0xc3500 0xc3500 0xcf850 0xc3500 0xc3500 0xcf850>; + opp-microvolt-L5 = <0xc042c 0xc042c 0xcf850 0xc042c 0xc042c 0xcf850>; + }; + + opp-b-300000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x11e1a300>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L0 = <0xadf34 0xadf34 0xcf850 0xadf34 0xadf34 0xcf850>; + opp-microvolt-L1 = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>; + opp-microvolt-L2 = <0xa7d8c 0xa7d8c 0xcf850 0xa7d8c 0xa7d8c 0xcf850>; + }; + + opp-b-400000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x17d78400>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L0 = <0xadf34 0xadf34 0xcf850 0xadf34 0xadf34 0xcf850>; + opp-microvolt-L1 = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>; + opp-microvolt-L2 = <0xa7d8c 0xa7d8c 0xcf850 0xa7d8c 0xa7d8c 0xcf850>; + }; + + opp-b-500000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x1dcd6500>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L0 = <0xadf34 0xadf34 0xcf850 0xadf34 0xadf34 0xcf850>; + opp-microvolt-L1 = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>; + opp-microvolt-L2 = <0xa7d8c 0xa7d8c 0xcf850 0xa7d8c 0xa7d8c 0xcf850>; + }; + + opp-b-600000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x23c34600>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L0 = <0xadf34 0xadf34 0xcf850 0xadf34 0xadf34 0xcf850>; + opp-microvolt-L1 = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>; + opp-microvolt-L2 = <0xa7d8c 0xa7d8c 0xcf850 0xa7d8c 0xa7d8c 0xcf850>; + }; + + opp-b-700000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x29b92700>; + opp-microvolt-L0 = <0xb40dc 0xb40dc 0xcf850 0xb40dc 0xb40dc 0xcf850>; + opp-microvolt-L1 = <0xb1008 0xb1008 0xcf850 0xb1008 0xb1008 0xcf850>; + opp-microvolt-L2 = <0xadf34 0xadf34 0xcf850 0xadf34 0xadf34 0xcf850>; + opp-microvolt-L3 = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>; + opp-microvolt-L4 = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>; + opp-microvolt-L5 = <0xa7d8c 0xa7d8c 0xcf850 0xa7d8c 0xa7d8c 0xcf850>; + opp-microvolt-L6 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L7 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L8 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + }; + + opp-b-800000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x2faf0800>; + opp-microvolt-L0 = <0xc042c 0xc042c 0xcf850 0xc042c 0xc042c 0xcf850>; + opp-microvolt-L1 = <0xbd358 0xbd358 0xcf850 0xbd358 0xbd358 0xcf850>; + opp-microvolt-L2 = <0xba284 0xba284 0xcf850 0xba284 0xba284 0xcf850>; + opp-microvolt-L3 = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>; + opp-microvolt-L4 = <0xb40dc 0xb40dc 0xcf850 0xb40dc 0xb40dc 0xcf850>; + opp-microvolt-L5 = <0xb1008 0xb1008 0xcf850 0xb1008 0xb1008 0xcf850>; + opp-microvolt-L6 = <0xadf34 0xadf34 0xcf850 0xadf34 0xadf34 0xcf850>; + opp-microvolt-L7 = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>; + opp-microvolt-L8 = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>; + }; + + opp-b-950000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x389fd980>; + opp-microvolt = <0xcf850 0xcf850 0xcf850 0xcf850 0xcf850 0xcf850>; + opp-microvolt-L2 = <0xcc77c 0xcc77c 0xcf850 0xcc77c 0xcc77c 0xcf850>; + opp-microvolt-L3 = <0xc96a8 0xc96a8 0xcf850 0xc96a8 0xc96a8 0xcf850>; + opp-microvolt-L4 = <0xc65d4 0xc65d4 0xcf850 0xc65d4 0xc65d4 0xcf850>; + opp-microvolt-L5 = <0xc3500 0xc3500 0xcf850 0xc3500 0xc3500 0xcf850>; + opp-microvolt-L6 = <0xc042c 0xc042c 0xcf850 0xc042c 0xc042c 0xcf850>; + opp-microvolt-L7 = <0xbd358 0xbd358 0xcf850 0xbd358 0xbd358 0xcf850>; + opp-microvolt-L8 = <0xba284 0xba284 0xcf850 0xba284 0xba284 0xcf850>; + }; + + opp-j-m-300000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x11e1a300>; + opp-microvolt = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>; + }; + + opp-j-m-400000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x17d78400>; + opp-microvolt = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>; + }; + + opp-j-m-500000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x1dcd6500>; + opp-microvolt = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>; + }; + + opp-j-m-600000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x23c34600>; + opp-microvolt = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>; + }; + + opp-j-m-700000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x29b92700>; + opp-microvolt = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>; + }; + + opp-j-850000000 { + opp-supported-hw = <0x04 0xffff>; + opp-hz = <0x00 0x32a9f880>; + opp-microvolt = <0xc042c 0xc042c 0xcf850 0xc042c 0xc042c 0xcf850>; + opp-microvolt-L1 = <0xbd358 0xbd358 0xcf850 0xbd358 0xbd358 0xcf850>; + opp-microvolt-L2 = <0xba284 0xba284 0xcf850 0xba284 0xba284 0xcf850>; + opp-microvolt-L3 = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>; + opp-microvolt-L4 = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>; + opp-microvolt-L5 = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>; + }; + + opp-m-800000000 { + opp-supported-hw = <0x02 0xffff>; + opp-hz = <0x00 0x2faf0800>; + opp-microvolt = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>; + }; + + opp-m-900000000 { + opp-supported-hw = <0x02 0xffff>; + opp-hz = <0x00 0x35a4e900>; + opp-microvolt = <0xc3500 0xc3500 0xcf850 0xc3500 0xc3500 0xcf850>; + opp-microvolt-L1 = <0xc042c 0xc042c 0xcf850 0xc042c 0xc042c 0xcf850>; + opp-microvolt-L2 = <0xbd358 0xbd358 0xcf850 0xbd358 0xbd358 0xcf850>; + opp-microvolt-L3 = <0xba284 0xba284 0xcf850 0xba284 0xba284 0xcf850>; + opp-microvolt-L4 = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>; + opp-microvolt-L5 = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>; + }; + + opp-m-1000000000 { + opp-supported-hw = <0x02 0xffff>; + opp-hz = <0x00 0x3b9aca00>; + opp-microvolt = <0xcf850 0xcf850 0xcf850 0xcf850 0xcf850 0xcf850>; + opp-microvolt-L1 = <0xcc77c 0xcc77c 0xcf850 0xcc77c 0xcc77c 0xcf850>; + opp-microvolt-L2 = <0xc96a8 0xc96a8 0xcf850 0xc96a8 0xc96a8 0xcf850>; + opp-microvolt-L3 = <0xc65d4 0xc65d4 0xcf850 0xc65d4 0xc65d4 0xcf850>; + opp-microvolt-L4 = <0xc3500 0xc3500 0xcf850 0xc3500 0xc3500 0xcf850>; + opp-microvolt-L5 = <0xc042c 0xc042c 0xcf850 0xc042c 0xc042c 0xcf850>; + }; + }; + + usbdrd3_0 { + compatible = "rockchip,rk3588-dwc3\0rockchip,rk3399-dwc3"; + clocks = <0x02 0x1a3 0x02 0x1a2 0x02 0x1a1>; + clock-names = "ref\0suspend\0bus"; + #address-cells = <0x02>; + #size-cells = <0x02>; + ranges; + status = "okay"; + phandle = <0x27a>; + + usb@fc000000 { + compatible = "snps,dwc3"; + reg = <0x00 0xfc000000 0x00 0x400000>; + interrupts = <0x00 0xdc 0x04>; + power-domains = <0x06 0x1f>; + resets = <0x02 0x2a4>; + reset-names = "usb3-otg"; + dr_mode = "otg"; + phys = <0x67 0x68>; + phy-names = "usb2-phy\0usb3-phy"; + phy_type = "utmi_wide"; + snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + snps,parkmode-disable-hs-quirk; + snps,parkmode-disable-ss-quirk; + quirk-skip-phy-init; + status = "okay"; + usb-role-switch; + phandle = <0x27b>; + + port { + #address-cells = <0x01>; + #size-cells = <0x00>; + + endpoint@0 { + reg = <0x00>; + remote-endpoint = <0x69>; + phandle = <0x192>; + }; + }; + }; + }; + + usb@fc800000 { + compatible = "rockchip,rk3588-ehci\0generic-ehci"; + reg = <0x00 0xfc800000 0x00 0x40000>; + interrupts = <0x00 0xd7 0x04>; + clocks = <0x02 0x19d 0x02 0x19e 0x6a 0x6b>; + clock-names = "usbhost\0arbiter\0utmi\0alk_usb"; + companion = <0x6c>; + phys = <0x6d>; + phy-names = "usb2-phy"; + power-domains = <0x06 0x1f>; + status = "okay"; + phandle = <0x27c>; + }; + + usb@fc840000 { + compatible = "rockchip,rk3588-ohci\0generic-ohci"; + reg = <0x00 0xfc840000 0x00 0x40000>; + interrupts = <0x00 0xd8 0x04>; + clocks = <0x02 0x19d 0x02 0x19e 0x6a 0x6b>; + clock-names = "usbhost\0arbiter\0utmi\0alk_usb"; + phys = <0x6d>; + phy-names = "usb2-phy"; + power-domains = <0x06 0x1f>; + status = "okay"; + phandle = <0x6c>; + }; + + usb@fc880000 { + compatible = "rockchip,rk3588-ehci\0generic-ehci"; + reg = <0x00 0xfc880000 0x00 0x40000>; + interrupts = <0x00 0xda 0x04>; + clocks = <0x02 0x19f 0x02 0x1a0 0x6e 0x6b>; + clock-names = "usbhost\0arbiter\0utmi\0alk_usb"; + companion = <0x6f>; + phys = <0x70>; + phy-names = "usb2-phy"; + power-domains = <0x06 0x1f>; + status = "okay"; + phandle = <0x27d>; + }; + + usb@fc8c0000 { + compatible = "rockchip,rk3588-ohci\0generic-ohci"; + reg = <0x00 0xfc8c0000 0x00 0x40000>; + interrupts = <0x00 0xdb 0x04>; + clocks = <0x02 0x19f 0x02 0x1a0 0x6e 0x6b>; + clock-names = "usbhost\0arbiter\0utmi\0alk_usb"; + phys = <0x70>; + phy-names = "usb2-phy"; + power-domains = <0x06 0x1f>; + status = "okay"; + phandle = <0x6f>; + }; + + iommu@fc900000 { + compatible = "arm,smmu-v3"; + reg = <0x00 0xfc900000 0x00 0x200000>; + interrupts = <0x00 0x171 0x04 0x00 0x173 0x04 0x00 0x176 0x04 0x00 0x16f 0x04>; + interrupt-names = "eventq\0gerror\0priq\0cmdq-sync"; + #iommu-cells = <0x01>; + status = "disabled"; + phandle = <0x27e>; + }; + + iommu@fcb00000 { + compatible = "arm,smmu-v3"; + reg = <0x00 0xfcb00000 0x00 0x200000>; + interrupts = <0x00 0x17d 0x04 0x00 0x17f 0x04 0x00 0x182 0x04 0x00 0x17b 0x04>; + interrupt-names = "eventq\0gerror\0priq\0cmdq-sync"; + #iommu-cells = <0x01>; + status = "disabled"; + phandle = <0x27f>; + }; + + usbhost3_0 { + compatible = "rockchip,rk3588-dwc3\0rockchip,rk3399-dwc3"; + clocks = <0x02 0x179 0x02 0x178 0x02 0x177 0x02 0x17a 0x02 0x166 0x02 0x181>; + clock-names = "ref\0suspend\0bus\0utmi\0php\0pipe"; + #address-cells = <0x02>; + #size-cells = <0x02>; + ranges; + status = "okay"; + phandle = <0x280>; + + usb@fcd00000 { + compatible = "snps,dwc3"; + reg = <0x00 0xfcd00000 0x00 0x400000>; + interrupts = <0x00 0xde 0x04>; + resets = <0x02 0x237>; + reset-names = "usb3-host"; + dr_mode = "host"; + phys = <0x71 0x04>; + phy-names = "usb3-phy"; + phy_type = "utmi_wide"; + snps,dis_enblslpm_quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + snps,dis_rxdet_inp3_quirk; + snps,parkmode-disable-hs-quirk; + snps,parkmode-disable-ss-quirk; + status = "okay"; + phandle = <0x281>; + }; + }; + + syscon@fd588000 { + compatible = "rockchip,rk3588-pmu0-grf\0syscon\0simple-mfd"; + reg = <0x00 0xfd588000 0x00 0x2000>; + phandle = <0x282>; + + reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x80>; + mode-bootloader = <0x5242c301>; + mode-charge = <0x5242c30b>; + mode-fastboot = <0x5242c309>; + mode-loader = <0x5242c301>; + mode-normal = <0x5242c300>; + mode-recovery = <0x5242c303>; + mode-ums = <0x5242c30c>; + mode-panic = <0x5242c307>; + mode-watchdog = <0x5242c308>; + mode-quiescent = <0x5242c30e>; + mode-winusb = <0x5242c30f>; + phandle = <0x283>; + }; + }; + + syscon@fd58a000 { + compatible = "rockchip,rk3588-pmu1-grf\0syscon"; + reg = <0x00 0xfd58a000 0x00 0x2000>; + phandle = <0x110>; + }; + + syscon@fd58c000 { + compatible = "rockchip,rk3588-sys-grf\0syscon\0simple-mfd"; + reg = <0x00 0xfd58c000 0x00 0x1000>; + phandle = <0xc9>; + + rgb { + compatible = "rockchip,rk3588-rgb"; + pinctrl-names = "default"; + pinctrl-0 = <0x72>; + status = "disabled"; + phandle = <0x284>; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + #address-cells = <0x01>; + #size-cells = <0x00>; + + endpoint@2 { + reg = <0x02>; + remote-endpoint = <0x3e>; + status = "disabled"; + phandle = <0xf3>; + }; + }; + }; + }; + }; + + syscon@fd590000 { + compatible = "rockchip,rk3588-bigcore0-grf\0syscon"; + reg = <0x00 0xfd590000 0x00 0x100>; + phandle = <0x28>; + }; + + syscon@fd592000 { + compatible = "rockchip,rk3588-bigcore1-grf\0syscon"; + reg = <0x00 0xfd592000 0x00 0x100>; + phandle = <0x2b>; + }; + + syscon@fd594000 { + compatible = "rockchip,rk3588-litcore-grf\0syscon"; + reg = <0x00 0xfd594000 0x00 0x100>; + phandle = <0x24>; + }; + + syscon@fd598000 { + compatible = "rockchip,rk3588-dsu-grf\0syscon"; + reg = <0x00 0xfd598000 0x00 0x100>; + phandle = <0x25>; + }; + + syscon@fd5a0000 { + compatible = "rockchip,rk3588-gpu-grf\0syscon"; + reg = <0x00 0xfd5a0000 0x00 0x100>; + phandle = <0x66>; + }; + + syscon@fd5a2000 { + compatible = "rockchip,rk3588-npu-grf\0syscon"; + reg = <0x00 0xfd5a2000 0x00 0x100>; + phandle = <0xb6>; + }; + + syscon@fd5a4000 { + compatible = "rockchip,rk3588-vop-grf\0syscon"; + reg = <0x00 0xfd5a4000 0x00 0x2000>; + phandle = <0xda>; + }; + + syscon@fd5a6000 { + compatible = "rockchip,rk3588-vo-grf\0syscon"; + reg = <0x00 0xfd5a6000 0x00 0x2000>; + clocks = <0x73>; + phandle = <0x102>; + }; + + syscon@fd5a8000 { + compatible = "rockchip,rk3588-vo-grf\0syscon"; + reg = <0x00 0xfd5a8000 0x00 0x100>; + clocks = <0x74>; + phandle = <0xdb>; + }; + + syscon@fd5ac000 { + compatible = "rockchip,rk3588-usb-grf\0syscon"; + reg = <0x00 0xfd5ac000 0x00 0x4000>; + phandle = <0x75>; + }; + + syscon@fd5b0000 { + compatible = "rockchip,rk3588-php-grf\0syscon"; + reg = <0x00 0xfd5b0000 0x00 0x1000>; + phandle = <0x77>; + }; + + syscon@fd5b4000 { + compatible = "rockchip,mipi-dphy-grf\0syscon"; + reg = <0x00 0xfd5b4000 0x00 0x1000>; + phandle = <0x1a5>; + }; + + syscon@fd5b5000 { + compatible = "rockchip,mipi-dphy-grf\0syscon"; + reg = <0x00 0xfd5b5000 0x00 0x1000>; + phandle = <0x1a6>; + }; + + syscon@fd5bc000 { + compatible = "rockchip,pipe-phy-grf\0syscon"; + reg = <0x00 0xfd5bc000 0x00 0x100>; + phandle = <0x1a7>; + }; + + syscon@fd5c4000 { + compatible = "rockchip,pipe-phy-grf\0syscon"; + reg = <0x00 0xfd5c4000 0x00 0x100>; + phandle = <0x1a8>; + }; + + syscon@fd5c8000 { + compatible = "rockchip,rk3588-usbdpphy-grf\0syscon"; + reg = <0x00 0xfd5c8000 0x00 0x4000>; + phandle = <0x19f>; + }; + + syscon@fd5d0000 { + compatible = "rockchip,rk3588-usb2phy-grf\0syscon\0simple-mfd"; + reg = <0x00 0xfd5d0000 0x00 0x4000>; + #address-cells = <0x01>; + #size-cells = <0x01>; + phandle = <0x19e>; + + usb2-phy@0 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0x00 0x10>; + interrupts = <0x00 0x189 0x04>; + resets = <0x02 0xc0047 0x02 0x488>; + reset-names = "phy\0apb"; + clocks = <0x02 0x2b5>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy0"; + #clock-cells = <0x00>; + rockchip,usbctrl-grf = <0x75>; + status = "okay"; + phandle = <0x1a0>; + + otg-port { + #phy-cells = <0x00>; + status = "okay"; + rockchip,typec-vbus-det; + phandle = <0x67>; + }; + }; + }; + + syscon@fd5d8000 { + compatible = "rockchip,rk3588-usb2phy-grf\0syscon\0simple-mfd"; + reg = <0x00 0xfd5d8000 0x00 0x4000>; + #address-cells = <0x01>; + #size-cells = <0x01>; + phandle = <0x285>; + + usb2-phy@8000 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0x8000 0x10>; + interrupts = <0x00 0x187 0x04>; + resets = <0x02 0xc0049 0x02 0x48a>; + reset-names = "phy\0apb"; + clocks = <0x02 0x2b5>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy2"; + #clock-cells = <0x00>; + status = "okay"; + phandle = <0x6a>; + + host-port { + #phy-cells = <0x00>; + status = "okay"; + phy-supply = <0x76>; + phandle = <0x6d>; + }; + }; + }; + + syscon@fd5dc000 { + compatible = "rockchip,rk3588-usb2phy-grf\0syscon\0simple-mfd"; + reg = <0x00 0xfd5dc000 0x00 0x4000>; + #address-cells = <0x01>; + #size-cells = <0x01>; + phandle = <0x286>; + + usb2-phy@c000 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0xc000 0x10>; + interrupts = <0x00 0x188 0x04>; + resets = <0x02 0xc004a 0x02 0x48b>; + reset-names = "phy\0apb"; + clocks = <0x02 0x2b5>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy3"; + #clock-cells = <0x00>; + status = "okay"; + phandle = <0x6e>; + + host-port { + #phy-cells = <0x00>; + status = "okay"; + phy-supply = <0x76>; + phandle = <0x70>; + }; + }; + }; + + syscon@fd5e0000 { + compatible = "rockchip,rk3588-hdptxphy-grf\0syscon"; + reg = <0x00 0xfd5e0000 0x00 0x100>; + phandle = <0x19d>; + }; + + syscon@fd5e8000 { + compatible = "rockchip,mipi-dcphy-grf\0syscon"; + reg = <0x00 0xfd5e8000 0x00 0x4000>; + phandle = <0x1a3>; + }; + + syscon@fd5ec000 { + compatible = "rockchip,mipi-dcphy-grf\0syscon"; + reg = <0x00 0xfd5ec000 0x00 0x4000>; + phandle = <0x1a4>; + }; + + syscon@fd5f0000 { + compatible = "rockchip,rk3588-ioc\0syscon"; + reg = <0x00 0xfd5f0000 0x00 0x10000>; + phandle = <0x1a9>; + }; + + clock-controller@fd7c0000 { + compatible = "rockchip,rk3588-cru"; + rockchip,grf = <0x77>; + reg = <0x00 0xfd7c0000 0x00 0x5c000>; + #clock-cells = <0x01>; + #reset-cells = <0x01>; + assigned-clocks = <0x02 0x09 0x02 0x05 0x02 0x08 0x02 0x07 0x02 0xd8 0x02 0xda 0x02 0xd9 0x02 0x10e 0x02 0x10f 0x02 0x110 0x02 0x299 0x02 0x29a 0x02 0x7b 0x02 0xec 0x02 0x114 0x02 0x208 0x02 0x20e 0x02 0x21f 0x02 0x77>; + assigned-clock-rates = <0x4190ab00 0x2ee00000 0x32a9f880 0x46cf7100 0x29d7ab80 0x17d78400 0x1dcd6500 0x2cb41780 0x5f5e100 0x17d78400 0x5f5e100 0xbebc200 0x165a0bc0 0x8f0d180 0xbebc200 0xb71b00 0xb71b00 0x5e69ec0 0x1312d00>; + phandle = <0x02>; + }; + + i2c@fd880000 { + compatible = "rockchip,rk3588-i2c\0rockchip,rk3399-i2c"; + reg = <0x00 0xfd880000 0x00 0x1000>; + clocks = <0x02 0x287 0x02 0x286>; + clock-names = "i2c\0pclk"; + interrupts = <0x00 0x13d 0x04>; + pinctrl-names = "default"; + pinctrl-0 = <0x78>; + resets = <0x02 0xc0022 0x02 0xc0021>; + reset-names = "i2c\0apb"; + #address-cells = <0x01>; + #size-cells = <0x00>; + status = "okay"; + phandle = <0x287>; + + rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <0x79>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big0_s0"; + regulator-min-microvolt = <0x86470>; + regulator-max-microvolt = <0x100590>; + regulator-ramp-delay = <0x8fc>; + rockchip,suspend-voltage-selector = <0x01>; + regulator-boot-on; + regulator-always-on; + phandle = <0x19>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk8603@43 { + compatible = "rockchip,rk8603"; + reg = <0x43>; + vin-supply = <0x79>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big1_s0"; + regulator-min-microvolt = <0x86470>; + regulator-max-microvolt = <0x100590>; + regulator-ramp-delay = <0x8fc>; + rockchip,suspend-voltage-selector = <0x01>; + regulator-boot-on; + regulator-always-on; + phandle = <0x1d>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + serial@fd890000 { + compatible = "rockchip,rk3588-uart\0snps,dw-apb-uart"; + reg = <0x00 0xfd890000 0x00 0x100>; + interrupts = <0x00 0x14b 0x04>; + clocks = <0x02 0x2ae 0x02 0x2af>; + clock-names = "baudclk\0apb_pclk"; + reg-shift = <0x02>; + reg-io-width = <0x04>; + dmas = <0x7a 0x06 0x7a 0x07>; + pinctrl-names = "default"; + pinctrl-0 = <0x7b>; + status = "disabled"; + phandle = <0x288>; + }; + + pwm@fd8b0000 { + compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm"; + reg = <0x00 0xfd8b0000 0x00 0x10>; + interrupts = <0x00 0x158 0x04>; + #pwm-cells = <0x03>; + pinctrl-names = "active"; + pinctrl-0 = <0x7c>; + clocks = <0x02 0x2a5 0x02 0x2a4>; + clock-names = "pwm\0pclk"; + status = "disabled"; + phandle = <0x289>; + }; + + pwm@fd8b0010 { + compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm"; + reg = <0x00 0xfd8b0010 0x00 0x10>; + interrupts = <0x00 0x158 0x04>; + #pwm-cells = <0x03>; + pinctrl-names = "active"; + pinctrl-0 = <0x7d>; + clocks = <0x02 0x2a5 0x02 0x2a4>; + clock-names = "pwm\0pclk"; + status = "okay"; + phandle = <0x1dc>; + }; + + pwm@fd8b0020 { + compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm"; + reg = <0x00 0xfd8b0020 0x00 0x10>; + interrupts = <0x00 0x158 0x04>; + #pwm-cells = <0x03>; + pinctrl-names = "active"; + pinctrl-0 = <0x7e>; + clocks = <0x02 0x2a5 0x02 0x2a4>; + clock-names = "pwm\0pclk"; + status = "disabled"; + phandle = <0x28a>; + }; + + pwm@fd8b0030 { + compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm"; + reg = <0x00 0xfd8b0030 0x00 0x10>; + interrupts = <0x00 0x158 0x04 0x00 0x159 0x04>; + #pwm-cells = <0x03>; + pinctrl-names = "active"; + pinctrl-0 = <0x7f>; + clocks = <0x02 0x2a5 0x02 0x2a4>; + clock-names = "pwm\0pclk"; + status = "okay"; + phandle = <0x1f3>; + }; + + power-management@fd8d8000 { + compatible = "rockchip,rk3588-pmu\0syscon\0simple-mfd"; + reg = <0x00 0xfd8d8000 0x00 0x400>; + phandle = <0xdc>; + + power-controller { + compatible = "rockchip,rk3588-power-controller"; + #power-domain-cells = <0x01>; + #address-cells = <0x01>; + #size-cells = <0x00>; + status = "okay"; + phandle = <0x06>; + + power-domain@8 { + reg = <0x08>; + #address-cells = <0x01>; + #size-cells = <0x00>; + + power-domain@9 { + reg = <0x09>; + #address-cells = <0x01>; + #size-cells = <0x00>; + clocks = <0x02 0x12f 0x02 0x131 0x02 0x130 0x02 0x126>; + pm_qos = <0x80 0x81 0x82>; + + power-domain@10 { + reg = <0x0a>; + clocks = <0x02 0x12f 0x02 0x131 0x02 0x130>; + pm_qos = <0x83>; + }; + + power-domain@11 { + reg = <0x0b>; + clocks = <0x02 0x12f 0x02 0x131 0x02 0x130>; + pm_qos = <0x84>; + }; + }; + }; + + power-domain@12 { + reg = <0x0c>; + clocks = <0x02 0x114 0x02 0x115 0x02 0x116>; + pm_qos = <0x85 0x86 0x87 0x88>; + }; + + power-domain@13 { + reg = <0x0d>; + #address-cells = <0x01>; + #size-cells = <0x00>; + + power-domain@14 { + reg = <0x0e>; + clocks = <0x02 0x18f 0x02 0x1be 0x02 0x1bc 0x02 0x190 0x02 0x18e>; + pm_qos = <0x89>; + }; + + power-domain@15 { + reg = <0x0f>; + clocks = <0x02 0x194 0x02 0x1be 0x02 0x1bc 0x02 0x195>; + pm_qos = <0x8a>; + }; + + power-domain@16 { + reg = <0x10>; + #address-cells = <0x01>; + #size-cells = <0x00>; + clocks = <0x02 0x1c4 0x02 0x1c5>; + pm_qos = <0x8b 0x8c 0x8d>; + + power-domain@17 { + reg = <0x11>; + clocks = <0x02 0x1c9 0x02 0x1c4 0x02 0x1c5 0x02 0x1ca>; + pm_qos = <0x8e 0x8f 0x90>; + }; + }; + }; + + power-domain@21 { + reg = <0x15>; + #address-cells = <0x01>; + #size-cells = <0x00>; + clocks = <0x02 0x1be 0x02 0x1bd 0x02 0x1bc 0x02 0x1bf 0x02 0x1aa 0x02 0x1a9 0x02 0x1ac 0x02 0x1ad 0x02 0x1ae 0x02 0x1af 0x02 0x1b0 0x02 0x1b1 0x02 0x1b2 0x02 0x1b3 0x02 0x1b4 0x02 0x1b5 0x02 0x1b7 0x02 0x1b6>; + pm_qos = <0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98>; + + power-domain@23 { + reg = <0x17>; + clocks = <0x02 0x4b 0x02 0x49 0x02 0x1be>; + pm_qos = <0x99>; + }; + + power-domain@14 { + reg = <0x0e>; + clocks = <0x02 0x18f 0x02 0x1be 0x02 0x1bc 0x02 0x190>; + pm_qos = <0x89>; + }; + + power-domain@15 { + reg = <0x0f>; + clocks = <0x02 0x194 0x02 0x1be 0x02 0x1bc>; + pm_qos = <0x8a>; + }; + + power-domain@22 { + reg = <0x16>; + clocks = <0x02 0x1ba 0x02 0x1b9>; + pm_qos = <0x9a>; + }; + }; + + power-domain@24 { + reg = <0x18>; + #address-cells = <0x01>; + #size-cells = <0x00>; + clocks = <0x02 0x26e 0x02 0x26d 0x02 0x270>; + pm_qos = <0x9b 0x9c>; + + power-domain@25 { + reg = <0x19>; + clocks = <0x02 0x1f6 0x02 0x1f7 0x02 0x1f5 0x02 0x1f3 0x02 0x1ee 0x02 0x1ed 0x02 0x26d>; + pm_qos = <0x9d>; + }; + }; + + power-domain@26 { + reg = <0x1a>; + clocks = <0x02 0x22e 0x02 0x22f 0x02 0x22d 0x02 0x218 0x02 0x217 0x02 0x22b 0x02 0x264>; + pm_qos = <0x9e 0x9f>; + }; + + power-domain@27 { + reg = <0x1b>; + #address-cells = <0x01>; + #size-cells = <0x00>; + clocks = <0x02 0x1e1 0x02 0x1e2 0x02 0x1df 0x02 0x1de 0x02 0x1e5 0x02 0x1e4>; + pm_qos = <0xa0 0xa1 0xa2 0xa3>; + + power-domain@28 { + reg = <0x1c>; + clocks = <0x02 0x121 0x02 0x120 0x02 0x1e1 0x02 0x1e2>; + pm_qos = <0xa4 0xa5>; + }; + + power-domain@29 { + reg = <0x1d>; + clocks = <0x02 0x1d6 0x02 0x1d5 0x02 0x1d9 0x02 0x1d8 0x02 0x1e2>; + pm_qos = <0xa6 0xa7>; + }; + }; + + power-domain@30 { + reg = <0x1e>; + clocks = <0x02 0x189 0x02 0x18a>; + pm_qos = <0xa8>; + }; + + power-domain@31 { + reg = <0x1f>; + clocks = <0x02 0x166 0x02 0x1a1 0x02 0x1a4 0x02 0x19d 0x02 0x19e 0x02 0x19f 0x02 0x1a0>; + pm_qos = <0xa9 0xaa 0xab 0xac>; + }; + + power-domain@33 { + reg = <0x21>; + clocks = <0x02 0x166 0x02 0x169 0x02 0x16a>; + }; + + power-domain@34 { + reg = <0x22>; + clocks = <0x02 0x166 0x02 0x169 0x02 0x16a>; + pm_qos = <0xad 0xae>; + }; + + power-domain@37 { + reg = <0x25>; + clocks = <0x02 0x199 0x02 0x140>; + pm_qos = <0xaf>; + }; + + power-domain@38 { + reg = <0x26>; + clocks = <0x02 0x3c 0x02 0x3d>; + }; + + power-domain@40 { + reg = <0x28>; + pm_qos = <0xb0>; + }; + }; + }; + + pvtm@fda40000 { + compatible = "rockchip,rk3588-bigcore0-pvtm"; + reg = <0x00 0xfda40000 0x00 0x100>; + #address-cells = <0x01>; + #size-cells = <0x00>; + + pvtm@0 { + reg = <0x00>; + clocks = <0x02 0x2c6 0x02 0x15>; + clock-names = "clk\0pclk"; + }; + }; + + pvtm@fda50000 { + compatible = "rockchip,rk3588-bigcore1-pvtm"; + reg = <0x00 0xfda50000 0x00 0x100>; + #address-cells = <0x01>; + #size-cells = <0x00>; + + pvtm@1 { + reg = <0x01>; + clocks = <0x02 0x2c8 0x02 0x17>; + clock-names = "clk\0pclk"; + }; + }; + + pvtm@fda60000 { + compatible = "rockchip,rk3588-litcore-pvtm"; + reg = <0x00 0xfda60000 0x00 0x100>; + #address-cells = <0x01>; + #size-cells = <0x00>; + + pvtm@2 { + reg = <0x02>; + clocks = <0x02 0x2ca 0x02 0x1b>; + clock-names = "clk\0pclk"; + }; + }; + + pvtm@fdaf0000 { + compatible = "rockchip,rk3588-npu-pvtm"; + reg = <0x00 0xfdaf0000 0x00 0x100>; + #address-cells = <0x01>; + #size-cells = <0x00>; + + pvtm@3 { + reg = <0x03>; + clocks = <0x02 0x12b 0x02 0x129>; + clock-names = "clk\0pclk"; + resets = <0x02 0x1de 0x02 0x1dc>; + reset-names = "rts\0rst-p"; + }; + }; + + pvtm@fdb30000 { + compatible = "rockchip,rk3588-gpu-pvtm"; + reg = <0x00 0xfdb30000 0x00 0x100>; + #address-cells = <0x01>; + #size-cells = <0x00>; + + pvtm@4 { + reg = <0x04>; + clocks = <0x02 0x118>; + clock-names = "clk"; + resets = <0x02 0x430 0x02 0x42f>; + reset-names = "rts\0rst-p"; + }; + }; + + npu@fdab0000 { + compatible = "rockchip,rk3588-rknpu"; + reg = <0x00 0xfdab0000 0x00 0x10000 0x00 0xfdac0000 0x00 0x10000 0x00 0xfdad0000 0x00 0x10000>; + interrupts = <0x00 0x6e 0x04 0x00 0x6f 0x04 0x00 0x70 0x04>; + interrupt-names = "npu0_irq\0npu1_irq\0npu2_irq"; + clocks = <0x0f 0x06 0x02 0x12d 0x02 0x122 0x02 0x124 0x02 0x12e 0x02 0x123 0x02 0x125 0x02 0x131>; + clock-names = "clk_npu\0aclk0\0aclk1\0aclk2\0hclk0\0hclk1\0hclk2\0pclk"; + assigned-clocks = <0x0f 0x06>; + assigned-clock-rates = <0xbebc200>; + resets = <0x02 0x1e6 0x02 0x1b0 0x02 0x1c0 0x02 0x1e8 0x02 0x1b2 0x02 0x1c2>; + reset-names = "srst_a0\0srst_a1\0srst_a2\0srst_h0\0srst_h1\0srst_h2"; + power-domains = <0x06 0x09 0x06 0x0a 0x06 0x0b>; + power-domain-names = "npu0\0npu1\0npu2"; + operating-points-v2 = <0xb1>; + iommus = <0xb2>; + status = "disabled"; + rknpu-supply = <0xb3>; + mem-supply = <0xb3>; + phandle = <0x28b>; + }; + + npu-opp-table { + compatible = "operating-points-v2"; + nvmem-cells = <0xb4 0xb5 0x22 0x23>; + nvmem-cell-names = "leakage\0opp-info\0specification_serial_number\0customer_demand"; + rockchip,supported-hw; + rockchip,pvtm-hw = <0x06>; + rockchip,pvtm-voltage-sel-hw = <0x00 0x31f 0x00 0x320 0x333 0x01 0x334 0x34c 0x02 0x34d 0x365 0x03 0x366 0x37e 0x04 0x37f 0x270f 0x05>; + rockchip,pvtm-voltage-sel-B4 = <0x00 0x2f3 0x00 0x2f4 0x307 0x01 0x308 0x31b 0x02 0x31c 0x32f 0x03 0x330 0x343 0x04 0x344 0x35c 0x05 0x35d 0x375 0x06 0x376 0x38e 0x07 0x38f 0x270f 0x08>; + rockchip,pvtm-voltage-sel = <0x00 0x32f 0x00 0x330 0x343 0x01 0x344 0x35c 0x02 0x35d 0x375 0x03 0x376 0x38e 0x04 0x38f 0x270f 0x05>; + rockchip,pvtm-pvtpll; + rockchip,pvtm-offset = <0x50>; + rockchip,pvtm-sample-time = <0x44c>; + rockchip,pvtm-freq = "\0\f5"; + rockchip,pvtm-volt = <0xb71b0>; + rockchip,pvtm-ref-temp = <0x19>; + rockchip,pvtm-temp-prop = <0xffffff8f 0xffffff8f>; + rockchip,pvtm-thermal-zone = "npu-thermal"; + rockchip,opp-clocks = <0x02 0x12a 0x02 0x12f>; + rockchip,grf = <0xb6>; + volt-mem-read-margin = <0xd0bd8 0x01 0xbac48 0x02 0xa4cb8 0x03 0x78d98 0x04>; + low-volt-mem-read-margin = <0x04>; + intermediate-threshold-freq = <0x7a120>; + rockchip,init-freq = <0xf4240>; + rockchip,temp-hysteresis = <0x1388>; + rockchip,low-temp = <0x3a98>; + rockchip,low-temp-min-volt = <0xb71b0>; + rockchip,high-temp = <0x14c08>; + rockchip,high-temp-max-freq = "\0\f5"; + phandle = <0xb1>; + + opp-300000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x11e1a300>; + opp-microvolt = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>; + opp-microvolt-L1 = <0xa7d8c 0xa7d8c 0xcf850 0xa7d8c 0xa7d8c 0xcf850>; + opp-microvolt-L2 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L3 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L4 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L5 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + }; + + opp-400000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x17d78400>; + opp-microvolt = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>; + opp-microvolt-L1 = <0xa7d8c 0xa7d8c 0xcf850 0xa7d8c 0xa7d8c 0xcf850>; + opp-microvolt-L2 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L3 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L4 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L5 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + }; + + opp-500000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x1dcd6500>; + opp-microvolt = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>; + opp-microvolt-L1 = <0xa7d8c 0xa7d8c 0xcf850 0xa7d8c 0xa7d8c 0xcf850>; + opp-microvolt-L2 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L3 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L4 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L5 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + }; + + opp-600000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x23c34600>; + opp-microvolt = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>; + opp-microvolt-L1 = <0xa7d8c 0xa7d8c 0xcf850 0xa7d8c 0xa7d8c 0xcf850>; + opp-microvolt-L2 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L3 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L4 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L5 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + }; + + opp-700000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x29b92700>; + opp-microvolt = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>; + opp-microvolt-L3 = <0xa7d8c 0xa7d8c 0xcf850 0xa7d8c 0xa7d8c 0xcf850>; + opp-microvolt-L4 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L5 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + }; + + opp-800000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x2faf0800>; + opp-microvolt = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>; + opp-microvolt-L2 = <0xb40dc 0xb40dc 0xcf850 0xb40dc 0xb40dc 0xcf850>; + opp-microvolt-L3 = <0xb1008 0xb1008 0xcf850 0xb1008 0xb1008 0xcf850>; + opp-microvolt-L4 = <0xadf34 0xadf34 0xcf850 0xadf34 0xadf34 0xcf850>; + opp-microvolt-L5 = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>; + }; + + opp-900000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x35a4e900>; + opp-microvolt = <0xc3500 0xc3500 0xcf850 0xc3500 0xc3500 0xcf850>; + opp-microvolt-L1 = <0xc042c 0xc042c 0xcf850 0xc042c 0xc042c 0xcf850>; + opp-microvolt-L2 = <0xbd358 0xbd358 0xcf850 0xbd358 0xbd358 0xcf850>; + opp-microvolt-L3 = <0xba284 0xba284 0xcf850 0xba284 0xba284 0xcf850>; + opp-microvolt-L4 = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>; + opp-microvolt-L5 = <0xb40dc 0xb40dc 0xcf850 0xb40dc 0xb40dc 0xcf850>; + }; + + opp-1000000000 { + opp-supported-hw = <0xe9 0xffff>; + opp-hz = <0x00 0x3b9aca00>; + opp-microvolt = <0xcf850 0xcf850 0xcf850 0xcf850 0xcf850 0xcf850>; + opp-microvolt-L1 = <0xcc77c 0xcc77c 0xcf850 0xcc77c 0xcc77c 0xcf850>; + opp-microvolt-L2 = <0xc96a8 0xc96a8 0xcf850 0xc96a8 0xc96a8 0xcf850>; + opp-microvolt-L3 = <0xc65d4 0xc65d4 0xcf850 0xc65d4 0xc65d4 0xcf850>; + opp-microvolt-L4 = <0xc3500 0xc3500 0xcf850 0xc3500 0xc3500 0xcf850>; + opp-microvolt-L5 = <0xc042c 0xc042c 0xcf850 0xc042c 0xc042c 0xcf850>; + }; + + opp-b-300000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x11e1a300>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L0 = <0xb1008 0xb1008 0xcf850 0xb1008 0xb1008 0xcf850>; + opp-microvolt-L1 = <0xadf34 0xadf34 0xcf850 0xadf34 0xadf34 0xcf850>; + opp-microvolt-L2 = <0xadf34 0xadf34 0xcf850 0xadf34 0xadf34 0xcf850>; + opp-microvolt-L3 = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>; + opp-microvolt-L4 = <0xa7d8c 0xa7d8c 0xcf850 0xa7d8c 0xa7d8c 0xcf850>; + }; + + opp-b-400000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x17d78400>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L0 = <0xb1008 0xb1008 0xcf850 0xb1008 0xb1008 0xcf850>; + opp-microvolt-L1 = <0xadf34 0xadf34 0xcf850 0xadf34 0xadf34 0xcf850>; + opp-microvolt-L2 = <0xadf34 0xadf34 0xcf850 0xadf34 0xadf34 0xcf850>; + opp-microvolt-L3 = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>; + opp-microvolt-L4 = <0xa7d8c 0xa7d8c 0xcf850 0xa7d8c 0xa7d8c 0xcf850>; + }; + + opp-b-500000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x1dcd6500>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L0 = <0xb1008 0xb1008 0xcf850 0xb1008 0xb1008 0xcf850>; + opp-microvolt-L1 = <0xadf34 0xadf34 0xcf850 0xadf34 0xadf34 0xcf850>; + opp-microvolt-L2 = <0xadf34 0xadf34 0xcf850 0xadf34 0xadf34 0xcf850>; + opp-microvolt-L3 = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>; + opp-microvolt-L4 = <0xa7d8c 0xa7d8c 0xcf850 0xa7d8c 0xa7d8c 0xcf850>; + }; + + opp-b-600000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x23c34600>; + opp-microvolt = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L0 = <0xb1008 0xb1008 0xcf850 0xb1008 0xb1008 0xcf850>; + opp-microvolt-L1 = <0xadf34 0xadf34 0xcf850 0xadf34 0xadf34 0xcf850>; + opp-microvolt-L2 = <0xadf34 0xadf34 0xcf850 0xadf34 0xadf34 0xcf850>; + opp-microvolt-L3 = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>; + opp-microvolt-L4 = <0xa7d8c 0xa7d8c 0xcf850 0xa7d8c 0xa7d8c 0xcf850>; + }; + + opp-b-700000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x29b92700>; + opp-microvolt = <0xb40dc 0xb40dc 0xcf850 0xb40dc 0xb40dc 0xcf850>; + opp-microvolt-L1 = <0xb1008 0xb1008 0xcf850 0xb1008 0xb1008 0xcf850>; + opp-microvolt-L2 = <0xadf34 0xadf34 0xcf850 0xadf34 0xadf34 0xcf850>; + opp-microvolt-L3 = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>; + opp-microvolt-L4 = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>; + opp-microvolt-L5 = <0xa7d8c 0xa7d8c 0xcf850 0xa7d8c 0xa7d8c 0xcf850>; + opp-microvolt-L6 = <0xa7d8c 0xa7d8c 0xcf850 0xa7d8c 0xa7d8c 0xcf850>; + opp-microvolt-L7 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + opp-microvolt-L8 = <0xa4cb8 0xa4cb8 0xcf850 0xa4cb8 0xa4cb8 0xcf850>; + }; + + opp-b-800000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x2faf0800>; + opp-microvolt = <0xc042c 0xc042c 0xcf850 0xc042c 0xc042c 0xcf850>; + opp-microvolt-L1 = <0xbd358 0xbd358 0xcf850 0xbd358 0xbd358 0xcf850>; + opp-microvolt-L2 = <0xba284 0xba284 0xcf850 0xba284 0xba284 0xcf850>; + opp-microvolt-L3 = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>; + opp-microvolt-L4 = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>; + opp-microvolt-L5 = <0xb40dc 0xb40dc 0xcf850 0xb40dc 0xb40dc 0xcf850>; + opp-microvolt-L6 = <0xb1008 0xb1008 0xcf850 0xb1008 0xb1008 0xcf850>; + opp-microvolt-L7 = <0xadf34 0xadf34 0xcf850 0xadf34 0xadf34 0xcf850>; + opp-microvolt-L8 = <0xaae60 0xaae60 0xcf850 0xaae60 0xaae60 0xcf850>; + }; + + opp-b-950000000 { + opp-supported-hw = <0x10 0xffff>; + opp-hz = <0x00 0x389fd980>; + opp-microvolt = <0xcf850 0xcf850 0xcf850 0xcf850 0xcf850 0xcf850>; + opp-microvolt-L2 = <0xcf850 0xcf850 0xcf850 0xcf850 0xcf850 0xcf850>; + opp-microvolt-L3 = <0xcc77c 0xcc77c 0xcf850 0xcc77c 0xcc77c 0xcf850>; + opp-microvolt-L4 = <0xc96a8 0xc96a8 0xcf850 0xc96a8 0xc96a8 0xcf850>; + opp-microvolt-L5 = <0xc65d4 0xc65d4 0xcf850 0xc65d4 0xc65d4 0xcf850>; + opp-microvolt-L6 = <0xc3500 0xc3500 0xcf850 0xc3500 0xc3500 0xcf850>; + opp-microvolt-L7 = <0xc042c 0xc042c 0xcf850 0xc042c 0xc042c 0xcf850>; + opp-microvolt-L8 = <0xbd358 0xbd358 0xcf850 0xbd358 0xbd358 0xcf850>; + }; + + opp-j-m-300000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x11e1a300>; + opp-microvolt = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>; + }; + + opp-j-m-400000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x17d78400>; + opp-microvolt = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>; + }; + + opp-j-m-500000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x1dcd6500>; + opp-microvolt = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>; + }; + + opp-j-m-600000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x23c34600>; + opp-microvolt = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>; + }; + + opp-j-m-700000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x29b92700>; + opp-microvolt = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>; + }; + + opp-j-m-800000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x2faf0800>; + opp-microvolt = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>; + }; + + opp-j-m-950000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = <0x00 0x389fd980>; + opp-microvolt = <0xcc77c 0xcc77c 0xcf850 0xcc77c 0xcc77c 0xcf850>; + opp-microvolt-L1 = <0xc96a8 0xc96a8 0xcf850 0xc96a8 0xc96a8 0xcf850>; + opp-microvolt-L2 = <0xc65d4 0xc65d4 0xcf850 0xc65d4 0xc65d4 0xcf850>; + opp-microvolt-L3 = <0xc3500 0xc3500 0xcf850 0xc3500 0xc3500 0xcf850>; + opp-microvolt-L4 = <0xc042c 0xc042c 0xcf850 0xc042c 0xc042c 0xcf850>; + opp-microvolt-L5 = <0xbd358 0xbd358 0xcf850 0xbd358 0xbd358 0xcf850>; + }; + }; + + iommu@fdab9000 { + compatible = "rockchip,iommu-v2"; + reg = <0x00 0xfdab9000 0x00 0x100 0x00 0xfdaba000 0x00 0x100 0x00 0xfdaca000 0x00 0x100 0x00 0xfdada000 0x00 0x100>; + interrupts = <0x00 0x6e 0x04 0x00 0x6f 0x04 0x00 0x70 0x04>; + interrupt-names = "npu0_mmu\0npu1_mmu\0npu2_mmu"; + clocks = <0x02 0x12d 0x02 0x122 0x02 0x124 0x02 0x12e 0x02 0x123 0x02 0x125>; + clock-names = "aclk0\0aclk1\0aclk2\0iface0\0iface1\0iface2"; + #iommu-cells = <0x00>; + status = "disabled"; + phandle = <0xb2>; + }; + + vepu@fdb50000 { + compatible = "rockchip,vpu-encoder-v2"; + reg = <0x00 0xfdb50000 0x00 0x400>; + interrupts = <0x00 0x78 0x04>; + interrupt-names = "irq_vepu"; + clocks = <0x02 0x1c0 0x02 0x1c1>; + clock-names = "aclk_vcodec\0hclk_vcodec"; + rockchip,normal-rates = <0x2367b880 0x00>; + assigned-clocks = <0x02 0x1c0>; + assigned-clock-rates = <0x2367b880>; + resets = <0x02 0x2c8 0x02 0x2c9>; + reset-names = "shared_video_a\0shared_video_h"; + rockchip,skip-pmu-idle-request; + rockchip,disable-auto-freq; + iommus = <0xb7>; + rockchip,srv = <0xb8>; + rockchip,taskqueue-node = <0x00>; + rockchip,resetgroup-node = <0x00>; + power-domains = <0x06 0x15>; + status = "okay"; + phandle = <0x28c>; + }; + + vdpu@fdb50400 { + compatible = "rockchip,vpu-decoder-v2"; + reg = <0x00 0xfdb50400 0x00 0x400>; + interrupts = <0x00 0x77 0x04>; + interrupt-names = "irq_vdpu"; + clocks = <0x02 0x1c0 0x02 0x1c1>; + clock-names = "aclk_vcodec\0hclk_vcodec"; + rockchip,normal-rates = <0x2367b880 0x00>; + assigned-clocks = <0x02 0x1c0>; + assigned-clock-rates = <0x2367b880>; + resets = <0x02 0x2c8 0x02 0x2c9>; + reset-names = "shared_video_a\0shared_video_h"; + rockchip,skip-pmu-idle-request; + rockchip,disable-auto-freq; + iommus = <0xb7>; + rockchip,srv = <0xb8>; + rockchip,taskqueue-node = <0x00>; + rockchip,resetgroup-node = <0x00>; + power-domains = <0x06 0x15>; + status = "okay"; + phandle = <0x28d>; + }; + + iommu@fdb50800 { + compatible = "rockchip,iommu-v2"; + reg = <0x00 0xfdb50800 0x00 0x40>; + interrupts = <0x00 0x76 0x04>; + interrupt-names = "irq_vdpu_mmu"; + clocks = <0x02 0x1c0 0x02 0x1c1>; + clock-names = "aclk\0iface"; + power-domains = <0x06 0x15>; + #iommu-cells = <0x00>; + status = "okay"; + phandle = <0xb7>; + }; + + avsd-plus@fdb51000 { + compatible = "rockchip,avs-plus-decoder"; + reg = <0x00 0xfdb51000 0x00 0x200>; + interrupts = <0x00 0x77 0x04>; + interrupt-names = "irq_avsd"; + clocks = <0x02 0x1c0 0x02 0x1c1>; + clock-names = "aclk_vcodec\0hclk_vcodec"; + rockchip,normal-rates = <0x2367b880 0x00>; + assigned-clocks = <0x02 0x1c0>; + assigned-clock-rates = <0x2367b880>; + resets = <0x02 0x2c8 0x02 0x2c9>; + reset-names = "shared_video_a\0shared_video_h"; + rockchip,skip-pmu-idle-request; + rockchip,disable-auto-freq; + iommus = <0xb7>; + power-domains = <0x06 0x15>; + rockchip,srv = <0xb8>; + rockchip,taskqueue-node = <0x00>; + rockchip,resetgroup-node = <0x00>; + status = "okay"; + phandle = <0x28e>; + }; + + rga@fdb60000 { + compatible = "rockchip,rga3_core0"; + reg = <0x00 0xfdb60000 0x00 0x1000>; + interrupts = <0x00 0x72 0x04>; + interrupt-names = "rga3_core0_irq"; + clocks = <0x02 0x1ba 0x02 0x1b9 0x02 0x1bb>; + clock-names = "aclk_rga3_0\0hclk_rga3_0\0clk_rga3_0"; + power-domains = <0x06 0x16>; + iommus = <0xb9>; + status = "okay"; + phandle = <0x28f>; + }; + + iommu@fdb60f00 { + compatible = "rockchip,iommu-v2"; + reg = <0x00 0xfdb60f00 0x00 0x100>; + interrupts = <0x00 0x72 0x04>; + interrupt-names = "rga3_0_mmu"; + clocks = <0x02 0x1ba 0x02 0x1b9>; + clock-names = "aclk\0iface"; + power-domains = <0x06 0x16>; + #iommu-cells = <0x00>; + status = "okay"; + phandle = <0xb9>; + }; + + rga@fdb70000 { + compatible = "rockchip,rga3_core1"; + reg = <0x00 0xfdb70000 0x00 0x1000>; + interrupts = <0x00 0x73 0x04>; + interrupt-names = "rga3_core1_irq"; + clocks = <0x02 0x18a 0x02 0x189 0x02 0x18b>; + clock-names = "aclk_rga3_1\0hclk_rga3_1\0clk_rga3_1"; + power-domains = <0x06 0x1e>; + iommus = <0xba>; + status = "okay"; + phandle = <0x290>; + }; + + iommu@fdb70f00 { + compatible = "rockchip,iommu-v2"; + reg = <0x00 0xfdb70f00 0x00 0x100>; + interrupts = <0x00 0x73 0x04>; + interrupt-names = "rga3_1_mmu"; + clocks = <0x02 0x18a 0x02 0x189>; + clock-names = "aclk\0iface"; + power-domains = <0x06 0x1e>; + #iommu-cells = <0x00>; + status = "okay"; + phandle = <0xba>; + }; + + rga@fdb80000 { + compatible = "rockchip,rga2_core0"; + reg = <0x00 0xfdb80000 0x00 0x1000>; + interrupts = <0x00 0x74 0x04>; + interrupt-names = "rga2_irq"; + clocks = <0x02 0x1b7 0x02 0x1b6 0x02 0x1b8>; + clock-names = "aclk_rga2\0hclk_rga2\0clk_rga2"; + power-domains = <0x06 0x15>; + status = "okay"; + phandle = <0x291>; + }; + + jpegd@fdb90000 { + compatible = "rockchip,rkv-jpeg-decoder-v1"; + reg = <0x00 0xfdb90000 0x00 0x400>; + interrupts = <0x00 0x81 0x04>; + interrupt-names = "irq_jpegd"; + clocks = <0x02 0x1b4 0x02 0x1b5>; + clock-names = "aclk_vcodec\0hclk_vcodec"; + rockchip,normal-rates = <0x23c34600 0x00>; + assigned-clocks = <0x02 0x1b4>; + assigned-clock-rates = <0x23c34600>; + resets = <0x02 0x2d2 0x02 0x2d3>; + reset-names = "video_a\0video_h"; + rockchip,skip-pmu-idle-request; + iommus = <0xbb>; + rockchip,srv = <0xb8>; + rockchip,taskqueue-node = <0x01>; + power-domains = <0x06 0x15>; + status = "okay"; + phandle = <0x292>; + }; + + iommu@fdb90480 { + compatible = "rockchip,iommu-v2"; + reg = <0x00 0xfdb90480 0x00 0x40>; + interrupts = <0x00 0x82 0x04>; + interrupt-names = "irq_jpegd_mmu"; + clocks = <0x02 0x1b4 0x02 0x1b5>; + clock-names = "aclk\0iface"; + power-domains = <0x06 0x15>; + #iommu-cells = <0x00>; + status = "okay"; + phandle = <0xbb>; + }; + + jpege-core@fdba0000 { + compatible = "rockchip,vpu-jpege-core"; + reg = <0x00 0xfdba0000 0x00 0x400>; + interrupts = <0x00 0x7a 0x04>; + interrupt-names = "irq_jpege0"; + clocks = <0x02 0x1ac 0x02 0x1ad>; + clock-names = "aclk_vcodec\0hclk_vcodec"; + rockchip,normal-rates = <0x2367b880 0x00>; + assigned-clocks = <0x02 0x1ac>; + assigned-clock-rates = <0x2367b880>; + resets = <0x02 0x2ca 0x02 0x2cb>; + reset-names = "video_a\0video_h"; + rockchip,skip-pmu-idle-request; + rockchip,disable-auto-freq; + iommus = <0xbc>; + rockchip,srv = <0xb8>; + rockchip,taskqueue-node = <0x02>; + rockchip,ccu = <0xbd>; + power-domains = <0x06 0x15>; + status = "okay"; + phandle = <0x293>; + }; + + iommu@fdba0800 { + compatible = "rockchip,iommu-v2"; + reg = <0x00 0xfdba0800 0x00 0x40>; + interrupts = <0x00 0x79 0x04>; + interrupt-names = "irq_jpege0_mmu"; + clocks = <0x02 0x1ac 0x02 0x1ad>; + clock-names = "aclk\0iface"; + power-domains = <0x06 0x15>; + #iommu-cells = <0x00>; + status = "okay"; + phandle = <0xbc>; + }; + + jpege-core@fdba4000 { + compatible = "rockchip,vpu-jpege-core"; + reg = <0x00 0xfdba4000 0x00 0x400>; + interrupts = <0x00 0x7c 0x04>; + interrupt-names = "irq_jpege1"; + clocks = <0x02 0x1ae 0x02 0x1af>; + clock-names = "aclk_vcodec\0hclk_vcodec"; + rockchip,normal-rates = <0x2367b880 0x00>; + assigned-clocks = <0x02 0x1ae>; + assigned-clock-rates = <0x2367b880>; + resets = <0x02 0x2cc 0x02 0x2cd>; + reset-names = "video_a\0video_h"; + rockchip,skip-pmu-idle-request; + rockchip,disable-auto-freq; + iommus = <0xbe>; + rockchip,srv = <0xb8>; + rockchip,taskqueue-node = <0x02>; + rockchip,ccu = <0xbd>; + power-domains = <0x06 0x15>; + status = "okay"; + phandle = <0x294>; + }; + + iommu@fdba4800 { + compatible = "rockchip,iommu-v2"; + reg = <0x00 0xfdba4800 0x00 0x40>; + interrupts = <0x00 0x7b 0x04>; + interrupt-names = "irq_jpege1_mmu"; + clocks = <0x02 0x1ae 0x02 0x1af>; + clock-names = "aclk\0iface"; + power-domains = <0x06 0x15>; + #iommu-cells = <0x00>; + status = "okay"; + phandle = <0xbe>; + }; + + jpege-core@fdba8000 { + compatible = "rockchip,vpu-jpege-core"; + reg = <0x00 0xfdba8000 0x00 0x400>; + interrupts = <0x00 0x7e 0x04>; + interrupt-names = "irq_jpege2"; + clocks = <0x02 0x1b0 0x02 0x1b1>; + clock-names = "aclk_vcodec\0hclk_vcodec"; + rockchip,normal-rates = <0x2367b880 0x00>; + assigned-clocks = <0x02 0x1b0>; + assigned-clock-rates = <0x2367b880>; + resets = <0x02 0x2ce 0x02 0x2cf>; + reset-names = "video_a\0video_h"; + rockchip,skip-pmu-idle-request; + rockchip,disable-auto-freq; + iommus = <0xbf>; + rockchip,srv = <0xb8>; + rockchip,taskqueue-node = <0x02>; + rockchip,ccu = <0xbd>; + power-domains = <0x06 0x15>; + status = "okay"; + phandle = <0x295>; + }; + + iommu@fdba8800 { + compatible = "rockchip,iommu-v2"; + reg = <0x00 0xfdba8800 0x00 0x40>; + interrupts = <0x00 0x7d 0x04>; + interrupt-names = "irq_jpege2_mmu"; + clocks = <0x02 0x1b0 0x02 0x1b1>; + clock-names = "aclk\0iface"; + power-domains = <0x06 0x15>; + #iommu-cells = <0x00>; + status = "okay"; + phandle = <0xbf>; + }; + + jpege-core@fdbac000 { + compatible = "rockchip,vpu-jpege-core"; + reg = <0x00 0xfdbac000 0x00 0x400>; + interrupts = <0x00 0x80 0x04>; + interrupt-names = "irq_jpege3"; + clocks = <0x02 0x1b2 0x02 0x1b3>; + clock-names = "aclk_vcodec\0hclk_vcodec"; + rockchip,normal-rates = <0x2367b880 0x00>; + assigned-clocks = <0x02 0x1b2>; + assigned-clock-rates = <0x2367b880>; + resets = <0x02 0x2d0 0x02 0x2d1>; + reset-names = "video_a\0video_h"; + rockchip,skip-pmu-idle-request; + rockchip,disable-auto-freq; + iommus = <0xc0>; + rockchip,srv = <0xb8>; + rockchip,taskqueue-node = <0x02>; + rockchip,ccu = <0xbd>; + power-domains = <0x06 0x15>; + status = "okay"; + phandle = <0x296>; + }; + + iommu@fdbac800 { + compatible = "rockchip,iommu-v2"; + reg = <0x00 0xfdbac800 0x00 0x40>; + interrupts = <0x00 0x7f 0x04>; + interrupt-names = "irq_jpege3_mmu"; + clocks = <0x02 0x1b2 0x02 0x1b3>; + clock-names = "aclk\0iface"; + power-domains = <0x06 0x15>; + #iommu-cells = <0x00>; + status = "okay"; + phandle = <0xc0>; + }; + + iep@fdbb0000 { + compatible = "rockchip,iep-v2"; + reg = <0x00 0xfdbb0000 0x00 0x500>; + interrupts = <0x00 0x75 0x04>; + interrupt-names = "irq_iep"; + clocks = <0x02 0x1aa 0x02 0x1a9 0x02 0x1ab>; + clock-names = "aclk\0hclk\0sclk"; + rockchip,normal-rates = <0x2367b880 0x00>; + assigned-clocks = <0x02 0x1aa>; + assigned-clock-rates = <0x2367b880>; + resets = <0x02 0x2d5 0x02 0x2d4 0x02 0x2d6>; + reset-names = "rst_a\0rst_h\0rst_s"; + rockchip,skip-pmu-idle-request; + rockchip,disable-auto-freq; + power-domains = <0x06 0x15>; + rockchip,srv = <0xb8>; + rockchip,taskqueue-node = <0x06>; + iommus = <0xc1>; + status = "okay"; + phandle = <0x297>; + }; + + iommu@fdbb0800 { + compatible = "rockchip,iommu-v2"; + reg = <0x00 0xfdbb0800 0x00 0x100>; + interrupts = <0x00 0x75 0x04>; + interrupt-names = "irq_iep_mmu"; + clocks = <0x02 0x1aa 0x02 0x1a9>; + clock-names = "aclk\0iface"; + #iommu-cells = <0x00>; + power-domains = <0x06 0x15>; + status = "okay"; + phandle = <0xc1>; + }; + + rkvenc-core@fdbd0000 { + compatible = "rockchip,rkv-encoder-v2-core"; + reg = <0x00 0xfdbd0000 0x00 0x6000>; + interrupts = <0x00 0x65 0x04>; + interrupt-names = "irq_rkvenc0"; + clocks = <0x02 0x1c5 0x02 0x1c4 0x02 0x1c6>; + clock-names = "aclk_vcodec\0hclk_vcodec\0clk_core"; + rockchip,normal-rates = <0x1dcd6500 0x00 0x2faf0800>; + assigned-clocks = <0x02 0x1c5 0x02 0x1c6>; + assigned-clock-rates = <0x1dcd6500 0x2faf0800>; + resets = <0x02 0x2f5 0x02 0x2f4 0x02 0x2f6>; + reset-names = "video_a\0video_h\0video_core"; + rockchip,skip-pmu-idle-request; + iommus = <0xc2>; + rockchip,srv = <0xb8>; + rockchip,ccu = <0xc3>; + rockchip,taskqueue-node = <0x07>; + rockchip,task-capacity = <0x08>; + power-domains = <0x06 0x10>; + operating-points-v2 = <0xc4>; + status = "okay"; + venc-supply = <0xc5>; + mem-supply = <0xc5>; + phandle = <0x298>; + }; + + iommu@fdbdf000 { + compatible = "rockchip,iommu-v2"; + reg = <0x00 0xfdbdf000 0x00 0x40 0x00 0xfdbdf040 0x00 0x40>; + interrupts = <0x00 0x63 0x04 0x00 0x64 0x04>; + interrupt-names = "irq_rkvenc0_mmu0\0irq_rkvenc0_mmu1"; + clocks = <0x02 0x1c5 0x02 0x1c4>; + clock-names = "aclk\0iface"; + rockchip,disable-mmu-reset; + rockchip,enable-cmd-retry; + rockchip,shootdown-entire; + #iommu-cells = <0x00>; + power-domains = <0x06 0x10>; + status = "okay"; + phandle = <0xc2>; + }; + + rkvenc-core@fdbe0000 { + compatible = "rockchip,rkv-encoder-v2-core"; + reg = <0x00 0xfdbe0000 0x00 0x6000>; + interrupts = <0x00 0x68 0x04>; + interrupt-names = "irq_rkvenc1"; + clocks = <0x02 0x1ca 0x02 0x1c9 0x02 0x1cb>; + clock-names = "aclk_vcodec\0hclk_vcodec\0clk_core"; + rockchip,normal-rates = <0x1dcd6500 0x00 0x2faf0800>; + assigned-clocks = <0x02 0x1ca 0x02 0x1cb>; + assigned-clock-rates = <0x1dcd6500 0x2faf0800>; + resets = <0x02 0x305 0x02 0x304 0x02 0x306>; + reset-names = "video_a\0video_h\0video_core"; + rockchip,skip-pmu-idle-request; + iommus = <0xc6>; + rockchip,srv = <0xb8>; + rockchip,ccu = <0xc3>; + rockchip,taskqueue-node = <0x07>; + rockchip,task-capacity = <0x08>; + power-domains = <0x06 0x11>; + operating-points-v2 = <0xc4>; + status = "okay"; + venc-supply = <0xc5>; + mem-supply = <0xc5>; + phandle = <0x299>; + }; + + iommu@fdbef000 { + compatible = "rockchip,iommu-v2"; + reg = <0x00 0xfdbef000 0x00 0x40 0x00 0xfdbef040 0x00 0x40>; + interrupts = <0x00 0x66 0x04 0x00 0x67 0x04>; + interrupt-names = "irq_rkvenc1_mmu0\0irq_rkvenc1_mmu1"; + clocks = <0x02 0x1ca 0x02 0x1c9>; + lock-names = "aclk\0iface"; + rockchip,disable-mmu-reset; + rockchip,enable-cmd-retry; + rockchip,shootdown-entire; + #iommu-cells = <0x00>; + power-domains = <0x06 0x11>; + status = "okay"; + phandle = <0xc6>; + }; + + venc-opp-table { + compatible = "operating-points-v2"; + nvmem-cells = <0xc7 0xc8>; + nvmem-cell-names = "leakage\0opp-info"; + rockchip,leakage-voltage-sel = <0x01 0x0f 0x00 0x10 0x19 0x01 0x1a 0xfe 0x02>; + rockchip,grf = <0xc9>; + volt-mem-read-margin = <0xd0bd8 0x01 0xbac48 0x02 0xa4cb8 0x03 0x78d98 0x04>; + phandle = <0xc4>; + + opp-800000000 { + opp-hz = <0x00 0x2faf0800>; + opp-microvolt = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>; + opp-microvolt-L0 = <0xc3500 0xc3500 0xcf850 0xc3500 0xc3500 0xcf850>; + opp-microvolt-L1 = <0xbd358 0xbd358 0xcf850 0xbd358 0xbd358 0xcf850>; + opp-microvolt-L2 = <0xb71b0 0xb71b0 0xcf850 0xb71b0 0xb71b0 0xcf850>; + }; + }; + + rkvdec-ccu@fdc30000 { + compatible = "rockchip,rkv-decoder-v2-ccu"; + reg = <0x00 0xfdc30000 0x00 0x100>; + reg-names = "ccu"; + clocks = <0x02 0x18e>; + clock-names = "aclk_ccu"; + assigned-clocks = <0x02 0x18e>; + assigned-clock-rates = <0x23c34600>; + resets = <0x02 0x282>; + reset-names = "video_ccu"; + rockchip,skip-pmu-idle-request; + rockchip,ccu-mode = <0x01>; + power-domains = <0x06 0x0e>; + status = "okay"; + phandle = <0xcb>; + }; + + rkvdec-core@fdc38000 { + compatible = "rockchip,rkv-decoder-v2"; + reg = <0x00 0xfdc38100 0x00 0x400 0x00 0xfdc38000 0x00 0x100>; + reg-names = "regs\0link"; + interrupts = <0x00 0x5f 0x04>; + interrupt-names = "irq_rkvdec0"; + clocks = <0x02 0x190 0x02 0x18f 0x02 0x193 0x02 0x191 0x02 0x192>; + clock-names = "aclk_vcodec\0hclk_vcodec\0clk_core\0clk_cabac\0clk_hevc_cabac"; + rockchip,normal-rates = <0x2faf0800 0x00 0x23c34600 0x23c34600 0x3b9aca00>; + assigned-clocks = <0x02 0x190 0x02 0x193 0x02 0x191 0x02 0x192>; + assigned-clock-rates = <0x2faf0800 0x23c34600 0x23c34600 0x3b9aca00>; + resets = <0x02 0x284 0x02 0x283 0x02 0x289 0x02 0x287 0x02 0x288>; + reset-names = "video_a\0video_h\0video_core\0video_cabac\0video_hevc_cabac"; + rockchip,skip-pmu-idle-request; + iommus = <0xca>; + rockchip,srv = <0xb8>; + rockchip,ccu = <0xcb>; + rockchip,core-mask = <0x10001>; + rockchip,task-capacity = <0x10>; + rockchip,taskqueue-node = <0x09>; + rockchip,sram = <0xcc>; + rockchip,rcb-iova = <0xfff00000 0x100000>; + rockchip,rcb-info = <0x88 0x6000 0x89 0xc000 0x8d 0x16000 0x8c 0xc000 0x8b 0x2c000 0x85 0xc000 0x86 0x2000 0x87 0x1100 0x8a 0x3300 0x8e 0x47300>; + rockchip,rcb-min-width = <0x200>; + power-domains = <0x06 0x0e>; + status = "okay"; + phandle = <0x29a>; + }; + + iommu@fdc38700 { + compatible = "rockchip,iommu-v2"; + reg = <0x00 0xfdc38700 0x00 0x40 0x00 0xfdc38740 0x00 0x40>; + interrupts = <0x00 0x60 0x04>; + interrupt-names = "irq_rkvdec0_mmu"; + clocks = <0x02 0x190 0x02 0x18f>; + clock-names = "aclk\0iface"; + rockchip,disable-mmu-reset; + rockchip,enable-cmd-retry; + rockchip,shootdown-entire; + rockchip,master-handle-irq; + #iommu-cells = <0x00>; + power-domains = <0x06 0x0e>; + status = "okay"; + phandle = <0xca>; + }; + + rkvdec-core@fdc48000 { + compatible = "rockchip,rkv-decoder-v2"; + reg = <0x00 0xfdc48100 0x00 0x400 0x00 0xfdc48000 0x00 0x100>; + reg-names = "regs\0link"; + interrupts = <0x00 0x61 0x04>; + interrupt-names = "irq_rkvdec1"; + clocks = <0x02 0x195 0x02 0x194 0x02 0x198 0x02 0x196 0x02 0x197>; + clock-names = "aclk_vcodec\0hclk_vcodec\0clk_core\0clk_cabac\0clk_hevc_cabac"; + rockchip,normal-rates = <0x2faf0800 0x00 0x23c34600 0x23c34600 0x3b9aca00>; + assigned-clocks = <0x02 0x195 0x02 0x198 0x02 0x196 0x02 0x197>; + assigned-clock-rates = <0x2faf0800 0x23c34600 0x23c34600 0x3b9aca00>; + resets = <0x02 0x293 0x02 0x292 0x02 0x298 0x02 0x296 0x02 0x297>; + reset-names = "video_a\0video_h\0video_core\0video_cabac\0video_hevc_cabac"; + rockchip,skip-pmu-idle-request; + iommus = <0xcd>; + rockchip,srv = <0xb8>; + rockchip,ccu = <0xcb>; + rockchip,core-mask = <0x20002>; + rockchip,task-capacity = <0x10>; + rockchip,taskqueue-node = <0x09>; + rockchip,sram = <0xce>; + rockchip,rcb-iova = <0xffe00000 0x100000>; + rockchip,rcb-info = <0x88 0x6000 0x89 0xc000 0x8d 0x16000 0x8c 0xc000 0x8b 0x2c000 0x85 0xc000 0x86 0x2000 0x87 0x1100 0x8a 0x3300 0x8e 0x47300>; + rockchip,rcb-min-width = <0x200>; + power-domains = <0x06 0x0f>; + status = "okay"; + phandle = <0x29b>; + }; + + iommu@fdc48700 { + compatible = "rockchip,iommu-v2"; + reg = <0x00 0xfdc48700 0x00 0x40 0x00 0xfdc48740 0x00 0x40>; + interrupts = <0x00 0x62 0x04>; + interrupt-names = "irq_rkvdec1_mmu"; + clocks = <0x02 0x195 0x02 0x194>; + clock-names = "aclk\0iface"; + rockchip,disable-mmu-reset; + rockchip,enable-cmd-retry; + rockchip,shootdown-entire; + rockchip,master-handle-irq; + #iommu-cells = <0x00>; + power-domains = <0x06 0x0f>; + status = "okay"; + phandle = <0xcd>; + }; + + av1d@fdc70000 { + compatible = "rockchip,av1-decoder"; + reg = <0x00 0xfdc70000 0x00 0x800 0x00 0xfdc80000 0x00 0x400 0x00 0xfdc90000 0x00 0x400>; + reg-names = "vcd\0cache\0afbc"; + interrupts = <0x00 0x6c 0x04 0x00 0x6b 0x04 0x00 0x6a 0x04>; + interrupt-names = "irq_av1d\0irq_cache\0irq_afbc"; + clocks = <0x02 0x49 0x02 0x4b>; + clock-names = "aclk_vcodec\0hclk_vcodec"; + rockchip,normal-rates = <0x17d78400 0x17d78400>; + assigned-clocks = <0x02 0x49 0x02 0x4b>; + assigned-clock-rates = <0x17d78400 0x17d78400>; + resets = <0x02 0x442 0x02 0x445>; + reset-names = "video_a\0video_h"; + iommus = <0xcf>; + rockchip,srv = <0xb8>; + rockchip,taskqueue-node = <0x0b>; + power-domains = <0x06 0x17>; + status = "okay"; + phandle = <0x29c>; + }; + + iommu@fdca0000 { + compatible = "rockchip,iommu-av1d"; + reg = <0x00 0xfdca0000 0x00 0x600>; + interrupts = <0x00 0x6d 0x04>; + interrupt-names = "irq_av1d_mmu"; + clocks = <0x02 0x49 0x02 0x4b>; + clock-names = "aclk\0iface"; + #iommu-cells = <0x00>; + power-domains = <0x06 0x17>; + status = "okay"; + phandle = <0xcf>; + }; + + rkisp-unite@fdcb0000 { + compatible = "rockchip,rk3588-rkisp-unite"; + reg = <0x00 0xfdcb0000 0x00 0x10000 0x00 0xfdcc0000 0x00 0x10000>; + interrupts = <0x00 0x87 0x04 0x00 0x89 0x04 0x00 0x8a 0x04>; + interrupt-names = "isp_irq\0mi_irq\0mipi_irq"; + clocks = <0x02 0x1de 0x02 0x1df 0x02 0x1db 0x02 0x1dc 0x02 0x1dd 0x02 0x120 0x02 0x121 0x02 0x11d 0x02 0x11e 0x02 0x11f>; + clock-names = "aclk_isp0\0hclk_isp0\0clk_isp_core0\0clk_isp_core_marvin0\0clk_isp_core_vicap0\0aclk_isp1\0hclk_isp1\0clk_isp_core1\0clk_isp_core_marvin1\0clk_isp_core_vicap1"; + power-domains = <0x06 0x1c>; + iommus = <0xd0>; + status = "disabled"; + phandle = <0x29d>; + }; + + rkisp@fdcb0000 { + compatible = "rockchip,rk3588-rkisp"; + reg = <0x00 0xfdcb0000 0x00 0x7f00>; + interrupts = <0x00 0x83 0x04 0x00 0x85 0x04 0x00 0x86 0x04>; + interrupt-names = "isp_irq\0mi_irq\0mipi_irq"; + clocks = <0x02 0x1de 0x02 0x1df 0x02 0x1db 0x02 0x1dc 0x02 0x1dd>; + clock-names = "aclk_isp\0hclk_isp\0clk_isp_core\0clk_isp_core_marvin\0clk_isp_core_vicap"; + power-domains = <0x06 0x1b>; + iommus = <0xd1>; + status = "okay"; + phandle = <0x5a>; + }; + + rkisp-unite-mmu@fdcb7f00 { + compatible = "rockchip,iommu-v2"; + reg = <0x00 0xfdcb7f00 0x00 0x100 0x00 0xfdcc7f00 0x00 0x100>; + interrupts = <0x00 0x84 0x04 0x00 0x88 0x04>; + interrupt-names = "isp0_mmu\0isp1_mmu"; + clocks = <0x02 0x1de 0x02 0x1df 0x02 0x120 0x02 0x121>; + clock-names = "aclk0\0iface0\0aclk1\0iface1"; + power-domains = <0x06 0x1c>; + #iommu-cells = <0x00>; + rockchip,disable-mmu-reset; + status = "disabled"; + phandle = <0xd0>; + }; + + iommu@fdcb7f00 { + compatible = "rockchip,iommu-v2"; + reg = <0x00 0xfdcb7f00 0x00 0x100>; + interrupts = <0x00 0x84 0x04>; + interrupt-names = "isp0_mmu"; + clocks = <0x02 0x1de 0x02 0x1df>; + clock-names = "aclk\0iface"; + power-domains = <0x06 0x1b>; + #iommu-cells = <0x00>; + rockchip,disable-mmu-reset; + status = "okay"; + phandle = <0xd1>; + }; + + rkisp@fdcc0000 { + compatible = "rockchip,rk3588-rkisp"; + reg = <0x00 0xfdcc0000 0x00 0x7f00>; + interrupts = <0x00 0x87 0x04 0x00 0x89 0x04 0x00 0x8a 0x04>; + interrupt-names = "isp_irq\0mi_irq\0mipi_irq"; + clocks = <0x02 0x120 0x02 0x121 0x02 0x11d 0x02 0x11e 0x02 0x11f>; + clock-names = "aclk_isp\0hclk_isp\0clk_isp_core\0clk_isp_core_marvin\0clk_isp_core_vicap"; + power-domains = <0x06 0x1c>; + iommus = <0xd2>; + status = "disabled"; + phandle = <0x5c>; + }; + + iommu@fdcc7f00 { + compatible = "rockchip,iommu-v2"; + reg = <0x00 0xfdcc7f00 0x00 0x100>; + interrupts = <0x00 0x88 0x04>; + interrupt-names = "isp1_mmu"; + clocks = <0x02 0x120 0x02 0x121>; + clock-names = "aclk\0iface"; + power-domains = <0x06 0x1c>; + #iommu-cells = <0x00>; + rockchip,disable-mmu-reset; + status = "disabled"; + phandle = <0xd2>; + }; + + rkispp@fdcd0000 { + compatible = "rockchip,rk3588-rkispp"; + reg = <0x00 0xfdcd0000 0x00 0xf00>; + interrupts = <0x00 0x8b 0x04>; + interrupt-names = "fec_irq"; + clocks = <0x02 0x1d5 0x02 0x1d6 0x02 0x1d7>; + clock-names = "aclk_ispp\0hclk_ispp\0clk_ispp"; + assigned-clocks = <0x02 0x1d6>; + assigned-clock-rates = <0x5f5e100>; + power-domains = <0x06 0x1d>; + iommus = <0xd3>; + status = "disabled"; + phandle = <0x5d>; + }; + + iommu@fdcd0f00 { + compatible = "rockchip,iommu-v2"; + reg = <0x00 0xfdcd0f00 0x00 0x100>; + interrupts = <0x00 0x8c 0x04>; + interrupt-names = "fec0_mmu"; + clocks = <0x02 0x1d5 0x02 0x1d6 0x02 0x1d7>; + clock-names = "aclk\0iface\0pclk"; + power-domains = <0x06 0x1d>; + #iommu-cells = <0x00>; + rockchip,disable-mmu-reset; + status = "disabled"; + phandle = <0xd3>; + }; + + rkispp@fdcd8000 { + compatible = "rockchip,rk3588-rkispp"; + reg = <0x00 0xfdcd8000 0x00 0xf00>; + interrupts = <0x00 0x8d 0x04>; + interrupt-names = "fec_irq"; + clocks = <0x02 0x1d8 0x02 0x1d9 0x02 0x1da>; + clock-names = "aclk_ispp\0hclk_ispp\0clk_ispp"; + assigned-clocks = <0x02 0x1d9>; + assigned-clock-rates = <0x5f5e100>; + power-domains = <0x06 0x1d>; + iommus = <0xd4>; + status = "disabled"; + phandle = <0x5e>; + }; + + iommu@fdcd8f00 { + compatible = "rockchip,iommu-v2"; + reg = <0x00 0xfdcd8f00 0x00 0x100>; + interrupts = <0x00 0x8e 0x04>; + interrupt-names = "fec1_mmu"; + clocks = <0x02 0x1d8 0x02 0x1d9 0x02 0x1da>; + clock-names = "aclk\0iface\0pclk"; + power-domains = <0x06 0x1d>; + #iommu-cells = <0x00>; + rockchip,disable-mmu-reset; + status = "disabled"; + phandle = <0xd4>; + }; + + rkcif@fdce0000 { + compatible = "rockchip,rk3588-cif"; + reg = <0x00 0xfdce0000 0x00 0x800>; + reg-names = "cif_regs"; + interrupts = <0x00 0x9b 0x04>; + interrupt-names = "cif-intr"; + clocks = <0x02 0x1e4 0x02 0x1e5 0x02 0x1e3 0x02 0x1cd 0x02 0x1ce>; + clock-names = "aclk_cif\0hclk_cif\0dclk_cif\0iclk_host0\0iclk_host1"; + resets = <0x02 0x317 0x02 0x318 0x02 0x316 0x02 0x334 0x02 0x335 0x02 0x336 0x02 0x337 0x02 0x338 0x02 0x339>; + reset-names = "rst_cif_a\0rst_cif_h\0rst_cif_d\0rst_cif_host0\0rst_cif_host1\0rst_cif_host2\0rst_cif_host3\0rst_cif_host4\0rst_cif_host5"; + assigned-clocks = <0x02 0x1e3>; + assigned-clock-rates = <0x23c34600>; + power-domains = <0x06 0x1b>; + rockchip,grf = <0xc9>; + iommus = <0xd5>; + nvmem-cells = <0x22 0xd6 0xd7>; + nvmem-cell-names = "specification\0package_low\0package_high"; + status = "okay"; + phandle = <0x50>; + }; + + iommu@fdce0800 { + compatible = "rockchip,iommu-v2"; + reg = <0x00 0xfdce0800 0x00 0x100 0x00 0xfdce0900 0x00 0x100>; + interrupts = <0x00 0x71 0x04>; + interrupt-names = "cif_mmu"; + clocks = <0x02 0x1e4 0x02 0x1e5>; + clock-names = "aclk\0iface"; + power-domains = <0x06 0x1b>; + rockchip,disable-mmu-reset; + #iommu-cells = <0x00>; + status = "okay"; + phandle = <0xd5>; + }; + + mipi0-csi2-hw@fdd10000 { + compatible = "rockchip,rk3588-mipi-csi2-hw"; + reg = <0x00 0xfdd10000 0x00 0x10000>; + reg-names = "csihost_regs"; + interrupts = <0x00 0x8f 0x04 0x00 0x90 0x04>; + interrupt-names = "csi-intr1\0csi-intr2"; + clocks = <0x02 0x1cf>; + clock-names = "pclk_csi2host"; + resets = <0x02 0x324>; + reset-names = "srst_csihost_p"; + status = "okay"; + phandle = <0x48>; + }; + + mipi1-csi2-hw@fdd20000 { + compatible = "rockchip,rk3588-mipi-csi2-hw"; + reg = <0x00 0xfdd20000 0x00 0x10000>; + reg-names = "csihost_regs"; + interrupts = <0x00 0x91 0x04 0x00 0x92 0x04>; + interrupt-names = "csi-intr1\0csi-intr2"; + clocks = <0x02 0x1d0>; + clock-names = "pclk_csi2host"; + resets = <0x02 0x325>; + reset-names = "srst_csihost_p"; + status = "okay"; + phandle = <0x49>; + }; + + mipi2-csi2-hw@fdd30000 { + compatible = "rockchip,rk3588-mipi-csi2-hw"; + reg = <0x00 0xfdd30000 0x00 0x10000>; + reg-names = "csihost_regs"; + interrupts = <0x00 0x93 0x04 0x00 0x94 0x04>; + interrupt-names = "csi-intr1\0csi-intr2"; + clocks = <0x02 0x1d1>; + clock-names = "pclk_csi2host"; + resets = <0x02 0x326>; + reset-names = "srst_csihost_p"; + status = "okay"; + phandle = <0x4a>; + }; + + mipi3-csi2-hw@fdd40000 { + compatible = "rockchip,rk3588-mipi-csi2-hw"; + reg = <0x00 0xfdd40000 0x00 0x10000>; + reg-names = "csihost_regs"; + interrupts = <0x00 0x95 0x04 0x00 0x96 0x04>; + interrupt-names = "csi-intr1\0csi-intr2"; + clocks = <0x02 0x1d2>; + clock-names = "pclk_csi2host"; + resets = <0x02 0x327>; + reset-names = "srst_csihost_p"; + status = "okay"; + phandle = <0x4b>; + }; + + mipi4-csi2-hw@fdd50000 { + compatible = "rockchip,rk3588-mipi-csi2-hw"; + reg = <0x00 0xfdd50000 0x00 0x10000>; + reg-names = "csihost_regs"; + interrupts = <0x00 0x97 0x04 0x00 0x98 0x04>; + interrupt-names = "csi-intr1\0csi-intr2"; + clocks = <0x02 0x1d3>; + clock-names = "pclk_csi2host"; + resets = <0x02 0x328>; + reset-names = "srst_csihost_p"; + status = "okay"; + phandle = <0x4c>; + }; + + mipi5-csi2-hw@fdd60000 { + compatible = "rockchip,rk3588-mipi-csi2-hw"; + reg = <0x00 0xfdd60000 0x00 0x10000>; + reg-names = "csihost_regs"; + interrupts = <0x00 0x99 0x04 0x00 0x9a 0x04>; + interrupt-names = "csi-intr1\0csi-intr2"; + clocks = <0x02 0x1d4>; + clock-names = "pclk_csi2host"; + resets = <0x02 0x329>; + reset-names = "srst_csihost_p"; + status = "okay"; + phandle = <0x4d>; + }; + + vop@fdd90000 { + compatible = "rockchip,rk3588-vop"; + reg = <0x00 0xfdd90000 0x00 0x4200 0x00 0xfdd95000 0x00 0x1000>; + reg-names = "regs\0gamma_lut"; + interrupts = <0x00 0x9c 0x04>; + clocks = <0x02 0x270 0x02 0x26f 0x02 0x274 0x02 0x275 0x02 0x276 0x02 0x277 0x02 0x26e 0x02 0x271 0x02 0x272 0x02 0x273 0x02 0x27d 0x02 0x27e 0x02 0x26b>; + clock-names = "aclk_vop\0hclk_vop\0dclk_vp0\0dclk_vp1\0dclk_vp2\0dclk_vp3\0pclk_vop\0dclk_src_vp0\0dclk_src_vp1\0dclk_src_vp2\0aclk_dovi\0aclk_vop_div2_src\0aclk_vop_root"; + assigned-clocks = <0x02 0x270>; + assigned-clock-rates = <0x2cb41780>; + resets = <0x02 0x349 0x02 0x348 0x02 0x34d 0x02 0x350 0x02 0x351 0x02 0x352>; + reset-names = "axi\0ahb\0dclk_vp0\0dclk_vp1\0dclk_vp2\0dclk_vp3"; + rockchip,aclk-normal-mode-rates = <0x1dcd6500>; + rockchip,aclk-advanced-mode-rates = <0x2cb41780>; + operating-points-v2 = <0xd8>; + iommus = <0xd9>; + power-domains = <0x06 0x18>; + rockchip,grf = <0xc9>; + rockchip,vop-grf = <0xda>; + rockchip,vo1-grf = <0xdb>; + rockchip,pmu = <0xdc>; + status = "okay"; + vop-supply = <0x44>; + phandle = <0x29e>; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + phandle = <0x35>; + + port@0 { + #address-cells = <0x01>; + #size-cells = <0x00>; + reg = <0x00>; + rockchip,plane-mask = <0x05>; + rockchip,primary-plane = <0x02>; + phandle = <0x29f>; + + endpoint@0 { + reg = <0x00>; + remote-endpoint = <0xdd>; + phandle = <0x104>; + }; + + endpoint@1 { + reg = <0x01>; + remote-endpoint = <0xde>; + phandle = <0x10e>; + }; + + endpoint@2 { + reg = <0x02>; + remote-endpoint = <0xdf>; + phandle = <0x3d>; + }; + + endpoint@3 { + reg = <0x03>; + remote-endpoint = <0xe0>; + phandle = <0x1bb>; + }; + + endpoint@4 { + reg = <0x04>; + remote-endpoint = <0xe1>; + phandle = <0x1c4>; + }; + + endpoint@5 { + reg = <0x05>; + remote-endpoint = <0xe2>; + phandle = <0x1c1>; + }; + }; + + port@1 { + #address-cells = <0x01>; + #size-cells = <0x00>; + reg = <0x01>; + rockchip,plane-mask = <0x0a>; + rockchip,primary-plane = <0x03>; + phandle = <0x2a0>; + + endpoint@0 { + reg = <0x00>; + remote-endpoint = <0xe3>; + phandle = <0x39>; + }; + + endpoint@1 { + reg = <0x01>; + remote-endpoint = <0xe4>; + phandle = <0x10f>; + }; + + endpoint@2 { + reg = <0x02>; + remote-endpoint = <0xe5>; + phandle = <0x10b>; + }; + + endpoint@3 { + reg = <0x03>; + remote-endpoint = <0xe6>; + phandle = <0x3f>; + }; + + endpoint@4 { + reg = <0x04>; + remote-endpoint = <0xe7>; + phandle = <0x1c5>; + }; + + endpoint@5 { + reg = <0x05>; + remote-endpoint = <0xe8>; + phandle = <0x40>; + }; + }; + + port@2 { + #address-cells = <0x01>; + #size-cells = <0x00>; + reg = <0x02>; + assigned-clocks = <0x02 0x273>; + assigned-clock-parents = <0x02 0x04>; + rockchip,plane-mask = <0x140>; + rockchip,primary-plane = <0x08>; + phandle = <0x2a1>; + + endpoint@0 { + reg = <0x00>; + remote-endpoint = <0xe9>; + phandle = <0x105>; + }; + + endpoint@1 { + reg = <0x01>; + remote-endpoint = <0xea>; + phandle = <0x3c>; + }; + + endpoint@2 { + reg = <0x02>; + remote-endpoint = <0xeb>; + phandle = <0x10c>; + }; + + endpoint@3 { + reg = <0x03>; + remote-endpoint = <0xec>; + phandle = <0xf6>; + }; + + endpoint@4 { + reg = <0x04>; + remote-endpoint = <0xed>; + phandle = <0xfe>; + }; + + endpoint@5 { + reg = <0x05>; + remote-endpoint = <0xee>; + phandle = <0x1bc>; + }; + + endpoint@6 { + reg = <0x06>; + remote-endpoint = <0xef>; + phandle = <0x1c6>; + }; + + endpoint@7 { + reg = <0x07>; + remote-endpoint = <0xf0>; + phandle = <0x1c2>; + }; + }; + + port@3 { + #address-cells = <0x01>; + #size-cells = <0x00>; + reg = <0x03>; + rockchip,plane-mask = <0x280>; + rockchip,primary-plane = <0x09>; + phandle = <0x2a2>; + + endpoint@0 { + reg = <0x00>; + remote-endpoint = <0xf1>; + phandle = <0x3a>; + }; + + endpoint@1 { + reg = <0x01>; + remote-endpoint = <0xf2>; + phandle = <0x3b>; + }; + + endpoint@2 { + reg = <0x02>; + remote-endpoint = <0xf3>; + phandle = <0x3e>; + }; + }; + }; + }; + + vop-opp-table { + compatible = "operating-points-v2"; + nvmem-cells = <0x45>; + nvmem-cell-names = "leakage"; + rockchip,init-freq = <0xb71b0>; + rockchip,leakage-voltage-sel = <0x01 0x1f 0x00 0x20 0x2c 0x01 0x2d 0x39 0x02 0x3a 0xfe 0x03>; + phandle = <0xd8>; + + opp-5000000000 { + opp-hz = <0x00 0x1dcd6500>; + opp-microvolt = <0xb1008 0xb1008 0xc3500>; + opp-microvolt-L1 = <0xaae60 0xaae60 0xc3500>; + opp-microvolt-L2 = <0xa7d8c 0xa7d8c 0xc3500>; + opp-microvolt-L3 = <0xa4cb8 0xa4cb8 0xc3500>; + }; + + opp-7500000000 { + opp-hz = <0x00 0x2cb41780>; + opp-microvolt = <0xb1008 0xb1008 0xc3500>; + opp-microvolt-L1 = <0xaae60 0xaae60 0xc3500>; + opp-microvolt-L2 = <0xa7d8c 0xa7d8c 0xc3500>; + opp-microvolt-L3 = <0xa4cb8 0xa4cb8 0xc3500>; + }; + + opp-8500000000 { + opp-hz = <0x00 0x32a9f880>; + opp-microvolt = "\0\f5\0\0\f5\0\0\f5"; + opp-microvolt-L1 = <0xbd358 0xbd358 0xc3500>; + opp-microvolt-L2 = <0xb71b0 0xb71b0 0xc3500>; + opp-microvolt-L3 = <0xb71b0 0xb71b0 0xc3500>; + }; + }; + + iommu@fdd97e00 { + compatible = "rockchip,iommu-v2"; + reg = <0x00 0xfdd97e00 0x00 0x100 0x00 0xfdd97f00 0x00 0x100>; + interrupts = <0x00 0x9c 0x04>; + interrupt-names = "vop_mmu"; + clocks = <0x02 0x270 0x02 0x26f>; + clock-names = "aclk\0iface"; + #iommu-cells = <0x00>; + rockchip,disable-device-link-resume; + rockchip,shootdown-entire; + status = "okay"; + phandle = <0xd9>; + }; + + spdif-tx@fddb0000 { + compatible = "rockchip,rk3588-spdif\0rockchip,rk3568-spdif"; + reg = <0x00 0xfddb0000 0x00 0x1000>; + interrupts = <0x00 0xc3 0x04>; + dmas = <0xf4 0x06>; + dma-names = "tx"; + clock-names = "mclk\0hclk"; + clocks = <0x02 0x209 0x02 0x204>; + assigned-clocks = <0x02 0x205>; + assigned-clock-parents = <0x02 0x05>; + power-domains = <0x06 0x19>; + #sound-dai-cells = <0x00>; + status = "disabled"; + phandle = <0x1e5>; + }; + + i2s@fddc0000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x00 0xfddc0000 0x00 0x1000>; + interrupts = <0x00 0xb8 0x04>; + clocks = <0x02 0x1fb 0x02 0x1fb 0x02 0x1f0>; + clock-names = "mclk_tx\0mclk_rx\0hclk"; + assigned-clocks = <0x02 0x1f9>; + assigned-clock-parents = <0x02 0x05>; + dmas = <0xf5 0x00>; + dma-names = "tx"; + power-domains = <0x06 0x19>; + resets = <0x02 0x38d>; + reset-names = "tx-m"; + rockchip,playback-only; + #sound-dai-cells = <0x00>; + status = "disabled"; + phandle = <0x2a3>; + }; + + spdif-tx@fdde0000 { + compatible = "rockchip,rk3588-spdif\0rockchip,rk3568-spdif"; + reg = <0x00 0xfdde0000 0x00 0x1000>; + interrupts = <0x00 0xc4 0x04>; + dmas = <0xf4 0x07>; + dma-names = "tx"; + clock-names = "mclk\0hclk"; + clocks = <0x02 0x257 0x02 0x253>; + assigned-clocks = <0x02 0x254>; + assigned-clock-parents = <0x02 0x05>; + power-domains = <0x06 0x1a>; + #sound-dai-cells = <0x00>; + status = "disabled"; + phandle = <0x2a4>; + }; + + i2s@fddf0000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x00 0xfddf0000 0x00 0x1000>; + interrupts = <0x00 0xb9 0x04>; + clocks = <0x02 0x246 0x02 0x246 0x02 0x248>; + clock-names = "mclk_tx\0mclk_rx\0hclk"; + assigned-clocks = <0x02 0x243>; + assigned-clock-parents = <0x02 0x07>; + dmas = <0xf5 0x02>; + dma-names = "tx"; + power-domains = <0x06 0x1a>; + resets = <0x02 0x3e8>; + reset-names = "tx-m"; + rockchip,always-on; + rockchip,hdmi-path; + rockchip,playback-only; + #sound-dai-cells = <0x00>; + status = "okay"; + phandle = <0x1df>; + }; + + i2s@fddfc000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x00 0xfddfc000 0x00 0x1000>; + interrupts = <0x00 0xbd 0x04>; + clocks = <0x02 0x242 0x02 0x242 0x02 0x23e>; + clock-names = "mclk_tx\0mclk_rx\0hclk"; + assigned-clocks = <0x02 0x23f>; + assigned-clock-parents = <0x02 0x05>; + dmas = <0xf5 0x17>; + dma-names = "rx"; + power-domains = <0x06 0x1a>; + resets = <0x02 0x413>; + reset-names = "rx-m"; + rockchip,capture-only; + #sound-dai-cells = <0x00>; + status = "disabled"; + phandle = <0x2a5>; + }; + + spdif-rx@fde08000 { + compatible = "rockchip,rk3588-spdifrx\0rockchip,rk3308-spdifrx"; + reg = <0x00 0xfde08000 0x00 0x1000>; + interrupts = <0x00 0xc7 0x04>; + clocks = <0x02 0x25e 0x02 0x25d>; + clock-names = "mclk\0hclk"; + assigned-clocks = <0x02 0x25e>; + assigned-clock-parents = <0x02 0x05>; + dmas = <0x7a 0x15>; + dma-names = "rx"; + power-domains = <0x06 0x1a>; + resets = <0x02 0x3fd>; + reset-names = "spdifrx-m"; + #sound-dai-cells = <0x00>; + status = "disabled"; + phandle = <0x2a6>; + }; + + dsi@fde20000 { + compatible = "rockchip,rk3588-mipi-dsi2"; + reg = <0x00 0xfde20000 0x00 0x10000>; + interrupts = <0x00 0xa7 0x04>; + clocks = <0x02 0x278 0x02 0x27a>; + clock-names = "pclk\0sys_clk"; + resets = <0x02 0x354>; + reset-names = "apb"; + power-domains = <0x06 0x18>; + phys = <0x31>; + phy-names = "dcphy"; + rockchip,grf = <0xda>; + #address-cells = <0x01>; + #size-cells = <0x00>; + status = "okay"; + phandle = <0x2a7>; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + #address-cells = <0x01>; + #size-cells = <0x00>; + phandle = <0x2a8>; + + endpoint@0 { + reg = <0x00>; + remote-endpoint = <0xf6>; + status = "disabled"; + phandle = <0xec>; + }; + + endpoint@1 { + reg = <0x01>; + remote-endpoint = <0x3a>; + status = "okay"; + phandle = <0xf1>; + }; + }; + + port@1 { + reg = <0x01>; + + endpoint { + remote-endpoint = <0xf7>; + phandle = <0xfd>; + }; + }; + }; + + panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0x00>; + backlight = <0xf8>; + reset-delay-ms = <0x0a>; + enable-delay-ms = <0x0a>; + prepare-delay-ms = <0x0a>; + init-delay-ms = <0x0a>; + unprepare-delay-ms = <0x0a>; + disable-delay-ms = <0x3c>; + width-mm = <0x44>; + height-mm = <0x79>; + dsi,flags = <0xa03>; + dsi,format = <0x00>; + dsi,lanes = <0x04>; + panel-init-sequence = [23 00 02 fe 21 23 00 02 04 00 23 00 02 00 64 23 00 02 2a 00 23 00 02 26 64 23 00 02 54 00 23 00 02 50 64 23 00 02 7b 00 23 00 02 77 64 23 00 02 a2 00 23 00 02 9d 64 23 00 02 c9 00 23 00 02 c5 64 23 00 02 01 71 23 00 02 27 71 23 00 02 51 71 23 00 02 78 71 23 00 02 9e 71 23 00 02 c6 71 23 00 02 02 89 23 00 02 28 89 23 00 02 52 89 23 00 02 79 89 23 00 02 9f 89 23 00 02 c7 89 23 00 02 03 9e 23 00 02 29 9e 23 00 02 53 9e 23 00 02 7a 9e 23 00 02 a0 9e 23 00 02 c8 9e 23 00 02 09 00 23 00 02 05 b0 23 00 02 31 00 23 00 02 2b b0 23 00 02 5a 00 23 00 02 55 b0 23 00 02 80 00 23 00 02 7c b0 23 00 02 a7 00 23 00 02 a3 b0 23 00 02 ce 00 23 00 02 ca b0 23 00 02 06 c0 23 00 02 2d c0 23 00 02 56 c0 23 00 02 7d c0 23 00 02 a4 c0 23 00 02 cb c0 23 00 02 07 cf 23 00 02 2f cf 23 00 02 58 cf 23 00 02 7e cf 23 00 02 a5 cf 23 00 02 cc cf 23 00 02 08 dd 23 00 02 30 dd 23 00 02 59 dd 23 00 02 7f dd 23 00 02 a6 dd 23 00 02 cd dd 23 00 02 0e 15 23 00 02 0a e9 23 00 02 36 15 23 00 02 32 e9 23 00 02 5f 15 23 00 02 5b e9 23 00 02 85 15 23 00 02 81 e9 23 00 02 ad 15 23 00 02 a9 e9 23 00 02 d3 15 23 00 02 cf e9 23 00 02 0b 14 23 00 02 33 14 23 00 02 5c 14 23 00 02 82 14 23 00 02 aa 14 23 00 02 d0 14 23 00 02 0c 36 23 00 02 34 36 23 00 02 5d 36 23 00 02 83 36 23 00 02 ab 36 23 00 02 d1 36 23 00 02 0d 6b 23 00 02 35 6b 23 00 02 5e 6b 23 00 02 84 6b 23 00 02 ac 6b 23 00 02 d2 6b 23 00 02 13 5a 23 00 02 0f 94 23 00 02 3b 5a 23 00 02 37 94 23 00 02 64 5a 23 00 02 60 94 23 00 02 8a 5a 23 00 02 86 94 23 00 02 b2 5a 23 00 02 ae 94 23 00 02 d8 5a 23 00 02 d4 94 23 00 02 10 d1 23 00 02 38 d1 23 00 02 61 d1 23 00 02 87 d1 23 00 02 af d1 23 00 02 d5 d1 23 00 02 11 04 23 00 02 39 04 23 00 02 62 04 23 00 02 88 04 23 00 02 b0 04 23 00 02 d6 04 23 00 02 12 05 23 00 02 3a 05 23 00 02 63 05 23 00 02 89 05 23 00 02 b1 05 23 00 02 d7 05 23 00 02 18 aa 23 00 02 14 36 23 00 02 42 aa 23 00 02 3d 36 23 00 02 69 aa 23 00 02 65 36 23 00 02 8f aa 23 00 02 8b 36 23 00 02 b7 aa 23 00 02 b3 36 23 00 02 dd aa 23 00 02 d9 36 23 00 02 15 74 23 00 02 3f 74 23 00 02 66 74 23 00 02 8c 74 23 00 02 b4 74 23 00 02 da 74 23 00 02 16 9f 23 00 02 40 9f 23 00 02 67 9f 23 00 02 8d 9f 23 00 02 b5 9f 23 00 02 db 9f 23 00 02 17 dc 23 00 02 41 dc 23 00 02 68 dc 23 00 02 8e dc 23 00 02 b6 dc 23 00 02 dc dc 23 00 02 1d ff 23 00 02 19 03 23 00 02 47 ff 23 00 02 43 03 23 00 02 6e ff 23 00 02 6a 03 23 00 02 94 ff 23 00 02 90 03 23 00 02 bc ff 23 00 02 b8 03 23 00 02 e2 ff 23 00 02 de 03 23 00 02 1a 35 23 00 02 44 35 23 00 02 6b 35 23 00 02 91 35 23 00 02 b9 35 23 00 02 df 35 23 00 02 1b 45 23 00 02 45 45 23 00 02 6c 45 23 00 02 92 45 23 00 02 ba 45 23 00 02 e0 45 23 00 02 1c 55 23 00 02 46 55 23 00 02 6d 55 23 00 02 93 55 23 00 02 bb 55 23 00 02 e1 55 23 00 02 22 ff 23 00 02 1e 68 23 00 02 4c ff 23 00 02 48 68 23 00 02 73 ff 23 00 02 6f 68 23 00 02 99 ff 23 00 02 95 68 23 00 02 c1 ff 23 00 02 bd 68 23 00 02 e7 ff 23 00 02 e3 68 23 00 02 1f 7e 23 00 02 49 7e 23 00 02 70 7e 23 00 02 96 7e 23 00 02 be 7e 23 00 02 e4 7e 23 00 02 20 97 23 00 02 4a 97 23 00 02 71 97 23 00 02 97 97 23 00 02 bf 97 23 00 02 e5 97 23 00 02 21 b5 23 00 02 4b b5 23 00 02 72 b5 23 00 02 98 b5 23 00 02 c0 b5 23 00 02 e6 b5 23 00 02 25 f0 23 00 02 23 e8 23 00 02 4f f0 23 00 02 4d e8 23 00 02 76 f0 23 00 02 74 e8 23 00 02 9c f0 23 00 02 9a e8 23 00 02 c4 f0 23 00 02 c2 e8 23 00 02 ea f0 23 00 02 e8 e8 23 00 02 24 ff 23 00 02 4e ff 23 00 02 75 ff 23 00 02 9b ff 23 00 02 c3 ff 23 00 02 e9 ff 23 00 02 fe 3d 23 00 02 00 04 23 00 02 fe 23 23 00 02 08 82 23 00 02 0a 00 23 00 02 0b 00 23 00 02 0c 01 23 00 02 16 00 23 00 02 18 02 23 00 02 1b 04 23 00 02 19 04 23 00 02 1c 81 23 00 02 1f 00 23 00 02 20 03 23 00 02 23 04 23 00 02 21 01 23 00 02 54 63 23 00 02 55 54 23 00 02 6e 45 23 00 02 6d 36 23 00 02 fe 3d 23 00 02 55 78 23 00 02 fe 20 23 00 02 26 30 23 00 02 fe 3d 23 00 02 20 71 23 00 02 50 8f 23 00 02 51 8f 23 00 02 fe 00 23 00 02 35 00 05 78 01 11 05 00 01 29]; + panel-exit-sequence = <0x5000128 0x5000110>; + power-supply = <0xf9>; + reset-gpios = <0xfa 0x1b 0x01>; + pinctrl-names = "default"; + pinctrl-0 = <0xfb>; + phandle = <0x2a9>; + + display-timings { + native-mode = <0xfc>; + phandle = <0x2aa>; + + timing0 { + clock-frequency = <0x7de2900>; + hactive = <0x438>; + vactive = <0x780>; + hfront-porch = <0x0f>; + hsync-len = <0x04>; + hback-porch = <0x1e>; + vfront-porch = <0x0f>; + vsync-len = <0x02>; + vback-porch = <0x0f>; + hsync-active = <0x00>; + vsync-active = <0x00>; + de-active = <0x00>; + pixelclk-active = <0x00>; + phandle = <0xfc>; + }; + }; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint { + remote-endpoint = <0xfd>; + phandle = <0xf7>; + }; + }; + }; + }; + }; + + dsi@fde30000 { + compatible = "rockchip,rk3588-mipi-dsi2"; + reg = <0x00 0xfde30000 0x00 0x10000>; + interrupts = <0x00 0xa8 0x04>; + clocks = <0x02 0x279 0x02 0x27b>; + clock-names = "pclk\0sys_clk"; + resets = <0x02 0x355>; + reset-names = "apb"; + power-domains = <0x06 0x18>; + phys = <0x32>; + phy-names = "dcphy"; + rockchip,grf = <0xda>; + #address-cells = <0x01>; + #size-cells = <0x00>; + status = "disabled"; + phandle = <0x2ab>; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + #address-cells = <0x01>; + #size-cells = <0x00>; + phandle = <0x2ac>; + + endpoint@0 { + reg = <0x00>; + remote-endpoint = <0xfe>; + status = "disabled"; + phandle = <0xed>; + }; + + endpoint@1 { + reg = <0x01>; + remote-endpoint = <0x3b>; + status = "disabled"; + phandle = <0xf2>; + }; + }; + + port@1 { + reg = <0x01>; + + endpoint { + remote-endpoint = <0xff>; + phandle = <0x101>; + }; + }; + }; + + panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0x00>; + backlight = <0xf8>; + reset-delay-ms = <0x0a>; + enable-delay-ms = <0x0a>; + prepare-delay-ms = <0x0a>; + init-delay-ms = <0x0a>; + unprepare-delay-ms = <0x0a>; + disable-delay-ms = <0x0a>; + width-mm = <0x44>; + height-mm = <0x79>; + dsi,flags = <0xa03>; + dsi,format = <0x00>; + dsi,lanes = <0x04>; + panel-init-sequence = [23 00 02 fe 21 23 00 02 04 00 23 00 02 00 64 23 00 02 2a 00 23 00 02 26 64 23 00 02 54 00 23 00 02 50 64 23 00 02 7b 00 23 00 02 77 64 23 00 02 a2 00 23 00 02 9d 64 23 00 02 c9 00 23 00 02 c5 64 23 00 02 01 71 23 00 02 27 71 23 00 02 51 71 23 00 02 78 71 23 00 02 9e 71 23 00 02 c6 71 23 00 02 02 89 23 00 02 28 89 23 00 02 52 89 23 00 02 79 89 23 00 02 9f 89 23 00 02 c7 89 23 00 02 03 9e 23 00 02 29 9e 23 00 02 53 9e 23 00 02 7a 9e 23 00 02 a0 9e 23 00 02 c8 9e 23 00 02 09 00 23 00 02 05 b0 23 00 02 31 00 23 00 02 2b b0 23 00 02 5a 00 23 00 02 55 b0 23 00 02 80 00 23 00 02 7c b0 23 00 02 a7 00 23 00 02 a3 b0 23 00 02 ce 00 23 00 02 ca b0 23 00 02 06 c0 23 00 02 2d c0 23 00 02 56 c0 23 00 02 7d c0 23 00 02 a4 c0 23 00 02 cb c0 23 00 02 07 cf 23 00 02 2f cf 23 00 02 58 cf 23 00 02 7e cf 23 00 02 a5 cf 23 00 02 cc cf 23 00 02 08 dd 23 00 02 30 dd 23 00 02 59 dd 23 00 02 7f dd 23 00 02 a6 dd 23 00 02 cd dd 23 00 02 0e 15 23 00 02 0a e9 23 00 02 36 15 23 00 02 32 e9 23 00 02 5f 15 23 00 02 5b e9 23 00 02 85 15 23 00 02 81 e9 23 00 02 ad 15 23 00 02 a9 e9 23 00 02 d3 15 23 00 02 cf e9 23 00 02 0b 14 23 00 02 33 14 23 00 02 5c 14 23 00 02 82 14 23 00 02 aa 14 23 00 02 d0 14 23 00 02 0c 36 23 00 02 34 36 23 00 02 5d 36 23 00 02 83 36 23 00 02 ab 36 23 00 02 d1 36 23 00 02 0d 6b 23 00 02 35 6b 23 00 02 5e 6b 23 00 02 84 6b 23 00 02 ac 6b 23 00 02 d2 6b 23 00 02 13 5a 23 00 02 0f 94 23 00 02 3b 5a 23 00 02 37 94 23 00 02 64 5a 23 00 02 60 94 23 00 02 8a 5a 23 00 02 86 94 23 00 02 b2 5a 23 00 02 ae 94 23 00 02 d8 5a 23 00 02 d4 94 23 00 02 10 d1 23 00 02 38 d1 23 00 02 61 d1 23 00 02 87 d1 23 00 02 af d1 23 00 02 d5 d1 23 00 02 11 04 23 00 02 39 04 23 00 02 62 04 23 00 02 88 04 23 00 02 b0 04 23 00 02 d6 04 23 00 02 12 05 23 00 02 3a 05 23 00 02 63 05 23 00 02 89 05 23 00 02 b1 05 23 00 02 d7 05 23 00 02 18 aa 23 00 02 14 36 23 00 02 42 aa 23 00 02 3d 36 23 00 02 69 aa 23 00 02 65 36 23 00 02 8f aa 23 00 02 8b 36 23 00 02 b7 aa 23 00 02 b3 36 23 00 02 dd aa 23 00 02 d9 36 23 00 02 15 74 23 00 02 3f 74 23 00 02 66 74 23 00 02 8c 74 23 00 02 b4 74 23 00 02 da 74 23 00 02 16 9f 23 00 02 40 9f 23 00 02 67 9f 23 00 02 8d 9f 23 00 02 b5 9f 23 00 02 db 9f 23 00 02 17 dc 23 00 02 41 dc 23 00 02 68 dc 23 00 02 8e dc 23 00 02 b6 dc 23 00 02 dc dc 23 00 02 1d ff 23 00 02 19 03 23 00 02 47 ff 23 00 02 43 03 23 00 02 6e ff 23 00 02 6a 03 23 00 02 94 ff 23 00 02 90 03 23 00 02 bc ff 23 00 02 b8 03 23 00 02 e2 ff 23 00 02 de 03 23 00 02 1a 35 23 00 02 44 35 23 00 02 6b 35 23 00 02 91 35 23 00 02 b9 35 23 00 02 df 35 23 00 02 1b 45 23 00 02 45 45 23 00 02 6c 45 23 00 02 92 45 23 00 02 ba 45 23 00 02 e0 45 23 00 02 1c 55 23 00 02 46 55 23 00 02 6d 55 23 00 02 93 55 23 00 02 bb 55 23 00 02 e1 55 23 00 02 22 ff 23 00 02 1e 68 23 00 02 4c ff 23 00 02 48 68 23 00 02 73 ff 23 00 02 6f 68 23 00 02 99 ff 23 00 02 95 68 23 00 02 c1 ff 23 00 02 bd 68 23 00 02 e7 ff 23 00 02 e3 68 23 00 02 1f 7e 23 00 02 49 7e 23 00 02 70 7e 23 00 02 96 7e 23 00 02 be 7e 23 00 02 e4 7e 23 00 02 20 97 23 00 02 4a 97 23 00 02 71 97 23 00 02 97 97 23 00 02 bf 97 23 00 02 e5 97 23 00 02 21 b5 23 00 02 4b b5 23 00 02 72 b5 23 00 02 98 b5 23 00 02 c0 b5 23 00 02 e6 b5 23 00 02 25 f0 23 00 02 23 e8 23 00 02 4f f0 23 00 02 4d e8 23 00 02 76 f0 23 00 02 74 e8 23 00 02 9c f0 23 00 02 9a e8 23 00 02 c4 f0 23 00 02 c2 e8 23 00 02 ea f0 23 00 02 e8 e8 23 00 02 24 ff 23 00 02 4e ff 23 00 02 75 ff 23 00 02 9b ff 23 00 02 c3 ff 23 00 02 e9 ff 23 00 02 fe 3d 23 00 02 00 04 23 00 02 fe 23 23 00 02 08 82 23 00 02 0a 00 23 00 02 0b 00 23 00 02 0c 01 23 00 02 16 00 23 00 02 18 02 23 00 02 1b 04 23 00 02 19 04 23 00 02 1c 81 23 00 02 1f 00 23 00 02 20 03 23 00 02 23 04 23 00 02 21 01 23 00 02 54 63 23 00 02 55 54 23 00 02 6e 45 23 00 02 6d 36 23 00 02 fe 3d 23 00 02 55 78 23 00 02 fe 20 23 00 02 26 30 23 00 02 fe 3d 23 00 02 20 71 23 00 02 50 8f 23 00 02 51 8f 23 00 02 fe 00 23 00 02 35 00 05 78 01 11 05 00 01 29]; + panel-exit-sequence = <0x5000128 0x5000110>; + power-supply = <0xf9>; + phandle = <0x2ad>; + + display-timings { + native-mode = <0x100>; + phandle = <0x2ae>; + + timing0 { + clock-frequency = <0x7de2900>; + hactive = <0x438>; + vactive = <0x780>; + hfront-porch = <0x0f>; + hsync-len = <0x04>; + hback-porch = <0x1e>; + vfront-porch = <0x0f>; + vsync-len = <0x02>; + vback-porch = <0x0f>; + hsync-active = <0x00>; + vsync-active = <0x00>; + de-active = <0x00>; + pixelclk-active = <0x00>; + phandle = <0x100>; + }; + }; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint { + remote-endpoint = <0x101>; + phandle = <0xff>; + }; + }; + }; + }; + }; + + hdcp@fde40000 { + compatible = "rockchip,rk3588-hdcp"; + reg = <0x00 0xfde40000 0x00 0x80>; + interrupts = <0x00 0x9f 0x04>; + clocks = <0x02 0x1ed 0x02 0x1ef 0x02 0x1ee 0x02 0x1ec 0x02 0x1f1 0x02 0x1f2>; + clock-names = "aclk\0pclk\0hclk\0hclk_key\0aclk_trng\0pclk_trng"; + resets = <0x02 0x37f 0x02 0x37d 0x02 0x37c 0x02 0x37b 0x02 0x381>; + reset-names = "hdcp\0h_hdcp\0a_hdcp\0hdcp_key\0trng"; + power-domains = <0x06 0x19>; + rockchip,vo-grf = <0x102>; + status = "disabled"; + phandle = <0x2af>; + }; + + dp@fde50000 { + compatible = "rockchip,rk3588-dp"; + reg = <0x00 0xfde50000 0x00 0x4000>; + interrupts = <0x00 0xa1 0x04>; + clocks = <0x02 0x1e6 0x02 0x2cc 0x02 0x1fb 0x02 0x207 0x04 0x02 0x1ea>; + clock-names = "apb\0aux\0i2s\0spdif\0hclk\0hdcp"; + assigned-clocks = <0x02 0x2cc>; + assigned-clock-rates = <0xf42400>; + resets = <0x02 0x388>; + phys = <0x103>; + power-domains = <0x06 0x19>; + #sound-dai-cells = <0x01>; + status = "okay"; + phandle = <0x1e6>; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + #address-cells = <0x01>; + #size-cells = <0x00>; + + endpoint@0 { + reg = <0x00>; + remote-endpoint = <0x104>; + status = "disabled"; + phandle = <0xdd>; + }; + + endpoint@1 { + reg = <0x01>; + remote-endpoint = <0x39>; + status = "disabled"; + phandle = <0xe3>; + }; + + endpoint@2 { + reg = <0x02>; + remote-endpoint = <0x105>; + status = "okay"; + phandle = <0xe9>; + }; + }; + + port@1 { + reg = <0x01>; + + endpoint { + phandle = <0x2b0>; + }; + }; + }; + }; + + hdcp@fde70000 { + compatible = "rockchip,rk3588-hdcp"; + reg = <0x00 0xfde70000 0x00 0x80>; + interrupts = <0x00 0xa0 0x04>; + clocks = <0x02 0x217 0x02 0x219 0x02 0x218 0x02 0x216 0x02 0x228 0x02 0x229>; + clock-names = "aclk\0pclk\0hclk\0hclk_key\0aclk_trng\0pclk_trng"; + resets = <0x02 0x3c8 0x02 0x3c6 0x02 0x3c5 0x02 0x3c4 0x02 0x3ca>; + reset-names = "hdcp\0h_hdcp\0a_hdcp\0hdcp_key\0trng"; + power-domains = <0x06 0x1a>; + rockchip,vo-grf = <0xdb>; + status = "disabled"; + phandle = <0x2b1>; + }; + + hdmi@fde80000 { + compatible = "rockchip,rk3588-dw-hdmi"; + reg = <0x00 0xfde80000 0x00 0x10000 0x00 0xfde90000 0x00 0x10000>; + interrupts = <0x00 0xa9 0x04 0x00 0xaa 0x04 0x00 0xab 0x04 0x00 0xac 0x04 0x00 0x168 0x04>; + clocks = <0x02 0x221 0x02 0x265 0x02 0x222 0x02 0x223 0x02 0x246 0x02 0x274 0x02 0x275 0x02 0x276 0x02 0x277 0x05 0x36>; + clock-names = "pclk\0hpd\0earc\0hdmitx_ref\0aud\0dclk_vp0\0dclk_vp1\0dclk_vp2\0dclk_vp3\0hclk_vo1\0link_clk"; + resets = <0x02 0x3d0 0x02 0x49c>; + reset-names = "ref\0hdp"; + power-domains = <0x06 0x1a>; + pinctrl-names = "default"; + pinctrl-0 = <0x106 0x107 0x108 0x109>; + reg-io-width = <0x04>; + rockchip,grf = <0xc9>; + rockchip,vo1_grf = <0xdb>; + phys = <0x36>; + phy-names = "hdmi"; + #sound-dai-cells = <0x00>; + status = "disabled"; + enable-gpios = <0x10a 0x09 0x00>; + phandle = <0x1e3>; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + #address-cells = <0x01>; + #size-cells = <0x00>; + phandle = <0x2b2>; + + endpoint@0 { + reg = <0x00>; + remote-endpoint = <0x3d>; + status = "disabled"; + phandle = <0xdf>; + }; + + endpoint@1 { + reg = <0x01>; + remote-endpoint = <0x10b>; + status = "disabled"; + phandle = <0xe5>; + }; + + endpoint@2 { + reg = <0x02>; + remote-endpoint = <0x10c>; + status = "disabled"; + phandle = <0xeb>; + }; + }; + }; + }; + + edp@fdec0000 { + compatible = "rockchip,rk3588-edp"; + reg = <0x00 0xfdec0000 0x00 0x1000>; + interrupts = <0x00 0xa3 0x04>; + clocks = <0x02 0x211 0x02 0x210 0x02 0x212 0x05>; + clock-names = "dp\0pclk\0spdif\0hclk"; + resets = <0x02 0x3e1 0x02 0x3e0>; + reset-names = "dp\0apb"; + phys = <0x10d>; + phy-names = "dp"; + power-domains = <0x06 0x1a>; + rockchip,grf = <0xdb>; + #sound-dai-cells = <0x01>; + status = "disabled"; + phandle = <0x1e0>; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + #address-cells = <0x01>; + #size-cells = <0x00>; + + endpoint@0 { + reg = <0x00>; + remote-endpoint = <0x10e>; + status = "disabled"; + phandle = <0xde>; + }; + + endpoint@1 { + reg = <0x01>; + remote-endpoint = <0x10f>; + status = "disabled"; + phandle = <0xe4>; + }; + + endpoint@2 { + reg = <0x02>; + remote-endpoint = <0x3c>; + status = "disabled"; + phandle = <0xea>; + }; + }; + + port@1 { + reg = <0x01>; + + endpoint { + phandle = <0x2b3>; + }; + }; + }; + }; + + qos@fdf35000 { + compatible = "syscon"; + reg = <0x00 0xfdf35000 0x00 0x20>; + phandle = <0x85>; + }; + + qos@fdf35200 { + compatible = "syscon"; + reg = <0x00 0xfdf35200 0x00 0x20>; + phandle = <0x86>; + }; + + qos@fdf35400 { + compatible = "syscon"; + reg = <0x00 0xfdf35400 0x00 0x20>; + phandle = <0x87>; + }; + + qos@fdf35600 { + compatible = "syscon"; + reg = <0x00 0xfdf35600 0x00 0x20>; + phandle = <0x88>; + }; + + qos@fdf36000 { + compatible = "syscon"; + reg = <0x00 0xfdf36000 0x00 0x20>; + phandle = <0xa8>; + }; + + qos@fdf39000 { + compatible = "syscon"; + reg = <0x00 0xfdf39000 0x00 0x20>; + phandle = <0xaf>; + }; + + qos@fdf3a000 { + compatible = "syscon"; + reg = <0x00 0xfdf3a000 0x00 0x20>; + phandle = <0xad>; + }; + + qos@fdf3a200 { + compatible = "syscon"; + reg = <0x00 0xfdf3a200 0x00 0x20>; + phandle = <0xae>; + }; + + qos@fdf3d800 { + compatible = "syscon"; + reg = <0x00 0xfdf3d800 0x00 0x20>; + phandle = <0xb0>; + }; + + qos@fdf3e000 { + compatible = "syscon"; + reg = <0x00 0xfdf3e000 0x00 0x20>; + phandle = <0xaa>; + }; + + qos@fdf3e200 { + compatible = "syscon"; + reg = <0x00 0xfdf3e200 0x00 0x20>; + phandle = <0xa9>; + }; + + qos@fdf3e400 { + compatible = "syscon"; + reg = <0x00 0xfdf3e400 0x00 0x20>; + phandle = <0xab>; + }; + + qos@fdf3e600 { + compatible = "syscon"; + reg = <0x00 0xfdf3e600 0x00 0x20>; + phandle = <0xac>; + }; + + qos@fdf40000 { + compatible = "syscon"; + reg = <0x00 0xfdf40000 0x00 0x20>; + phandle = <0xa6>; + }; + + qos@fdf40200 { + compatible = "syscon"; + reg = <0x00 0xfdf40200 0x00 0x20>; + phandle = <0xa7>; + }; + + qos@fdf40400 { + compatible = "syscon"; + reg = <0x00 0xfdf40400 0x00 0x20>; + phandle = <0xa0>; + }; + + qos@fdf40500 { + compatible = "syscon"; + reg = <0x00 0xfdf40500 0x00 0x20>; + phandle = <0xa1>; + }; + + qos@fdf40600 { + compatible = "syscon"; + reg = <0x00 0xfdf40600 0x00 0x20>; + phandle = <0xa2>; + }; + + qos@fdf40800 { + compatible = "syscon"; + reg = <0x00 0xfdf40800 0x00 0x20>; + phandle = <0xa3>; + }; + + qos@fdf41000 { + compatible = "syscon"; + reg = <0x00 0xfdf41000 0x00 0x20>; + phandle = <0xa4>; + }; + + qos@fdf41100 { + compatible = "syscon"; + reg = <0x00 0xfdf41100 0x00 0x20>; + phandle = <0xa5>; + }; + + qos@fdf60000 { + compatible = "syscon"; + reg = <0x00 0xfdf60000 0x00 0x20>; + phandle = <0x8b>; + }; + + qos@fdf60200 { + compatible = "syscon"; + reg = <0x00 0xfdf60200 0x00 0x20>; + phandle = <0x8c>; + }; + + qos@fdf60400 { + compatible = "syscon"; + reg = <0x00 0xfdf60400 0x00 0x20>; + phandle = <0x8d>; + }; + + qos@fdf61000 { + compatible = "syscon"; + reg = <0x00 0xfdf61000 0x00 0x20>; + phandle = <0x8e>; + }; + + qos@fdf61200 { + compatible = "syscon"; + reg = <0x00 0xfdf61200 0x00 0x20>; + phandle = <0x8f>; + }; + + qos@fdf61400 { + compatible = "syscon"; + reg = <0x00 0xfdf61400 0x00 0x20>; + phandle = <0x90>; + }; + + qos@fdf62000 { + compatible = "syscon"; + reg = <0x00 0xfdf62000 0x00 0x20>; + phandle = <0x89>; + }; + + qos@fdf63000 { + compatible = "syscon"; + reg = <0x00 0xfdf63000 0x00 0x20>; + phandle = <0x8a>; + }; + + qos@fdf64000 { + compatible = "syscon"; + reg = <0x00 0xfdf64000 0x00 0x20>; + phandle = <0x99>; + }; + + qos@fdf66000 { + compatible = "syscon"; + reg = <0x00 0xfdf66000 0x00 0x20>; + phandle = <0x91>; + }; + + qos@fdf66200 { + compatible = "syscon"; + reg = <0x00 0xfdf66200 0x00 0x20>; + phandle = <0x92>; + }; + + qos@fdf66400 { + compatible = "syscon"; + reg = <0x00 0xfdf66400 0x00 0x20>; + phandle = <0x93>; + }; + + qos@fdf66600 { + compatible = "syscon"; + reg = <0x00 0xfdf66600 0x00 0x20>; + phandle = <0x94>; + }; + + qos@fdf66800 { + compatible = "syscon"; + reg = <0x00 0xfdf66800 0x00 0x20>; + phandle = <0x95>; + }; + + qos@fdf66a00 { + compatible = "syscon"; + reg = <0x00 0xfdf66a00 0x00 0x20>; + phandle = <0x96>; + }; + + qos@fdf66c00 { + compatible = "syscon"; + reg = <0x00 0xfdf66c00 0x00 0x20>; + phandle = <0x97>; + }; + + qos@fdf66e00 { + compatible = "syscon"; + reg = <0x00 0xfdf66e00 0x00 0x20>; + phandle = <0x98>; + }; + + qos@fdf67000 { + compatible = "syscon"; + reg = <0x00 0xfdf67000 0x00 0x20>; + phandle = <0x9a>; + }; + + qos@fdf67200 { + compatible = "syscon"; + reg = <0x00 0xfdf67200 0x00 0x20>; + phandle = <0x2b4>; + }; + + qos@fdf70000 { + compatible = "syscon"; + reg = <0x00 0xfdf70000 0x00 0x20>; + phandle = <0x83>; + }; + + qos@fdf71000 { + compatible = "syscon"; + reg = <0x00 0xfdf71000 0x00 0x20>; + phandle = <0x84>; + }; + + qos@fdf72000 { + compatible = "syscon"; + reg = <0x00 0xfdf72000 0x00 0x20>; + phandle = <0x80>; + }; + + qos@fdf72200 { + compatible = "syscon"; + reg = <0x00 0xfdf72200 0x00 0x20>; + phandle = <0x81>; + }; + + qos@fdf72400 { + compatible = "syscon"; + reg = <0x00 0xfdf72400 0x00 0x20>; + phandle = <0x82>; + }; + + qos@fdf80000 { + compatible = "syscon"; + reg = <0x00 0xfdf80000 0x00 0x20>; + phandle = <0x9d>; + }; + + qos@fdf81000 { + compatible = "syscon"; + reg = <0x00 0xfdf81000 0x00 0x20>; + phandle = <0x9e>; + }; + + qos@fdf81200 { + compatible = "syscon"; + reg = <0x00 0xfdf81200 0x00 0x20>; + phandle = <0x9f>; + }; + + qos@fdf82000 { + compatible = "syscon"; + reg = <0x00 0xfdf82000 0x00 0x20>; + phandle = <0x9b>; + }; + + qos@fdf82200 { + compatible = "syscon"; + reg = <0x00 0xfdf82200 0x00 0x20>; + phandle = <0x9c>; + }; + + dfi@fe060000 { + compatible = "rockchip,rk3588-dfi"; + reg = <0x00 0xfe060000 0x00 0x10000>; + rockchip,pmu_grf = <0x110>; + clocks = <0x02 0x2d2 0x02 0x2d3 0x02 0x2d4 0x02 0x2d5>; + clock-names = "pclk_ddr_mon_ch0\0pclk_ddr_mon_ch1\0pclk_ddr_mon_ch2\0pclk_ddr_mon_ch3"; + status = "okay"; + phandle = <0x41>; + }; + + pcie@fe180000 { + compatible = "rockchip,rk3588-pcie\0snps,dw-pcie"; + #address-cells = <0x03>; + #size-cells = <0x02>; + bus-range = <0x30 0x3f>; + clocks = <0x02 0x151 0x02 0x156 0x02 0x14c 0x02 0x15c 0x02 0x161 0x02 0x2c5>; + clock-names = "aclk_mst\0aclk_slv\0aclk_dbi\0pclk\0aux\0pipe"; + device_type = "pci"; + interrupts = <0x00 0xf8 0x04 0x00 0xf7 0x04 0x00 0xf6 0x04 0x00 0xf5 0x04 0x00 0xf4 0x04>; + interrupt-names = "sys\0pmc\0msg\0legacy\0err"; + #interrupt-cells = <0x01>; + interrupt-map-mask = <0x00 0x00 0x00 0x07>; + interrupt-map = <0x00 0x00 0x00 0x01 0x111 0x00 0x00 0x00 0x00 0x02 0x111 0x01 0x00 0x00 0x00 0x03 0x111 0x02 0x00 0x00 0x00 0x04 0x111 0x03>; + linux,pci-domain = <0x03>; + num-ib-windows = <0x08>; + num-ob-windows = <0x08>; + num-viewport = <0x04>; + max-link-speed = <0x02>; + msi-map = <0x3000 0x112 0x3000 0x1000>; + num-lanes = <0x01>; + phys = <0x71 0x02>; + phy-names = "pcie-phy"; + ranges = <0x81000000 0x00 0xf3100000 0x00 0xf3100000 0x00 0x100000 0x82000000 0x00 0xf3200000 0x00 0xf3200000 0x00 0xe00000 0xc3000000 0x09 0xc0000000 0x09 0xc0000000 0x00 0x40000000>; + reg = <0x00 0xfe180000 0x00 0x10000 0x0a 0x40c00000 0x00 0x400000 0x00 0xf3000000 0x00 0x100000>; + reg-names = "pcie-apb\0pcie-dbi\0config"; + resets = <0x02 0x210 0x02 0x21f>; + reset-names = "pcie\0periph"; + rockchip,pipe-grf = <0x77>; + status = "disabled"; + phandle = <0x2b5>; + + legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0x00>; + #interrupt-cells = <0x01>; + interrupt-parent = <0x01>; + interrupts = <0x00 0xf5 0x01>; + phandle = <0x111>; + }; + }; + + pcie@fe190000 { + compatible = "rockchip,rk3588-pcie\0snps,dw-pcie"; + #address-cells = <0x03>; + #size-cells = <0x02>; + bus-range = <0x40 0x4f>; + clocks = <0x02 0x152 0x02 0x157 0x02 0x14d 0x02 0x15d 0x02 0x162 0x02 0x182>; + clock-names = "aclk_mst\0aclk_slv\0aclk_dbi\0pclk\0aux\0pipe"; + device_type = "pci"; + interrupts = <0x00 0xfd 0x04 0x00 0xfc 0x04 0x00 0xfb 0x04 0x00 0xfa 0x04 0x00 0xf9 0x04>; + interrupt-names = "sys\0pmc\0msg\0legacy\0err"; + #interrupt-cells = <0x01>; + interrupt-map-mask = <0x00 0x00 0x00 0x07>; + interrupt-map = <0x00 0x00 0x00 0x01 0x113 0x00 0x00 0x00 0x00 0x02 0x113 0x01 0x00 0x00 0x00 0x03 0x113 0x02 0x00 0x00 0x00 0x04 0x113 0x03>; + linux,pci-domain = <0x04>; + num-ib-windows = <0x08>; + num-ob-windows = <0x08>; + num-viewport = <0x04>; + max-link-speed = <0x02>; + msi-map = <0x4000 0x112 0x4000 0x1000>; + num-lanes = <0x01>; + phys = <0x114 0x02>; + phy-names = "pcie-phy"; + ranges = <0x81000000 0x00 0xf4100000 0x00 0xf4100000 0x00 0x100000 0x82000000 0x00 0xf4200000 0x00 0xf4200000 0x00 0xe00000 0xc3000000 0x0a 0x00 0x0a 0x00 0x00 0x40000000>; + reg = <0x00 0xfe190000 0x00 0x10000 0x0a 0x41000000 0x00 0x400000 0x00 0xf4000000 0x00 0x100000>; + reg-names = "pcie-apb\0pcie-dbi\0config"; + resets = <0x02 0x211 0x02 0x220>; + reset-names = "pcie\0periph"; + rockchip,pipe-grf = <0x77>; + status = "disabled"; + phandle = <0x2b6>; + + legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0x00>; + #interrupt-cells = <0x01>; + interrupt-parent = <0x01>; + interrupts = <0x00 0xfa 0x01>; + phandle = <0x113>; + }; + }; + + uio@fe1c0000 { + compatible = "rockchip,uio-gmac"; + reg = <0x00 0xfe1c0000 0x00 0x10000>; + rockchip,ethernet = <0x115>; + status = "disabled"; + phandle = <0x2b7>; + }; + + ethernet@fe1c0000 { + local-mac-address = [46 ae fd 14 a7 64]; + compatible = "rockchip,rk3588-gmac\0snps,dwmac-4.20a"; + reg = <0x00 0xfe1c0000 0x00 0x10000>; + interrupts = <0x00 0xea 0x04 0x00 0xe9 0x04>; + interrupt-names = "macirq\0eth_wake_irq"; + rockchip,grf = <0xc9>; + rockchip,php_grf = <0x77>; + clocks = <0x02 0x144 0x02 0x145 0x02 0x168 0x02 0x16d 0x02 0x143>; + clock-names = "stmmaceth\0clk_mac_ref\0pclk_mac\0aclk_mac\0ptp_ref"; + resets = <0x02 0x20b>; + reset-names = "stmmaceth"; + power-domains = <0x06 0x21>; + snps,mixed-burst; + snps,tso; + snps,axi-config = <0x116>; + snps,mtl-rx-config = <0x117>; + snps,mtl-tx-config = <0x118>; + status = "okay"; + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + snps,reset-gpio = <0x119 0x0f 0x01>; + snps,reset-active-low; + snps,reset-delays-us = <0x00 0x4e20 0x186a0>; + pinctrl-names = "default"; + pinctrl-0 = <0x11a 0x11b 0x11c 0x11d 0x11e>; + tx_delay = <0x43>; + phy-handle = <0x11f>; + phandle = <0x115>; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <0x01>; + #size-cells = <0x00>; + phandle = <0x2b8>; + + phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x01>; + phandle = <0x11f>; + }; + }; + + stmmac-axi-config { + snps,wr_osr_lmt = <0x04>; + snps,rd_osr_lmt = <0x08>; + snps,blen = <0x00 0x00 0x00 0x00 0x10 0x08 0x04>; + phandle = <0x116>; + }; + + rx-queues-config { + snps,rx-queues-to-use = <0x01>; + phandle = <0x117>; + + queue0 { + }; + }; + + tx-queues-config { + snps,tx-queues-to-use = <0x01>; + phandle = <0x118>; + + queue0 { + }; + }; + }; + + sata@fe210000 { + compatible = "rockchip,rk-ahci\0snps,dwc-ahci"; + reg = <0x00 0xfe210000 0x00 0x1000>; + clocks = <0x02 0x171 0x02 0x16e 0x02 0x174 0x02 0x163 0x02 0x17e>; + clock-names = "sata\0pmalive\0rxoob\0ref\0asic"; + interrupts = <0x00 0x111 0x04>; + interrupt-names = "hostc"; + phys = <0x114 0x01>; + phy-names = "sata-phy"; + ports-implemented = <0x01>; + status = "okay"; + phandle = <0x2b9>; + }; + + sata@fe230000 { + compatible = "rockchip,rk-ahci\0snps,dwc-ahci"; + reg = <0x00 0xfe230000 0x00 0x1000>; + clocks = <0x02 0x173 0x02 0x170 0x02 0x176 0x02 0x165 0x02 0x180>; + clock-names = "sata\0pmalive\0rxoob\0ref\0asic"; + interrupts = <0x00 0x113 0x04>; + interrupt-names = "hostc"; + phys = <0x71 0x01>; + phy-names = "sata-phy"; + ports-implemented = <0x01>; + status = "disabled"; + phandle = <0x2ba>; + }; + + spi@fe2b0000 { + compatible = "rockchip,sfc"; + reg = <0x00 0xfe2b0000 0x00 0x4000>; + interrupts = <0x00 0xce 0x04>; + clocks = <0x02 0x13d 0x02 0x13e>; + clock-names = "clk_sfc\0hclk_sfc"; + #address-cells = <0x01>; + #size-cells = <0x00>; + status = "disabled"; + phandle = <0x2bb>; + }; + + mmc@fe2c0000 { + compatible = "rockchip,rk3588-dw-mshc\0rockchip,rk3288-dw-mshc"; + reg = <0x00 0xfe2c0000 0x00 0x4000>; + interrupts = <0x00 0xcb 0x04>; + clocks = <0x0f 0x17 0x0f 0x09 0x02 0x2c2 0x02 0x2c3>; + clock-names = "biu\0ciu\0ciu-drive\0ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <0x8f0d180>; + pinctrl-names = "default"; + pinctrl-0 = <0x120 0x121 0x122 0x123>; + power-domains = <0x06 0x28>; + status = "okay"; + no-sdio; + no-mmc; + bus-width = <0x04>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vqmmc-supply = <0x124>; + vmmc-supply = <0x125>; + phandle = <0x2bc>; + }; + + mmc@fe2d0000 { + compatible = "rockchip,rk3588-dw-mshc\0rockchip,rk3288-dw-mshc"; + reg = <0x00 0xfe2d0000 0x00 0x4000>; + interrupts = <0x00 0xcc 0x04>; + clocks = <0x02 0x199 0x02 0x19a 0x02 0x2c0 0x02 0x2c1>; + clock-names = "biu\0ciu\0ciu-drive\0ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <0x8f0d180>; + pinctrl-names = "default"; + pinctrl-0 = <0x126>; + power-domains = <0x06 0x25>; + status = "okay"; + no-sd; + no-mmc; + bus-width = <0x04>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <0x127>; + non-removable; + sd-uhs-sdr104; + phandle = <0x2bd>; + }; + + mmc@fe2e0000 { + compatible = "rockchip,rk3588-dwcmshc\0rockchip,dwcmshc-sdhci"; + reg = <0x00 0xfe2e0000 0x00 0x10000>; + interrupts = <0x00 0xcd 0x04>; + assigned-clocks = <0x02 0x13b 0x02 0x13c 0x02 0x13a>; + assigned-clock-rates = <0xbebc200 0x16e3600 0xbebc200>; + clocks = <0x02 0x13a 0x02 0x138 0x02 0x139 0x02 0x13b 0x02 0x13c>; + clock-names = "core\0bus\0axi\0block\0timer"; + resets = <0x02 0x1f6 0x02 0x1f4 0x02 0x1f5 0x02 0x1f7 0x02 0x1f8>; + reset-names = "core\0bus\0axi\0block\0timer"; + max-frequency = <0xbebc200>; + supports-cqe; + status = "okay"; + bus-width = <0x08>; + no-sdio; + no-sd; + non-removable; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + full-pwr-cycle-in-suspend; + phandle = <0x2be>; + }; + + crypto@fe370000 { + compatible = "rockchip,rk3588-crypto"; + reg = <0x00 0xfe370000 0x00 0x2000>; + interrupts = <0x00 0xd1 0x04>; + clocks = <0x0f 0x0b 0x0f 0x0c 0x0f 0x14 0x0f 0x15>; + clock-names = "aclk\0hclk\0sclk\0pka"; + resets = <0x128 0x0f>; + reset-names = "crypto-rst"; + status = "disabled"; + phandle = <0x2bf>; + }; + + rng@fe378000 { + compatible = "rockchip,trngv1"; + reg = <0x00 0xfe378000 0x00 0x200>; + interrupts = <0x00 0x190 0x04>; + clocks = <0x0f 0x0c>; + clock-names = "hclk_trng"; + resets = <0x128 0x30>; + reset-names = "reset"; + status = "okay"; + phandle = <0x2c0>; + }; + + i2s@fe470000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x00 0xfe470000 0x00 0x1000>; + interrupts = <0x00 0xb4 0x04>; + clocks = <0x02 0x33 0x02 0x37 0x02 0x30>; + clock-names = "mclk_tx\0mclk_rx\0hclk"; + assigned-clocks = <0x02 0x31 0x02 0x35>; + assigned-clock-parents = <0x02 0x05 0x02 0x05>; + dmas = <0x7a 0x00 0x7a 0x01>; + dma-names = "tx\0rx"; + power-domains = <0x06 0x26>; + resets = <0x02 0x77 0x02 0x7a>; + reset-names = "tx-m\0rx-m"; + rockchip,trcm-sync-tx-only; + i2s-lrck-gpio = <0x129 0x15 0x00>; + pinctrl-names = "default\0idle\0clk"; + pinctrl-0 = <0x12a 0x12b 0x12c 0x12d>; + pinctrl-1 = <0x12e>; + pinctrl-2 = <0x12a 0x12b>; + #sound-dai-cells = <0x00>; + status = "okay"; + phandle = <0x1f0>; + }; + + i2s@fe480000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x00 0xfe480000 0x00 0x1000>; + interrupts = <0x00 0xb5 0x04>; + clocks = <0x02 0x28c 0x02 0x290 0x02 0x288>; + clock-names = "mclk_tx\0mclk_rx\0hclk"; + dmas = <0x7a 0x02 0x7a 0x03>; + dma-names = "tx\0rx"; + resets = <0x02 0xc002a 0x02 0xc002d>; + reset-names = "tx-m\0rx-m"; + rockchip,trcm-sync-tx-only; + i2s-lrck-gpio = <0x10a 0x02 0x00>; + pinctrl-names = "default"; + pinctrl-0 = <0x12f 0x130 0x131 0x132 0x133 0x134 0x135 0x136 0x137 0x138>; + #sound-dai-cells = <0x00>; + status = "disabled"; + phandle = <0x2c1>; + }; + + i2s@fe490000 { + compatible = "rockchip,rk3588-i2s\0rockchip,rk3066-i2s"; + reg = <0x00 0xfe490000 0x00 0x1000>; + interrupts = <0x00 0xb6 0x04>; + clocks = <0x02 0x27 0x02 0x22>; + clock-names = "i2s_clk\0i2s_hclk"; + assigned-clocks = <0x02 0x24>; + assigned-clock-parents = <0x02 0x05>; + dmas = <0xf4 0x00 0xf4 0x01>; + dma-names = "tx\0rx"; + power-domains = <0x06 0x26>; + rockchip,trcm-sync-tx-only; + pinctrl-names = "default\0idle\0clk"; + pinctrl-0 = <0x139 0x13a 0x13b 0x13c>; + pinctrl-1 = <0x13d>; + pinctrl-2 = <0x139 0x13a>; + #sound-dai-cells = <0x00>; + status = "disabled"; + rockchip,bclk-fs = <0x20>; + phandle = <0x1dd>; + }; + + i2s@fe4a0000 { + compatible = "rockchip,rk3588-i2s\0rockchip,rk3066-i2s"; + reg = <0x00 0xfe4a0000 0x00 0x1000>; + interrupts = <0x00 0xb7 0x04>; + clocks = <0x02 0x2d 0x02 0x23>; + clock-names = "i2s_clk\0i2s_hclk"; + assigned-clocks = <0x02 0x2a>; + assigned-clock-parents = <0x02 0x05>; + dmas = <0xf4 0x02 0xf4 0x03>; + dma-names = "tx\0rx"; + power-domains = <0x06 0x26>; + rockchip,trcm-sync-tx-only; + pinctrl-names = "default\0idle\0clk"; + pinctrl-0 = <0x13e 0x13f>; + pinctrl-1 = <0x140>; + pinctrl-2 = <0x141 0x142>; + #sound-dai-cells = <0x00>; + status = "disabled"; + phandle = <0x2c2>; + }; + + pdm@fe4b0000 { + compatible = "rockchip,rk3588-pdm"; + reg = <0x00 0xfe4b0000 0x00 0x1000>; + clocks = <0x02 0x29f 0x02 0x29e>; + clock-names = "pdm_clk\0pdm_hclk"; + dmas = <0x7a 0x04>; + dma-names = "rx"; + pinctrl-names = "default\0idle\0clk"; + pinctrl-0 = <0x143 0x144 0x145 0x146>; + pinctrl-1 = <0x147>; + pinctrl-2 = <0x148 0x149>; + #sound-dai-cells = <0x00>; + status = "disabled"; + phandle = <0x2c3>; + }; + + pdm@fe4c0000 { + compatible = "rockchip,rk3588-pdm"; + reg = <0x00 0xfe4c0000 0x00 0x1000>; + clocks = <0x02 0x3b 0x02 0x3a>; + clock-names = "pdm_clk\0pdm_hclk"; + assigned-clocks = <0x02 0x3b>; + assigned-clock-parents = <0x02 0x05>; + dmas = <0xf4 0x04>; + dma-names = "rx"; + power-domains = <0x06 0x26>; + pinctrl-names = "default\0idle\0clk"; + pinctrl-0 = <0x14a 0x14b 0x14c 0x14d>; + pinctrl-1 = <0x14e>; + pinctrl-2 = <0x14f 0x150>; + #sound-dai-cells = <0x00>; + status = "disabled"; + phandle = <0x2c4>; + }; + + vad@fe4d0000 { + compatible = "rockchip,rk3588-vad"; + reg = <0x00 0xfe4d0000 0x00 0x1000>; + reg-names = "vad"; + clocks = <0x02 0x2a0>; + clock-names = "hclk"; + interrupts = <0x00 0xca 0x04>; + rockchip,audio-src = <0x00>; + rockchip,det-channel = <0x00>; + rockchip,mode = <0x00>; + #sound-dai-cells = <0x00>; + status = "disabled"; + phandle = <0x2c5>; + }; + + spdif-tx@fe4e0000 { + compatible = "rockchip,rk3588-spdif\0rockchip,rk3568-spdif"; + reg = <0x00 0xfe4e0000 0x00 0x1000>; + interrupts = <0x00 0xc1 0x04>; + dmas = <0x7a 0x05>; + dma-names = "tx"; + clock-names = "mclk\0hclk"; + clocks = <0x02 0x41 0x02 0x3e>; + assigned-clocks = <0x02 0x3f>; + assigned-clock-parents = <0x02 0x05>; + power-domains = <0x06 0x26>; + pinctrl-names = "default"; + pinctrl-0 = <0x151>; + #sound-dai-cells = <0x00>; + status = "disabled"; + phandle = <0x1ea>; + }; + + spdif-tx@fe4f0000 { + compatible = "rockchip,rk3588-spdif\0rockchip,rk3568-spdif"; + reg = <0x00 0xfe4f0000 0x00 0x1000>; + interrupts = <0x00 0xc2 0x04>; + dmas = <0xf4 0x05>; + dma-names = "tx"; + clock-names = "mclk\0hclk"; + clocks = <0x02 0x47 0x02 0x44>; + assigned-clocks = <0x02 0x45>; + assigned-clock-parents = <0x02 0x05>; + power-domains = <0x06 0x26>; + pinctrl-names = "default"; + pinctrl-0 = <0x152>; + #sound-dai-cells = <0x00>; + status = "disabled"; + phandle = <0x1ec>; + }; + + codec-digital@fe500000 { + compatible = "rockchip,rk3588-codec-digital\0rockchip,codec-digital-v1"; + reg = <0x00 0xfe500000 0x00 0x1000>; + clocks = <0x02 0x29 0x02 0x2f>; + clock-names = "dac\0pclk"; + power-domains = <0x06 0x26>; + resets = <0x02 0x84>; + reset-names = "reset"; + rockchip,grf = <0xc9>; + rockchip,pwm-output-mode; + pinctrl-names = "default"; + pinctrl-0 = <0x153>; + #sound-dai-cells = <0x00>; + status = "disabled"; + phandle = <0x2c6>; + }; + + hwspinlock@fe5a0000 { + compatible = "rockchip,hwspinlock"; + reg = <0x00 0xfe5a0000 0x00 0x100>; + #hwlock-cells = <0x01>; + phandle = <0x2c7>; + }; + + interrupt-controller@fe600000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <0x03>; + #address-cells = <0x02>; + #size-cells = <0x02>; + ranges; + interrupt-controller; + reg = <0x00 0xfe600000 0x00 0x10000 0x00 0xfe680000 0x00 0x100000>; + interrupts = <0x01 0x09 0x04>; + phandle = <0x01>; + + // msi-controller@fe640000 { + // compatible = "arm,gic-v3-its"; + // msi-controller; + // #msi-cells = <0x01>; + // reg = <0x00 0xfe640000 0x00 0x20000>; + // phandle = <0x112>; + // }; + + // msi-controller@fe660000 { + // compatible = "arm,gic-v3-its"; + // msi-controller; + // #msi-cells = <0x01>; + // reg = <0x00 0xfe660000 0x00 0x20000>; + // phandle = <0x1ca>; + // }; + }; + + dma-controller@fea10000 { + compatible = "arm,pl330\0arm,primecell"; + reg = <0x00 0xfea10000 0x00 0x4000>; + interrupts = <0x00 0x56 0x04 0x00 0x57 0x04>; + clocks = <0x02 0x78>; + clock-names = "apb_pclk"; + #dma-cells = <0x01>; + arm,pl330-periph-burst; + phandle = <0x7a>; + }; + + dma-controller@fea30000 { + compatible = "arm,pl330\0arm,primecell"; + reg = <0x00 0xfea30000 0x00 0x4000>; + interrupts = <0x00 0x58 0x04 0x00 0x59 0x04>; + clocks = <0x02 0x79>; + clock-names = "apb_pclk"; + #dma-cells = <0x01>; + arm,pl330-periph-burst; + phandle = <0xf4>; + }; + + can@fea50000 { + compatible = "rockchip,can-2.0"; + reg = <0x00 0xfea50000 0x00 0x1000>; + interrupts = <0x00 0x155 0x04>; + clocks = <0x02 0x70 0x02 0x6f>; + clock-names = "baudclk\0apb_pclk"; + resets = <0x02 0xb9 0x02 0xb8>; + reset-names = "can\0can-apb"; + pinctrl-names = "default"; + pinctrl-0 = <0x154>; + tx-fifo-depth = <0x01>; + rx-fifo-depth = <0x06>; + status = "disabled"; + phandle = <0x2c8>; + }; + + can@fea60000 { + compatible = "rockchip,can-2.0"; + reg = <0x00 0xfea60000 0x00 0x1000>; + interrupts = <0x00 0x156 0x04>; + clocks = <0x02 0x72 0x02 0x71>; + clock-names = "baudclk\0apb_pclk"; + resets = <0x02 0xbb 0x02 0xba>; + reset-names = "can\0can-apb"; + pinctrl-names = "default"; + pinctrl-0 = <0x155>; + tx-fifo-depth = <0x01>; + rx-fifo-depth = <0x06>; + status = "disabled"; + phandle = <0x2c9>; + }; + + can@fea70000 { + compatible = "rockchip,can-2.0"; + reg = <0x00 0xfea70000 0x00 0x1000>; + interrupts = <0x00 0x157 0x04>; + clocks = <0x02 0x74 0x02 0x73>; + clock-names = "baudclk\0apb_pclk"; + resets = <0x02 0xbd 0x02 0xbc>; + reset-names = "can\0can-apb"; + pinctrl-names = "default"; + pinctrl-0 = <0x156>; + tx-fifo-depth = <0x01>; + rx-fifo-depth = <0x06>; + status = "disabled"; + phandle = <0x2ca>; + }; + + decompress@fea80000 { + compatible = "rockchip,hw-decompress"; + reg = <0x00 0xfea80000 0x00 0x1000>; + interrupts = <0x00 0x55 0x04>; + clocks = <0x02 0x75 0x02 0x77 0x02 0x76>; + clock-names = "aclk\0dclk\0pclk"; + resets = <0x02 0x118>; + reset-names = "dresetn"; + status = "disabled"; + phandle = <0x2cb>; + }; + + i2c@fea90000 { + compatible = "rockchip,rk3588-i2c\0rockchip,rk3399-i2c"; + reg = <0x00 0xfea90000 0x00 0x1000>; + clocks = <0x02 0x8d 0x02 0x85>; + clock-names = "i2c\0pclk"; + interrupts = <0x00 0x13e 0x04>; + pinctrl-names = "default"; + pinctrl-0 = <0x157>; + resets = <0x02 0xb0 0x02 0xa8>; + reset-names = "i2c\0apb"; + #address-cells = <0x01>; + #size-cells = <0x00>; + status = "okay"; + phandle = <0x2cc>; + + rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <0x79>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_npu_s0"; + regulator-min-microvolt = <0x86470>; + regulator-max-microvolt = <0xe7ef0>; + regulator-ramp-delay = <0x8fc>; + rockchip,suspend-voltage-selector = <0x01>; + regulator-boot-on; + regulator-always-on; + phandle = <0xb3>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + i2c@feaa0000 { + compatible = "rockchip,rk3588-i2c\0rockchip,rk3399-i2c"; + reg = <0x00 0xfeaa0000 0x00 0x1000>; + clocks = <0x02 0x8e 0x02 0x86>; + clock-names = "i2c\0pclk"; + interrupts = <0x00 0x13f 0x04>; + pinctrl-names = "default"; + pinctrl-0 = <0x158>; + resets = <0x02 0xb1 0x02 0xa9>; + reset-names = "i2c\0apb"; + #address-cells = <0x01>; + #size-cells = <0x00>; + status = "disabled"; + phandle = <0x2cd>; + }; + + i2c@feab0000 { + compatible = "rockchip,rk3588-i2c\0rockchip,rk3399-i2c"; + reg = <0x00 0xfeab0000 0x00 0x1000>; + clocks = <0x02 0x8f 0x02 0x87>; + clock-names = "i2c\0pclk"; + interrupts = <0x00 0x140 0x04>; + pinctrl-names = "default"; + pinctrl-0 = <0x159>; + resets = <0x02 0xb2 0x02 0xaa>; + reset-names = "i2c\0apb"; + #address-cells = <0x01>; + #size-cells = <0x00>; + status = "okay"; + phandle = <0x2ce>; + + imx415@1a { + compatible = "sony,imx415"; + reg = <0x1a>; + clocks = <0x02 0x102>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <0x15a>; + power-domains = <0x06 0x1b>; + pwdn-gpios = <0x129 0x07 0x00>; + avdd-supply = <0x15b>; + rockchip,camera-module-index = <0x00>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT2022-PX1"; + rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20"; + phandle = <0x2cf>; + + port { + + endpoint { + remote-endpoint = <0x15c>; + data-lanes = <0x01 0x02 0x03 0x04>; + phandle = <0x33>; + }; + }; + }; + }; + + i2c@feac0000 { + compatible = "rockchip,rk3588-i2c\0rockchip,rk3399-i2c"; + reg = <0x00 0xfeac0000 0x00 0x1000>; + clocks = <0x02 0x90 0x02 0x88>; + clock-names = "i2c\0pclk"; + interrupts = <0x00 0x141 0x04>; + pinctrl-names = "default"; + pinctrl-0 = <0x15d>; + resets = <0x02 0xb3 0x02 0xab>; + reset-names = "i2c\0apb"; + #address-cells = <0x01>; + #size-cells = <0x00>; + status = "okay"; + phandle = <0x2d0>; + + light@47 { + compatible = "ls_stk3332"; + status = "disabled"; + reg = <0x47>; + type = <0x05>; + irq_enable = <0x00>; + als_threshold_high = <0x64>; + als_threshold_low = <0x0a>; + als_ctrl_gain = <0x02>; + poll_delay_ms = <0x64>; + phandle = <0x2d1>; + }; + + proximity@47 { + compatible = "ps_stk3332"; + status = "disabled"; + reg = <0x47>; + type = <0x06>; + ps_threshold_high = <0x200>; + ps_threshold_low = <0x100>; + ps_ctrl_gain = <0x03>; + ps_led_current = <0x04>; + poll_delay_ms = <0x64>; + phandle = <0x2d2>; + }; + + icm_acc@68 { + status = "okay"; + compatible = "icm42607_acc"; + reg = <0x68>; + irq-gpio = <0x10a 0x12 0x01>; + irq_enable = <0x00>; + poll_delay_ms = <0x1e>; + type = <0x02>; + layout = <0x00>; + phandle = <0x2d3>; + }; + + icm_gyro@68 { + status = "okay"; + compatible = "icm42607_gyro"; + reg = <0x68>; + poll_delay_ms = <0x1e>; + type = <0x04>; + layout = <0x00>; + phandle = <0x2d4>; + }; + }; + + i2c@fead0000 { + compatible = "rockchip,rk3588-i2c\0rockchip,rk3399-i2c"; + reg = <0x00 0xfead0000 0x00 0x1000>; + clocks = <0x02 0x91 0x02 0x89>; + clock-names = "i2c\0pclk"; + interrupts = <0x00 0x142 0x04>; + pinctrl-names = "default"; + pinctrl-0 = <0x15e>; + resets = <0x02 0xb4 0x02 0xac>; + reset-names = "i2c\0apb"; + #address-cells = <0x01>; + #size-cells = <0x00>; + status = "okay"; + phandle = <0x2d5>; + + gt1x@14 { + compatible = "goodix,gt1x"; + reg = <0x14>; + pinctrl-names = "default"; + pinctrl-0 = <0x15f>; + goodix,rst-gpio = <0x119 0x11 0x00>; + goodix,irq-gpio = <0x119 0x10 0x08>; + power-supply = <0xf9>; + phandle = <0x2d6>; + }; + + hynitron@5a { + compatible = "hyn,3240"; + reg = <0x5a>; + pinctrl-names = "ts_active\0ts_suspend"; + pinctrl-0 = <0x160 0x161>; + pinctrl-1 = <0x162 0x163>; + reset-gpios = <0x119 0x11 0x00>; + irq-gpios = <0x119 0x10 0x01>; + max-touch-number = <0x05>; + display-coords = <0x00 0x00 0x438 0x780>; + pos-swap = <0x00>; + posx-reverse = <0x00>; + posy-reverse = <0x00>; + phandle = <0x2d7>; + }; + }; + + timer@feae0000 { + compatible = "rockchip,rk3588-timer\0rockchip,rk3288-timer"; + reg = <0x00 0xfeae0000 0x00 0x20>; + interrupts = <0x00 0x121 0x04>; + clocks = <0x02 0x5c 0x02 0x5f>; + clock-names = "pclk\0timer"; + phandle = <0x2d8>; + }; + + watchdog@feaf0000 { + compatible = "snps,dw-wdt"; + reg = <0x00 0xfeaf0000 0x00 0x100>; + clocks = <0x02 0x6c 0x02 0x6b>; + clock-names = "tclk\0pclk"; + interrupts = <0x00 0x13b 0x04>; + status = "disabled"; + phandle = <0x2d9>; + }; + + spi@feb00000 { + compatible = "rockchip,rk3066-spi"; + reg = <0x00 0xfeb00000 0x00 0x1000>; + interrupts = <0x00 0x146 0x04>; + #address-cells = <0x01>; + #size-cells = <0x00>; + clocks = <0x02 0xa3 0x02 0x9e>; + clock-names = "spiclk\0apb_pclk"; + dmas = <0x7a 0x0e 0x7a 0x0f>; + dma-names = "tx\0rx"; + pinctrl-names = "default"; + pinctrl-0 = <0x164 0x165 0x166>; + num-cs = <0x02>; + status = "disabled"; + phandle = <0x2da>; + }; + + spi@feb10000 { + compatible = "rockchip,rk3066-spi"; + reg = <0x00 0xfeb10000 0x00 0x1000>; + interrupts = <0x00 0x147 0x04>; + #address-cells = <0x01>; + #size-cells = <0x00>; + clocks = <0x02 0xa4 0x02 0x9f>; + clock-names = "spiclk\0apb_pclk"; + dmas = <0x7a 0x10 0x7a 0x11>; + dma-names = "tx\0rx"; + pinctrl-names = "default"; + pinctrl-0 = <0x167 0x168 0x169>; + num-cs = <0x02>; + status = "disabled"; + phandle = <0x2db>; + }; + + spi@feb20000 { + compatible = "rockchip,rk3066-spi"; + reg = <0x00 0xfeb20000 0x00 0x1000>; + interrupts = <0x00 0x148 0x04>; + #address-cells = <0x01>; + #size-cells = <0x00>; + clocks = <0x02 0xa5 0x02 0xa0>; + clock-names = "spiclk\0apb_pclk"; + dmas = <0xf4 0x0f 0xf4 0x10>; + dma-names = "tx\0rx"; + pinctrl-names = "default"; + pinctrl-0 = <0x16a 0x16b>; + num-cs = <0x01>; + status = "okay"; + assigned-clocks = <0x02 0xa5>; + assigned-clock-rates = <0xbebc200>; + phandle = <0x2dc>; + + rk806single@0 { + compatible = "rockchip,rk806"; + spi-max-frequency = <0xf4240>; + reg = <0x00>; + interrupt-parent = <0xfa>; + interrupts = <0x07 0x08>; + pinctrl-names = "default\0pmic-power-off"; + pinctrl-0 = <0x16c 0x16d 0x16e 0x16f>; + pinctrl-1 = <0x170>; + low_voltage_threshold = <0xbb8>; + shutdown_voltage_threshold = <0xa8c>; + shutdown_temperture_threshold = <0xa0>; + hotdie_temperture_threshold = <0x73>; + pmic-reset-func = <0x01>; + vcc1-supply = <0x79>; + vcc2-supply = <0x79>; + vcc3-supply = <0x79>; + vcc4-supply = <0x79>; + vcc5-supply = <0x79>; + vcc6-supply = <0x79>; + vcc7-supply = <0x79>; + vcc8-supply = <0x79>; + vcc9-supply = <0x79>; + vcc10-supply = <0x79>; + vcc11-supply = <0x171>; + vcc12-supply = <0x79>; + vcc13-supply = <0x172>; + vcc14-supply = <0x172>; + vcca-supply = <0x79>; + phandle = <0x2dd>; + + pwrkey { + status = "okay"; + }; + + pinctrl_rk806 { + gpio-controller; + #gpio-cells = <0x02>; + phandle = <0x2de>; + + rk806_dvs1_null { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + phandle = <0x16d>; + }; + + rk806_dvs1_slp { + pins = "gpio_pwrctrl1"; + function = "pin_fun1"; + phandle = <0x2df>; + }; + + rk806_dvs1_pwrdn { + pins = "gpio_pwrctrl1"; + function = "pin_fun2"; + phandle = <0x170>; + }; + + rk806_dvs1_rst { + pins = "gpio_pwrctrl1"; + function = "pin_fun3"; + phandle = <0x2e0>; + }; + + rk806_dvs2_null { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + phandle = <0x16e>; + }; + + rk806_dvs2_slp { + pins = "gpio_pwrctrl2"; + function = "pin_fun1"; + phandle = <0x2e1>; + }; + + rk806_dvs2_pwrdn { + pins = "gpio_pwrctrl2"; + function = "pin_fun2"; + phandle = <0x2e2>; + }; + + rk806_dvs2_rst { + pins = "gpio_pwrctrl2"; + function = "pin_fun3"; + phandle = <0x2e3>; + }; + + rk806_dvs2_dvs { + pins = "gpio_pwrctrl2"; + function = "pin_fun4"; + phandle = <0x2e4>; + }; + + rk806_dvs2_gpio { + pins = "gpio_pwrctrl2"; + function = "pin_fun5"; + phandle = <0x2e5>; + }; + + rk806_dvs3_null { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + phandle = <0x16f>; + }; + + rk806_dvs3_slp { + pins = "gpio_pwrctrl3"; + function = "pin_fun1"; + phandle = <0x2e6>; + }; + + rk806_dvs3_pwrdn { + pins = "gpio_pwrctrl3"; + function = "pin_fun2"; + phandle = <0x2e7>; + }; + + rk806_dvs3_rst { + pins = "gpio_pwrctrl3"; + function = "pin_fun3"; + phandle = <0x2e8>; + }; + + rk806_dvs3_dvs { + pins = "gpio_pwrctrl3"; + function = "pin_fun4"; + phandle = <0x2e9>; + }; + + rk806_dvs3_gpio { + pins = "gpio_pwrctrl3"; + function = "pin_fun5"; + phandle = <0x2ea>; + }; + }; + + regulators { + + DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x86470>; + regulator-max-microvolt = <0xe7ef0>; + regulator-ramp-delay = <0x30d4>; + regulator-name = "vdd_gpu_s0"; + regulator-enable-ramp-delay = <0x190>; + phandle = <0x63>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-init-microvolt = "\0\f5"; + regulator-min-microvolt = <0x86470>; + regulator-max-microvolt = <0xe7ef0>; + regulator-ramp-delay = <0x30d4>; + regulator-name = "vdd_cpu_lit_s0"; + phandle = <0x13>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0xa4cb8>; + regulator-max-microvolt = "\0\f5"; + regulator-ramp-delay = <0x30d4>; + regulator-name = "vdd_log_s0"; + phandle = <0x44>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <0xb71b0>; + }; + }; + + DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x86470>; + regulator-max-microvolt = <0xe7ef0>; + regulator-init-microvolt = <0xb71b0>; + regulator-ramp-delay = <0x30d4>; + regulator-name = "vdd_vdenc_s0"; + phandle = <0xc5>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + DCDC_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0xa4cb8>; + regulator-max-microvolt = <0xdbba0>; + regulator-ramp-delay = <0x30d4>; + regulator-name = "vdd_ddr_s0"; + phandle = <0x43>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <0xcf850>; + }; + }; + + DCDC_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd2_ddr_s3"; + phandle = <0x2eb>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + DCDC_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x1e8480>; + regulator-max-microvolt = <0x1e8480>; + regulator-name = "vdd_2v0_pldo_s3"; + phandle = <0x171>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <0x1e8480>; + }; + }; + + DCDC_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x325aa0>; + regulator-max-microvolt = <0x325aa0>; + regulator-name = "vcc_3v3_s3"; + phandle = <0x2ec>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <0x325aa0>; + }; + }; + + DCDC_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vddq_ddr_s0"; + phandle = <0x2ed>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + DCDC_REG10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x1b7740>; + regulator-max-microvolt = <0x1b7740>; + regulator-name = "vcc_1v8_s3"; + phandle = <0x2ee>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <0x1b7740>; + }; + }; + + PLDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x1b7740>; + regulator-max-microvolt = <0x1b7740>; + regulator-name = "avcc_1v8_s0"; + phandle = <0x1f7>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + PLDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x1b7740>; + regulator-max-microvolt = <0x1b7740>; + regulator-name = "vcc_1v8_s0"; + phandle = <0x18e>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <0x1b7740>; + }; + }; + + PLDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x124f80>; + regulator-max-microvolt = <0x124f80>; + regulator-name = "avdd_1v2_s0"; + phandle = <0x2ef>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + PLDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x325aa0>; + regulator-max-microvolt = <0x325aa0>; + regulator-name = "vcc_3v3_s0"; + phandle = <0x2f0>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + PLDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x1b7740>; + regulator-max-microvolt = <0x325aa0>; + regulator-name = "vccio_sd_s0"; + phandle = <0x124>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + PLDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x1b7740>; + regulator-max-microvolt = <0x1b7740>; + regulator-name = "pldo6_s3"; + phandle = <0x2f1>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <0x1b7740>; + }; + }; + + NLDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0xb71b0>; + regulator-max-microvolt = <0xb71b0>; + regulator-name = "vdd_0v75_s3"; + phandle = <0x2f2>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <0xb71b0>; + }; + }; + + NLDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0xcf850>; + regulator-max-microvolt = <0xcf850>; + regulator-name = "vdd_ddr_pll_s0"; + phandle = <0x2f3>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <0xcf850>; + }; + }; + + NLDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0xcc77c>; + regulator-max-microvolt = <0xcc77c>; + regulator-name = "avdd_0v75_s0"; + phandle = <0x1f8>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + NLDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0xcf850>; + regulator-max-microvolt = <0xcf850>; + regulator-name = "vdd_0v85_s0"; + phandle = <0x1f6>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + NLDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0xb71b0>; + regulator-max-microvolt = <0xb71b0>; + regulator-name = "vdd_0v75_s0"; + phandle = <0x2f4>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + }; + + spi@feb30000 { + compatible = "rockchip,rk3066-spi"; + reg = <0x00 0xfeb30000 0x00 0x1000>; + interrupts = <0x00 0x149 0x04>; + #address-cells = <0x01>; + #size-cells = <0x00>; + clocks = <0x02 0xa6 0x02 0xa1>; + clock-names = "spiclk\0apb_pclk"; + dmas = <0xf4 0x11 0xf4 0x12>; + dma-names = "tx\0rx"; + pinctrl-names = "default"; + pinctrl-0 = <0x173 0x174 0x175>; + num-cs = <0x02>; + status = "disabled"; + phandle = <0x2f5>; + }; + + serial@feb40000 { + compatible = "rockchip,rk3588-uart\0snps,dw-apb-uart"; + reg = <0x00 0xfeb40000 0x00 0x100>; + interrupts = <0x00 0x14c 0x04>; + clocks = <0x02 0xb7 0x02 0xab>; + clock-names = "baudclk\0apb_pclk"; + reg-shift = <0x02>; + reg-io-width = <0x04>; + dmas = <0x7a 0x08 0x7a 0x09>; + pinctrl-names = "default"; + pinctrl-0 = <0x176>; + status = "disabled"; + phandle = <0x2f6>; + }; + + serial@feb50000 { + compatible = "rockchip,rk3588-uart\0snps,dw-apb-uart"; + reg = <0x00 0xfeb50000 0x00 0x100>; + interrupts = <0x00 0x14d 0x04>; + clocks = <0x02 0xbb 0x02 0xac>; + clock-names = "baudclk\0apb_pclk"; + reg-shift = <0x02>; + reg-io-width = <0x04>; + dmas = <0x7a 0x0a 0x7a 0x0b>; + pinctrl-names = "default"; + pinctrl-0 = <0x177>; + status = "disabled"; + phandle = <0x2f7>; + }; + + serial@feb60000 { + compatible = "rockchip,rk3588-uart\0snps,dw-apb-uart"; + reg = <0x00 0xfeb60000 0x00 0x100>; + interrupts = <0x00 0x14e 0x04>; + clocks = <0x02 0xbf 0x02 0xad>; + clock-names = "baudclk\0apb_pclk"; + reg-shift = <0x02>; + reg-io-width = <0x04>; + dmas = <0x7a 0x0c 0x7a 0x0d>; + pinctrl-names = "default"; + pinctrl-0 = <0x178>; + status = "disabled"; + phandle = <0x2f8>; + }; + + serial@feb70000 { + compatible = "rockchip,rk3588-uart\0snps,dw-apb-uart"; + reg = <0x00 0xfeb70000 0x00 0x100>; + interrupts = <0x00 0x14f 0x04>; + clocks = <0x02 0xc3 0x02 0xae>; + clock-names = "baudclk\0apb_pclk"; + reg-shift = <0x02>; + reg-io-width = <0x04>; + dmas = <0xf4 0x09 0xf4 0x0a>; + pinctrl-names = "default"; + pinctrl-0 = <0x179>; + status = "disabled"; + phandle = <0x2f9>; + }; + + serial@feb80000 { + compatible = "rockchip,rk3588-uart\0snps,dw-apb-uart"; + reg = <0x00 0xfeb80000 0x00 0x100>; + interrupts = <0x00 0x150 0x04>; + clocks = <0x02 0xc7 0x02 0xaf>; + clock-names = "baudclk\0apb_pclk"; + reg-shift = <0x02>; + reg-io-width = <0x04>; + dmas = <0xf4 0x0b 0xf4 0x0c>; + pinctrl-names = "default"; + pinctrl-0 = <0x17a>; + status = "disabled"; + phandle = <0x2fa>; + }; + + serial@feb90000 { + compatible = "rockchip,rk3588-uart\0snps,dw-apb-uart"; + reg = <0x00 0xfeb90000 0x00 0x100>; + interrupts = <0x00 0x151 0x04>; + clocks = <0x02 0xcb 0x02 0xb0>; + clock-names = "baudclk\0apb_pclk"; + reg-shift = <0x02>; + reg-io-width = <0x04>; + dmas = <0xf4 0x0d 0xf4 0x0e>; + pinctrl-names = "default"; + pinctrl-0 = <0x17b>; + status = "disabled"; + phandle = <0x2fb>; + }; + + serial@feba0000 { + compatible = "rockchip,rk3588-uart\0snps,dw-apb-uart"; + reg = <0x00 0xfeba0000 0x00 0x100>; + interrupts = <0x00 0x152 0x04>; + clocks = <0x02 0xcf 0x02 0xb1>; + clock-names = "baudclk\0apb_pclk"; + reg-shift = <0x02>; + reg-io-width = <0x04>; + dmas = <0xf5 0x07 0xf5 0x08>; + pinctrl-names = "default"; + pinctrl-0 = <0x17c>; + status = "disabled"; + phandle = <0x2fc>; + }; + + serial@febb0000 { + compatible = "rockchip,rk3588-uart\0snps,dw-apb-uart"; + reg = <0x00 0xfebb0000 0x00 0x100>; + interrupts = <0x00 0x153 0x04>; + clocks = <0x02 0xd3 0x02 0xb2>; + clock-names = "baudclk\0apb_pclk"; + reg-shift = <0x02>; + reg-io-width = <0x04>; + dmas = <0xf5 0x09 0xf5 0x0a>; + pinctrl-names = "default"; + pinctrl-0 = <0x17d>; + status = "disabled"; + phandle = <0x2fd>; + }; + + serial@febc0000 { + compatible = "rockchip,rk3588-uart\0snps,dw-apb-uart"; + reg = <0x00 0xfebc0000 0x00 0x100>; + interrupts = <0x00 0x154 0x04>; + clocks = <0x02 0xd7 0x02 0xb3>; + clock-names = "baudclk\0apb_pclk"; + reg-shift = <0x02>; + reg-io-width = <0x04>; + dmas = <0xf5 0x0b 0xf5 0x0c>; + pinctrl-names = "default"; + pinctrl-0 = <0x17e 0x17f>; + status = "okay"; + phandle = <0x2fe>; + }; + + pwm@febd0000 { + compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm"; + reg = <0x00 0xfebd0000 0x00 0x10>; + interrupts = <0x00 0x15a 0x04>; + #pwm-cells = <0x03>; + pinctrl-names = "active"; + pinctrl-0 = <0x180>; + clocks = <0x02 0x54 0x02 0x53>; + clock-names = "pwm\0pclk"; + status = "disabled"; + phandle = <0x2ff>; + }; + + pwm@febd0010 { + compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm"; + reg = <0x00 0xfebd0010 0x00 0x10>; + interrupts = <0x00 0x15a 0x04>; + #pwm-cells = <0x03>; + pinctrl-names = "active"; + pinctrl-0 = <0x181>; + clocks = <0x02 0x54 0x02 0x53>; + clock-names = "pwm\0pclk"; + status = "disabled"; + phandle = <0x300>; + }; + + pwm@febd0020 { + compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm"; + reg = <0x00 0xfebd0020 0x00 0x10>; + interrupts = <0x00 0x15a 0x04>; + #pwm-cells = <0x03>; + pinctrl-names = "active"; + pinctrl-0 = <0x182>; + clocks = <0x02 0x54 0x02 0x53>; + clock-names = "pwm\0pclk"; + status = "disabled"; + phandle = <0x301>; + }; + + pwm@febd0030 { + compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm"; + reg = <0x00 0xfebd0030 0x00 0x10>; + interrupts = <0x00 0x15a 0x04 0x00 0x15b 0x04>; + #pwm-cells = <0x03>; + pinctrl-names = "active"; + pinctrl-0 = <0x183>; + clocks = <0x02 0x54 0x02 0x53>; + clock-names = "pwm\0pclk"; + status = "disabled"; + phandle = <0x302>; + }; + + pwm@febe0000 { + compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm"; + reg = <0x00 0xfebe0000 0x00 0x10>; + interrupts = <0x00 0x15c 0x04>; + #pwm-cells = <0x03>; + pinctrl-names = "active"; + pinctrl-0 = <0x184>; + clocks = <0x02 0x57 0x02 0x56>; + clock-names = "pwm\0pclk"; + status = "disabled"; + phandle = <0x303>; + }; + + pwm@febe0010 { + compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm"; + reg = <0x00 0xfebe0010 0x00 0x10>; + interrupts = <0x00 0x15c 0x04>; + #pwm-cells = <0x03>; + pinctrl-names = "active"; + pinctrl-0 = <0x185>; + clocks = <0x02 0x57 0x02 0x56>; + clock-names = "pwm\0pclk"; + status = "disabled"; + phandle = <0x304>; + }; + + pwm@febe0020 { + compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm"; + reg = <0x00 0xfebe0020 0x00 0x10>; + interrupts = <0x00 0x15c 0x04>; + #pwm-cells = <0x03>; + pinctrl-names = "active"; + pinctrl-0 = <0x186>; + clocks = <0x02 0x57 0x02 0x56>; + clock-names = "pwm\0pclk"; + status = "disabled"; + phandle = <0x305>; + }; + + pwm@febe0030 { + compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm"; + reg = <0x00 0xfebe0030 0x00 0x10>; + interrupts = <0x00 0x15c 0x04 0x00 0x15d 0x04>; + #pwm-cells = <0x03>; + pinctrl-names = "active"; + pinctrl-0 = <0x187>; + clocks = <0x02 0x57 0x02 0x56>; + clock-names = "pwm\0pclk"; + status = "disabled"; + phandle = <0x306>; + }; + + pwm@febf0000 { + compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm"; + reg = <0x00 0xfebf0000 0x00 0x10>; + interrupts = <0x00 0x15e 0x04>; + #pwm-cells = <0x03>; + pinctrl-names = "active"; + pinctrl-0 = <0x188>; + clocks = <0x02 0x5a 0x02 0x59>; + clock-names = "pwm\0pclk"; + status = "disabled"; + phandle = <0x307>; + }; + + pwm@febf0010 { + compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm"; + reg = <0x00 0xfebf0010 0x00 0x10>; + interrupts = <0x00 0x15e 0x04>; + #pwm-cells = <0x03>; + pinctrl-names = "active"; + pinctrl-0 = <0x189>; + clocks = <0x02 0x5a 0x02 0x59>; + clock-names = "pwm\0pclk"; + status = "disabled"; + phandle = <0x308>; + }; + + pwm@febf0020 { + compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm"; + reg = <0x00 0xfebf0020 0x00 0x10>; + interrupts = <0x00 0x15e 0x04>; + #pwm-cells = <0x03>; + pinctrl-names = "active"; + pinctrl-0 = <0x18a>; + clocks = <0x02 0x5a 0x02 0x59>; + clock-names = "pwm\0pclk"; + status = "disabled"; + phandle = <0x309>; + }; + + pwm@febf0030 { + compatible = "rockchip,rk3588-pwm\0rockchip,rk3328-pwm"; + reg = <0x00 0xfebf0030 0x00 0x10>; + interrupts = <0x00 0x15e 0x04 0x00 0x15f 0x04>; + #pwm-cells = <0x03>; + pinctrl-names = "active"; + pinctrl-0 = <0x18b>; + clocks = <0x02 0x5a 0x02 0x59>; + clock-names = "pwm\0pclk"; + status = "disabled"; + phandle = <0x30a>; + }; + + tsadc@fec00000 { + compatible = "rockchip,rk3588-tsadc"; + reg = <0x00 0xfec00000 0x00 0x400>; + interrupts = <0x00 0x18d 0x04>; + clocks = <0x02 0xaa 0x02 0xa9>; + clock-names = "tsadc\0apb_pclk"; + assigned-clocks = <0x02 0xaa>; + assigned-clock-rates = <0x1e8480>; + resets = <0x02 0xc1 0x02 0xc0>; + reset-names = "tsadc\0tsadc-apb"; + #thermal-sensor-cells = <0x01>; + rockchip,hw-tshut-temp = <0x1d4c0>; + rockchip,hw-tshut-mode = <0x00>; + rockchip,hw-tshut-polarity = <0x00>; + pinctrl-names = "gpio\0otpout"; + pinctrl-0 = <0x18c>; + pinctrl-1 = <0x18d>; + status = "okay"; + phandle = <0x5f>; + }; + + saradc@fec10000 { + compatible = "rockchip,rk3588-saradc"; + reg = <0x00 0xfec10000 0x00 0x10000>; + interrupts = <0x00 0x18e 0x04>; + #io-channel-cells = <0x01>; + clocks = <0x02 0x9d 0x02 0x9c>; + clock-names = "saradc\0apb_pclk"; + resets = <0x02 0xbe>; + reset-names = "saradc-apb"; + status = "okay"; + vref-supply = <0x18e>; + phandle = <0x1db>; + }; + + mailbox@fec60000 { + compatible = "rockchip,rk3588-mailbox\0rockchip,rk3368-mailbox"; + reg = <0x00 0xfec60000 0x00 0x200>; + interrupts = <0x00 0x3d 0x04 0x00 0x3e 0x04 0x00 0x3f 0x04 0x00 0x40 0x04>; + clocks = <0x02 0x4c>; + clock-names = "pclk_mailbox"; + #mbox-cells = <0x01>; + status = "disabled"; + phandle = <0x30b>; + }; + + mailbox@fec70000 { + compatible = "rockchip,rk3588-mailbox\0rockchip,rk3368-mailbox"; + reg = <0x00 0xfec70000 0x00 0x200>; + interrupts = <0x00 0x45 0x04 0x00 0x46 0x04 0x00 0x47 0x04 0x00 0x48 0x04>; + clocks = <0x02 0x4d>; + clock-names = "pclk_mailbox"; + #mbox-cells = <0x01>; + status = "disabled"; + phandle = <0x30c>; + }; + + i2c@fec80000 { + compatible = "rockchip,rk3588-i2c\0rockchip,rk3399-i2c"; + reg = <0x00 0xfec80000 0x00 0x1000>; + clocks = <0x02 0x92 0x02 0x8a>; + clock-names = "i2c\0pclk"; + interrupts = <0x00 0x143 0x04>; + pinctrl-names = "default"; + pinctrl-0 = <0x18f>; + resets = <0x02 0xb5 0x02 0xad>; + reset-names = "i2c\0apb"; + #address-cells = <0x01>; + #size-cells = <0x00>; + status = "okay"; + phandle = <0x30d>; + + husb311@4e { + compatible = "hynetek,husb311"; + reg = <0x4e>; + interrupt-parent = <0x119>; + interrupts = <0x0e 0x08>; + pinctrl-names = "default"; + pinctrl-0 = <0x190>; + vbus-supply = <0x191>; + status = "okay"; + phandle = <0x30e>; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint@0 { + remote-endpoint = <0x192>; + phandle = <0x69>; + }; + }; + }; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + op-sink-microwatt = <0xf4240>; + sink-pdos = <0x4019064>; + source-pdos = <0x401912c>; + phandle = <0x30f>; + + altmodes { + #address-cells = <0x01>; + #size-cells = <0x00>; + + altmode@0 { + reg = <0x00>; + svid = <0xff01>; + vdo = <0xffffffff>; + }; + }; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint { + remote-endpoint = <0x193>; + phandle = <0x1a1>; + }; + }; + + port@1 { + reg = <0x01>; + + endpoint { + remote-endpoint = <0x194>; + phandle = <0x1a2>; + }; + }; + }; + }; + }; + + hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0x00>; + clock-frequency = <0x8000>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <0x195>; + interrupt-parent = <0xfa>; + interrupts = <0x08 0x08>; + wakeup-source; + phandle = <0x1f9>; + }; + }; + + i2c@fec90000 { + compatible = "rockchip,rk3588-i2c\0rockchip,rk3399-i2c"; + reg = <0x00 0xfec90000 0x00 0x1000>; + clocks = <0x02 0x93 0x02 0x8b>; + clock-names = "i2c\0pclk"; + interrupts = <0x00 0x144 0x04>; + pinctrl-names = "default"; + pinctrl-0 = <0x196>; + resets = <0x02 0xb6 0x02 0xae>; + reset-names = "i2c\0apb"; + #address-cells = <0x01>; + #size-cells = <0x00>; + status = "okay"; + phandle = <0x310>; + + es8388@11 { + status = "okay"; + #sound-dai-cells = <0x00>; + compatible = "everest,es8388\0everest,es8323"; + reg = <0x11>; + clocks = <0x197>; + clock-names = "mclk"; + assigned-clocks = <0x197>; + assigned-clock-rates = <0xbb8000>; + pinctrl-names = "default"; + pinctrl-0 = <0x198>; + phandle = <0x1f1>; + }; + }; + + i2c@feca0000 { + compatible = "rockchip,rk3588-i2c\0rockchip,rk3399-i2c"; + reg = <0x00 0xfeca0000 0x00 0x1000>; + clocks = <0x02 0x94 0x02 0x8c>; + clock-names = "i2c\0pclk"; + interrupts = <0x00 0x145 0x04>; + pinctrl-names = "default"; + pinctrl-0 = <0x199>; + resets = <0x02 0xb7 0x02 0xaf>; + reset-names = "i2c\0apb"; + #address-cells = <0x01>; + #size-cells = <0x00>; + status = "disabled"; + phandle = <0x311>; + }; + + spi@fecb0000 { + compatible = "rockchip,rk3066-spi"; + reg = <0x00 0xfecb0000 0x00 0x1000>; + interrupts = <0x00 0x14a 0x04>; + #address-cells = <0x01>; + #size-cells = <0x00>; + clocks = <0x02 0xa7 0x02 0xa2>; + clock-names = "spiclk\0apb_pclk"; + dmas = <0xf5 0x0d 0xf5 0x0e>; + dma-names = "tx\0rx"; + pinctrl-names = "default"; + pinctrl-0 = <0x19a 0x19b 0x19c>; + num-cs = <0x02>; + status = "disabled"; + phandle = <0x312>; + }; + + otp@fecc0000 { + compatible = "rockchip,rk3588-otp"; + reg = <0x00 0xfecc0000 0x00 0x400>; + #address-cells = <0x01>; + #size-cells = <0x01>; + clocks = <0x02 0x96 0x02 0x95 0x02 0x99>; + clock-names = "otpc\0apb\0phy"; + resets = <0x02 0x12a 0x02 0x129 0x02 0x12b>; + reset-names = "otpc\0apb\0arb"; + phandle = <0x313>; + + cpu-code@2 { + reg = <0x02 0x02>; + phandle = <0x2e>; + }; + + package-serial-number-high@5 { + reg = <0x05 0x01>; + bits = <0x00 0x01>; + phandle = <0xd7>; + }; + + package-serial-number-low@6 { + reg = <0x06 0x01>; + bits = <0x05 0x03>; + phandle = <0xd6>; + }; + + specification-serial-number@6 { + reg = <0x06 0x01>; + bits = <0x00 0x05>; + phandle = <0x22>; + }; + + id@7 { + reg = <0x07 0x10>; + phandle = <0x2c>; + }; + + cpu-version@1c { + reg = <0x1c 0x01>; + bits = <0x03 0x03>; + phandle = <0x2d>; + }; + + cpub0-leakage@17 { + reg = <0x17 0x01>; + phandle = <0x26>; + }; + + cpub1-leakage@18 { + reg = <0x18 0x01>; + phandle = <0x29>; + }; + + cpul-leakage@19 { + reg = <0x19 0x01>; + phandle = <0x20>; + }; + + log-leakage@1a { + reg = <0x1a 0x01>; + phandle = <0x45>; + }; + + gpu-leakage@1b { + reg = <0x1b 0x01>; + phandle = <0x64>; + }; + + customer-demand@22 { + reg = <0x22 0x01>; + bits = <0x04 0x04>; + phandle = <0x23>; + }; + + npu-leakage@28 { + reg = <0x28 0x01>; + phandle = <0xb4>; + }; + + codec-leakage@29 { + reg = <0x29 0x01>; + phandle = <0xc7>; + }; + + cpul-opp-info@3d { + reg = <0x3d 0x06>; + phandle = <0x21>; + }; + + cpub01-opp-info@43 { + reg = <0x43 0x06>; + phandle = <0x27>; + }; + + cpub23-opp-info@49 { + reg = <0x49 0x06>; + phandle = <0x2a>; + }; + + gpu-opp-info@4f { + reg = <0x4f 0x06>; + phandle = <0x65>; + }; + + npu-opp-info@55 { + reg = <0x55 0x06>; + phandle = <0xb5>; + }; + + dmc-opp-info@5b { + reg = <0x5b 0x06>; + phandle = <0x46>; + }; + + vop-opp-info@61 { + reg = <0x61 0x06>; + phandle = <0x314>; + }; + + venc-opp-info@67 { + reg = <0x67 0x06>; + phandle = <0xc8>; + }; + }; + + mailbox@fece0000 { + compatible = "rockchip,rk3588-mailbox\0rockchip,rk3368-mailbox"; + reg = <0x00 0xfece0000 0x00 0x200>; + interrupts = <0x00 0x4d 0x04 0x00 0x4e 0x04 0x00 0x4f 0x04 0x00 0x50 0x04>; + clocks = <0x02 0x4e>; + clock-names = "pclk_mailbox"; + #mbox-cells = <0x01>; + status = "disabled"; + phandle = <0x315>; + }; + + dma-controller@fed10000 { + compatible = "arm,pl330\0arm,primecell"; + reg = <0x00 0xfed10000 0x00 0x4000>; + interrupts = <0x00 0x5a 0x04 0x00 0x5b 0x04>; + clocks = <0x02 0x7a>; + clock-names = "apb_pclk"; + #dma-cells = <0x01>; + arm,pl330-periph-burst; + phandle = <0xf5>; + }; + + phy@fed60000 { + compatible = "rockchip,rk3588-hdptx-phy"; + reg = <0x00 0xfed60000 0x00 0x2000>; + clocks = <0x02 0x2b5 0x02 0x267>; + clock-names = "ref\0apb"; + resets = <0x02 0x485 0x02 0xc003b 0x02 0xc003c 0x02 0xc003d>; + reset-names = "apb\0init\0cmn\0lane"; + rockchip,grf = <0x19d>; + #phy-cells = <0x00>; + status = "disabled"; + phandle = <0x10d>; + }; + + hdmiphy@fed60000 { + compatible = "rockchip,rk3588-hdptx-phy-hdmi"; + reg = <0x00 0xfed60000 0x00 0x2000>; + clocks = <0x02 0x2b5 0x02 0x267>; + clock-names = "ref\0apb"; + clock-output-names = "clk_hdmiphy_pixel0"; + #clock-cells = <0x00>; + resets = <0x02 0x48e 0x02 0x485 0x02 0xc003b 0x02 0xc003c 0x02 0xc003d 0x02 0x48c 0x02 0x48d>; + reset-names = "phy\0apb\0init\0cmn\0lane\0ropll\0lcpll"; + rockchip,grf = <0x19d>; + #phy-cells = <0x00>; + /* + * Keep DISABLED: the phy is passed through to zone2 (fed60000), + * whose phy driver probes it and registers clk_hdmiphy_pixel0 + * locally. If this node were enabled, root's phy driver would + * hold these 7 resets EXCLUSIVELY and zone2's SCMI reset requests + * for the same lines would fail (reset core WARN -EBUSY). + */ + status = "disabled"; + phandle = <0x36>; + }; + + phy@fed80000 { + compatible = "rockchip,rk3588-usbdp-phy"; + reg = <0x00 0xfed80000 0x00 0x10000>; + rockchip,u2phy-grf = <0x19e>; + rockchip,usb-grf = <0x75>; + rockchip,usbdpphy-grf = <0x19f>; + rockchip,vo-grf = <0x102>; + clocks = <0x02 0x2b6 0x02 0x27f 0x02 0x269 0x1a0>; + clock-names = "refclk\0immortal\0pclk\0utmi"; + resets = <0x02 0x28 0x02 0x29 0x02 0x2a 0x02 0x2b 0x02 0x482>; + reset-names = "init\0cmn\0lane\0pcs_apb\0pma_apb"; + status = "okay"; + orientation-switch; + svid = <0xff01>; + sbu1-dc-gpios = <0x10a 0x00 0x00>; + sbu2-dc-gpios = <0x10a 0x01 0x00>; + phandle = <0x316>; + + dp-port { + #phy-cells = <0x00>; + status = "okay"; + phandle = <0x103>; + }; + + u3-port { + #phy-cells = <0x00>; + status = "okay"; + phandle = <0x68>; + }; + + port { + #address-cells = <0x01>; + #size-cells = <0x00>; + + endpoint@0 { + reg = <0x00>; + remote-endpoint = <0x1a1>; + phandle = <0x193>; + }; + + endpoint@1 { + reg = <0x01>; + remote-endpoint = <0x1a2>; + phandle = <0x194>; + }; + }; + }; + + phy@feda0000 { + compatible = "rockchip,rk3588-mipi-dcphy"; + reg = <0x00 0xfeda0000 0x00 0x10000>; + rockchip,grf = <0x1a3>; + clocks = <0x02 0x108 0x02 0x2b6>; + clock-names = "pclk\0ref"; + resets = <0x02 0xc0043 0x02 0x3e 0x02 0x3f 0x02 0xc0044>; + reset-names = "m_phy\0apb\0grf\0s_phy"; + #phy-cells = <0x00>; + status = "okay"; + phandle = <0x31>; + }; + + phy@fedb0000 { + compatible = "rockchip,rk3588-mipi-dcphy"; + reg = <0x00 0xfedb0000 0x00 0x10000>; + rockchip,grf = <0x1a4>; + clocks = <0x02 0x109 0x02 0x2b6>; + clock-names = "pclk\0ref"; + resets = <0x02 0xc0045 0x02 0x43 0x02 0x44 0x02 0xc0046>; + reset-names = "m_phy\0apb\0grf\0s_phy"; + #phy-cells = <0x00>; + status = "okay"; + phandle = <0x32>; + }; + + csi2-dphy0-hw@fedc0000 { + compatible = "rockchip,rk3588-csi2-dphy-hw"; + reg = <0x00 0xfedc0000 0x00 0x8000>; + clocks = <0x02 0x10c>; + clock-names = "pclk"; + resets = <0x02 0x17 0x02 0x16>; + reset-names = "srst_csiphy0\0srst_p_csiphy0"; + rockchip,grf = <0x1a5>; + rockchip,sys_grf = <0xc9>; + status = "okay"; + phandle = <0x2f>; + }; + + csi2-dphy1-hw@fedc8000 { + compatible = "rockchip,rk3588-csi2-dphy-hw"; + reg = <0x00 0xfedc8000 0x00 0x8000>; + clocks = <0x02 0x10d>; + clock-names = "pclk"; + resets = <0x02 0x19 0x02 0x18>; + reset-names = "srst_csiphy1\0srst_p_csiphy1"; + rockchip,grf = <0x1a6>; + rockchip,sys_grf = <0xc9>; + status = "okay"; + phandle = <0x30>; + }; + + phy@fee00000 { + compatible = "rockchip,rk3588-naneng-combphy"; + reg = <0x00 0xfee00000 0x00 0x100>; + #phy-cells = <0x01>; + clocks = <0x02 0x2bd 0x02 0x185 0x02 0x166>; + clock-names = "refclk\0apbclk\0phpclk"; + assigned-clocks = <0x02 0x2bd>; + assigned-clock-rates = <0x5f5e100>; + resets = <0x02 0x20005 0x02 0x4d6>; + reset-names = "combphy-apb\0combphy"; + rockchip,pipe-grf = <0x77>; + rockchip,pipe-phy-grf = <0x1a7>; + status = "okay"; + phandle = <0x114>; + }; + + phy@fee20000 { + compatible = "rockchip,rk3588-naneng-combphy"; + reg = <0x00 0xfee20000 0x00 0x100>; + #phy-cells = <0x01>; + clocks = <0x02 0x2bf 0x02 0x187 0x02 0x166>; + clock-names = "refclk\0apbclk\0phpclk"; + assigned-clocks = <0x02 0x2bf>; + assigned-clock-rates = <0x5f5e100>; + resets = <0x02 0x20007 0x02 0x4d8>; + reset-names = "combphy-apb\0combphy"; + rockchip,pipe-grf = <0x77>; + rockchip,pipe-phy-grf = <0x1a8>; + rockchip,pcie1ln-sel-bits = <0x100 0x01 0x01 0x00>; + status = "okay"; + phandle = <0x71>; + }; + + sram@ff001000 { + compatible = "mmio-sram"; + reg = <0x00 0xff001000 0x00 0xef000>; + #address-cells = <0x01>; + #size-cells = <0x01>; + ranges = <0x00 0x00 0xff001000 0xef000>; + phandle = <0x317>; + + rkvdec-sram@0 { + reg = <0x00 0x78000>; + phandle = <0xcc>; + }; + + rkvdec-sram@78000 { + reg = <0x78000 0x77000>; + phandle = <0xce>; + }; + }; + + pinctrl { + compatible = "rockchip,rk3588-pinctrl"; + rockchip,grf = <0x1a9>; + #address-cells = <0x02>; + #size-cells = <0x02>; + ranges; + phandle = <0x1aa>; + + gpio@fd8a0000 { + compatible = "rockchip,gpio-bank"; + reg = <0x00 0xfd8a0000 0x00 0x100>; + interrupts = <0x00 0x115 0x04>; + clocks = <0x02 0x284 0x02 0x285>; + gpio-controller; + #gpio-cells = <0x02>; + gpio-ranges = <0x1aa 0x00 0x00 0x20>; + interrupt-controller; + #interrupt-cells = <0x02>; + phandle = <0xfa>; + }; + + gpio@fec20000 { + compatible = "rockchip,gpio-bank"; + reg = <0x00 0xfec20000 0x00 0x100>; + interrupts = <0x00 0x116 0x04>; + clocks = <0x02 0x7d 0x02 0x7e>; + gpio-controller; + #gpio-cells = <0x02>; + gpio-ranges = <0x1aa 0x00 0x20 0x20>; + interrupt-controller; + #interrupt-cells = <0x02>; + phandle = <0x129>; + }; + + gpio@fec30000 { + compatible = "rockchip,gpio-bank"; + reg = <0x00 0xfec30000 0x00 0x100>; + interrupts = <0x00 0x117 0x04>; + clocks = <0x02 0x7f 0x02 0x80>; + gpio-controller; + #gpio-cells = <0x02>; + gpio-ranges = <0x1aa 0x00 0x40 0x20>; + interrupt-controller; + #interrupt-cells = <0x02>; + phandle = <0x1fd>; + }; + + gpio@fec40000 { + compatible = "rockchip,gpio-bank"; + reg = <0x00 0xfec40000 0x00 0x100>; + interrupts = <0x00 0x118 0x04>; + clocks = <0x02 0x81 0x02 0x82>; + gpio-controller; + #gpio-cells = <0x02>; + gpio-ranges = <0x1aa 0x00 0x60 0x20>; + interrupt-controller; + #interrupt-cells = <0x02>; + phandle = <0x119>; + }; + + gpio@fec50000 { + compatible = "rockchip,gpio-bank"; + reg = <0x00 0xfec50000 0x00 0x100>; + interrupts = <0x00 0x119 0x04>; + clocks = <0x02 0x83 0x02 0x84>; + gpio-controller; + #gpio-cells = <0x02>; + gpio-ranges = <0x1aa 0x00 0x80 0x20>; + interrupt-controller; + #interrupt-cells = <0x02>; + phandle = <0x10a>; + }; + + pcfg-pull-up { + bias-pull-up; + phandle = <0x1b1>; + }; + + pcfg-pull-down { + bias-pull-down; + phandle = <0x1b5>; + }; + + pcfg-pull-none { + bias-disable; + phandle = <0x1ab>; + }; + + pcfg-pull-none-drv-level-0 { + bias-disable; + drive-strength = <0x00>; + phandle = <0x318>; + }; + + pcfg-pull-none-drv-level-1 { + bias-disable; + drive-strength = <0x01>; + phandle = <0x319>; + }; + + pcfg-pull-none-drv-level-2 { + bias-disable; + drive-strength = <0x02>; + phandle = <0x1b4>; + }; + + pcfg-pull-none-drv-level-3 { + bias-disable; + drive-strength = <0x03>; + phandle = <0x31a>; + }; + + pcfg-pull-none-drv-level-4 { + bias-disable; + drive-strength = <0x04>; + phandle = <0x31b>; + }; + + pcfg-pull-none-drv-level-5 { + bias-disable; + drive-strength = <0x05>; + phandle = <0x31c>; + }; + + pcfg-pull-none-drv-level-6 { + bias-disable; + drive-strength = <0x06>; + phandle = <0x31d>; + }; + + pcfg-pull-up-drv-level-0 { + bias-pull-up; + drive-strength = <0x00>; + phandle = <0x31e>; + }; + + pcfg-pull-up-drv-level-1 { + bias-pull-up; + drive-strength = <0x01>; + phandle = <0x1b3>; + }; + + pcfg-pull-up-drv-level-2 { + bias-pull-up; + drive-strength = <0x02>; + phandle = <0x1ac>; + }; + + pcfg-pull-up-drv-level-3 { + bias-pull-up; + drive-strength = <0x03>; + phandle = <0x31f>; + }; + + pcfg-pull-up-drv-level-4 { + bias-pull-up; + drive-strength = <0x04>; + phandle = <0x320>; + }; + + pcfg-pull-up-drv-level-5 { + bias-pull-up; + drive-strength = <0x05>; + phandle = <0x321>; + }; + + pcfg-pull-up-drv-level-6 { + bias-pull-up; + drive-strength = <0x06>; + phandle = <0x1b2>; + }; + + pcfg-pull-down-drv-level-0 { + bias-pull-down; + drive-strength = <0x00>; + phandle = <0x322>; + }; + + pcfg-pull-down-drv-level-1 { + bias-pull-down; + drive-strength = <0x01>; + phandle = <0x323>; + }; + + pcfg-pull-down-drv-level-2 { + bias-pull-down; + drive-strength = <0x02>; + phandle = <0x324>; + }; + + pcfg-pull-down-drv-level-3 { + bias-pull-down; + drive-strength = <0x03>; + phandle = <0x325>; + }; + + pcfg-pull-down-drv-level-4 { + bias-pull-down; + drive-strength = <0x04>; + phandle = <0x326>; + }; + + pcfg-pull-down-drv-level-5 { + bias-pull-down; + drive-strength = <0x05>; + phandle = <0x327>; + }; + + pcfg-pull-down-drv-level-6 { + bias-pull-down; + drive-strength = <0x06>; + phandle = <0x328>; + }; + + pcfg-pull-up-smt { + bias-pull-up; + input-schmitt-enable; + phandle = <0x329>; + }; + + pcfg-pull-down-smt { + bias-pull-down; + input-schmitt-enable; + phandle = <0x32a>; + }; + + pcfg-pull-none-smt { + bias-disable; + input-schmitt-enable; + phandle = <0x1af>; + }; + + pcfg-pull-none-drv-level-0-smt { + bias-disable; + drive-strength = <0x00>; + input-schmitt-enable; + phandle = <0x32b>; + }; + + pcfg-pull-none-drv-level-1-smt { + bias-disable; + drive-strength = <0x01>; + input-schmitt-enable; + phandle = <0x1ae>; + }; + + pcfg-pull-none-drv-level-2-smt { + bias-disable; + drive-strength = <0x02>; + input-schmitt-enable; + phandle = <0x32c>; + }; + + pcfg-pull-none-drv-level-3-smt { + bias-disable; + drive-strength = <0x03>; + input-schmitt-enable; + phandle = <0x1b0>; + }; + + pcfg-pull-none-drv-level-4-smt { + bias-disable; + drive-strength = <0x04>; + input-schmitt-enable; + phandle = <0x32d>; + }; + + pcfg-pull-none-drv-level-5-smt { + bias-disable; + drive-strength = <0x05>; + input-schmitt-enable; + phandle = <0x1ad>; + }; + + pcfg-pull-none-drv-level-6-smt { + bias-disable; + drive-strength = <0x06>; + input-schmitt-enable; + phandle = <0x32e>; + }; + + pcfg-output-high { + output-high; + phandle = <0x32f>; + }; + + pcfg-output-high-pull-up { + output-high; + bias-pull-up; + phandle = <0x330>; + }; + + pcfg-output-high-pull-down { + output-high; + bias-pull-down; + phandle = <0x331>; + }; + + pcfg-output-high-pull-none { + output-high; + bias-disable; + phandle = <0x332>; + }; + + pcfg-output-low { + output-low; + phandle = <0x1b6>; + }; + + pcfg-output-low-pull-up { + output-low; + bias-pull-up; + phandle = <0x333>; + }; + + pcfg-output-low-pull-down { + output-low; + bias-pull-down; + phandle = <0x334>; + }; + + pcfg-output-low-pull-none { + output-low; + bias-disable; + phandle = <0x335>; + }; + + auddsm { + + auddsm-pins { + rockchip,pins = <0x03 0x01 0x04 0x1ab 0x03 0x02 0x04 0x1ab 0x03 0x03 0x04 0x1ab 0x03 0x04 0x04 0x1ab>; + phandle = <0x153>; + }; + }; + + bt1120 { + + bt1120-pins { + rockchip,pins = <0x04 0x08 0x02 0x1ab 0x04 0x00 0x02 0x1ab 0x04 0x01 0x02 0x1ab 0x04 0x02 0x02 0x1ab 0x04 0x03 0x02 0x1ab 0x04 0x04 0x02 0x1ab 0x04 0x05 0x02 0x1ab 0x04 0x06 0x02 0x1ab 0x04 0x07 0x02 0x1ab 0x04 0x0a 0x02 0x1ab 0x04 0x0b 0x02 0x1ab 0x04 0x0c 0x02 0x1ab 0x04 0x0d 0x02 0x1ab 0x04 0x0e 0x02 0x1ab 0x04 0x0f 0x02 0x1ab 0x04 0x10 0x02 0x1ab 0x04 0x11 0x02 0x1ab>; + phandle = <0x72>; + }; + }; + + can0 { + + can0m0-pins { + rockchip,pins = <0x00 0x10 0x0b 0x1ab 0x00 0x0f 0x0b 0x1ab>; + phandle = <0x154>; + }; + + can0m1-pins { + rockchip,pins = <0x04 0x1d 0x09 0x1ab 0x04 0x1c 0x09 0x1ab>; + phandle = <0x336>; + }; + }; + + can1 { + + can1m0-pins { + rockchip,pins = <0x03 0x0d 0x09 0x1ab 0x03 0x0e 0x09 0x1ab>; + phandle = <0x155>; + }; + + can1m1-pins { + rockchip,pins = <0x04 0x0a 0x0c 0x1ab 0x04 0x0b 0x0c 0x1ab>; + phandle = <0x337>; + }; + }; + + can2 { + + can2m0-pins { + rockchip,pins = <0x03 0x14 0x09 0x1ab 0x03 0x15 0x09 0x1ab>; + phandle = <0x156>; + }; + + can2m1-pins { + rockchip,pins = <0x00 0x1c 0x0a 0x1ab 0x00 0x1d 0x0a 0x1ab>; + phandle = <0x338>; + }; + }; + + cif { + + cif-clk { + rockchip,pins = <0x04 0x0c 0x01 0x1ab>; + phandle = <0x339>; + }; + + cif-dvp-clk { + rockchip,pins = <0x04 0x08 0x01 0x1ab 0x04 0x0a 0x01 0x1ab 0x04 0x0b 0x01 0x1ab>; + phandle = <0x33a>; + }; + + cif-dvp-bus16 { + rockchip,pins = <0x03 0x14 0x01 0x1ab 0x03 0x15 0x01 0x1ab 0x03 0x16 0x01 0x1ab 0x03 0x17 0x01 0x1ab 0x03 0x18 0x01 0x1ab 0x03 0x19 0x01 0x1ab 0x03 0x1a 0x01 0x1ab 0x03 0x1b 0x01 0x1ab>; + phandle = <0x33b>; + }; + + cif-dvp-bus8 { + rockchip,pins = <0x04 0x00 0x01 0x1ab 0x04 0x01 0x01 0x1ab 0x04 0x02 0x01 0x1ab 0x04 0x03 0x01 0x1ab 0x04 0x04 0x01 0x1ab 0x04 0x05 0x01 0x1ab 0x04 0x06 0x01 0x1ab 0x04 0x07 0x01 0x1ab>; + phandle = <0x33c>; + }; + }; + + clk32k { + + clk32k-in { + rockchip,pins = <0x00 0x0a 0x01 0x1ab>; + phandle = <0x33d>; + }; + + clk32k-out0 { + rockchip,pins = <0x00 0x0a 0x02 0x1ab>; + phandle = <0x33e>; + }; + + clk32k-out1 { + rockchip,pins = <0x02 0x15 0x01 0x1ab>; + phandle = <0x33f>; + }; + }; + + cpu { + + cpu-pins { + rockchip,pins = <0x00 0x19 0x02 0x1ab 0x00 0x1d 0x02 0x1ab>; + phandle = <0x340>; + }; + }; + + ddrphych0 { + + ddrphych0-pins { + rockchip,pins = <0x04 0x00 0x07 0x1ab 0x04 0x01 0x07 0x1ab 0x04 0x02 0x07 0x1ab 0x04 0x03 0x07 0x1ab>; + phandle = <0x341>; + }; + }; + + ddrphych1 { + + ddrphych1-pins { + rockchip,pins = <0x04 0x04 0x07 0x1ab 0x04 0x05 0x07 0x1ab 0x04 0x06 0x07 0x1ab 0x04 0x07 0x07 0x1ab>; + phandle = <0x342>; + }; + }; + + ddrphych2 { + + ddrphych2-pins { + rockchip,pins = <0x04 0x08 0x07 0x1ab 0x04 0x09 0x07 0x1ab 0x04 0x0a 0x07 0x1ab 0x04 0x0b 0x07 0x1ab>; + phandle = <0x343>; + }; + }; + + ddrphych3 { + + ddrphych3-pins { + rockchip,pins = <0x04 0x0c 0x07 0x1ab 0x04 0x0d 0x07 0x1ab 0x04 0x0e 0x07 0x1ab 0x04 0x0f 0x07 0x1ab>; + phandle = <0x344>; + }; + }; + + dp0 { + + dp0m0-pins { + rockchip,pins = <0x04 0x0c 0x05 0x1ab>; + phandle = <0x345>; + }; + + dp0m1-pins { + rockchip,pins = <0x00 0x14 0x0a 0x1ab>; + phandle = <0x346>; + }; + + dp0m2-pins { + rockchip,pins = <0x01 0x00 0x05 0x1ab>; + phandle = <0x347>; + }; + }; + + dp1 { + + dp1m0-pins { + rockchip,pins = <0x03 0x1d 0x05 0x1ab>; + phandle = <0x1ba>; + }; + + dp1m1-pins { + rockchip,pins = <0x00 0x15 0x0a 0x1ab>; + phandle = <0x348>; + }; + + dp1m2-pins { + rockchip,pins = <0x01 0x01 0x05 0x1ab>; + phandle = <0x349>; + }; + }; + + emmc { + + emmc-rstnout { + rockchip,pins = <0x02 0x03 0x01 0x1ab>; + phandle = <0x34a>; + }; + + emmc-bus8 { + rockchip,pins = <0x02 0x18 0x01 0x1ac 0x02 0x19 0x01 0x1ac 0x02 0x1a 0x01 0x1ac 0x02 0x1b 0x01 0x1ac 0x02 0x1c 0x01 0x1ac 0x02 0x1d 0x01 0x1ac 0x02 0x1e 0x01 0x1ac 0x02 0x1f 0x01 0x1ac>; + phandle = <0x34b>; + }; + + emmc-clk { + rockchip,pins = <0x02 0x01 0x01 0x1ac>; + phandle = <0x34c>; + }; + + emmc-cmd { + rockchip,pins = <0x02 0x00 0x01 0x1ac>; + phandle = <0x34d>; + }; + + emmc-data-strobe { + rockchip,pins = <0x02 0x02 0x01 0x1ab>; + phandle = <0x34e>; + }; + }; + + eth1 { + + eth1-pins { + rockchip,pins = <0x03 0x06 0x01 0x1ab>; + phandle = <0x34f>; + }; + }; + + fspi { + + fspim0-pins { + rockchip,pins = <0x02 0x00 0x02 0x1ac 0x02 0x1e 0x02 0x1ac 0x02 0x18 0x02 0x1ac 0x02 0x19 0x02 0x1ac 0x02 0x1a 0x02 0x1ac 0x02 0x1b 0x02 0x1ac>; + phandle = <0x350>; + }; + + fspim0-cs1 { + rockchip,pins = <0x02 0x1f 0x02 0x1ac>; + phandle = <0x351>; + }; + + fspim2-pins { + rockchip,pins = <0x03 0x05 0x05 0x1ac 0x03 0x14 0x02 0x1ac 0x03 0x00 0x05 0x1ac 0x03 0x01 0x05 0x1ac 0x03 0x02 0x05 0x1ac 0x03 0x03 0x05 0x1ac>; + phandle = <0x352>; + }; + + fspim2-cs1 { + rockchip,pins = <0x03 0x15 0x02 0x1ac>; + phandle = <0x353>; + }; + + fspim1-pins { + rockchip,pins = <0x02 0x0b 0x03 0x1ac 0x02 0x0c 0x03 0x1ac 0x02 0x06 0x03 0x1ac 0x02 0x07 0x03 0x1ac 0x02 0x08 0x03 0x1ac 0x02 0x09 0x03 0x1ac>; + phandle = <0x354>; + }; + + fspim1-cs1 { + rockchip,pins = <0x02 0x0d 0x03 0x1ac>; + phandle = <0x355>; + }; + }; + + gmac1 { + + gmac1-miim { + rockchip,pins = <0x03 0x12 0x01 0x1ab 0x03 0x13 0x01 0x1ab>; + phandle = <0x11a>; + }; + + gmac1-clkinout { + rockchip,pins = <0x03 0x0e 0x01 0x1ab>; + phandle = <0x356>; + }; + + gmac1-rx-bus2 { + rockchip,pins = <0x03 0x07 0x01 0x1ab 0x03 0x08 0x01 0x1ab 0x03 0x09 0x01 0x1ab>; + phandle = <0x11c>; + }; + + gmac1-tx-bus2 { + rockchip,pins = <0x03 0x0b 0x01 0x1ab 0x03 0x0c 0x01 0x1ab 0x03 0x0d 0x01 0x1ab>; + phandle = <0x11b>; + }; + + gmac1-rgmii-clk { + rockchip,pins = <0x03 0x05 0x01 0x1ab 0x03 0x04 0x01 0x1ab>; + phandle = <0x11d>; + }; + + gmac1-rgmii-bus { + rockchip,pins = <0x03 0x02 0x01 0x1ab 0x03 0x03 0x01 0x1ab 0x03 0x00 0x01 0x1ab 0x03 0x01 0x01 0x1ab>; + phandle = <0x11e>; + }; + + gmac1-ppsclk { + rockchip,pins = <0x03 0x11 0x01 0x1ab>; + phandle = <0x357>; + }; + + gmac1-ppstrig { + rockchip,pins = <0x03 0x10 0x01 0x1ab>; + phandle = <0x358>; + }; + + gmac1-ptp-ref-clk { + rockchip,pins = <0x03 0x0f 0x01 0x1ab>; + phandle = <0x359>; + }; + + gmac1-txer { + rockchip,pins = <0x03 0x0a 0x01 0x1ab>; + phandle = <0x35a>; + }; + }; + + gpu { + + gpu-pins { + rockchip,pins = <0x00 0x15 0x02 0x1ab>; + phandle = <0x35b>; + }; + }; + + hdmi { + + hdmim0-rx-cec { + rockchip,pins = <0x04 0x0d 0x05 0x1ab>; + phandle = <0x35c>; + }; + + hdmim0-rx-hpdin { + rockchip,pins = <0x04 0x0e 0x05 0x1ab>; + phandle = <0x35d>; + }; + + hdmim0-rx-scl { + rockchip,pins = <0x00 0x1a 0x0b 0x1ab>; + phandle = <0x35e>; + }; + + hdmim0-rx-sda { + rockchip,pins = <0x00 0x19 0x0b 0x1ab>; + phandle = <0x35f>; + }; + + hdmim0-tx0-cec { + rockchip,pins = <0x04 0x11 0x05 0x1ab>; + phandle = <0x106>; + }; + + hdmim0-tx0-hpd { + rockchip,pins = <0x01 0x05 0x05 0x1ab>; + phandle = <0x107>; + }; + + hdmim0-tx0-scl { + rockchip,pins = <0x04 0x0f 0x05 0x1ad>; + phandle = <0x108>; + }; + + hdmim0-tx0-sda { + rockchip,pins = <0x04 0x10 0x05 0x1ae>; + phandle = <0x109>; + }; + + hdmim0-tx1-hpd { + rockchip,pins = <0x01 0x06 0x05 0x1ab>; + phandle = <0x1be>; + }; + + hdmim1-rx { + rockchip,pins = <0x03 0x19 0x05 0x1ab 0x03 0x1a 0x05 0x1af 0x03 0x1b 0x05 0x1af 0x03 0x1c 0x05 0x1ab>; + phandle = <0x1c7>; + }; + + hdmim1-rx-cec { + rockchip,pins = <0x03 0x19 0x05 0x1ab>; + phandle = <0x360>; + }; + + hdmim1-rx-hpdin { + rockchip,pins = <0x03 0x1c 0x05 0x1ab>; + phandle = <0x361>; + }; + + hdmim1-rx-scl { + rockchip,pins = <0x03 0x1a 0x05 0x1af>; + phandle = <0x362>; + }; + + hdmim1-rx-sda { + rockchip,pins = <0x03 0x1b 0x05 0x1af>; + phandle = <0x363>; + }; + + hdmim1-tx0-cec { + rockchip,pins = <0x00 0x19 0x0d 0x1ab>; + phandle = <0x364>; + }; + + hdmim1-tx0-hpd { + rockchip,pins = <0x03 0x1c 0x03 0x1ab>; + phandle = <0x365>; + }; + + hdmim1-tx0-scl { + rockchip,pins = <0x00 0x1d 0x0b 0x1ad>; + phandle = <0x366>; + }; + + hdmim1-tx0-sda { + rockchip,pins = <0x00 0x1c 0x0b 0x1ae>; + phandle = <0x367>; + }; + + hdmim1-tx1-cec { + rockchip,pins = <0x00 0x1a 0x0d 0x1ab>; + phandle = <0x368>; + }; + + hdmim1-tx1-hpd { + rockchip,pins = <0x03 0x0f 0x05 0x1ab>; + phandle = <0x369>; + }; + + hdmim1-tx1-scl { + rockchip,pins = <0x03 0x16 0x05 0x1ad>; + phandle = <0x1bf>; + }; + + hdmim1-tx1-sda { + rockchip,pins = <0x03 0x15 0x05 0x1ae>; + phandle = <0x1c0>; + }; + + hdmim2-rx-cec { + rockchip,pins = <0x01 0x0f 0x05 0x1ab>; + phandle = <0x36a>; + }; + + hdmim2-rx-hpdin { + rockchip,pins = <0x01 0x0e 0x05 0x1ab>; + phandle = <0x36b>; + }; + + hdmim2-rx-scl { + rockchip,pins = <0x01 0x1e 0x05 0x1ab>; + phandle = <0x36c>; + }; + + hdmim2-rx-sda { + rockchip,pins = <0x01 0x1f 0x05 0x1ab>; + phandle = <0x36d>; + }; + + hdmim2-tx0-scl { + rockchip,pins = <0x03 0x17 0x05 0x1ad>; + phandle = <0x36e>; + }; + + hdmim2-tx0-sda { + rockchip,pins = <0x03 0x18 0x05 0x1ae>; + phandle = <0x36f>; + }; + + hdmim2-tx1-cec { + rockchip,pins = <0x03 0x14 0x05 0x1ab>; + phandle = <0x1bd>; + }; + + hdmim2-tx1-scl { + rockchip,pins = <0x01 0x04 0x05 0x1ad>; + phandle = <0x370>; + }; + + hdmim2-tx1-sda { + rockchip,pins = <0x01 0x03 0x05 0x1ae>; + phandle = <0x371>; + }; + + hdmi-debug0 { + rockchip,pins = <0x01 0x07 0x07 0x1ab>; + phandle = <0x372>; + }; + + hdmi-debug1 { + rockchip,pins = <0x01 0x08 0x07 0x1ab>; + phandle = <0x373>; + }; + + hdmi-debug2 { + rockchip,pins = <0x01 0x09 0x07 0x1ab>; + phandle = <0x374>; + }; + + hdmi-debug3 { + rockchip,pins = <0x01 0x0a 0x07 0x1ab>; + phandle = <0x375>; + }; + + hdmi-debug4 { + rockchip,pins = <0x01 0x0b 0x07 0x1ab>; + phandle = <0x376>; + }; + + hdmi-debug5 { + rockchip,pins = <0x01 0x0c 0x07 0x1ab>; + phandle = <0x377>; + }; + + hdmi-debug6 { + rockchip,pins = <0x01 0x00 0x07 0x1ab>; + phandle = <0x378>; + }; + + hdmim0-tx1-cec { + rockchip,pins = <0x02 0x14 0x04 0x1ab>; + phandle = <0x379>; + }; + + hdmim0-tx1-scl { + rockchip,pins = <0x02 0x0d 0x04 0x1b0>; + phandle = <0x37a>; + }; + + hdmim0-tx1-sda { + rockchip,pins = <0x02 0x0c 0x04 0x1ae>; + phandle = <0x37b>; + }; + + hdmirx-det { + rockchip,pins = <0x01 0x1d 0x00 0x1b1>; + phandle = <0x1c8>; + }; + }; + + i2c0 { + + i2c0m0-xfer { + rockchip,pins = <0x00 0x0b 0x02 0x1af 0x00 0x06 0x02 0x1af>; + phandle = <0x37c>; + }; + + i2c0m2-xfer { + rockchip,pins = <0x00 0x19 0x03 0x1af 0x00 0x1a 0x03 0x1af>; + phandle = <0x78>; + }; + + i2c0m1-xfer { + rockchip,pins = <0x04 0x15 0x09 0x1af 0x04 0x16 0x09 0x1af>; + phandle = <0x37d>; + }; + }; + + i2c1 { + + i2c1m0-xfer { + rockchip,pins = <0x00 0x0d 0x09 0x1af 0x00 0x0e 0x09 0x1af>; + phandle = <0x37e>; + }; + + i2c1m1-xfer { + rockchip,pins = <0x00 0x08 0x02 0x1af 0x00 0x09 0x02 0x1af>; + phandle = <0x37f>; + }; + + i2c1m2-xfer { + rockchip,pins = <0x00 0x1c 0x09 0x1af 0x00 0x1d 0x09 0x1af>; + phandle = <0x157>; + }; + + i2c1m3-xfer { + rockchip,pins = <0x02 0x1c 0x09 0x1af 0x02 0x1d 0x09 0x1af>; + phandle = <0x380>; + }; + + i2c1m4-xfer { + rockchip,pins = <0x01 0x1a 0x09 0x1af 0x01 0x1b 0x09 0x1af>; + phandle = <0x381>; + }; + }; + + i2c2 { + + i2c2m0-xfer { + rockchip,pins = <0x00 0x0f 0x09 0x1af 0x00 0x10 0x09 0x1af>; + phandle = <0x158>; + }; + + i2c2m2-xfer { + rockchip,pins = <0x02 0x03 0x09 0x1af 0x02 0x02 0x09 0x1af>; + phandle = <0x382>; + }; + + i2c2m3-xfer { + rockchip,pins = <0x01 0x15 0x09 0x1af 0x01 0x14 0x09 0x1af>; + phandle = <0x383>; + }; + + i2c2m4-xfer { + rockchip,pins = <0x01 0x01 0x09 0x1af 0x01 0x00 0x09 0x1af>; + phandle = <0x384>; + }; + + i2c2m1-xfer { + rockchip,pins = <0x02 0x11 0x09 0x1af 0x02 0x10 0x09 0x1af>; + phandle = <0x385>; + }; + }; + + i2c3 { + + i2c3m0-xfer { + rockchip,pins = <0x01 0x11 0x09 0x1af 0x01 0x10 0x09 0x1af>; + phandle = <0x159>; + }; + + i2c3m1-xfer { + rockchip,pins = <0x03 0x0f 0x09 0x1af 0x03 0x10 0x09 0x1af>; + phandle = <0x386>; + }; + + i2c3m2-xfer { + rockchip,pins = <0x04 0x04 0x09 0x1af 0x04 0x05 0x09 0x1af>; + phandle = <0x387>; + }; + + i2c3m4-xfer { + rockchip,pins = <0x04 0x18 0x09 0x1af 0x04 0x19 0x09 0x1af>; + phandle = <0x388>; + }; + + i2c3m3-xfer { + rockchip,pins = <0x02 0x0a 0x09 0x1af 0x02 0x0b 0x09 0x1af>; + phandle = <0x389>; + }; + }; + + i2c4 { + + i2c4m0-xfer { + rockchip,pins = <0x03 0x06 0x09 0x1af 0x03 0x05 0x09 0x1af>; + phandle = <0x38a>; + }; + + i2c4m2-xfer { + rockchip,pins = <0x00 0x15 0x09 0x1af 0x00 0x14 0x09 0x1af>; + phandle = <0x38b>; + }; + + i2c4m3-xfer { + rockchip,pins = <0x01 0x03 0x09 0x1af 0x01 0x02 0x09 0x1af>; + phandle = <0x38c>; + }; + + i2c4m4-xfer { + rockchip,pins = <0x01 0x17 0x09 0x1af 0x01 0x16 0x09 0x1af>; + phandle = <0x38d>; + }; + + i2c4m1-xfer { + rockchip,pins = <0x02 0x0d 0x09 0x1af 0x02 0x0c 0x09 0x1af>; + phandle = <0x15d>; + }; + }; + + i2c5 { + + i2c5m0-xfer { + rockchip,pins = <0x03 0x17 0x09 0x1af 0x03 0x18 0x09 0x1af>; + phandle = <0x15e>; + }; + + i2c5m1-xfer { + rockchip,pins = <0x04 0x0e 0x09 0x1af 0x04 0x0f 0x09 0x1af>; + phandle = <0x38e>; + }; + + i2c5m2-xfer { + rockchip,pins = <0x04 0x06 0x09 0x1af 0x04 0x07 0x09 0x1af>; + phandle = <0x38f>; + }; + + i2c5m3-xfer { + rockchip,pins = <0x01 0x0e 0x09 0x1af 0x01 0x0f 0x09 0x1af>; + phandle = <0x390>; + }; + + i2c5m4-xfer { + rockchip,pins = <0x02 0x0e 0x09 0x1af 0x02 0x0f 0x09 0x1af>; + phandle = <0x391>; + }; + }; + + i2c6 { + + i2c6m0-xfer { + rockchip,pins = <0x00 0x18 0x09 0x1af 0x00 0x17 0x09 0x1af>; + phandle = <0x18f>; + }; + + i2c6m1-xfer { + rockchip,pins = <0x01 0x13 0x09 0x1af 0x01 0x12 0x09 0x1af>; + phandle = <0x392>; + }; + + i2c6m3-xfer { + rockchip,pins = <0x04 0x09 0x09 0x1af 0x04 0x08 0x09 0x1af>; + phandle = <0x393>; + }; + + i2c6m4-xfer { + rockchip,pins = <0x03 0x01 0x09 0x1af 0x03 0x00 0x09 0x1af>; + phandle = <0x394>; + }; + + i2c6m2-xfer { + rockchip,pins = <0x02 0x13 0x09 0x1af 0x02 0x12 0x09 0x1af>; + phandle = <0x395>; + }; + }; + + i2c7 { + + i2c7m0-xfer { + rockchip,pins = <0x01 0x18 0x09 0x1af 0x01 0x19 0x09 0x1af>; + phandle = <0x196>; + }; + + i2c7m2-xfer { + rockchip,pins = <0x03 0x1a 0x09 0x1af 0x03 0x1b 0x09 0x1af>; + phandle = <0x396>; + }; + + i2c7m3-xfer { + rockchip,pins = <0x04 0x0a 0x09 0x1af 0x04 0x0b 0x09 0x1af>; + phandle = <0x397>; + }; + + i2c7m1-xfer { + rockchip,pins = <0x04 0x13 0x09 0x1af 0x04 0x14 0x09 0x1af>; + phandle = <0x398>; + }; + }; + + i2c8 { + + i2c8m0-xfer { + rockchip,pins = <0x04 0x1a 0x09 0x1af 0x04 0x1b 0x09 0x1af>; + phandle = <0x199>; + }; + + i2c8m2-xfer { + rockchip,pins = <0x01 0x1e 0x09 0x1af 0x01 0x1f 0x09 0x1af>; + phandle = <0x399>; + }; + + i2c8m3-xfer { + rockchip,pins = <0x04 0x10 0x09 0x1af 0x04 0x11 0x09 0x1af>; + phandle = <0x39a>; + }; + + i2c8m4-xfer { + rockchip,pins = <0x03 0x12 0x09 0x1af 0x03 0x13 0x09 0x1af>; + phandle = <0x39b>; + }; + + i2c8m1-xfer { + rockchip,pins = <0x02 0x08 0x09 0x1af 0x02 0x09 0x09 0x1af>; + phandle = <0x39c>; + }; + }; + + i2s0 { + + i2s0-idle { + rockchip,pins = <0x01 0x15 0x00 0x1ab 0x01 0x13 0x00 0x1ab>; + phandle = <0x12e>; + }; + + i2s0-lrck { + rockchip,pins = <0x01 0x15 0x01 0x1af>; + phandle = <0x12a>; + }; + + i2s0-mclk { + rockchip,pins = <0x01 0x12 0x01 0x1af>; + phandle = <0x198>; + }; + + i2s0-sclk { + rockchip,pins = <0x01 0x13 0x01 0x1af>; + phandle = <0x12b>; + }; + + i2s0-sdi0 { + rockchip,pins = <0x01 0x1c 0x02 0x1ab>; + phandle = <0x12c>; + }; + + i2s0-sdi1 { + rockchip,pins = <0x01 0x1b 0x02 0x1ab>; + phandle = <0x39d>; + }; + + i2s0-sdi2 { + rockchip,pins = <0x01 0x1a 0x02 0x1ab>; + phandle = <0x39e>; + }; + + i2s0-sdi3 { + rockchip,pins = <0x01 0x19 0x02 0x1ab>; + phandle = <0x39f>; + }; + + i2s0-sdo0 { + rockchip,pins = <0x01 0x17 0x01 0x1ab>; + phandle = <0x12d>; + }; + + i2s0-sdo1 { + rockchip,pins = <0x01 0x18 0x01 0x1ab>; + phandle = <0x3a0>; + }; + + i2s0-sdo2 { + rockchip,pins = <0x01 0x19 0x01 0x1ab>; + phandle = <0x3a1>; + }; + + i2s0-sdo3 { + rockchip,pins = <0x01 0x1a 0x01 0x1ab>; + phandle = <0x3a2>; + }; + }; + + i2s1 { + + i2s1m0-lrck { + rockchip,pins = <0x04 0x02 0x03 0x1af>; + phandle = <0x12f>; + }; + + i2s1m0-mclk { + rockchip,pins = <0x04 0x00 0x03 0x1af>; + phandle = <0x3a3>; + }; + + i2s1m0-sclk { + rockchip,pins = <0x04 0x01 0x03 0x1af>; + phandle = <0x130>; + }; + + i2s1m0-sdi0 { + rockchip,pins = <0x04 0x05 0x03 0x1ab>; + phandle = <0x131>; + }; + + i2s1m0-sdi1 { + rockchip,pins = <0x04 0x06 0x03 0x1ab>; + phandle = <0x132>; + }; + + i2s1m0-sdi2 { + rockchip,pins = <0x04 0x07 0x03 0x1ab>; + phandle = <0x133>; + }; + + i2s1m0-sdi3 { + rockchip,pins = <0x04 0x08 0x03 0x1ab>; + phandle = <0x134>; + }; + + i2s1m0-sdo0 { + rockchip,pins = <0x04 0x09 0x03 0x1ab>; + phandle = <0x135>; + }; + + i2s1m0-sdo1 { + rockchip,pins = <0x04 0x0a 0x03 0x1ab>; + phandle = <0x136>; + }; + + i2s1m0-sdo2 { + rockchip,pins = <0x04 0x0b 0x03 0x1ab>; + phandle = <0x137>; + }; + + i2s1m0-sdo3 { + rockchip,pins = <0x04 0x0c 0x03 0x1ab>; + phandle = <0x138>; + }; + + i2s1m1-lrck { + rockchip,pins = <0x00 0x0f 0x01 0x1af>; + phandle = <0x3a4>; + }; + + i2s1m1-mclk { + rockchip,pins = <0x00 0x0d 0x01 0x1af>; + phandle = <0x3a5>; + }; + + i2s1m1-sclk { + rockchip,pins = <0x00 0x0e 0x01 0x1af>; + phandle = <0x3a6>; + }; + + i2s1m1-sdi0 { + rockchip,pins = <0x00 0x15 0x01 0x1ab>; + phandle = <0x3a7>; + }; + + i2s1m1-sdi1 { + rockchip,pins = <0x00 0x16 0x01 0x1ab>; + phandle = <0x3a8>; + }; + + i2s1m1-sdi2 { + rockchip,pins = <0x00 0x17 0x01 0x1ab>; + phandle = <0x3a9>; + }; + + i2s1m1-sdi3 { + rockchip,pins = <0x00 0x18 0x01 0x1ab>; + phandle = <0x3aa>; + }; + + i2s1m1-sdo0 { + rockchip,pins = <0x00 0x19 0x01 0x1ab>; + phandle = <0x3ab>; + }; + + i2s1m1-sdo1 { + rockchip,pins = <0x00 0x1a 0x01 0x1ab>; + phandle = <0x3ac>; + }; + + i2s1m1-sdo2 { + rockchip,pins = <0x00 0x1c 0x01 0x1ab>; + phandle = <0x3ad>; + }; + + i2s1m1-sdo3 { + rockchip,pins = <0x00 0x1d 0x01 0x1ab>; + phandle = <0x3ae>; + }; + }; + + i2s2 { + + i2s2m1-idle { + rockchip,pins = <0x03 0x0e 0x00 0x1ab 0x03 0x0d 0x00 0x1ab>; + phandle = <0x13d>; + }; + + i2s2m1-lrck { + rockchip,pins = <0x03 0x0e 0x03 0x1af>; + phandle = <0x139>; + }; + + i2s2m1-mclk { + rockchip,pins = <0x03 0x0c 0x03 0x1af>; + phandle = <0x3af>; + }; + + i2s2m1-sclk { + rockchip,pins = <0x03 0x0d 0x03 0x1af>; + phandle = <0x13a>; + }; + + i2s2m1-sdi { + rockchip,pins = <0x03 0x0a 0x03 0x1ab>; + phandle = <0x13b>; + }; + + i2s2m1-sdo { + rockchip,pins = <0x03 0x0b 0x03 0x1ab>; + phandle = <0x13c>; + }; + + i2s2m0-idle { + rockchip,pins = <0x02 0x10 0x00 0x1ab 0x02 0x0f 0x00 0x1ab>; + phandle = <0x3b0>; + }; + + i2s2m0-lrck { + rockchip,pins = <0x02 0x10 0x02 0x1af>; + phandle = <0x3b1>; + }; + + i2s2m0-mclk { + rockchip,pins = <0x02 0x0e 0x02 0x1af>; + phandle = <0x3b2>; + }; + + i2s2m0-sclk { + rockchip,pins = <0x02 0x0f 0x02 0x1af>; + phandle = <0x3b3>; + }; + + i2s2m0-sdi { + rockchip,pins = <0x02 0x13 0x02 0x1ab>; + phandle = <0x3b4>; + }; + + i2s2m0-sdo { + rockchip,pins = <0x04 0x13 0x02 0x1ab>; + phandle = <0x3b5>; + }; + }; + + i2s3 { + + i2s3-idle { + rockchip,pins = <0x03 0x02 0x00 0x1ab 0x03 0x01 0x00 0x1ab>; + phandle = <0x140>; + }; + + i2s3-lrck { + rockchip,pins = <0x03 0x02 0x03 0x1af>; + phandle = <0x141>; + }; + + i2s3-mclk { + rockchip,pins = <0x03 0x00 0x03 0x1af>; + phandle = <0x3b6>; + }; + + i2s3-sclk { + rockchip,pins = <0x03 0x01 0x03 0x1af>; + phandle = <0x142>; + }; + + i2s3-sdi { + rockchip,pins = <0x03 0x04 0x03 0x1ab>; + phandle = <0x13e>; + }; + + i2s3-sdo { + rockchip,pins = <0x03 0x03 0x03 0x1ab>; + phandle = <0x13f>; + }; + }; + + jtag { + + jtagm0-pins { + rockchip,pins = <0x04 0x1a 0x05 0x1ab 0x04 0x1b 0x05 0x1ab>; + phandle = <0x3b7>; + }; + + jtagm1-pins { + rockchip,pins = <0x04 0x18 0x05 0x1ab 0x04 0x19 0x05 0x1ab>; + phandle = <0x3b8>; + }; + + jtagm2-pins { + rockchip,pins = <0x00 0x0d 0x02 0x1ab 0x00 0x0e 0x02 0x1ab>; + phandle = <0x3b9>; + }; + }; + + litcpu { + + litcpu-pins { + rockchip,pins = <0x00 0x1b 0x01 0x1ab>; + phandle = <0x3ba>; + }; + }; + + mcu { + + mcum0-pins { + rockchip,pins = <0x04 0x1c 0x05 0x1ab 0x04 0x1d 0x05 0x1ab>; + phandle = <0x3bb>; + }; + + mcum1-pins { + rockchip,pins = <0x03 0x1c 0x06 0x1ab 0x03 0x1d 0x06 0x1ab>; + phandle = <0x3bc>; + }; + }; + + mipi { + + mipim0-camera0-clk { + rockchip,pins = <0x04 0x09 0x01 0x1ab>; + phandle = <0x3bd>; + }; + + mipim0-camera1-clk { + rockchip,pins = <0x01 0x0e 0x02 0x1ab>; + phandle = <0x3be>; + }; + + mipim0-camera2-clk { + rockchip,pins = <0x01 0x0f 0x02 0x1ab>; + phandle = <0x3bf>; + }; + + mipim0-camera3-clk { + rockchip,pins = <0x01 0x1e 0x02 0x1ab>; + phandle = <0x15a>; + }; + + mipim0-camera4-clk { + rockchip,pins = <0x01 0x1f 0x02 0x1ab>; + phandle = <0x3c0>; + }; + + mipim1-camera0-clk { + rockchip,pins = <0x03 0x05 0x04 0x1ab>; + phandle = <0x3c1>; + }; + + mipim1-camera1-clk { + rockchip,pins = <0x03 0x06 0x04 0x1ab>; + phandle = <0x3c2>; + }; + + mipim1-camera2-clk { + rockchip,pins = <0x03 0x07 0x04 0x1ab>; + phandle = <0x3c3>; + }; + + mipim1-camera3-clk { + rockchip,pins = <0x03 0x08 0x04 0x1ab>; + phandle = <0x3c4>; + }; + + mipim1-camera4-clk { + rockchip,pins = <0x03 0x09 0x04 0x1ab>; + phandle = <0x3c5>; + }; + + mipi-te0 { + rockchip,pins = <0x03 0x12 0x02 0x1ab>; + phandle = <0x3c6>; + }; + + mipi-te1 { + rockchip,pins = <0x03 0x13 0x02 0x1ab>; + phandle = <0x3c7>; + }; + }; + + npu { + + npu-pins { + rockchip,pins = <0x00 0x16 0x02 0x1ab>; + phandle = <0x3c8>; + }; + }; + + pcie20x1 { + + pcie20x1m0-pins { + rockchip,pins = <0x03 0x17 0x04 0x1ab 0x03 0x19 0x04 0x1ab 0x03 0x18 0x04 0x1ab>; + phandle = <0x3c9>; + }; + + pcie20x1m1-pins { + rockchip,pins = <0x04 0x0f 0x04 0x1ab 0x04 0x11 0x04 0x1ab 0x04 0x10 0x04 0x1ab>; + phandle = <0x3ca>; + }; + + pcie20x1-2-button-rstn { + rockchip,pins = <0x04 0x0b 0x04 0x1ab>; + phandle = <0x3cb>; + }; + }; + + pcie30phy { + + pcie30phy-pins { + rockchip,pins = <0x01 0x14 0x04 0x1ab 0x01 0x19 0x04 0x1ab>; + phandle = <0x3cc>; + }; + }; + + pcie30x1 { + + pcie30x1m0-pins { + rockchip,pins = <0x00 0x10 0x0c 0x1ab 0x00 0x15 0x0c 0x1ab 0x00 0x14 0x0c 0x1ab 0x00 0x0d 0x0c 0x1ab 0x00 0x0f 0x0c 0x1ab 0x00 0x0e 0x0c 0x1ab>; + phandle = <0x3cd>; + }; + + pcie30x1m1-pins { + rockchip,pins = <0x04 0x03 0x04 0x1ab 0x04 0x05 0x04 0x1ab 0x04 0x04 0x04 0x1ab 0x04 0x00 0x04 0x1ab 0x04 0x02 0x04 0x1ab 0x04 0x01 0x04 0x1ab>; + phandle = <0x3ce>; + }; + + pcie30x1m2-pins { + rockchip,pins = <0x01 0x0d 0x04 0x1ab 0x01 0x0c 0x04 0x1ab 0x01 0x0b 0x04 0x1ab 0x01 0x00 0x04 0x1ab 0x01 0x07 0x04 0x1ab 0x01 0x01 0x04 0x1ab>; + phandle = <0x3cf>; + }; + + pcie30x1-0-button-rstn { + rockchip,pins = <0x04 0x09 0x04 0x1ab>; + phandle = <0x3d0>; + }; + + pcie30x1-1-button-rstn { + rockchip,pins = <0x04 0x0a 0x04 0x1ab>; + phandle = <0x3d1>; + }; + }; + + pcie30x2 { + + pcie30x2m0-pins { + rockchip,pins = <0x00 0x19 0x0c 0x1ab 0x00 0x1c 0x0c 0x1ab 0x00 0x1a 0x0c 0x1ab>; + phandle = <0x3d2>; + }; + + pcie30x2m1-pins { + rockchip,pins = <0x04 0x06 0x04 0x1ab 0x04 0x08 0x04 0x1ab 0x04 0x07 0x04 0x1ab>; + phandle = <0x3d3>; + }; + + pcie30x2m2-pins { + rockchip,pins = <0x03 0x1a 0x04 0x1ab 0x03 0x1c 0x04 0x1ab 0x03 0x1b 0x04 0x1ab>; + phandle = <0x3d4>; + }; + + pcie30x2m3-pins { + rockchip,pins = <0x01 0x1f 0x04 0x1ab 0x01 0x0f 0x04 0x1ab 0x01 0x0e 0x04 0x1ab>; + phandle = <0x3d5>; + }; + + pcie30x2-button-rstn { + rockchip,pins = <0x03 0x11 0x04 0x1ab>; + phandle = <0x3d6>; + }; + }; + + pcie30x4 { + + pcie30x4m0-pins { + rockchip,pins = <0x00 0x16 0x0c 0x1ab 0x00 0x18 0x0c 0x1ab 0x00 0x17 0x0c 0x1ab>; + phandle = <0x3d7>; + }; + + pcie30x4m1-pins { + rockchip,pins = <0x04 0x0c 0x04 0x1ab 0x04 0x0e 0x04 0x1ab 0x04 0x0d 0x04 0x1ab>; + phandle = <0x3d8>; + }; + + pcie30x4m2-pins { + rockchip,pins = <0x03 0x14 0x04 0x1ab 0x03 0x16 0x04 0x1ab 0x03 0x15 0x04 0x1ab>; + phandle = <0x3d9>; + }; + + pcie30x4m3-pins { + rockchip,pins = <0x01 0x08 0x04 0x1ab 0x01 0x0a 0x04 0x1ab 0x01 0x09 0x04 0x1ab>; + phandle = <0x3da>; + }; + + pcie30x4-button-rstn { + rockchip,pins = <0x03 0x1d 0x04 0x1ab>; + phandle = <0x3db>; + }; + }; + + pdm0 { + + pdm0m0-clk { + rockchip,pins = <0x01 0x16 0x03 0x1ab>; + phandle = <0x148>; + }; + + pdm0m0-clk1 { + rockchip,pins = <0x01 0x14 0x03 0x1ab>; + phandle = <0x149>; + }; + + pdm0m0-idle { + rockchip,pins = <0x01 0x16 0x00 0x1ab 0x01 0x14 0x00 0x1ab>; + phandle = <0x147>; + }; + + pdm0m0-sdi0 { + rockchip,pins = <0x01 0x1d 0x03 0x1ab>; + phandle = <0x143>; + }; + + pdm0m0-sdi1 { + rockchip,pins = <0x01 0x19 0x03 0x1ab>; + phandle = <0x144>; + }; + + pdm0m0-sdi2 { + rockchip,pins = <0x01 0x1a 0x03 0x1ab>; + phandle = <0x145>; + }; + + pdm0m0-sdi3 { + rockchip,pins = <0x01 0x1b 0x03 0x1ab>; + phandle = <0x146>; + }; + + pdm0m1-clk { + rockchip,pins = <0x00 0x10 0x02 0x1ab>; + phandle = <0x3dc>; + }; + + pdm0m1-clk1 { + rockchip,pins = <0x00 0x14 0x02 0x1ab>; + phandle = <0x3dd>; + }; + + pdm0m1-idle { + rockchip,pins = <0x00 0x10 0x00 0x1ab 0x00 0x14 0x00 0x1ab>; + phandle = <0x3de>; + }; + + pdm0m1-sdi0 { + rockchip,pins = <0x00 0x17 0x02 0x1ab>; + phandle = <0x3df>; + }; + + pdm0m1-sdi1 { + rockchip,pins = <0x00 0x18 0x02 0x1ab>; + phandle = <0x3e0>; + }; + + pdm0m1-sdi2 { + rockchip,pins = <0x00 0x1c 0x02 0x1ab>; + phandle = <0x3e1>; + }; + + pdm0m1-sdi3 { + rockchip,pins = <0x00 0x1e 0x02 0x1ab>; + phandle = <0x3e2>; + }; + }; + + pdm1 { + + pdm1m0-clk { + rockchip,pins = <0x04 0x1d 0x02 0x1ab>; + phandle = <0x14f>; + }; + + pdm1m0-clk1 { + rockchip,pins = <0x04 0x1c 0x02 0x1ab>; + phandle = <0x150>; + }; + + pdm1m0-idle { + rockchip,pins = <0x04 0x1d 0x00 0x1ab 0x04 0x1c 0x00 0x1ab>; + phandle = <0x14e>; + }; + + pdm1m0-sdi0 { + rockchip,pins = <0x04 0x1b 0x02 0x1ab>; + phandle = <0x14a>; + }; + + pdm1m0-sdi1 { + rockchip,pins = <0x04 0x1a 0x02 0x1ab>; + phandle = <0x14b>; + }; + + pdm1m0-sdi2 { + rockchip,pins = <0x04 0x19 0x02 0x1ab>; + phandle = <0x14c>; + }; + + pdm1m0-sdi3 { + rockchip,pins = <0x04 0x18 0x02 0x1ab>; + phandle = <0x14d>; + }; + + pdm1m1-clk { + rockchip,pins = <0x01 0x0c 0x02 0x1ab>; + phandle = <0x3e3>; + }; + + pdm1m1-clk1 { + rockchip,pins = <0x01 0x0b 0x02 0x1ab>; + phandle = <0x3e4>; + }; + + pdm1m1-idle { + rockchip,pins = <0x01 0x0c 0x00 0x1ab 0x01 0x0b 0x00 0x1ab>; + phandle = <0x3e5>; + }; + + pdm1m1-sdi0 { + rockchip,pins = <0x01 0x07 0x02 0x1ab>; + phandle = <0x3e6>; + }; + + pdm1m1-sdi1 { + rockchip,pins = <0x01 0x08 0x02 0x1ab>; + phandle = <0x3e7>; + }; + + pdm1m1-sdi2 { + rockchip,pins = <0x01 0x09 0x02 0x1ab>; + phandle = <0x3e8>; + }; + + pdm1m1-sdi3 { + rockchip,pins = <0x01 0x0a 0x02 0x1ab>; + phandle = <0x3e9>; + }; + }; + + pmic { + + pmic-pins { + rockchip,pins = <0x00 0x07 0x00 0x1b1 0x00 0x02 0x01 0x1ab 0x00 0x03 0x01 0x1ab 0x00 0x11 0x01 0x1ab 0x00 0x12 0x01 0x1ab 0x00 0x13 0x01 0x1ab 0x00 0x1e 0x01 0x1ab>; + phandle = <0x16c>; + }; + }; + + pmu { + + pmu-pins { + rockchip,pins = <0x00 0x05 0x03 0x1ab>; + phandle = <0x3ea>; + }; + }; + + pwm0 { + + pwm0m0-pins { + rockchip,pins = <0x00 0x0f 0x03 0x1ab>; + phandle = <0x7c>; + }; + + pwm0m1-pins { + rockchip,pins = <0x01 0x1a 0x0b 0x1ab>; + phandle = <0x3eb>; + }; + + pwm0m2-pins { + rockchip,pins = <0x01 0x02 0x0b 0x1ab>; + phandle = <0x3ec>; + }; + }; + + pwm1 { + + pwm1m0-pins { + rockchip,pins = <0x00 0x10 0x03 0x1ab>; + phandle = <0x7d>; + }; + + pwm1m1-pins { + rockchip,pins = <0x01 0x1b 0x0b 0x1ab>; + phandle = <0x3ed>; + }; + + pwm1m2-pins { + rockchip,pins = <0x01 0x03 0x0b 0x1ab>; + phandle = <0x3ee>; + }; + }; + + pwm2 { + + pwm2m0-pins { + rockchip,pins = <0x00 0x14 0x03 0x1ab>; + phandle = <0x7e>; + }; + + pwm2m1-pins { + rockchip,pins = <0x03 0x09 0x0b 0x1ab>; + phandle = <0x3ef>; + }; + + pwm2m2-pins { + rockchip,pins = <0x04 0x12 0x0b 0x1ab>; + phandle = <0x3f0>; + }; + }; + + pwm3 { + + pwm3m0-pins { + rockchip,pins = <0x00 0x1c 0x03 0x1ab>; + phandle = <0x3f1>; + }; + + pwm3m1-pins { + rockchip,pins = <0x03 0x0a 0x0b 0x1ab>; + phandle = <0x7f>; + }; + + pwm3m2-pins { + rockchip,pins = <0x01 0x12 0x0b 0x1ab>; + phandle = <0x3f2>; + }; + + pwm3m3-pins { + rockchip,pins = <0x01 0x07 0x0b 0x1ab>; + phandle = <0x3f3>; + }; + }; + + pwm4 { + + pwm4m0-pins { + rockchip,pins = <0x00 0x15 0x0b 0x1ab>; + phandle = <0x180>; + }; + + pwm4m1-pins { + rockchip,pins = <0x04 0x13 0x0b 0x1ab>; + phandle = <0x3f4>; + }; + }; + + pwm5 { + + pwm5m0-pins { + rockchip,pins = <0x00 0x09 0x03 0x1ab>; + phandle = <0x181>; + }; + + pwm5m1-pins { + rockchip,pins = <0x00 0x16 0x0b 0x1ab>; + phandle = <0x3f5>; + }; + + pwm5m2-pins { + rockchip,pins = <0x04 0x14 0x0b 0x1ab>; + phandle = <0x3f6>; + }; + }; + + pwm6 { + + pwm6m0-pins { + rockchip,pins = <0x00 0x17 0x0b 0x1ab>; + phandle = <0x182>; + }; + + pwm6m1-pins { + rockchip,pins = <0x04 0x11 0x0b 0x1ab>; + phandle = <0x3f7>; + }; + + pwm6m2-pins { + rockchip,pins = <0x04 0x15 0x0b 0x1ab>; + phandle = <0x3f8>; + }; + }; + + pwm7 { + + pwm7m0-pins { + rockchip,pins = <0x00 0x18 0x0b 0x1ab>; + phandle = <0x183>; + }; + + pwm7m1-pins { + rockchip,pins = <0x04 0x1c 0x0b 0x1ab>; + phandle = <0x3f9>; + }; + + pwm7m2-pins { + rockchip,pins = <0x01 0x13 0x0b 0x1ab>; + phandle = <0x3fa>; + }; + + pwm7m3-pins { + rockchip,pins = <0x04 0x16 0x0b 0x1ab>; + phandle = <0x3fb>; + }; + }; + + pwm8 { + + pwm8m0-pins { + rockchip,pins = <0x03 0x07 0x0b 0x1ab>; + phandle = <0x184>; + }; + + pwm8m1-pins { + rockchip,pins = <0x04 0x18 0x0b 0x1ab>; + phandle = <0x3fc>; + }; + + pwm8m2-pins { + rockchip,pins = <0x03 0x18 0x0b 0x1ab>; + phandle = <0x3fd>; + }; + }; + + pwm9 { + + pwm9m0-pins { + rockchip,pins = <0x03 0x08 0x0b 0x1ab>; + phandle = <0x185>; + }; + + pwm9m1-pins { + rockchip,pins = <0x04 0x19 0x0b 0x1ab>; + phandle = <0x3fe>; + }; + + pwm9m2-pins { + rockchip,pins = <0x03 0x19 0x0b 0x1ab>; + phandle = <0x3ff>; + }; + }; + + pwm10 { + + pwm10m0-pins { + rockchip,pins = <0x03 0x00 0x0b 0x1ab>; + phandle = <0x186>; + }; + + pwm10m1-pins { + rockchip,pins = <0x04 0x1b 0x0b 0x1ab>; + phandle = <0x400>; + }; + + pwm10m2-pins { + rockchip,pins = <0x03 0x1b 0x0b 0x1ab>; + phandle = <0x401>; + }; + }; + + pwm11 { + + pwm11m0-pins { + rockchip,pins = <0x03 0x01 0x0b 0x1ab>; + phandle = <0x187>; + }; + + pwm11m1-pins { + rockchip,pins = <0x04 0x0c 0x0b 0x1ab>; + phandle = <0x402>; + }; + + pwm11m2-pins { + rockchip,pins = <0x01 0x14 0x0b 0x1ab>; + phandle = <0x403>; + }; + + pwm11m3-pins { + rockchip,pins = <0x03 0x1d 0x0b 0x1ab>; + phandle = <0x404>; + }; + }; + + pwm12 { + + pwm12m0-pins { + rockchip,pins = <0x03 0x0d 0x0b 0x1ab>; + phandle = <0x188>; + }; + + pwm12m1-pins { + rockchip,pins = <0x04 0x0d 0x0b 0x1ab>; + phandle = <0x405>; + }; + }; + + pwm13 { + + pwm13m0-pins { + rockchip,pins = <0x03 0x0e 0x0b 0x1ab>; + phandle = <0x189>; + }; + + pwm13m1-pins { + rockchip,pins = <0x04 0x0e 0x0b 0x1ab>; + phandle = <0x406>; + }; + + pwm13m2-pins { + rockchip,pins = <0x01 0x0f 0x0b 0x1ab>; + phandle = <0x407>; + }; + }; + + pwm14 { + + pwm14m0-pins { + rockchip,pins = <0x03 0x12 0x0b 0x1ab>; + phandle = <0x18a>; + }; + + pwm14m1-pins { + rockchip,pins = <0x04 0x0a 0x0b 0x1ab>; + phandle = <0x408>; + }; + + pwm14m2-pins { + rockchip,pins = <0x01 0x1e 0x0b 0x1ab>; + phandle = <0x409>; + }; + }; + + pwm15 { + + pwm15m0-pins { + rockchip,pins = <0x03 0x13 0x0b 0x1ab>; + phandle = <0x18b>; + }; + + pwm15m1-pins { + rockchip,pins = <0x04 0x0b 0x0b 0x1ab>; + phandle = <0x40a>; + }; + + pwm15m2-pins { + rockchip,pins = <0x01 0x16 0x0b 0x1ab>; + phandle = <0x40b>; + }; + + pwm15m3-pins { + rockchip,pins = <0x01 0x1f 0x0b 0x1ab>; + phandle = <0x40c>; + }; + }; + + refclk { + + refclk-pins { + rockchip,pins = <0x00 0x00 0x01 0x1ab>; + phandle = <0x40d>; + }; + }; + + sata { + + sata-pins { + rockchip,pins = <0x00 0x16 0x0d 0x1ab 0x00 0x1c 0x0d 0x1ab 0x00 0x1d 0x0d 0x1ab>; + phandle = <0x40e>; + }; + }; + + sata0 { + + sata0m0-pins { + rockchip,pins = <0x04 0x0e 0x06 0x1ab>; + phandle = <0x40f>; + }; + + sata0m1-pins { + rockchip,pins = <0x01 0x0b 0x06 0x1ab>; + phandle = <0x410>; + }; + }; + + sata1 { + + sata1m0-pins { + rockchip,pins = <0x04 0x0d 0x06 0x1ab>; + phandle = <0x411>; + }; + + sata1m1-pins { + rockchip,pins = <0x01 0x01 0x06 0x1ab>; + phandle = <0x412>; + }; + }; + + sata2 { + + sata2m0-pins { + rockchip,pins = <0x04 0x09 0x06 0x1ab>; + phandle = <0x413>; + }; + + sata2m1-pins { + rockchip,pins = <0x01 0x0f 0x06 0x1ab>; + phandle = <0x414>; + }; + }; + + sdio { + + sdiom1-pins { + rockchip,pins = <0x03 0x05 0x02 0x1ab 0x03 0x04 0x02 0x1b1 0x03 0x00 0x02 0x1b1 0x03 0x01 0x02 0x1b1 0x03 0x02 0x02 0x1b1 0x03 0x03 0x02 0x1b1>; + phandle = <0x415>; + }; + + sdiom0-pins { + rockchip,pins = <0x02 0x0b 0x02 0x1ab 0x02 0x0a 0x02 0x1b1 0x02 0x06 0x02 0x1b1 0x02 0x07 0x02 0x1b1 0x02 0x08 0x02 0x1b1 0x02 0x09 0x02 0x1b1>; + phandle = <0x126>; + }; + }; + + sdmmc { + + sdmmc-bus4 { + rockchip,pins = <0x04 0x18 0x01 0x1ac 0x04 0x19 0x01 0x1ac 0x04 0x1a 0x01 0x1ac 0x04 0x1b 0x01 0x1ac>; + phandle = <0x123>; + }; + + sdmmc-clk { + rockchip,pins = <0x04 0x1d 0x01 0x1ac>; + phandle = <0x120>; + }; + + sdmmc-cmd { + rockchip,pins = <0x04 0x1c 0x01 0x1ac>; + phandle = <0x121>; + }; + + sdmmc-det { + rockchip,pins = <0x00 0x04 0x01 0x1b1>; + phandle = <0x122>; + }; + + sdmmc-pwren { + rockchip,pins = <0x00 0x05 0x02 0x1ab>; + phandle = <0x416>; + }; + + sd-s0-pwr { + rockchip,pins = <0x00 0x0f 0x00 0x1b1>; + phandle = <0x202>; + }; + }; + + spdif0 { + + spdif0m0-tx { + rockchip,pins = <0x01 0x0e 0x03 0x1ab>; + phandle = <0x151>; + }; + + spdif0m1-tx { + rockchip,pins = <0x04 0x0c 0x06 0x1ab>; + phandle = <0x417>; + }; + }; + + spdif1 { + + spdif1m0-tx { + rockchip,pins = <0x01 0x0f 0x03 0x1ab>; + phandle = <0x152>; + }; + + spdif1m1-tx { + rockchip,pins = <0x04 0x09 0x02 0x1ab>; + phandle = <0x418>; + }; + + spdif1m2-tx { + rockchip,pins = <0x04 0x11 0x03 0x1ab>; + phandle = <0x419>; + }; + }; + + spi0 { + + spi0m0-pins { + rockchip,pins = <0x00 0x16 0x08 0x1b2 0x00 0x17 0x08 0x1b2 0x00 0x10 0x08 0x1b2>; + phandle = <0x166>; + }; + + spi0m0-cs0 { + rockchip,pins = <0x00 0x19 0x08 0x1b2>; + phandle = <0x164>; + }; + + spi0m0-cs1 { + rockchip,pins = <0x00 0x0f 0x08 0x1b2>; + phandle = <0x165>; + }; + + spi0m1-pins { + rockchip,pins = <0x04 0x02 0x08 0x1b2 0x04 0x00 0x08 0x1b2 0x04 0x01 0x08 0x1b2>; + phandle = <0x41a>; + }; + + spi0m1-cs0 { + rockchip,pins = <0x04 0x0a 0x08 0x1b2>; + phandle = <0x41b>; + }; + + spi0m1-cs1 { + rockchip,pins = <0x04 0x09 0x08 0x1b2>; + phandle = <0x41c>; + }; + + spi0m2-pins { + rockchip,pins = <0x01 0x0b 0x08 0x1b2 0x01 0x09 0x08 0x1b2 0x01 0x0a 0x08 0x1b2>; + phandle = <0x41d>; + }; + + spi0m2-cs0 { + rockchip,pins = <0x01 0x0c 0x08 0x1b2>; + phandle = <0x41e>; + }; + + spi0m2-cs1 { + rockchip,pins = <0x01 0x0d 0x08 0x1b2>; + phandle = <0x41f>; + }; + + spi0m3-pins { + rockchip,pins = <0x03 0x1b 0x08 0x1b2 0x03 0x19 0x08 0x1b2 0x03 0x1a 0x08 0x1b2>; + phandle = <0x420>; + }; + + spi0m3-cs0 { + rockchip,pins = <0x03 0x1c 0x08 0x1b2>; + phandle = <0x421>; + }; + + spi0m3-cs1 { + rockchip,pins = <0x03 0x1d 0x08 0x1b2>; + phandle = <0x422>; + }; + }; + + spi1 { + + spi1m1-pins { + rockchip,pins = <0x03 0x11 0x08 0x1b2 0x03 0x10 0x08 0x1b2 0x03 0x0f 0x08 0x1b2>; + phandle = <0x169>; + }; + + spi1m1-cs0 { + rockchip,pins = <0x03 0x12 0x08 0x1b2>; + phandle = <0x167>; + }; + + spi1m1-cs1 { + rockchip,pins = <0x03 0x13 0x08 0x1b2>; + phandle = <0x168>; + }; + + spi1m2-pins { + rockchip,pins = <0x01 0x1a 0x08 0x1b2 0x01 0x18 0x08 0x1b2 0x01 0x19 0x08 0x1b2>; + phandle = <0x423>; + }; + + spi1m2-cs0 { + rockchip,pins = <0x01 0x1b 0x08 0x1b2>; + phandle = <0x424>; + }; + + spi1m2-cs1 { + rockchip,pins = <0x01 0x1d 0x08 0x1b2>; + phandle = <0x425>; + }; + + spi1m0-pins { + rockchip,pins = <0x02 0x10 0x08 0x1b3 0x02 0x11 0x08 0x1b3 0x02 0x12 0x08 0x1b3>; + phandle = <0x426>; + }; + + spi1m0-cs0 { + rockchip,pins = <0x02 0x13 0x08 0x1b3>; + phandle = <0x427>; + }; + + spi1m0-cs1 { + rockchip,pins = <0x02 0x14 0x08 0x1b3>; + phandle = <0x428>; + }; + }; + + spi2 { + + spi2m0-pins { + rockchip,pins = <0x01 0x06 0x08 0x1b2 0x01 0x04 0x08 0x1b2 0x01 0x05 0x08 0x1b2>; + phandle = <0x429>; + }; + + spi2m0-cs0 { + rockchip,pins = <0x01 0x07 0x08 0x1b2>; + phandle = <0x42a>; + }; + + spi2m0-cs1 { + rockchip,pins = <0x01 0x08 0x08 0x1b2>; + phandle = <0x42b>; + }; + + spi2m1-pins { + rockchip,pins = <0x04 0x06 0x08 0x1b2 0x04 0x04 0x08 0x1b2 0x04 0x05 0x08 0x1b2>; + phandle = <0x42c>; + }; + + spi2m1-cs0 { + rockchip,pins = <0x04 0x07 0x08 0x1b2>; + phandle = <0x42d>; + }; + + spi2m1-cs1 { + rockchip,pins = <0x04 0x08 0x08 0x1b2>; + phandle = <0x42e>; + }; + + spi2m2-pins { + rockchip,pins = <0x00 0x05 0x01 0x1b3 0x00 0x0b 0x01 0x1b3 0x00 0x06 0x01 0x1b3>; + phandle = <0x16b>; + }; + + spi2m2-cs0 { + rockchip,pins = <0x00 0x09 0x01 0x1b3>; + phandle = <0x16a>; + }; + + spi2m2-cs1 { + rockchip,pins = <0x00 0x08 0x01 0x1b3>; + phandle = <0x42f>; + }; + }; + + spi3 { + + spi3m1-pins { + rockchip,pins = <0x04 0x0f 0x08 0x1b2 0x04 0x0d 0x08 0x1b2 0x04 0x0e 0x08 0x1b2>; + phandle = <0x175>; + }; + + spi3m1-cs0 { + rockchip,pins = <0x04 0x10 0x08 0x1b2>; + phandle = <0x173>; + }; + + spi3m1-cs1 { + rockchip,pins = <0x04 0x11 0x08 0x1b2>; + phandle = <0x174>; + }; + + spi3m2-pins { + rockchip,pins = <0x00 0x1b 0x08 0x1b2 0x00 0x18 0x08 0x1b2 0x00 0x1a 0x08 0x1b2>; + phandle = <0x430>; + }; + + spi3m2-cs0 { + rockchip,pins = <0x00 0x1c 0x08 0x1b2>; + phandle = <0x431>; + }; + + spi3m2-cs1 { + rockchip,pins = <0x00 0x1d 0x08 0x1b2>; + phandle = <0x432>; + }; + + spi3m3-pins { + rockchip,pins = <0x03 0x18 0x08 0x1b2 0x03 0x16 0x08 0x1b2 0x03 0x17 0x08 0x1b2>; + phandle = <0x433>; + }; + + spi3m3-cs0 { + rockchip,pins = <0x03 0x14 0x08 0x1b2>; + phandle = <0x434>; + }; + + spi3m3-cs1 { + rockchip,pins = <0x03 0x15 0x08 0x1b2>; + phandle = <0x435>; + }; + + spi3m0-pins { + rockchip,pins = <0x04 0x16 0x08 0x1b3 0x04 0x14 0x08 0x1b3 0x04 0x15 0x08 0x1b3>; + phandle = <0x436>; + }; + + spi3m0-cs0 { + rockchip,pins = <0x04 0x12 0x08 0x1b3>; + phandle = <0x437>; + }; + + spi3m0-cs1 { + rockchip,pins = <0x04 0x13 0x08 0x1b3>; + phandle = <0x438>; + }; + }; + + spi4 { + + spi4m0-pins { + rockchip,pins = <0x01 0x12 0x08 0x1b2 0x01 0x10 0x08 0x1b2 0x01 0x11 0x08 0x1b2>; + phandle = <0x19c>; + }; + + spi4m0-cs0 { + rockchip,pins = <0x01 0x13 0x08 0x1b2>; + phandle = <0x19a>; + }; + + spi4m0-cs1 { + rockchip,pins = <0x01 0x14 0x08 0x1b2>; + phandle = <0x19b>; + }; + + spi4m1-pins { + rockchip,pins = <0x03 0x02 0x08 0x1b2 0x03 0x00 0x08 0x1b2 0x03 0x01 0x08 0x1b2>; + phandle = <0x439>; + }; + + spi4m1-cs0 { + rockchip,pins = <0x03 0x03 0x08 0x1b2>; + phandle = <0x43a>; + }; + + spi4m1-cs1 { + rockchip,pins = <0x03 0x04 0x08 0x1b2>; + phandle = <0x43b>; + }; + + spi4m2-pins { + rockchip,pins = <0x01 0x02 0x08 0x1b2 0x01 0x00 0x08 0x1b2 0x01 0x01 0x08 0x1b2>; + phandle = <0x43c>; + }; + + spi4m2-cs0 { + rockchip,pins = <0x01 0x03 0x08 0x1b2>; + phandle = <0x43d>; + }; + }; + + tsadc { + + tsadcm1-shut { + rockchip,pins = <0x00 0x02 0x02 0x1ab>; + phandle = <0x43e>; + }; + + tsadc-shut { + rockchip,pins = <0x00 0x01 0x02 0x1ab>; + phandle = <0x18d>; + }; + + tsadc-shut-org { + rockchip,pins = <0x00 0x01 0x01 0x1ab>; + phandle = <0x43f>; + }; + }; + + uart0 { + + uart0m0-xfer { + rockchip,pins = <0x00 0x14 0x04 0x1b1 0x00 0x15 0x04 0x1b1>; + phandle = <0x440>; + }; + + uart0m1-xfer { + rockchip,pins = <0x00 0x08 0x04 0x1b1 0x00 0x09 0x04 0x1b1>; + phandle = <0x7b>; + }; + + uart0m2-xfer { + rockchip,pins = <0x04 0x04 0x0a 0x1b1 0x04 0x03 0x0a 0x1b1>; + phandle = <0x441>; + }; + + uart0-ctsn { + rockchip,pins = <0x00 0x19 0x04 0x1ab>; + phandle = <0x442>; + }; + + uart0-rtsn { + rockchip,pins = <0x00 0x16 0x04 0x1ab>; + phandle = <0x443>; + }; + }; + + uart1 { + + uart1m1-xfer { + rockchip,pins = <0x01 0x0f 0x0a 0x1b1 0x01 0x0e 0x0a 0x1b1>; + phandle = <0x176>; + }; + + uart1m1-ctsn { + rockchip,pins = <0x01 0x1f 0x0a 0x1ab>; + phandle = <0x444>; + }; + + uart1m1-rtsn { + rockchip,pins = <0x01 0x1e 0x0a 0x1ab>; + phandle = <0x445>; + }; + + uart1m2-xfer { + rockchip,pins = <0x00 0x1a 0x0a 0x1b1 0x00 0x19 0x0a 0x1b1>; + phandle = <0x446>; + }; + + uart1m2-ctsn { + rockchip,pins = <0x00 0x18 0x0a 0x1ab>; + phandle = <0x447>; + }; + + uart1m2-rtsn { + rockchip,pins = <0x00 0x17 0x0a 0x1ab>; + phandle = <0x448>; + }; + + uart1m0-xfer { + rockchip,pins = <0x02 0x0e 0x0a 0x1b1 0x02 0x0f 0x0a 0x1b1>; + phandle = <0x449>; + }; + + uart1m0-ctsn { + rockchip,pins = <0x02 0x11 0x0a 0x1ab>; + phandle = <0x44a>; + }; + + uart1m0-rtsn { + rockchip,pins = <0x02 0x10 0x0a 0x1ab>; + phandle = <0x44b>; + }; + }; + + uart2 { + + uart2m0-xfer { + rockchip,pins = <0x00 0x0e 0x0a 0x1b1 0x00 0x0d 0x0a 0x1b1>; + phandle = <0x209>; + }; + + uart2m1-xfer { + rockchip,pins = <0x04 0x19 0x0a 0x1b1 0x04 0x18 0x0a 0x1b1>; + phandle = <0x177>; + }; + + uart2m2-xfer { + rockchip,pins = <0x03 0x0a 0x0a 0x1b1 0x03 0x09 0x0a 0x1b1>; + phandle = <0x44c>; + }; + + uart2-ctsn { + rockchip,pins = <0x03 0x0c 0x0a 0x1ab>; + phandle = <0x44d>; + }; + + uart2-rtsn { + rockchip,pins = <0x03 0x0b 0x0a 0x1ab>; + phandle = <0x44e>; + }; + }; + + uart3 { + + uart3m0-xfer { + rockchip,pins = <0x01 0x10 0x0a 0x1b1 0x01 0x11 0x0a 0x1b1>; + phandle = <0x44f>; + }; + + uart3m1-xfer { + rockchip,pins = <0x03 0x0e 0x0a 0x1b1 0x03 0x0d 0x0a 0x1b1>; + phandle = <0x178>; + }; + + uart3m2-xfer { + rockchip,pins = <0x04 0x06 0x0a 0x1b1 0x04 0x05 0x0a 0x1b1>; + phandle = <0x450>; + }; + + uart3-ctsn { + rockchip,pins = <0x01 0x13 0x0a 0x1ab>; + phandle = <0x451>; + }; + + uart3-rtsn { + rockchip,pins = <0x01 0x12 0x0a 0x1ab>; + phandle = <0x452>; + }; + }; + + uart4 { + + uart4m0-xfer { + rockchip,pins = <0x01 0x1b 0x0a 0x1b1 0x01 0x1a 0x0a 0x1b1>; + phandle = <0x453>; + }; + + uart4m1-xfer { + rockchip,pins = <0x03 0x18 0x0a 0x1b1 0x03 0x19 0x0a 0x1b1>; + phandle = <0x179>; + }; + + uart4m2-xfer { + rockchip,pins = <0x01 0x0a 0x0a 0x1b1 0x01 0x0b 0x0a 0x1b1>; + phandle = <0x454>; + }; + + uart4-ctsn { + rockchip,pins = <0x01 0x17 0x0a 0x1ab>; + phandle = <0x455>; + }; + + uart4-rtsn { + rockchip,pins = <0x01 0x15 0x0a 0x1ab>; + phandle = <0x456>; + }; + }; + + uart5 { + + uart5m0-xfer { + rockchip,pins = <0x04 0x1c 0x0a 0x1b1 0x04 0x1d 0x0a 0x1b1>; + phandle = <0x457>; + }; + + uart5m0-ctsn { + rockchip,pins = <0x04 0x1a 0x0a 0x1ab>; + phandle = <0x458>; + }; + + uart5m0-rtsn { + rockchip,pins = <0x04 0x1b 0x0a 0x1ab>; + phandle = <0x459>; + }; + + uart5m1-xfer { + rockchip,pins = <0x03 0x15 0x0a 0x1b1 0x03 0x14 0x0a 0x1b1>; + phandle = <0x17a>; + }; + + uart5m1-ctsn { + rockchip,pins = <0x02 0x02 0x0a 0x1ab>; + phandle = <0x45a>; + }; + + uart5m1-rtsn { + rockchip,pins = <0x02 0x03 0x0a 0x1ab>; + phandle = <0x45b>; + }; + + uart5m2-xfer { + rockchip,pins = <0x02 0x1c 0x0a 0x1b1 0x02 0x1d 0x0a 0x1b1>; + phandle = <0x45c>; + }; + }; + + uart6 { + + uart6m1-xfer { + rockchip,pins = <0x01 0x00 0x0a 0x1b1 0x01 0x01 0x0a 0x1b1>; + phandle = <0x17b>; + }; + + uart6m1-ctsn { + rockchip,pins = <0x01 0x03 0x0a 0x1ab>; + phandle = <0x45d>; + }; + + uart6m1-rtsn { + rockchip,pins = <0x01 0x02 0x0a 0x1ab>; + phandle = <0x45e>; + }; + + uart6m2-xfer { + rockchip,pins = <0x01 0x19 0x0a 0x1b1 0x01 0x18 0x0a 0x1b1>; + phandle = <0x45f>; + }; + + uart6m0-xfer { + rockchip,pins = <0x02 0x06 0x0a 0x1b1 0x02 0x07 0x0a 0x1b1>; + phandle = <0x460>; + }; + + uart6m0-ctsn { + rockchip,pins = <0x02 0x09 0x0a 0x1ab>; + phandle = <0x461>; + }; + + uart6m0-rtsn { + rockchip,pins = <0x02 0x08 0x0a 0x1ab>; + phandle = <0x462>; + }; + }; + + uart7 { + + uart7m1-xfer { + rockchip,pins = <0x03 0x11 0x0a 0x1b1 0x03 0x10 0x0a 0x1b1>; + phandle = <0x17c>; + }; + + uart7m1-ctsn { + rockchip,pins = <0x03 0x13 0x0a 0x1ab>; + phandle = <0x463>; + }; + + uart7m1-rtsn { + rockchip,pins = <0x03 0x12 0x0a 0x1ab>; + phandle = <0x464>; + }; + + uart7m2-xfer { + rockchip,pins = <0x01 0x0c 0x0a 0x1b1 0x01 0x0d 0x0a 0x1b1>; + phandle = <0x465>; + }; + + uart7m0-xfer { + rockchip,pins = <0x02 0x0c 0x0a 0x1b1 0x02 0x0d 0x0a 0x1b1>; + phandle = <0x466>; + }; + + uart7m0-ctsn { + rockchip,pins = <0x04 0x16 0x0a 0x1ab>; + phandle = <0x467>; + }; + + uart7m0-rtsn { + rockchip,pins = <0x04 0x12 0x0a 0x1ab>; + phandle = <0x468>; + }; + }; + + uart8 { + + uart8m0-xfer { + rockchip,pins = <0x04 0x09 0x0a 0x1b1 0x04 0x08 0x0a 0x1b1>; + phandle = <0x469>; + }; + + uart8m0-ctsn { + rockchip,pins = <0x04 0x0b 0x0a 0x1ab>; + phandle = <0x46a>; + }; + + uart8m0-rtsn { + rockchip,pins = <0x04 0x0a 0x0a 0x1ab>; + phandle = <0x46b>; + }; + + uart8m1-xfer { + rockchip,pins = <0x03 0x03 0x0a 0x1b1 0x03 0x02 0x0a 0x1b1>; + phandle = <0x17d>; + }; + + uart8m1-ctsn { + rockchip,pins = <0x03 0x05 0x0a 0x1ab>; + phandle = <0x46c>; + }; + + uart8m1-rtsn { + rockchip,pins = <0x03 0x04 0x0a 0x1ab>; + phandle = <0x46d>; + }; + + uart8-xfer { + rockchip,pins = <0x04 0x09 0x0a 0x1b1>; + phandle = <0x46e>; + }; + }; + + uart9 { + + uart9m1-xfer { + rockchip,pins = <0x04 0x0d 0x0a 0x1b1 0x04 0x0c 0x0a 0x1b1>; + phandle = <0x46f>; + }; + + uart9m1-ctsn { + rockchip,pins = <0x04 0x01 0x0a 0x1ab>; + phandle = <0x470>; + }; + + uart9m1-rtsn { + rockchip,pins = <0x04 0x00 0x0a 0x1ab>; + phandle = <0x471>; + }; + + uart9m2-xfer { + rockchip,pins = <0x03 0x1c 0x0a 0x1b1 0x03 0x1d 0x0a 0x1b1>; + phandle = <0x472>; + }; + + uart9m2-ctsn { + rockchip,pins = <0x03 0x1b 0x0a 0x1ab>; + phandle = <0x473>; + }; + + uart9m2-rtsn { + rockchip,pins = <0x03 0x1a 0x0a 0x1ab>; + phandle = <0x474>; + }; + + uart9m0-xfer { + rockchip,pins = <0x02 0x14 0x0a 0x1b1 0x02 0x12 0x0a 0x1b1>; + phandle = <0x17e>; + }; + + uart9m0-ctsn { + rockchip,pins = <0x04 0x15 0x0a 0x1ab>; + phandle = <0x17f>; + }; + + uart9m0-rtsn { + rockchip,pins = <0x04 0x14 0x0a 0x1ab>; + phandle = <0x203>; + }; + }; + + vop { + + vop-pins { + rockchip,pins = <0x01 0x02 0x01 0x1ab>; + phandle = <0x475>; + }; + }; + + bt656 { + + bt656-pins { + rockchip,pins = <0x04 0x08 0x02 0x1b4 0x04 0x00 0x02 0x1b4 0x04 0x01 0x02 0x1b4 0x04 0x02 0x02 0x1b4 0x04 0x03 0x02 0x1b4 0x04 0x04 0x02 0x1b4 0x04 0x05 0x02 0x1b4 0x04 0x06 0x02 0x1b4 0x04 0x07 0x02 0x1b4>; + phandle = <0x476>; + }; + }; + + gpio-func { + + tsadc-gpio-func { + rockchip,pins = <0x00 0x01 0x00 0x1ab>; + phandle = <0x18c>; + }; + }; + + pcfg-pull-none-drv-level-7 { + bias-disable; + drive-strength = <0x07>; + phandle = <0x477>; + }; + + pcfg-pull-none-drv-level-8 { + bias-disable; + drive-strength = <0x08>; + phandle = <0x478>; + }; + + pcfg-pull-none-drv-level-9 { + bias-disable; + drive-strength = <0x09>; + phandle = <0x479>; + }; + + pcfg-pull-none-drv-level-10 { + bias-disable; + drive-strength = <0x0a>; + phandle = <0x47a>; + }; + + pcfg-pull-none-drv-level-11 { + bias-disable; + drive-strength = <0x0b>; + phandle = <0x47b>; + }; + + pcfg-pull-none-drv-level-12 { + bias-disable; + drive-strength = <0x0c>; + phandle = <0x47c>; + }; + + pcfg-pull-none-drv-level-13 { + bias-disable; + drive-strength = <0x0d>; + phandle = <0x47d>; + }; + + pcfg-pull-none-drv-level-14 { + bias-disable; + drive-strength = <0x0e>; + phandle = <0x47e>; + }; + + pcfg-pull-none-drv-level-15 { + bias-disable; + drive-strength = <0x0f>; + phandle = <0x47f>; + }; + + pcfg-pull-up-drv-level-7 { + bias-pull-up; + drive-strength = <0x07>; + phandle = <0x480>; + }; + + pcfg-pull-up-drv-level-8 { + bias-pull-up; + drive-strength = <0x08>; + phandle = <0x481>; + }; + + pcfg-pull-up-drv-level-9 { + bias-pull-up; + drive-strength = <0x09>; + phandle = <0x482>; + }; + + pcfg-pull-up-drv-level-10 { + bias-pull-up; + drive-strength = <0x0a>; + phandle = <0x483>; + }; + + pcfg-pull-up-drv-level-11 { + bias-pull-up; + drive-strength = <0x0b>; + phandle = <0x484>; + }; + + pcfg-pull-up-drv-level-12 { + bias-pull-up; + drive-strength = <0x0c>; + phandle = <0x485>; + }; + + pcfg-pull-up-drv-level-13 { + bias-pull-up; + drive-strength = <0x0d>; + phandle = <0x486>; + }; + + pcfg-pull-up-drv-level-14 { + bias-pull-up; + drive-strength = <0x0e>; + phandle = <0x487>; + }; + + pcfg-pull-up-drv-level-15 { + bias-pull-up; + drive-strength = <0x0f>; + phandle = <0x488>; + }; + + pcfg-pull-down-drv-level-7 { + bias-pull-down; + drive-strength = <0x07>; + phandle = <0x489>; + }; + + pcfg-pull-down-drv-level-8 { + bias-pull-down; + drive-strength = <0x08>; + phandle = <0x48a>; + }; + + pcfg-pull-down-drv-level-9 { + bias-pull-down; + drive-strength = <0x09>; + phandle = <0x48b>; + }; + + pcfg-pull-down-drv-level-10 { + bias-pull-down; + drive-strength = <0x0a>; + phandle = <0x48c>; + }; + + pcfg-pull-down-drv-level-11 { + bias-pull-down; + drive-strength = <0x0b>; + phandle = <0x48d>; + }; + + pcfg-pull-down-drv-level-12 { + bias-pull-down; + drive-strength = <0x0c>; + phandle = <0x48e>; + }; + + pcfg-pull-down-drv-level-13 { + bias-pull-down; + drive-strength = <0x0d>; + phandle = <0x48f>; + }; + + pcfg-pull-down-drv-level-14 { + bias-pull-down; + drive-strength = <0x0e>; + phandle = <0x490>; + }; + + pcfg-pull-down-drv-level-15 { + bias-pull-down; + drive-strength = <0x0f>; + phandle = <0x491>; + }; + + eth0 { + + eth0-pins { + rockchip,pins = <0x02 0x13 0x01 0x1ab>; + phandle = <0x492>; + }; + }; + + gmac0 { + + gmac0-miim { + rockchip,pins = <0x04 0x14 0x01 0x1ab 0x04 0x15 0x01 0x1ab>; + phandle = <0x493>; + }; + + gmac0-clkinout { + rockchip,pins = <0x04 0x13 0x01 0x1ab>; + phandle = <0x494>; + }; + + gmac0-rx-bus2 { + rockchip,pins = <0x02 0x11 0x01 0x1ab 0x02 0x12 0x01 0x1ab 0x04 0x12 0x01 0x1ab>; + phandle = <0x495>; + }; + + gmac0-tx-bus2 { + rockchip,pins = <0x02 0x0e 0x01 0x1ab 0x02 0x0f 0x01 0x1ab 0x02 0x10 0x01 0x1ab>; + phandle = <0x496>; + }; + + gmac0-rgmii-clk { + rockchip,pins = <0x02 0x08 0x01 0x1ab 0x02 0x0b 0x01 0x1ab>; + phandle = <0x497>; + }; + + gmac0-rgmii-bus { + rockchip,pins = <0x02 0x06 0x01 0x1ab 0x02 0x07 0x01 0x1ab 0x02 0x09 0x01 0x1ab 0x02 0x0a 0x01 0x1ab>; + phandle = <0x498>; + }; + + gmac0-ppsclk { + rockchip,pins = <0x02 0x14 0x01 0x1ab>; + phandle = <0x499>; + }; + + gmac0-ppstring { + rockchip,pins = <0x02 0x0d 0x01 0x1ab>; + phandle = <0x49a>; + }; + + gmac0-ptp-refclk { + rockchip,pins = <0x02 0x0c 0x01 0x1ab>; + phandle = <0x49b>; + }; + + gmac0-txer { + rockchip,pins = <0x04 0x16 0x01 0x1ab>; + phandle = <0x49c>; + }; + }; + + cam { + + mipicsi0-pwr { + rockchip,pins = <0x01 0x1a 0x00 0x1ab>; + phandle = <0x1ff>; + }; + + mipicsi1-pwr { + rockchip,pins = <0x01 0x1b 0x00 0x1ab>; + phandle = <0x200>; + }; + + mipidcphy0-pwr { + rockchip,pins = <0x02 0x14 0x00 0x1ab>; + phandle = <0x49d>; + }; + + mipidphy0-pwr { + rockchip,pins = <0x01 0x0a 0x00 0x1ab>; + phandle = <0x201>; + }; + }; + + headphone { + + hp-det { + rockchip,pins = <0x01 0x14 0x00 0x1ab>; + phandle = <0x1f2>; + }; + }; + + hym8563 { + + hym8563-int { + rockchip,pins = <0x00 0x08 0x00 0x1b1>; + phandle = <0x195>; + }; + }; + + lcd { + + lcd-rst-gpio { + rockchip,pins = <0x00 0x1b 0x00 0x1ab>; + phandle = <0xfb>; + }; + }; + + leds { + + work-leds-gpio { + rockchip,pins = <0x01 0x16 0x00 0x1b5>; + phandle = <0x1e9>; + }; + }; + + sdio-pwrseq { + + wifi-enable-h { + rockchip,pins = <0x00 0x14 0x00 0x1b1>; + phandle = <0x1fa>; + }; + }; + + touch { + + touch-gpio { + rockchip,pins = <0x03 0x11 0x00 0x1b5 0x03 0x10 0x00 0x1b1>; + phandle = <0x15f>; + }; + + ts_int_active { + rockchip,pins = <0x03 0x10 0x00 0x1b1>; + phandle = <0x160>; + }; + + ts_reset_active { + rockchip,pins = <0x03 0x11 0x00 0x1b1>; + phandle = <0x161>; + }; + + ts_int_suspend { + rockchip,pins = <0x03 0x10 0x00 0x1b5>; + phandle = <0x162>; + }; + + ts_reset_suspend { + rockchip,pins = <0x03 0x11 0x00 0x1b5>; + phandle = <0x163>; + }; + }; + + usb { + + vcc5v0-host-en { + rockchip,pins = <0x04 0x08 0x00 0x1ab>; + phandle = <0x1fe>; + }; + }; + + usb-typec { + + usbc0-int { + rockchip,pins = <0x03 0x0e 0x00 0x1b1>; + phandle = <0x190>; + }; + + typec5v-pwren { + rockchip,pins = <0x03 0x06 0x00 0x1ab>; + phandle = <0x1fc>; + }; + }; + + wireless-bluetooth { + + uart9-gpios { + rockchip,pins = <0x04 0x14 0x00 0x1ab>; + phandle = <0x207>; + }; + + bt-reset-gpio { + rockchip,pins = <0x00 0x16 0x00 0x1ab>; + phandle = <0x204>; + }; + + bt-wake-gpio { + rockchip,pins = <0x00 0x15 0x00 0x1ab>; + phandle = <0x205>; + }; + + bt-irq-gpio { + rockchip,pins = <0x00 0x00 0x00 0x1ab>; + phandle = <0x206>; + }; + }; + + wireless-wlan { + + wifi-host-wake-irq { + rockchip,pins = <0x00 0x0a 0x00 0x1b5>; + phandle = <0x208>; + }; + }; + + pcie { + + pcie20x1-0-clkreqn-m1 { + rockchip,pins = <0x04 0x0c 0x00 0x1b6>; + phandle = <0x1cd>; + }; + }; + }; + + usbdrd3_1 { + compatible = "rockchip,rk3588-dwc3\0rockchip,rk3399-dwc3"; + clocks = <0x02 0x1a6 0x02 0x1a5 0x02 0x1a4>; + clock-names = "ref\0suspend\0bus"; + #address-cells = <0x02>; + #size-cells = <0x02>; + ranges; + status = "okay"; + phandle = <0x49e>; + + usb@fc400000 { + compatible = "snps,dwc3"; + reg = <0x00 0xfc400000 0x00 0x400000>; + interrupts = <0x00 0xdd 0x04>; + power-domains = <0x06 0x1f>; + resets = <0x02 0x2a7>; + reset-names = "usb3-otg"; + dr_mode = "host"; + phys = <0x1b7 0x1b8>; + phy-names = "usb2-phy\0usb3-phy"; + phy_type = "utmi_wide"; + snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + snps,parkmode-disable-hs-quirk; + snps,parkmode-disable-ss-quirk; + status = "okay"; + phandle = <0x49f>; + }; + }; + + syscon@fd5b8000 { + compatible = "rockchip,pcie30-phy-grf\0syscon"; + reg = <0x00 0xfd5b8000 0x00 0x10000>; + phandle = <0x1da>; + }; + + syscon@fd5c0000 { + compatible = "rockchip,pipe-phy-grf\0syscon"; + reg = <0x00 0xfd5c0000 0x00 0x100>; + phandle = <0x1d9>; + }; + + syscon@fd5cc000 { + compatible = "rockchip,rk3588-usbdpphy-grf\0syscon"; + reg = <0x00 0xfd5cc000 0x00 0x4000>; + phandle = <0x1d7>; + }; + + syscon@fd5d4000 { + compatible = "rockchip,rk3588-usb2phy-grf\0syscon\0simple-mfd"; + reg = <0x00 0xfd5d4000 0x00 0x4000>; + #address-cells = <0x01>; + #size-cells = <0x01>; + phandle = <0x1d6>; + + usb2-phy@4000 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0x4000 0x10>; + interrupts = <0x00 0x18a 0x04>; + resets = <0x02 0xc0048 0x02 0x489>; + reset-names = "phy\0apb"; + clocks = <0x02 0x2b5>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy1"; + #clock-cells = <0x00>; + rockchip,usbctrl-grf = <0x75>; + status = "okay"; + phandle = <0x1d8>; + + otg-port { + #phy-cells = <0x00>; + status = "okay"; + phy-supply = <0x76>; + phandle = <0x1b7>; + }; + }; + }; + + syscon@fd5e4000 { + compatible = "rockchip,rk3588-hdptxphy-grf\0syscon"; + reg = <0x00 0xfd5e4000 0x00 0x100>; + phandle = <0x1d5>; + }; + + spdif-tx@fddb8000 { + compatible = "rockchip,rk3588-spdif\0rockchip,rk3568-spdif"; + reg = <0x00 0xfddb8000 0x00 0x1000>; + interrupts = <0x00 0xc6 0x04>; + dmas = <0xf4 0x16>; + dma-names = "tx"; + clock-names = "mclk\0hclk"; + clocks = <0x02 0x20f 0x02 0x20a>; + assigned-clocks = <0x02 0x20b>; + assigned-clock-parents = <0x02 0x05>; + power-domains = <0x06 0x19>; + #sound-dai-cells = <0x00>; + status = "disabled"; + phandle = <0x1e7>; + }; + + i2s@fddc8000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x00 0xfddc8000 0x00 0x1000>; + interrupts = <0x00 0xbc 0x04>; + clocks = <0x02 0x201 0x02 0x1fe>; + clock-names = "mclk_tx\0hclk"; + assigned-clocks = <0x02 0x1ff>; + assigned-clock-parents = <0x02 0x05>; + dmas = <0xf5 0x16>; + dma-names = "tx"; + power-domains = <0x06 0x19>; + resets = <0x02 0x391>; + reset-names = "tx-m"; + rockchip,playback-only; + #sound-dai-cells = <0x00>; + status = "disabled"; + phandle = <0x4a0>; + }; + + spdif-tx@fdde8000 { + compatible = "rockchip,rk3588-spdif\0rockchip,rk3568-spdif"; + reg = <0x00 0xfdde8000 0x00 0x1000>; + interrupts = <0x00 0xc5 0x04>; + dmas = <0xf4 0x08>; + dma-names = "tx"; + clock-names = "mclk\0hclk"; + clocks = <0x02 0x25c 0x02 0x258>; + assigned-clocks = <0x02 0x259>; + assigned-clock-parents = <0x02 0x05>; + power-domains = <0x06 0x1a>; + #sound-dai-cells = <0x00>; + status = "disabled"; + phandle = <0x4a1>; + }; + + i2s@fddf4000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x00 0xfddf4000 0x00 0x1000>; + interrupts = <0x00 0xba 0x04>; + clocks = <0x02 0x24c 0x02 0x24c 0x02 0x252>; + clock-names = "mclk_tx\0mclk_rx\0hclk"; + assigned-clocks = <0x02 0x249>; + assigned-clock-parents = <0x02 0x07>; + dmas = <0xf5 0x04>; + dma-names = "tx"; + power-domains = <0x06 0x1a>; + resets = <0x02 0x3ef>; + reset-names = "tx-m"; + rockchip,always-on; + rockchip,hdmi-path; + rockchip,playback-only; + #sound-dai-cells = <0x00>; + status = "okay"; + phandle = <0x1e1>; + }; + + i2s@fddf8000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x00 0xfddf8000 0x00 0x1000>; + interrupts = <0x00 0xbb 0x04>; + clocks = <0x02 0x23c 0x02 0x23c 0x02 0x238>; + clock-names = "mclk_tx\0mclk_rx\0hclk"; + assigned-clocks = <0x02 0x239>; + assigned-clock-parents = <0x02 0x05>; + dmas = <0xf5 0x15>; + dma-names = "rx"; + power-domains = <0x06 0x1a>; + resets = <0x02 0x3c3>; + reset-names = "rx-m"; + rockchip,capture-only; + rockchip,i2s-rx-wait-time-ms = <0x32>; + #sound-dai-cells = <0x00>; + status = "okay"; + phandle = <0x1f5>; + }; + + i2s@fde00000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x00 0xfde00000 0x00 0x1000>; + interrupts = <0x00 0xbe 0x04>; + clocks = <0x02 0x237 0x02 0x237 0x02 0x233>; + clock-names = "mclk_tx\0mclk_rx\0hclk"; + assigned-clocks = <0x02 0x234>; + assigned-clock-parents = <0x02 0x05>; + dmas = <0xf5 0x18>; + dma-names = "rx"; + power-domains = <0x06 0x1a>; + resets = <0x02 0x417>; + reset-names = "rx-m"; + rockchip,capture-only; + #sound-dai-cells = <0x00>; + status = "disabled"; + phandle = <0x4a2>; + }; + + spdif-rx@fde10000 { + compatible = "rockchip,rk3588-spdifrx\0rockchip,rk3308-spdifrx"; + reg = <0x00 0xfde10000 0x00 0x1000>; + interrupts = <0x00 0xc8 0x04>; + clocks = <0x02 0x260 0x02 0x25f>; + clock-names = "mclk\0hclk"; + assigned-clocks = <0x02 0x260>; + assigned-clock-parents = <0x02 0x05>; + dmas = <0x7a 0x16>; + dma-names = "rx"; + power-domains = <0x06 0x1a>; + resets = <0x02 0x3ff>; + reset-names = "spdifrx-m"; + #sound-dai-cells = <0x00>; + status = "disabled"; + phandle = <0x4a3>; + }; + + spdif-rx@fde18000 { + compatible = "rockchip,rk3588-spdifrx\0rockchip,rk3308-spdifrx"; + reg = <0x00 0xfde18000 0x00 0x1000>; + interrupts = <0x00 0xc9 0x04>; + clocks = <0x02 0x262 0x02 0x261>; + clock-names = "mclk\0hclk"; + assigned-clocks = <0x02 0x262>; + assigned-clock-parents = <0x02 0x05>; + dmas = <0x7a 0x17>; + dma-names = "rx"; + power-domains = <0x06 0x1a>; + resets = <0x02 0x401>; + reset-names = "spdifrx-m"; + #sound-dai-cells = <0x00>; + status = "disabled"; + phandle = <0x4a4>; + }; + + dp@fde60000 { + compatible = "rockchip,rk3588-dp"; + reg = <0x00 0xfde60000 0x00 0x4000>; + interrupts = <0x00 0xa2 0x04>; + clocks = <0x02 0x1e7 0x02 0x2cd 0x02 0x201 0x02 0x20d 0x04 0x02 0x1eb>; + clock-names = "apb\0aux\0i2s\0spdif\0hclk\0hdcp"; + assigned-clocks = <0x02 0x2cd>; + assigned-clock-rates = <0xf42400>; + resets = <0x02 0x389>; + phys = <0x1b9>; + power-domains = <0x06 0x19>; + #sound-dai-cells = <0x01>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <0x1ba>; + phandle = <0x1e8>; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + #address-cells = <0x01>; + #size-cells = <0x00>; + + endpoint@0 { + reg = <0x00>; + remote-endpoint = <0x1bb>; + status = "disabled"; + phandle = <0xe0>; + }; + + endpoint@1 { + reg = <0x01>; + remote-endpoint = <0x3f>; + status = "disabled"; + phandle = <0xe6>; + }; + + endpoint@2 { + reg = <0x02>; + remote-endpoint = <0x1bc>; + status = "okay"; + phandle = <0xee>; + }; + }; + + port@1 { + reg = <0x01>; + + endpoint { + phandle = <0x4a5>; + }; + }; + }; + }; + + hdmi@fdea0000 { + compatible = "rockchip,rk3588-dw-hdmi"; + reg = <0x00 0xfdea0000 0x00 0x10000 0x00 0xfdeb0000 0x00 0x10000>; + interrupts = <0x00 0xad 0x04 0x00 0xae 0x04 0x00 0xaf 0x04 0x00 0xb0 0x04 0x00 0x169 0x04>; + clocks = <0x02 0x224 0x02 0x266 0x02 0x225 0x02 0x226 0x02 0x24c 0x02 0x274 0x02 0x275 0x02 0x276 0x02 0x277 0x05 0x37>; + clock-names = "pclk\0hpd\0earc\0hdmitx_ref\0aud\0dclk_vp0\0dclk_vp1\0dclk_vp2\0dclk_vp3\0hclk_vo1\0link_clk"; + resets = <0x02 0x3d7 0x02 0x49d>; + reset-names = "ref\0hdp"; + power-domains = <0x06 0x1a>; + pinctrl-names = "default"; + pinctrl-0 = <0x1bd 0x1be 0x1bf 0x1c0>; + reg-io-width = <0x04>; + rockchip,grf = <0xc9>; + rockchip,vo1_grf = <0xdb>; + phys = <0x37>; + phy-names = "hdmi"; + #sound-dai-cells = <0x00>; + status = "disabled"; + enable-gpios = <0x10a 0x0a 0x00>; + phandle = <0x1e4>; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + #address-cells = <0x01>; + #size-cells = <0x00>; + phandle = <0x4a6>; + + endpoint@0 { + reg = <0x00>; + remote-endpoint = <0x1c1>; + status = "disabled"; + phandle = <0xe2>; + }; + + endpoint@1 { + reg = <0x01>; + remote-endpoint = <0x40>; + status = "okay"; + phandle = <0xe8>; + }; + + endpoint@2 { + reg = <0x02>; + remote-endpoint = <0x1c2>; + status = "disabled"; + phandle = <0xf0>; + }; + }; + }; + }; + + edp@fded0000 { + compatible = "rockchip,rk3588-edp"; + reg = <0x00 0xfded0000 0x00 0x1000>; + interrupts = <0x00 0xa4 0x04>; + clocks = <0x02 0x214 0x02 0x213 0x02 0x215 0x05>; + clock-names = "dp\0pclk\0spdif\0hclk"; + resets = <0x02 0x3e4 0x02 0x3e3>; + reset-names = "dp\0apb"; + phys = <0x1c3>; + phy-names = "dp"; + power-domains = <0x06 0x1a>; + rockchip,grf = <0xdb>; + #sound-dai-cells = <0x01>; + status = "disabled"; + phandle = <0x1e2>; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + #address-cells = <0x01>; + #size-cells = <0x00>; + + endpoint@0 { + reg = <0x00>; + remote-endpoint = <0x1c4>; + status = "disabled"; + phandle = <0xe1>; + }; + + endpoint@1 { + reg = <0x01>; + remote-endpoint = <0x1c5>; + status = "disabled"; + phandle = <0xe7>; + }; + + endpoint@2 { + reg = <0x02>; + remote-endpoint = <0x1c6>; + status = "disabled"; + phandle = <0xef>; + }; + }; + + port@1 { + reg = <0x01>; + + endpoint { + phandle = <0x4a7>; + }; + }; + }; + }; + + hdmirx-controller@fdee0000 { + compatible = "rockchip,rk3588-hdmirx-ctrler\0rockchip,hdmirx-ctrler"; + reg = <0x00 0xfdee0000 0x00 0x6000>; + reg-names = "hdmirx_regs"; + power-domains = <0x06 0x1a>; + rockchip,grf = <0xc9>; + rockchip,vo1_grf = <0xdb>; + interrupts = <0x00 0xb1 0x04 0x00 0x1b4 0x04 0x00 0xb3 0x04>; + interrupt-names = "cec\0hdmi\0dma"; + clocks = <0x02 0x21a 0x02 0x21f 0x02 0x2b2 0x02 0x21b 0x02 0x21c 0x02 0x232 0x05>; + clock-names = "aclk\0audio\0cr_para\0pclk\0ref\0hclk_s_hdmirx\0hclk_vo1"; + resets = <0x02 0x3d9 0x02 0x3da 0x02 0x3db 0x02 0x3b7>; + reset-names = "rst_a\0rst_p\0rst_ref\0rst_biu"; + pinctrl-0 = <0x1c7 0x1c8>; + pinctrl-names = "default"; + status = "okay"; + #sound-dai-cells = <0x01>; + hpd-trigger-level = <0x01>; + hdmirx-det-gpios = <0x129 0x1d 0x01>; + phandle = <0x1f4>; + }; + + pcie@fe150000 { + compatible = "rockchip,rk3588-pcie\0snps,dw-pcie"; + #address-cells = <0x03>; + #size-cells = <0x02>; + bus-range = <0x00 0x0f>; + clocks = <0x02 0x14e 0x02 0x153 0x02 0x149 0x02 0x158 0x02 0x15e 0x02 0x183>; + clock-names = "aclk_mst\0aclk_slv\0aclk_dbi\0pclk\0aux\0pipe"; + device_type = "pci"; + interrupts = <0x00 0x107 0x04 0x00 0x106 0x04 0x00 0x105 0x04 0x00 0x104 0x04 0x00 0x103 0x04>; + interrupt-names = "sys\0pmc\0msg\0legacy\0err"; + #interrupt-cells = <0x01>; + interrupt-map-mask = <0x00 0x00 0x00 0x07>; + interrupt-map = <0x00 0x00 0x00 0x01 0x1c9 0x00 0x00 0x00 0x00 0x02 0x1c9 0x01 0x00 0x00 0x00 0x03 0x1c9 0x02 0x00 0x00 0x00 0x04 0x1c9 0x03>; + linux,pci-domain = <0x00>; + num-ib-windows = <0x10>; + num-ob-windows = <0x10>; + num-viewport = <0x08>; + max-link-speed = <0x03>; + msi-map = <0x00 0x1ca 0x00 0x1000>; + num-lanes = <0x04>; + phys = <0x1cb>; + phy-names = "pcie-phy"; + power-domains = <0x06 0x22>; + ranges = <0x81000000 0x00 0xf0100000 0x00 0xf0100000 0x00 0x100000 0x82000000 0x00 0xf0200000 0x00 0xf0200000 0x00 0xe00000 0xc3000000 0x09 0x00 0x09 0x00 0x00 0x40000000>; + reg = <0x00 0xfe150000 0x00 0x10000 0x0a 0x40000000 0x00 0x400000 0x00 0xf0000000 0x00 0x100000>; + reg-names = "pcie-apb\0pcie-dbi\0config"; + resets = <0x02 0x20d 0x02 0x21c>; + reset-names = "pcie\0periph"; + rockchip,pipe-grf = <0x77>; + status = "okay"; + reset-gpios = <0x10a 0x0e 0x00>; + vpcie3v3-supply = <0x1cc>; + pinctrl-names = "default"; + pinctrl-0 = <0x1cd>; + phandle = <0x4a8>; + + legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0x00>; + #interrupt-cells = <0x01>; + interrupt-parent = <0x01>; + interrupts = <0x00 0x104 0x01>; + phandle = <0x1c9>; + }; + }; + + pcie@fe160000 { + compatible = "rockchip,rk3588-pcie\0snps,dw-pcie"; + #address-cells = <0x03>; + #size-cells = <0x02>; + bus-range = <0x10 0x1f>; + clocks = <0x02 0x14f 0x02 0x154 0x02 0x14a 0x02 0x159 0x02 0x15f 0x02 0x184>; + clock-names = "aclk_mst\0aclk_slv\0aclk_dbi\0pclk\0aux\0pipe"; + device_type = "pci"; + interrupts = <0x00 0x102 0x04 0x00 0x101 0x04 0x00 0x100 0x04 0x00 0xff 0x04 0x00 0xfe 0x04>; + interrupt-names = "sys\0pmc\0msg\0legacy\0err"; + #interrupt-cells = <0x01>; + interrupt-map-mask = <0x00 0x00 0x00 0x07>; + interrupt-map = <0x00 0x00 0x00 0x01 0x1ce 0x00 0x00 0x00 0x00 0x02 0x1ce 0x01 0x00 0x00 0x00 0x03 0x1ce 0x02 0x00 0x00 0x00 0x04 0x1ce 0x03>; + linux,pci-domain = <0x01>; + num-ib-windows = <0x10>; + num-ob-windows = <0x10>; + num-viewport = <0x08>; + max-link-speed = <0x03>; + msi-map = <0x1000 0x1ca 0x1000 0x1000>; + num-lanes = <0x02>; + phys = <0x1cb>; + phy-names = "pcie-phy"; + power-domains = <0x06 0x22>; + ranges = <0x81000000 0x00 0xf1100000 0x00 0xf1100000 0x00 0x100000 0x82000000 0x00 0xf1200000 0x00 0xf1200000 0x00 0xe00000 0xc3000000 0x09 0x40000000 0x09 0x40000000 0x00 0x40000000>; + reg = <0x00 0xfe160000 0x00 0x10000 0x0a 0x40400000 0x00 0x400000 0x00 0xf1000000 0x00 0x100000>; + reg-names = "pcie-apb\0pcie-dbi\0config"; + resets = <0x02 0x20e 0x02 0x21d>; + reset-names = "pcie\0periph"; + rockchip,pipe-grf = <0x77>; + status = "disabled"; + phandle = <0x4a9>; + + legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0x00>; + #interrupt-cells = <0x01>; + interrupt-parent = <0x01>; + interrupts = <0x00 0xff 0x01>; + phandle = <0x1ce>; + }; + }; + + pcie@fe170000 { + compatible = "rockchip,rk3588-pcie\0snps,dw-pcie"; + #address-cells = <0x03>; + #size-cells = <0x02>; + bus-range = <0x20 0x2f>; + clocks = <0x02 0x150 0x02 0x155 0x02 0x14b 0x02 0x15b 0x02 0x160 0x02 0x2c4>; + clock-names = "aclk_mst\0aclk_slv\0aclk_dbi\0pclk\0aux\0pipe"; + device_type = "pci"; + interrupts = <0x00 0xf3 0x04 0x00 0xf2 0x04 0x00 0xf1 0x04 0x00 0xf0 0x04 0x00 0xef 0x04>; + interrupt-names = "sys\0pmc\0msg\0legacy\0err"; + #interrupt-cells = <0x01>; + interrupt-map-mask = <0x00 0x00 0x00 0x07>; + interrupt-map = <0x00 0x00 0x00 0x01 0x1cf 0x00 0x00 0x00 0x00 0x02 0x1cf 0x01 0x00 0x00 0x00 0x03 0x1cf 0x02 0x00 0x00 0x00 0x04 0x1cf 0x03>; + linux,pci-domain = <0x02>; + num-ib-windows = <0x08>; + num-ob-windows = <0x08>; + num-viewport = <0x04>; + max-link-speed = <0x02>; + msi-map = <0x2000 0x112 0x2000 0x1000>; + num-lanes = <0x01>; + phys = <0x1d0 0x02>; + phy-names = "pcie-phy"; + ranges = <0x81000000 0x00 0xf2100000 0x00 0xf2100000 0x00 0x100000 0x82000000 0x00 0xf2200000 0x00 0xf2200000 0x00 0xe00000 0xc3000000 0x09 0x80000000 0x09 0x80000000 0x00 0x40000000>; + reg = <0x00 0xfe170000 0x00 0x10000 0x0a 0x40800000 0x00 0x400000 0x00 0xf2000000 0x00 0x100000>; + reg-names = "pcie-apb\0pcie-dbi\0config"; + resets = <0x02 0x20f 0x02 0x21e>; + reset-names = "pcie\0periph"; + rockchip,pipe-grf = <0x77>; + status = "okay"; + reset-gpios = <0x129 0x0c 0x00>; + phandle = <0x4aa>; + + legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0x00>; + #interrupt-cells = <0x01>; + interrupt-parent = <0x01>; + interrupts = <0x00 0xf0 0x01>; + phandle = <0x1cf>; + }; + }; + + uio@fe1b0000 { + compatible = "rockchip,uio-gmac"; + reg = <0x00 0xfe1b0000 0x00 0x10000>; + rockchip,ethernet = <0x1d1>; + status = "disabled"; + phandle = <0x4ab>; + }; + + ethernet@fe1b0000 { + local-mac-address = [42 ae fd 14 a7 64]; + compatible = "rockchip,rk3588-gmac\0snps,dwmac-4.20a"; + reg = <0x00 0xfe1b0000 0x00 0x10000>; + interrupts = <0x00 0xe3 0x04 0x00 0xe2 0x04>; + interrupt-names = "macirq\0eth_wake_irq"; + rockchip,grf = <0xc9>; + rockchip,php_grf = <0x77>; + clocks = <0x02 0x144 0x02 0x145 0x02 0x167 0x02 0x16c 0x02 0x142>; + clock-names = "stmmaceth\0clk_mac_ref\0pclk_mac\0aclk_mac\0ptp_ref"; + resets = <0x02 0x20a>; + reset-names = "stmmaceth"; + power-domains = <0x06 0x21>; + snps,mixed-burst; + snps,tso; + snps,axi-config = <0x1d2>; + snps,mtl-rx-config = <0x1d3>; + snps,mtl-tx-config = <0x1d4>; + status = "disabled"; + phandle = <0x1d1>; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <0x01>; + #size-cells = <0x00>; + phandle = <0x4ac>; + }; + + stmmac-axi-config { + snps,wr_osr_lmt = <0x04>; + snps,rd_osr_lmt = <0x08>; + snps,blen = <0x00 0x00 0x00 0x00 0x10 0x08 0x04>; + phandle = <0x1d2>; + }; + + rx-queues-config { + snps,rx-queues-to-use = <0x01>; + phandle = <0x1d3>; + + queue0 { + }; + }; + + tx-queues-config { + snps,tx-queues-to-use = <0x01>; + phandle = <0x1d4>; + + queue0 { + }; + }; + }; + + sata@fe220000 { + compatible = "rockchip,rk-ahci\0snps,dwc-ahci"; + reg = <0x00 0xfe220000 0x00 0x1000>; + clocks = <0x02 0x172 0x02 0x16f 0x02 0x175 0x02 0x164 0x02 0x17f>; + clock-names = "sata\0pmalive\0rxoob\0ref\0asic"; + interrupts = <0x00 0x112 0x04>; + interrupt-names = "hostc"; + phys = <0x1d0 0x01>; + phy-names = "sata-phy"; + ports-implemented = <0x01>; + status = "disabled"; + phandle = <0x4ad>; + }; + + phy@fed70000 { + compatible = "rockchip,rk3588-hdptx-phy"; + reg = <0x00 0xfed70000 0x00 0x2000>; + clocks = <0x02 0x2b5 0x02 0x268>; + clock-names = "ref\0apb"; + resets = <0x02 0x486 0x02 0xc003f 0x02 0xc0040 0x02 0xc0041>; + reset-names = "apb\0init\0cmn\0lane"; + rockchip,grf = <0x1d5>; + #phy-cells = <0x00>; + status = "disabled"; + phandle = <0x1c3>; + }; + + hdmiphy@fed70000 { + compatible = "rockchip,rk3588-hdptx-phy-hdmi"; + reg = <0x00 0xfed70000 0x00 0x2000>; + clocks = <0x02 0x2b5 0x02 0x268>; + clock-names = "ref\0apb"; + clock-output-names = "clk_hdmiphy_pixel1"; + #clock-cells = <0x00>; + resets = <0x02 0x491 0x02 0x486 0x02 0xc003f 0x02 0xc0040 0x02 0xc0041 0x02 0x48f 0x02 0x490>; + reset-names = "phy\0apb\0init\0cmn\0lane\0ropll\0lcpll"; + rockchip,grf = <0x1d5>; + #phy-cells = <0x00>; + status = "disabled"; + phandle = <0x37>; + }; + + phy@fed90000 { + compatible = "rockchip,rk3588-usbdp-phy"; + reg = <0x00 0xfed90000 0x00 0x10000>; + rockchip,u2phy-grf = <0x1d6>; + rockchip,usb-grf = <0x75>; + rockchip,usbdpphy-grf = <0x1d7>; + rockchip,vo-grf = <0x102>; + clocks = <0x02 0x2b6 0x02 0x280 0x02 0x26a 0x1d8>; + clock-names = "refclk\0immortal\0pclk\0utmi"; + resets = <0x02 0x2f 0x02 0x30 0x02 0x31 0x02 0x32 0x02 0x484>; + reset-names = "init\0cmn\0lane\0pcs_apb\0pma_apb"; + status = "okay"; + rockchip,dp-lane-mux = <0x00 0x01 0x02 0x03>; + phandle = <0x4ae>; + + dp-port { + #phy-cells = <0x00>; + status = "okay"; + phandle = <0x1b9>; + }; + + u3-port { + #phy-cells = <0x00>; + status = "okay"; + phandle = <0x1b8>; + }; + }; + + phy@fee10000 { + compatible = "rockchip,rk3588-naneng-combphy"; + reg = <0x00 0xfee10000 0x00 0x100>; + #phy-cells = <0x01>; + clocks = <0x02 0x2be 0x02 0x186 0x02 0x166>; + clock-names = "refclk\0apbclk\0phpclk"; + assigned-clocks = <0x02 0x2be>; + assigned-clock-rates = <0x5f5e100>; + resets = <0x02 0x20006 0x02 0x4d7>; + reset-names = "combphy-apb\0combphy"; + rockchip,pipe-grf = <0x77>; + rockchip,pipe-phy-grf = <0x1d9>; + rockchip,pcie1ln-sel-bits = <0x100 0x00 0x00 0x00>; + status = "okay"; + phandle = <0x1d0>; + }; + + phy@fee80000 { + compatible = "rockchip,rk3588-pcie3-phy"; + reg = <0x00 0xfee80000 0x00 0x20000>; + #phy-cells = <0x00>; + clocks = <0x02 0x188 0x02 0x166>; + clock-names = "pclk\0phpclk"; + resets = <0x02 0x2000a>; + reset-names = "phy"; + rockchip,pipe-grf = <0x77>; + rockchip,phy-grf = <0x1da>; + status = "okay"; + rockchip,pcie30-phymode = <0x04>; + phandle = <0x1cb>; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <0x1db 0x01>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <0x1b7740>; + poll-interval = <0x64>; + phandle = <0x4af>; + + vol-up-key { + label = "volume up"; + linux,code = <0x73>; + press-threshold-microvolt = <0x4268>; + }; + + vol-down-key { + label = "volume down"; + linux,code = <0x72>; + press-threshold-microvolt = <0x65ce8>; + }; + + menu-key { + label = "menu"; + linux,code = <0x8b>; + press-threshold-microvolt = <0xd9490>; + }; + + back-key { + label = "back"; + linux,code = <0x9e>; + press-threshold-microvolt = <0x12d838>; + }; + }; + + backlight { + compatible = "pwm-backlight"; + brightness-levels = <0x00 0x14 0x14 0x15 0x15 0x16 0x16 0x17 0x17 0x18 0x18 0x19 0x19 0x1a 0x1a 0x1b 0x1b 0x1c 0x1c 0x1d 0x1d 0x1e 0x1e 0x1f 0x1f 0x20 0x20 0x21 0x21 0x22 0x22 0x23 0x23 0x24 0x24 0x25 0x25 0x26 0x26 0x27 0x28 0x29 0x2a 0x2b 0x2c 0x2d 0x2e 0x2f 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3a 0x3b 0x3c 0x3d 0x3e 0x3f 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4a 0x4b 0x4c 0x4d 0x4e 0x4f 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5a 0x5b 0x5c 0x5d 0x5e 0x5f 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6a 0x6b 0x6c 0x6d 0x6e 0x6f 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7a 0x7b 0x7c 0x7d 0x7e 0x7f 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9a 0x9b 0x9c 0x9d 0x9e 0x9f 0xa0 0xa1 0xa2 0xa3 0xa4 0xa5 0xa6 0xa7 0xa8 0xa9 0xaa 0xab 0xac 0xad 0xae 0xaf 0xb0 0xb1 0xb2 0xb3 0xb4 0xb5 0xb6 0xb7 0xb8 0xb9 0xba 0xbb 0xbc 0xbd 0xbe 0xbf 0xc0 0xc1 0xc2 0xc3 0xc4 0xc5 0xc6 0xc7 0xc8 0xc9 0xca 0xcb 0xcc 0xcd 0xce 0xcf 0xd0 0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 0xd7 0xd8 0xd9 0xda 0xdb 0xdc 0xdd 0xde 0xdf 0xe0 0xe1 0xe2 0xe3 0xe4 0xe5 0xe6 0xe7 0xe8 0xe9 0xea 0xeb 0xec 0xed 0xee 0xef 0xf0 0xf1 0xf2 0xf3 0xf4 0xf5 0xf6 0xf7 0xf8 0xf9 0xfa 0xfb 0xfc 0xfd 0xfe 0xff>; + default-brightness-level = <0xc8>; + pwms = <0x1dc 0x00 0x61a8 0x00>; + status = "okay"; + phandle = <0xf8>; + }; + + bt-sco { + status = "disabled"; + compatible = "delta,dfbmcs320"; + #sound-dai-cells = <0x01>; + phandle = <0x1de>; + }; + + bt-sound { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,format = "dsp_a"; + simple-audio-card,bitclock-inversion; + simple-audio-card,mclk-fs = <0x100>; + simple-audio-card,name = "rockchip,bt"; + phandle = <0x4b0>; + + simple-audio-card,cpu { + sound-dai = <0x1dd>; + }; + + simple-audio-card,codec { + sound-dai = <0x1de 0x01>; + }; + }; + + edp0-sound { + status = "disabled"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <0x80>; + rockchip,card-name = "rockchip-edp0"; + rockchip,cpu = <0x1df>; + rockchip,codec = <0x1e0 0x00>; + phandle = <0x4b1>; + }; + + edp1-sound { + status = "disabled"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <0x80>; + rockchip,card-name = "rockchip-edp1"; + rockchip,cpu = <0x1e1>; + rockchip,codec = <0x1e2 0x00>; + phandle = <0x4b2>; + }; + + hdmi0-sound { + status = "okay"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <0x80>; + rockchip,card-name = "rockchip-hdmi0"; + rockchip,cpu = <0x1df>; + rockchip,codec = <0x1e3>; + rockchip,jack-det; + phandle = <0x4b3>; + }; + + hdmi1-sound { + status = "okay"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <0x80>; + rockchip,card-name = "rockchip-hdmi1"; + rockchip,cpu = <0x1e1>; + rockchip,codec = <0x1e4>; + rockchip,jack-det; + phandle = <0x4b4>; + }; + + dp0-sound { + status = "okay"; + compatible = "rockchip,hdmi"; + rockchip,card-name = "rockchip-dp0"; + rockchip,mclk-fs = <0x200>; + rockchip,cpu = <0x1e5>; + rockchip,codec = <0x1e6 0x01>; + rockchip,jack-det; + phandle = <0x4b5>; + }; + + dp1-sound { + status = "disabled"; + compatible = "rockchip,hdmi"; + rockchip,card-name = "rockchip-dp1"; + rockchip,mclk-fs = <0x200>; + rockchip,cpu = <0x1e7>; + rockchip,codec = <0x1e8 0x01>; + rockchip,jack-det; + phandle = <0x4b6>; + }; + + leds { + compatible = "gpio-leds"; + phandle = <0x4b7>; + + work { + gpios = <0x129 0x16 0x00>; + linux,default-trigger = "heartbeat"; + pinctrl-names = "default"; + pinctrl-0 = <0x1e9>; + phandle = <0x4b8>; + }; + }; + + spdif-tx0-dc { + status = "disabled"; + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0x00>; + phandle = <0x1eb>; + }; + + spdif-tx0-sound { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,mclk-fs = <0x80>; + simple-audio-card,name = "rockchip,spdif-tx0"; + phandle = <0x4b9>; + + simple-audio-card,cpu { + sound-dai = <0x1ea>; + }; + + simple-audio-card,codec { + sound-dai = <0x1eb>; + }; + }; + + spdif-tx1-dc { + status = "disabled"; + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0x00>; + phandle = <0x1ed>; + }; + + spdif-tx1-sound { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,mclk-fs = <0x80>; + simple-audio-card,name = "rockchip,spdif-tx1"; + phandle = <0x4ba>; + + simple-audio-card,cpu { + sound-dai = <0x1ec>; + }; + + simple-audio-card,codec { + sound-dai = <0x1ed>; + }; + }; + + test-power { + status = "okay"; + }; + + vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0xb71b00>; + regulator-max-microvolt = <0xb71b00>; + phandle = <0x1ee>; + }; + + vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x4c4b40>; + regulator-max-microvolt = <0x4c4b40>; + vin-supply = <0x1ee>; + phandle = <0x79>; + }; + + vcc5v0-usbdcin { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usbdcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x4c4b40>; + regulator-max-microvolt = <0x4c4b40>; + vin-supply = <0x1ee>; + phandle = <0x1ef>; + }; + + vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x4c4b40>; + regulator-max-microvolt = <0x4c4b40>; + vin-supply = <0x1ef>; + phandle = <0x1fb>; + }; + + reserved-memory { + #address-cells = <0x02>; + #size-cells = <0x02>; + ranges; + + cma { + compatible = "shared-dma-pool"; + reusable; + reg = <0x00 0x10000000 0x00 0x10000000>; + linux,cma-default; + size = <0x00 0x800000>; + }; + + drm-logo@0 { + compatible = "rockchip,drm-logo"; + reg = <0x00 0xede00000 0x00 0x2e0000>; + phandle = <0x38>; + status = "disabled"; + }; + + drm-cubic-lut@0 { + compatible = "rockchip,drm-cubic-lut"; + reg = <0x00 0x00 0x00 0x00>; + phandle = <0x4bb>; + status = "disabled"; + }; + + ramoops@110000 { + compatible = "ramoops"; + reg = <0x00 0x110000 0x00 0xe0000>; + boot-log-size = <0x8000>; + boot-log-count = <0x01>; + console-size = <0x80000>; + pmsg-size = <0x30000>; + ftrace-size = <0x00>; + record-size = <0x14000>; + phandle = <0x4bc>; + }; + + minidump-smem@1f0000 { + reg = <0x00 0x1f0000 0x00 0x100>; + no-map; + status = "disabled"; + phandle = <0x20a>; + }; + + minidump-mem@c000000 { + reg = <0x00 0xc000000 0x00 0x2000000>; + no-map; + status = "disabled"; + phandle = <0x20b>; + }; + }; + + es8388-sound { + status = "okay"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip-es8388"; + hp-det-gpio = <0x129 0x14 0x01>; + io-channels = <0x1db 0x03>; + io-channel-names = "adc-detect"; + keyup-threshold-microvolt = <0x1b7740>; + poll-interval = <0x64>; + spk-con-gpio = <0x10a 0x02 0x00>; + hp-con-gpio = <0x10a 0x07 0x00>; + rockchip,pre-power-on-delay-ms = <0x1e>; + rockchip,post-power-down-delay-ms = <0x28>; + rockchip,format = "i2s"; + rockchip,mclk-fs = <0x100>; + rockchip,cpu = <0x1f0>; + rockchip,codec = <0x1f1>; + rockchip,audio-routing = "Headphone\0LOUT1\0Headphone\0ROUT1\0Speaker\0LOUT2\0Speaker\0ROUT2\0Headphone\0Headphone Power\0Headphone\0Headphone Power\0Speaker\0Speaker Power\0Speaker\0Speaker Power\0LINPUT1\0Main Mic\0LINPUT2\0Main Mic\0RINPUT1\0Headset Mic\0RINPUT2\0Headset Mic"; + pinctrl-names = "default"; + pinctrl-0 = <0x1f2>; + phandle = <0x4bd>; + + play-pause-key { + label = "playpause"; + linux,code = <0xa4>; + press-threshold-microvolt = <0x7d0>; + }; + }; + + pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <0x02>; + pwms = <0x1f3 0x00 0xc350 0x00>; + cooling-levels = <0x00 0x32 0x64 0x96 0xc8 0xff>; + rockchip,temp-trips = <0xc350 0x01 0xd6d8 0x02 0xea60 0x03 0xfde8 0x04 0x11170 0x05>; + phandle = <0x4be>; + }; + + hdmiin-sound { + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <0x80>; + rockchip,format = "i2s"; + rockchip,bitclock-master = <0x1f4>; + rockchip,frame-master = <0x1f4>; + rockchip,card-name = "rockchip,hdmiin"; + rockchip,cpu = <0x1f5>; + rockchip,codec = <0x1f4 0x00>; + rockchip,jack-det; + }; + + pcie20-avdd0v85 { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd0v85"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <0xcf850>; + regulator-max-microvolt = <0xcf850>; + vin-supply = <0x1f6>; + phandle = <0x4bf>; + }; + + pcie20-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <0x1b7740>; + regulator-max-microvolt = <0x1b7740>; + vin-supply = <0x1f7>; + phandle = <0x4c0>; + }; + + pcie30-avdd0v75 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v75"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <0xb71b0>; + regulator-max-microvolt = <0xb71b0>; + vin-supply = <0x1f8>; + phandle = <0x4c1>; + }; + + pcie30-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <0x1b7740>; + regulator-max-microvolt = <0x1b7740>; + vin-supply = <0x1f7>; + phandle = <0x4c2>; + }; + + sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <0x1f9>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <0x1fa>; + post-power-on-delay-ms = <0xc8>; + reset-gpios = <0xfa 0x14 0x01>; + phandle = <0x127>; + }; + + rk-headset { + status = "disabled"; + compatible = "rockchip_headset"; + headset_gpio = <0x129 0x1d 0x01>; + pinctrl-names = "default"; + pinctrl-0 = <0x1f2>; + io-channels = <0x1db 0x03>; + phandle = <0x4c3>; + }; + + vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x10c8e0>; + regulator-max-microvolt = <0x10c8e0>; + vin-supply = <0x79>; + phandle = <0x172>; + }; + + vbus5v0-typec { + compatible = "regulator-fixed"; + regulator-name = "vbus5v0_typec"; + regulator-min-microvolt = <0x4c4b40>; + regulator-max-microvolt = <0x4c4b40>; + enable-active-high; + gpio = <0x119 0x06 0x00>; + vin-supply = <0x1fb>; + pinctrl-names = "default"; + pinctrl-0 = <0x1fc>; + phandle = <0x191>; + }; + + vcc3v3-lcd0-n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd0_n"; + regulator-boot-on; + enable-active-high; + gpio = <0x1fd 0x11 0x00>; + vin-supply = <0x18e>; + phandle = <0xf9>; + }; + + vcc3v3-pcie30 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie30"; + regulator-min-microvolt = <0x325aa0>; + regulator-max-microvolt = <0x325aa0>; + enable-active-high; + gpios = <0x1fd 0x15 0x00>; + startup-delay-us = <0x1388>; + vin-supply = <0x1ee>; + phandle = <0x1cc>; + }; + + vcc5v0-host { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <0x4c4b40>; + regulator-max-microvolt = <0x4c4b40>; + enable-active-high; + gpio = <0x10a 0x08 0x00>; + vin-supply = <0x1fb>; + pinctrl-names = "default"; + pinctrl-0 = <0x1fe>; + phandle = <0x76>; + }; + + vcc-mipicsi0-regulator { + compatible = "regulator-fixed"; + gpio = <0x129 0x1a 0x00>; + pinctrl-names = "default"; + pinctrl-0 = <0x1ff>; + regulator-name = "vcc_mipicsi0"; + enable-active-high; + phandle = <0x4c4>; + }; + + vcc-mipicsi1-regulator { + compatible = "regulator-fixed"; + gpio = <0x129 0x1b 0x00>; + pinctrl-names = "default"; + pinctrl-0 = <0x200>; + regulator-name = "vcc_mipicsi1"; + enable-active-high; + phandle = <0x4c5>; + }; + + vcc-mipidcphy0-regulator { + compatible = "regulator-fixed"; + gpio = <0x129 0x0a 0x00>; + pinctrl-names = "default"; + pinctrl-0 = <0x201>; + regulator-name = "vcc_mipidphy0"; + enable-active-high; + phandle = <0x15b>; + }; + + vcc-3v3-sd-s0-regulator { + compatible = "regulator-fixed"; + gpio = <0xfa 0x0f 0x00>; + pinctrl-names = "default"; + pinctrl-0 = <0x202>; + regulator-name = "vcc_3v3_sd_s0"; + enable-active-high; + phandle = <0x125>; + }; + + wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <0x1f9>; + clock-names = "ext_clock"; + uart_rts_gpios = <0x10a 0x14 0x01>; + pinctrl-names = "default\0rts_gpio"; + pinctrl-0 = <0x203 0x204 0x205 0x206>; + pinctrl-1 = <0x207>; + BT,reset_gpio = <0xfa 0x16 0x00>; + BT,wake_gpio = <0xfa 0x15 0x00>; + BT,wake_host_irq = <0xfa 0x00 0x00>; + status = "okay"; + phandle = <0x4c6>; + }; + + wireless-wlan { + compatible = "wlan-platdata"; + wifi_chip_type = "ap6398s"; + pinctrl-names = "default"; + pinctrl-0 = <0x208>; + WIFI,host_wake_irq = <0xfa 0x0a 0x00>; + WIFI,poweren_gpio = <0xfa 0x14 0x00>; + status = "okay"; + phandle = <0x4c7>; + }; + + chosen { + bootargs = "storagemedia=emmc androidboot.storagemedia=emmc androidboot.mode=normal dsi-0=1 androidboot.verifiedbootstate=orange ro rootwait earlycon=uart8250,mmio32,0xfeb50000 console=ttyFIQ0 irqchip.gicv3_pseudo_nmi=0 root=PARTLABEL=rootfs rootfstype=ext4 overlayroot=device:dev=PARTLABEL=userdata,fstype=ext4,mkfs=1 rcupdate.rcu_expedited=1 rcu_nocbs=all net.ifnames=0 fastboot=n comm-04/19/2026 androidboot.fwver=ddr-v1.19-ff1a08bde6,spl-v1.13,bl31-v1.51,bl32-v1.20,uboot--boot rockchip_pm_domains.always_on=1"; + phandle = <0x4c8>; + }; + + cspmu@fd10c000 { + compatible = "rockchip,cspmu"; + reg = <0x00 0xfd10c000 0x00 0x1000 0x00 0xfd10d000 0x00 0x1000 0x00 0xfd10e000 0x00 0x1000 0x00 0xfd10f000 0x00 0x1000 0x00 0xfd12c000 0x00 0x1000 0x00 0xfd12d000 0x00 0x1000 0x00 0xfd12e000 0x00 0x1000 0x00 0xfd12f000 0x00 0x1000>; + phandle = <0x4c9>; + }; + + debug@fd104000 { + compatible = "rockchip,debug"; + reg = <0x00 0xfd104000 0x00 0x1000 0x00 0xfd105000 0x00 0x1000 0x00 0xfd106000 0x00 0x1000 0x00 0xfd107000 0x00 0x1000 0x00 0xfd124000 0x00 0x1000 0x00 0xfd125000 0x00 0x1000 0x00 0xfd126000 0x00 0x1000 0x00 0xfd127000 0x00 0x1000>; + phandle = <0x4ca>; + }; + + fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <0x02>; + rockchip,wake-irq = <0x00>; + rockchip,irq-mode-enable = <0x01>; + rockchip,baudrate = <0x16e360>; + interrupts = <0x00 0x1a7 0x08>; + pinctrl-names = "default"; + pinctrl-0 = <0x209>; + status = "okay"; + phandle = <0x4cb>; + }; + + minidump { + compatible = "rockchip,minidump"; + smem-region = <0x20a>; + minidump-region = <0x20b>; + status = "disabled"; + phandle = <0x4cc>; + }; + + __symbols__ { + spll = "/clocks/spll"; + xin32k = "/clocks/xin32k"; + xin24m = "/clocks/xin24m"; + hclk_vo1 = "/clocks/hclk_vo1@fd7c08ec"; + aclk_vdpu_low_pre = "/clocks/aclk_vdpu_low_pre@fd7c08b0"; + hclk_vo0 = "/clocks/hclk_vo0@fd7c08dc"; + hclk_usb = "/clocks/hclk_usb@fd7c08a8"; + hclk_nvm = "/clocks/hclk_nvm@fd7c087c"; + aclk_usb = "/clocks/aclk_usb@fd7c08a8"; + hclk_isp1_pre = "/clocks/hclk_isp1_pre@fd7c0868"; + aclk_isp1_pre = "/clocks/aclk_isp1_pre@fd7c0868"; + aclk_rkvdec0_pre = "/clocks/aclk_rkvdec0_pre@fd7c08a0"; + hclk_rkvdec0_pre = "/clocks/hclk_rkvdec0_pre@fd7c08a0"; + aclk_rkvdec1_pre = "/clocks/aclk_rkvdec1_pre@fd7c08a4"; + hclk_rkvdec1_pre = "/clocks/hclk_rkvdec1_pre@fd7c08a4"; + aclk_jpeg_decoder_pre = "/clocks/aclk_jpeg_decoder_pre@fd7c08b0"; + aclk_rkvenc1_pre = "/clocks/aclk_rkvenc1_pre@fd7c08c0"; + hclk_rkvenc1_pre = "/clocks/hclk_rkvenc1_pre@fd7c08c0"; + aclk_hdcp0_pre = "/clocks/aclk_hdcp0_pre@fd7c08dc"; + aclk_hdcp1_pre = "/clocks/aclk_hdcp1_pre@fd7c08ec"; + pclk_av1_pre = "/clocks/pclk_av1_pre@fd7c0910"; + aclk_av1_pre = "/clocks/aclk_av1_pre@fd7c0910"; + hclk_sdio_pre = "/clocks/hclk_sdio_pre@fd7c092c"; + pclk_vo0_grf = "/clocks/pclk_vo0_grf@fd7c08dc"; + pclk_vo1_grf = "/clocks/pclk_vo1_grf@fd7c08ec"; + mclkin_i2s0 = "/clocks/mclkin-i2s0"; + mclkin_i2s1 = "/clocks/mclkin-i2s1"; + mclkin_i2s2 = "/clocks/mclkin-i2s2"; + mclkin_i2s3 = "/clocks/mclkin-i2s3"; + mclkout_i2s0 = "/clocks/mclkout-i2s0@fd58c318"; + mclkout_i2s1 = "/clocks/mclkout-i2s1@fd58c318"; + mclkout_i2s1m1 = "/clocks/mclkout-i2s1@fd58a000"; + mclkout_i2s2 = "/clocks/mclkout-i2s2@fd58c318"; + mclkout_i2s3 = "/clocks/mclkout-i2s3@fd58c318"; + cpu_l0 = "/cpus/cpu@0"; + cpu_l1 = "/cpus/cpu@100"; + cpu_l2 = "/cpus/cpu@200"; + cpu_l3 = "/cpus/cpu@300"; + cpu_b0 = "/cpus/cpu@400"; + cpu_b1 = "/cpus/cpu@500"; + cpu_b2 = "/cpus/cpu@600"; + cpu_b3 = "/cpus/cpu@700"; + CPU_SLEEP = "/cpus/idle-states/cpu-sleep"; + l2_cache_l0 = "/cpus/l2-cache-l0"; + l2_cache_l1 = "/cpus/l2-cache-l1"; + l2_cache_l2 = "/cpus/l2-cache-l2"; + l2_cache_l3 = "/cpus/l2-cache-l3"; + l2_cache_b0 = "/cpus/l2-cache-b0"; + l2_cache_b1 = "/cpus/l2-cache-b1"; + l2_cache_b2 = "/cpus/l2-cache-b2"; + l2_cache_b3 = "/cpus/l2-cache-b3"; + l3_cache = "/cpus/l3-cache"; + cluster0_opp_table = "/cluster0-opp-table"; + cluster1_opp_table = "/cluster1-opp-table"; + cluster2_opp_table = "/cluster2-opp-table"; + arm_pmu = "/arm-pmu"; + csi2_dcphy0 = "/csi2-dcphy0"; + csi2_dcphy1 = "/csi2-dcphy1"; + csi2_dphy0 = "/csi2-dphy0"; + mipidphy0_in_ucam0 = "/csi2-dphy0/ports/port@0/endpoint@1"; + csidphy0_out = "/csi2-dphy0/ports/port@1/endpoint@0"; + csi2_dphy1 = "/csi2-dphy1"; + csi2_dphy2 = "/csi2-dphy2"; + csi2_dphy3 = "/csi2-dphy3"; + csi2_dphy4 = "/csi2-dphy4"; + csi2_dphy5 = "/csi2-dphy5"; + display_subsystem = "/display-subsystem"; + route_dp0 = "/display-subsystem/route/route-dp0"; + route_dsi0 = "/display-subsystem/route/route-dsi0"; + route_dsi1 = "/display-subsystem/route/route-dsi1"; + route_edp0 = "/display-subsystem/route/route-edp0"; + route_edp1 = "/display-subsystem/route/route-edp1"; + route_hdmi0 = "/display-subsystem/route/route-hdmi0"; + route_rgb = "/display-subsystem/route/route-rgb"; + route_dp1 = "/display-subsystem/route/route-dp1"; + route_hdmi1 = "/display-subsystem/route/route-hdmi1"; + dmc = "/dmc"; + dmc_opp_table = "/dmc-opp-table"; + dmcdbg = "/dmcdbg"; + scmi = "/firmware/scmi"; + scmi_clk = "/firmware/scmi/protocol@14"; + scmi_reset = "/firmware/scmi/protocol@16"; + sdei = "/firmware/sdei"; + optee = "/firmware/optee"; + jpege_ccu = "/jpege-ccu"; + mipi_dcphy1 = "/mipi-dcphy-dummy"; + mipi_dcphy0 = "/mipi-dcphy-dummy"; + mipi0_csi2 = "/mipi0-csi2"; + mipi1_csi2 = "/mipi1-csi2"; + mipi2_csi2 = "/mipi2-csi2"; + mipi2_csi2_input = "/mipi2-csi2/ports/port@0/endpoint@1"; + mipi2_csi2_output = "/mipi2-csi2/ports/port@1/endpoint@0"; + mipi3_csi2 = "/mipi3-csi2"; + mipi4_csi2 = "/mipi4-csi2"; + mipi5_csi2 = "/mipi5-csi2"; + mpp_srv = "/mpp-srv"; + rkcif_dvp = "/rkcif-dvp"; + rkcif_dvp_sditf = "/rkcif-dvp-sditf"; + rkcif_mipi_lvds = "/rkcif-mipi-lvds"; + rkcif_mipi_lvds_sditf = "/rkcif-mipi-lvds-sditf"; + rkcif_mipi_lvds_sditf_vir1 = "/rkcif-mipi-lvds-sditf-vir1"; + rkcif_mipi_lvds_sditf_vir2 = "/rkcif-mipi-lvds-sditf-vir2"; + rkcif_mipi_lvds_sditf_vir3 = "/rkcif-mipi-lvds-sditf-vir3"; + rkcif_mipi_lvds1 = "/rkcif-mipi-lvds1"; + rkcif_mipi_lvds1_sditf = "/rkcif-mipi-lvds1-sditf"; + rkcif_mipi_lvds1_sditf_vir1 = "/rkcif-mipi-lvds1-sditf-vir1"; + rkcif_mipi_lvds1_sditf_vir2 = "/rkcif-mipi-lvds1-sditf-vir2"; + rkcif_mipi_lvds1_sditf_vir3 = "/rkcif-mipi-lvds1-sditf-vir3"; + rkcif_mipi_lvds2 = "/rkcif-mipi-lvds2"; + cif_mipi2_in0 = "/rkcif-mipi-lvds2/port/endpoint"; + rkcif_mipi_lvds2_sditf = "/rkcif-mipi-lvds2-sditf"; + mipi_lvds2_sditf = "/rkcif-mipi-lvds2-sditf/port/endpoint"; + rkcif_mipi_lvds2_sditf_vir1 = "/rkcif-mipi-lvds2-sditf-vir1"; + rkcif_mipi_lvds2_sditf_vir2 = "/rkcif-mipi-lvds2-sditf-vir2"; + rkcif_mipi_lvds2_sditf_vir3 = "/rkcif-mipi-lvds2-sditf-vir3"; + rkcif_mipi_lvds3 = "/rkcif-mipi-lvds3"; + rkcif_mipi_lvds3_sditf = "/rkcif-mipi-lvds3-sditf"; + rkcif_mipi_lvds3_sditf_vir1 = "/rkcif-mipi-lvds3-sditf-vir1"; + rkcif_mipi_lvds3_sditf_vir2 = "/rkcif-mipi-lvds3-sditf-vir2"; + rkcif_mipi_lvds3_sditf_vir3 = "/rkcif-mipi-lvds3-sditf-vir3"; + rkcif_mipi_lvds4 = "/rkcif-mipi-lvds4"; + rkcif_mipi_lvds4_sditf = "/rkcif-mipi-lvds4-sditf"; + rkcif_mipi_lvds4_sditf_vir1 = "/rkcif-mipi-lvds4-sditf-vir1"; + rkcif_mipi_lvds4_sditf_vir2 = "/rkcif-mipi-lvds4-sditf-vir2"; + rkcif_mipi_lvds4_sditf_vir3 = "/rkcif-mipi-lvds4-sditf-vir3"; + rkcif_mipi_lvds5 = "/rkcif-mipi-lvds5"; + rkcif_mipi_lvds5_sditf = "/rkcif-mipi-lvds5-sditf"; + rkcif_mipi_lvds5_sditf_vir1 = "/rkcif-mipi-lvds5-sditf-vir1"; + rkisp0_vir0 = "/rkisp0-vir0"; + isp0_vir0 = "/rkisp0-vir0/port/endpoint@0"; + rkisp0_vir1 = "/rkisp0-vir1"; + rkisp0_vir2 = "/rkisp0-vir2"; + rkisp0_vir3 = "/rkisp0-vir3"; + rkisp1_vir0 = "/rkisp1-vir0"; + rkisp1_vir1 = "/rkisp1-vir1"; + rkisp1_vir2 = "/rkisp1-vir2"; + rkisp1_vir3 = "/rkisp1-vir3"; + rkispp0_vir0 = "/rkispp0-vir0"; + rkispp1_vir0 = "/rkispp1-vir0"; + rkvenc_ccu = "/rkvenc-ccu"; + rkvtunnel = "/rkvtunnel"; + rockchip_suspend = "/rockchip-suspend"; + rockchip_system_monitor = "/rockchip-system-monitor"; + thermal_zones = "/thermal-zones"; + soc_thermal = "/thermal-zones/soc-thermal"; + threshold = "/thermal-zones/soc-thermal/trips/trip-point-0"; + target = "/thermal-zones/soc-thermal/trips/trip-point-1"; + soc_crit = "/thermal-zones/soc-thermal/trips/soc-crit"; + bigcore0_thermal = "/thermal-zones/bigcore0-thermal"; + bigcore0_crit = "/thermal-zones/bigcore0-thermal/trips/bigcore0-crit"; + bigcore1_thermal = "/thermal-zones/bigcore1-thermal"; + bigcore1_crit = "/thermal-zones/bigcore1-thermal/trips/bigcore1-crit"; + little_core_thermal = "/thermal-zones/littlecore-thermal"; + litcore_crit = "/thermal-zones/littlecore-thermal/trips/litcore-crit"; + center_thermal = "/thermal-zones/center-thermal"; + center_crit = "/thermal-zones/center-thermal/trips/center-crit"; + gpu_thermal = "/thermal-zones/gpu-thermal"; + gpu_crit = "/thermal-zones/gpu-thermal/trips/gpu-crit"; + npu_thermal = "/thermal-zones/npu-thermal"; + npu_crit = "/thermal-zones/npu-thermal/trips/npu-crit"; + scmi_shmem = "/sram@10f000/sram@0"; + gpu = "/gpu@fb000000"; + gpu_opp_table = "/gpu-opp-table"; + usbdrd3_0 = "/usbdrd3_0"; + usbdrd_dwc3_0 = "/usbdrd3_0/usb@fc000000"; + dwc3_0_role_switch = "/usbdrd3_0/usb@fc000000/port/endpoint@0"; + usb_host0_ehci = "/usb@fc800000"; + usb_host0_ohci = "/usb@fc840000"; + usb_host1_ehci = "/usb@fc880000"; + usb_host1_ohci = "/usb@fc8c0000"; + mmu600_pcie = "/iommu@fc900000"; + mmu600_php = "/iommu@fcb00000"; + usbhost3_0 = "/usbhost3_0"; + usbhost_dwc3_0 = "/usbhost3_0/usb@fcd00000"; + pmu0_grf = "/syscon@fd588000"; + reboot_mode = "/syscon@fd588000/reboot-mode"; + pmu1_grf = "/syscon@fd58a000"; + sys_grf = "/syscon@fd58c000"; + rgb = "/syscon@fd58c000/rgb"; + rgb_in_vp3 = "/syscon@fd58c000/rgb/ports/port@0/endpoint@2"; + bigcore0_grf = "/syscon@fd590000"; + bigcore1_grf = "/syscon@fd592000"; + litcore_grf = "/syscon@fd594000"; + dsu_grf = "/syscon@fd598000"; + gpu_grf = "/syscon@fd5a0000"; + npu_grf = "/syscon@fd5a2000"; + vop_grf = "/syscon@fd5a4000"; + vo0_grf = "/syscon@fd5a6000"; + vo1_grf = "/syscon@fd5a8000"; + usb_grf = "/syscon@fd5ac000"; + php_grf = "/syscon@fd5b0000"; + mipidphy0_grf = "/syscon@fd5b4000"; + mipidphy1_grf = "/syscon@fd5b5000"; + pipe_phy0_grf = "/syscon@fd5bc000"; + pipe_phy2_grf = "/syscon@fd5c4000"; + usbdpphy0_grf = "/syscon@fd5c8000"; + usb2phy0_grf = "/syscon@fd5d0000"; + u2phy0 = "/syscon@fd5d0000/usb2-phy@0"; + u2phy0_otg = "/syscon@fd5d0000/usb2-phy@0/otg-port"; + usb2phy2_grf = "/syscon@fd5d8000"; + u2phy2 = "/syscon@fd5d8000/usb2-phy@8000"; + u2phy2_host = "/syscon@fd5d8000/usb2-phy@8000/host-port"; + usb2phy3_grf = "/syscon@fd5dc000"; + u2phy3 = "/syscon@fd5dc000/usb2-phy@c000"; + u2phy3_host = "/syscon@fd5dc000/usb2-phy@c000/host-port"; + hdptxphy0_grf = "/syscon@fd5e0000"; + mipidcphy0_grf = "/syscon@fd5e8000"; + mipidcphy1_grf = "/syscon@fd5ec000"; + ioc = "/syscon@fd5f0000"; + cru = "/clock-controller@fd7c0000"; + i2c0 = "/i2c@fd880000"; + vdd_cpu_big0_s0 = "/i2c@fd880000/rk8602@42"; + vdd_cpu_big0_mem_s0 = "/i2c@fd880000/rk8602@42"; + vdd_cpu_big1_s0 = "/i2c@fd880000/rk8603@43"; + vdd_cpu_big1_mem_s0 = "/i2c@fd880000/rk8603@43"; + uart0 = "/serial@fd890000"; + pwm0 = "/pwm@fd8b0000"; + pwm1 = "/pwm@fd8b0010"; + pwm2 = "/pwm@fd8b0020"; + pwm3 = "/pwm@fd8b0030"; + pmu = "/power-management@fd8d8000"; + power = "/power-management@fd8d8000/power-controller"; + rknpu = "/npu@fdab0000"; + npu_opp_table = "/npu-opp-table"; + rknpu_mmu = "/iommu@fdab9000"; + vepu = "/vepu@fdb50000"; + vdpu = "/vdpu@fdb50400"; + vdpu_mmu = "/iommu@fdb50800"; + avsd = "/avsd-plus@fdb51000"; + rga3_core0 = "/rga@fdb60000"; + rga3_0_mmu = "/iommu@fdb60f00"; + rga3_core1 = "/rga@fdb70000"; + rga3_1_mmu = "/iommu@fdb70f00"; + rga2 = "/rga@fdb80000"; + jpegd = "/jpegd@fdb90000"; + jpegd_mmu = "/iommu@fdb90480"; + jpege0 = "/jpege-core@fdba0000"; + jpege0_mmu = "/iommu@fdba0800"; + jpege1 = "/jpege-core@fdba4000"; + jpege1_mmu = "/iommu@fdba4800"; + jpege2 = "/jpege-core@fdba8000"; + jpege2_mmu = "/iommu@fdba8800"; + jpege3 = "/jpege-core@fdbac000"; + jpege3_mmu = "/iommu@fdbac800"; + iep = "/iep@fdbb0000"; + iep_mmu = "/iommu@fdbb0800"; + rkvenc0 = "/rkvenc-core@fdbd0000"; + rkvenc0_mmu = "/iommu@fdbdf000"; + rkvenc1 = "/rkvenc-core@fdbe0000"; + rkvenc1_mmu = "/iommu@fdbef000"; + venc_opp_table = "/venc-opp-table"; + rkvdec_ccu = "/rkvdec-ccu@fdc30000"; + rkvdec0 = "/rkvdec-core@fdc38000"; + rkvdec0_mmu = "/iommu@fdc38700"; + rkvdec1 = "/rkvdec-core@fdc48000"; + rkvdec1_mmu = "/iommu@fdc48700"; + av1d = "/av1d@fdc70000"; + av1d_mmu = "/iommu@fdca0000"; + rkisp_unite = "/rkisp-unite@fdcb0000"; + rkisp0 = "/rkisp@fdcb0000"; + rkisp_unite_mmu = "/rkisp-unite-mmu@fdcb7f00"; + isp0_mmu = "/iommu@fdcb7f00"; + rkisp1 = "/rkisp@fdcc0000"; + isp1_mmu = "/iommu@fdcc7f00"; + rkispp0 = "/rkispp@fdcd0000"; + fec0_mmu = "/iommu@fdcd0f00"; + rkispp1 = "/rkispp@fdcd8000"; + fec1_mmu = "/iommu@fdcd8f00"; + rkcif = "/rkcif@fdce0000"; + rkcif_mmu = "/iommu@fdce0800"; + mipi0_csi2_hw = "/mipi0-csi2-hw@fdd10000"; + mipi1_csi2_hw = "/mipi1-csi2-hw@fdd20000"; + mipi2_csi2_hw = "/mipi2-csi2-hw@fdd30000"; + mipi3_csi2_hw = "/mipi3-csi2-hw@fdd40000"; + mipi4_csi2_hw = "/mipi4-csi2-hw@fdd50000"; + mipi5_csi2_hw = "/mipi5-csi2-hw@fdd60000"; + vop = "/vop@fdd90000"; + vop_out = "/vop@fdd90000/ports"; + vp0 = "/vop@fdd90000/ports/port@0"; + vp0_out_dp0 = "/vop@fdd90000/ports/port@0/endpoint@0"; + vp0_out_edp0 = "/vop@fdd90000/ports/port@0/endpoint@1"; + vp0_out_hdmi0 = "/vop@fdd90000/ports/port@0/endpoint@2"; + vp0_out_dp1 = "/vop@fdd90000/ports/port@0/endpoint@3"; + vp0_out_edp1 = "/vop@fdd90000/ports/port@0/endpoint@4"; + vp0_out_hdmi1 = "/vop@fdd90000/ports/port@0/endpoint@5"; + vp1 = "/vop@fdd90000/ports/port@1"; + vp1_out_dp0 = "/vop@fdd90000/ports/port@1/endpoint@0"; + vp1_out_edp0 = "/vop@fdd90000/ports/port@1/endpoint@1"; + vp1_out_hdmi0 = "/vop@fdd90000/ports/port@1/endpoint@2"; + vp1_out_dp1 = "/vop@fdd90000/ports/port@1/endpoint@3"; + vp1_out_edp1 = "/vop@fdd90000/ports/port@1/endpoint@4"; + vp1_out_hdmi1 = "/vop@fdd90000/ports/port@1/endpoint@5"; + vp2 = "/vop@fdd90000/ports/port@2"; + vp2_out_dp0 = "/vop@fdd90000/ports/port@2/endpoint@0"; + vp2_out_edp0 = "/vop@fdd90000/ports/port@2/endpoint@1"; + vp2_out_hdmi0 = "/vop@fdd90000/ports/port@2/endpoint@2"; + vp2_out_dsi0 = "/vop@fdd90000/ports/port@2/endpoint@3"; + vp2_out_dsi1 = "/vop@fdd90000/ports/port@2/endpoint@4"; + vp2_out_dp1 = "/vop@fdd90000/ports/port@2/endpoint@5"; + vp2_out_edp1 = "/vop@fdd90000/ports/port@2/endpoint@6"; + vp2_out_hdmi1 = "/vop@fdd90000/ports/port@2/endpoint@7"; + vp3 = "/vop@fdd90000/ports/port@3"; + vp3_out_dsi0 = "/vop@fdd90000/ports/port@3/endpoint@0"; + vp3_out_dsi1 = "/vop@fdd90000/ports/port@3/endpoint@1"; + vp3_out_rgb = "/vop@fdd90000/ports/port@3/endpoint@2"; + vop_opp_table = "/vop-opp-table"; + vop_mmu = "/iommu@fdd97e00"; + spdif_tx2 = "/spdif-tx@fddb0000"; + i2s4_8ch = "/i2s@fddc0000"; + spdif_tx3 = "/spdif-tx@fdde0000"; + i2s5_8ch = "/i2s@fddf0000"; + i2s9_8ch = "/i2s@fddfc000"; + spdif_rx0 = "/spdif-rx@fde08000"; + dsi0 = "/dsi@fde20000"; + dsi0_in = "/dsi@fde20000/ports/port@0"; + dsi0_in_vp2 = "/dsi@fde20000/ports/port@0/endpoint@0"; + dsi0_in_vp3 = "/dsi@fde20000/ports/port@0/endpoint@1"; + dsi_out_panel = "/dsi@fde20000/ports/port@1/endpoint"; + dsi0_panel = "/dsi@fde20000/panel@0"; + disp_timings0 = "/dsi@fde20000/panel@0/display-timings"; + dsi0_timing0 = "/dsi@fde20000/panel@0/display-timings/timing0"; + panel_in_dsi = "/dsi@fde20000/panel@0/ports/port@0/endpoint"; + dsi1 = "/dsi@fde30000"; + dsi1_in = "/dsi@fde30000/ports/port@0"; + dsi1_in_vp2 = "/dsi@fde30000/ports/port@0/endpoint@0"; + dsi1_in_vp3 = "/dsi@fde30000/ports/port@0/endpoint@1"; + dsi1_out_panel = "/dsi@fde30000/ports/port@1/endpoint"; + dsi1_panel = "/dsi@fde30000/panel@0"; + disp_timings1 = "/dsi@fde30000/panel@0/display-timings"; + dsi1_timing0 = "/dsi@fde30000/panel@0/display-timings/timing0"; + panel_in_dsi1 = "/dsi@fde30000/panel@0/ports/port@0/endpoint"; + hdcp0 = "/hdcp@fde40000"; + dp0 = "/dp@fde50000"; + dp0_in_vp0 = "/dp@fde50000/ports/port@0/endpoint@0"; + dp0_in_vp1 = "/dp@fde50000/ports/port@0/endpoint@1"; + dp0_in_vp2 = "/dp@fde50000/ports/port@0/endpoint@2"; + dp0_out = "/dp@fde50000/ports/port@1/endpoint"; + hdcp1 = "/hdcp@fde70000"; + hdmi0 = "/hdmi@fde80000"; + hdmi0_in = "/hdmi@fde80000/ports/port@0"; + hdmi0_in_vp0 = "/hdmi@fde80000/ports/port@0/endpoint@0"; + hdmi0_in_vp1 = "/hdmi@fde80000/ports/port@0/endpoint@1"; + hdmi0_in_vp2 = "/hdmi@fde80000/ports/port@0/endpoint@2"; + edp0 = "/edp@fdec0000"; + edp0_in_vp0 = "/edp@fdec0000/ports/port@0/endpoint@0"; + edp0_in_vp1 = "/edp@fdec0000/ports/port@0/endpoint@1"; + edp0_in_vp2 = "/edp@fdec0000/ports/port@0/endpoint@2"; + edp0_out = "/edp@fdec0000/ports/port@1/endpoint"; + qos_gpu_m0 = "/qos@fdf35000"; + qos_gpu_m1 = "/qos@fdf35200"; + qos_gpu_m2 = "/qos@fdf35400"; + qos_gpu_m3 = "/qos@fdf35600"; + qos_rga3_1 = "/qos@fdf36000"; + qos_sdio = "/qos@fdf39000"; + qos_gic600_m0 = "/qos@fdf3a000"; + qos_gic600_m1 = "/qos@fdf3a200"; + qos_sdmmc = "/qos@fdf3d800"; + qos_usb3_1 = "/qos@fdf3e000"; + qos_usb3_0 = "/qos@fdf3e200"; + qos_usb2host_0 = "/qos@fdf3e400"; + qos_usb2host_1 = "/qos@fdf3e600"; + qos_fisheye0 = "/qos@fdf40000"; + qos_fisheye1 = "/qos@fdf40200"; + qos_isp0_mro = "/qos@fdf40400"; + qos_isp0_mwo = "/qos@fdf40500"; + qos_vicap_m0 = "/qos@fdf40600"; + qos_vicap_m1 = "/qos@fdf40800"; + qos_isp1_mwo = "/qos@fdf41000"; + qos_isp1_mro = "/qos@fdf41100"; + qos_rkvenc0_m0ro = "/qos@fdf60000"; + qos_rkvenc0_m1ro = "/qos@fdf60200"; + qos_rkvenc0_m2wo = "/qos@fdf60400"; + qos_rkvenc1_m0ro = "/qos@fdf61000"; + qos_rkvenc1_m1ro = "/qos@fdf61200"; + qos_rkvenc1_m2wo = "/qos@fdf61400"; + qos_rkvdec0 = "/qos@fdf62000"; + qos_rkvdec1 = "/qos@fdf63000"; + qos_av1 = "/qos@fdf64000"; + qos_iep = "/qos@fdf66000"; + qos_jpeg_dec = "/qos@fdf66200"; + qos_jpeg_enc0 = "/qos@fdf66400"; + qos_jpeg_enc1 = "/qos@fdf66600"; + qos_jpeg_enc2 = "/qos@fdf66800"; + qos_jpeg_enc3 = "/qos@fdf66a00"; + qos_rga2_mro = "/qos@fdf66c00"; + qos_rga2_mwo = "/qos@fdf66e00"; + qos_rga3_0 = "/qos@fdf67000"; + qos_vdpu = "/qos@fdf67200"; + qos_npu1 = "/qos@fdf70000"; + qos_npu2 = "/qos@fdf71000"; + qos_npu0_mwr = "/qos@fdf72000"; + qos_npu0_mro = "/qos@fdf72200"; + qos_mcu_npu = "/qos@fdf72400"; + qos_hdcp0 = "/qos@fdf80000"; + qos_hdcp1 = "/qos@fdf81000"; + qos_hdmirx = "/qos@fdf81200"; + qos_vop_m0 = "/qos@fdf82000"; + qos_vop_m1 = "/qos@fdf82200"; + dfi = "/dfi@fe060000"; + pcie2x1l1 = "/pcie@fe180000"; + pcie2x1l1_intc = "/pcie@fe180000/legacy-interrupt-controller"; + pcie2x1l2 = "/pcie@fe190000"; + pcie2x1l2_intc = "/pcie@fe190000/legacy-interrupt-controller"; + gmac_uio1 = "/uio@fe1c0000"; + gmac1 = "/ethernet@fe1c0000"; + mdio1 = "/ethernet@fe1c0000/mdio"; + rgmii_phy = "/ethernet@fe1c0000/mdio/phy@1"; + gmac1_stmmac_axi_setup = "/ethernet@fe1c0000/stmmac-axi-config"; + gmac1_mtl_rx_setup = "/ethernet@fe1c0000/rx-queues-config"; + gmac1_mtl_tx_setup = "/ethernet@fe1c0000/tx-queues-config"; + sata0 = "/sata@fe210000"; + sata2 = "/sata@fe230000"; + sfc = "/spi@fe2b0000"; + sdmmc = "/mmc@fe2c0000"; + sdio = "/mmc@fe2d0000"; + sdhci = "/mmc@fe2e0000"; + crypto = "/crypto@fe370000"; + rng = "/rng@fe378000"; + i2s0_8ch = "/i2s@fe470000"; + i2s1_8ch = "/i2s@fe480000"; + i2s2_2ch = "/i2s@fe490000"; + i2s3_2ch = "/i2s@fe4a0000"; + pdm0 = "/pdm@fe4b0000"; + pdm1 = "/pdm@fe4c0000"; + vad = "/vad@fe4d0000"; + spdif_tx0 = "/spdif-tx@fe4e0000"; + spdif_tx1 = "/spdif-tx@fe4f0000"; + acdcdig_dsm = "/codec-digital@fe500000"; + hwlock = "/hwspinlock@fe5a0000"; + gic = "/interrupt-controller@fe600000"; + its0 = "/interrupt-controller@fe600000/msi-controller@fe640000"; + its1 = "/interrupt-controller@fe600000/msi-controller@fe660000"; + dmac0 = "/dma-controller@fea10000"; + dmac1 = "/dma-controller@fea30000"; + can0 = "/can@fea50000"; + can1 = "/can@fea60000"; + can2 = "/can@fea70000"; + hw_decompress = "/decompress@fea80000"; + i2c1 = "/i2c@fea90000"; + vdd_npu_s0 = "/i2c@fea90000/rk8602@42"; + vdd_npu_mem_s0 = "/i2c@fea90000/rk8602@42"; + i2c2 = "/i2c@feaa0000"; + i2c3 = "/i2c@feab0000"; + imx415 = "/i2c@feab0000/imx415@1a"; + imx415_out0 = "/i2c@feab0000/imx415@1a/port/endpoint"; + i2c4 = "/i2c@feac0000"; + ls_stk3332 = "/i2c@feac0000/light@47"; + ps_stk3332 = "/i2c@feac0000/proximity@47"; + icm42607_acc = "/i2c@feac0000/icm_acc@68"; + icm42607_gyro = "/i2c@feac0000/icm_gyro@68"; + i2c5 = "/i2c@fead0000"; + gt1x = "/i2c@fead0000/gt1x@14"; + hynitron = "/i2c@fead0000/hynitron@5a"; + rktimer = "/timer@feae0000"; + wdt = "/watchdog@feaf0000"; + spi0 = "/spi@feb00000"; + spi1 = "/spi@feb10000"; + spi2 = "/spi@feb20000"; + rk806single = "/spi@feb20000/rk806single@0"; + pinctrl_rk806 = "/spi@feb20000/rk806single@0/pinctrl_rk806"; + rk806_dvs1_null = "/spi@feb20000/rk806single@0/pinctrl_rk806/rk806_dvs1_null"; + rk806_dvs1_slp = "/spi@feb20000/rk806single@0/pinctrl_rk806/rk806_dvs1_slp"; + rk806_dvs1_pwrdn = "/spi@feb20000/rk806single@0/pinctrl_rk806/rk806_dvs1_pwrdn"; + rk806_dvs1_rst = "/spi@feb20000/rk806single@0/pinctrl_rk806/rk806_dvs1_rst"; + rk806_dvs2_null = "/spi@feb20000/rk806single@0/pinctrl_rk806/rk806_dvs2_null"; + rk806_dvs2_slp = "/spi@feb20000/rk806single@0/pinctrl_rk806/rk806_dvs2_slp"; + rk806_dvs2_pwrdn = "/spi@feb20000/rk806single@0/pinctrl_rk806/rk806_dvs2_pwrdn"; + rk806_dvs2_rst = "/spi@feb20000/rk806single@0/pinctrl_rk806/rk806_dvs2_rst"; + rk806_dvs2_dvs = "/spi@feb20000/rk806single@0/pinctrl_rk806/rk806_dvs2_dvs"; + rk806_dvs2_gpio = "/spi@feb20000/rk806single@0/pinctrl_rk806/rk806_dvs2_gpio"; + rk806_dvs3_null = "/spi@feb20000/rk806single@0/pinctrl_rk806/rk806_dvs3_null"; + rk806_dvs3_slp = "/spi@feb20000/rk806single@0/pinctrl_rk806/rk806_dvs3_slp"; + rk806_dvs3_pwrdn = "/spi@feb20000/rk806single@0/pinctrl_rk806/rk806_dvs3_pwrdn"; + rk806_dvs3_rst = "/spi@feb20000/rk806single@0/pinctrl_rk806/rk806_dvs3_rst"; + rk806_dvs3_dvs = "/spi@feb20000/rk806single@0/pinctrl_rk806/rk806_dvs3_dvs"; + rk806_dvs3_gpio = "/spi@feb20000/rk806single@0/pinctrl_rk806/rk806_dvs3_gpio"; + vdd_gpu_s0 = "/spi@feb20000/rk806single@0/regulators/DCDC_REG1"; + vdd_gpu_mem_s0 = "/spi@feb20000/rk806single@0/regulators/DCDC_REG1"; + vdd_cpu_lit_s0 = "/spi@feb20000/rk806single@0/regulators/DCDC_REG2"; + vdd_cpu_lit_mem_s0 = "/spi@feb20000/rk806single@0/regulators/DCDC_REG2"; + vdd_log_s0 = "/spi@feb20000/rk806single@0/regulators/DCDC_REG3"; + vdd_vdenc_s0 = "/spi@feb20000/rk806single@0/regulators/DCDC_REG4"; + vdd_vdenc_mem_s0 = "/spi@feb20000/rk806single@0/regulators/DCDC_REG4"; + vdd_ddr_s0 = "/spi@feb20000/rk806single@0/regulators/DCDC_REG5"; + vdd2_ddr_s3 = "/spi@feb20000/rk806single@0/regulators/DCDC_REG6"; + vcc_2v0_pldo_s3 = "/spi@feb20000/rk806single@0/regulators/DCDC_REG7"; + vcc_3v3_s3 = "/spi@feb20000/rk806single@0/regulators/DCDC_REG8"; + vddq_ddr_s0 = "/spi@feb20000/rk806single@0/regulators/DCDC_REG9"; + vcc_1v8_s3 = "/spi@feb20000/rk806single@0/regulators/DCDC_REG10"; + avcc_1v8_s0 = "/spi@feb20000/rk806single@0/regulators/PLDO_REG1"; + vcc_1v8_s0 = "/spi@feb20000/rk806single@0/regulators/PLDO_REG2"; + avdd_1v2_s0 = "/spi@feb20000/rk806single@0/regulators/PLDO_REG3"; + vcc_3v3_s0 = "/spi@feb20000/rk806single@0/regulators/PLDO_REG4"; + vccio_sd_s0 = "/spi@feb20000/rk806single@0/regulators/PLDO_REG5"; + pldo6_s3 = "/spi@feb20000/rk806single@0/regulators/PLDO_REG6"; + vdd_0v75_s3 = "/spi@feb20000/rk806single@0/regulators/NLDO_REG1"; + vdd_ddr_pll_s0 = "/spi@feb20000/rk806single@0/regulators/NLDO_REG2"; + avdd_0v75_s0 = "/spi@feb20000/rk806single@0/regulators/NLDO_REG3"; + vdd_0v85_s0 = "/spi@feb20000/rk806single@0/regulators/NLDO_REG4"; + vdd_0v75_s0 = "/spi@feb20000/rk806single@0/regulators/NLDO_REG5"; + spi3 = "/spi@feb30000"; + uart1 = "/serial@feb40000"; + uart2 = "/serial@feb50000"; + uart3 = "/serial@feb60000"; + uart4 = "/serial@feb70000"; + uart5 = "/serial@feb80000"; + uart6 = "/serial@feb90000"; + uart7 = "/serial@feba0000"; + uart8 = "/serial@febb0000"; + uart9 = "/serial@febc0000"; + pwm4 = "/pwm@febd0000"; + pwm5 = "/pwm@febd0010"; + pwm6 = "/pwm@febd0020"; + pwm7 = "/pwm@febd0030"; + pwm8 = "/pwm@febe0000"; + pwm9 = "/pwm@febe0010"; + pwm10 = "/pwm@febe0020"; + pwm11 = "/pwm@febe0030"; + pwm12 = "/pwm@febf0000"; + pwm13 = "/pwm@febf0010"; + pwm14 = "/pwm@febf0020"; + pwm15 = "/pwm@febf0030"; + tsadc = "/tsadc@fec00000"; + saradc = "/saradc@fec10000"; + mailbox0 = "/mailbox@fec60000"; + mailbox1 = "/mailbox@fec70000"; + i2c6 = "/i2c@fec80000"; + usbc0 = "/i2c@fec80000/husb311@4e"; + usbc0_role_sw = "/i2c@fec80000/husb311@4e/ports/port@0/endpoint@0"; + usb_con = "/i2c@fec80000/husb311@4e/connector"; + usbc0_orien_sw = "/i2c@fec80000/husb311@4e/connector/ports/port@0/endpoint"; + dp_altmode_mux = "/i2c@fec80000/husb311@4e/connector/ports/port@1/endpoint"; + hym8563 = "/i2c@fec80000/hym8563@51"; + i2c7 = "/i2c@fec90000"; + es8388 = "/i2c@fec90000/es8388@11"; + i2c8 = "/i2c@feca0000"; + spi4 = "/spi@fecb0000"; + otp = "/otp@fecc0000"; + cpu_code = "/otp@fecc0000/cpu-code@2"; + package_serial_number_high = "/otp@fecc0000/package-serial-number-high@5"; + package_serial_number_low = "/otp@fecc0000/package-serial-number-low@6"; + specification_serial_number = "/otp@fecc0000/specification-serial-number@6"; + otp_id = "/otp@fecc0000/id@7"; + otp_cpu_version = "/otp@fecc0000/cpu-version@1c"; + cpub0_leakage = "/otp@fecc0000/cpub0-leakage@17"; + cpub1_leakage = "/otp@fecc0000/cpub1-leakage@18"; + cpul_leakage = "/otp@fecc0000/cpul-leakage@19"; + log_leakage = "/otp@fecc0000/log-leakage@1a"; + gpu_leakage = "/otp@fecc0000/gpu-leakage@1b"; + customer_demand = "/otp@fecc0000/customer-demand@22"; + npu_leakage = "/otp@fecc0000/npu-leakage@28"; + codec_leakage = "/otp@fecc0000/codec-leakage@29"; + cpul_opp_info = "/otp@fecc0000/cpul-opp-info@3d"; + cpub01_opp_info = "/otp@fecc0000/cpub01-opp-info@43"; + cpub23_opp_info = "/otp@fecc0000/cpub23-opp-info@49"; + gpu_opp_info = "/otp@fecc0000/gpu-opp-info@4f"; + npu_opp_info = "/otp@fecc0000/npu-opp-info@55"; + dmc_opp_info = "/otp@fecc0000/dmc-opp-info@5b"; + vop_opp_info = "/otp@fecc0000/vop-opp-info@61"; + venc_opp_info = "/otp@fecc0000/venc-opp-info@67"; + mailbox2 = "/mailbox@fece0000"; + dmac2 = "/dma-controller@fed10000"; + hdptxphy0 = "/phy@fed60000"; + hdptxphy_hdmi0 = "/hdmiphy@fed60000"; + usbdp_phy0 = "/phy@fed80000"; + usbdp_phy0_dp = "/phy@fed80000/dp-port"; + usbdp_phy0_u3 = "/phy@fed80000/u3-port"; + usbdp_phy0_orientation_switch = "/phy@fed80000/port/endpoint@0"; + usbdp_phy0_dp_altmode_mux = "/phy@fed80000/port/endpoint@1"; + mipidcphy0 = "/phy@feda0000"; + mipidcphy1 = "/phy@fedb0000"; + csi2_dphy0_hw = "/csi2-dphy0-hw@fedc0000"; + csi2_dphy1_hw = "/csi2-dphy1-hw@fedc8000"; + combphy0_ps = "/phy@fee00000"; + combphy2_psu = "/phy@fee20000"; + syssram = "/sram@ff001000"; + rkvdec0_sram = "/sram@ff001000/rkvdec-sram@0"; + rkvdec1_sram = "/sram@ff001000/rkvdec-sram@78000"; + pinctrl = "/pinctrl"; + gpio0 = "/pinctrl/gpio@fd8a0000"; + gpio1 = "/pinctrl/gpio@fec20000"; + gpio2 = "/pinctrl/gpio@fec30000"; + gpio3 = "/pinctrl/gpio@fec40000"; + gpio4 = "/pinctrl/gpio@fec50000"; + pcfg_pull_up = "/pinctrl/pcfg-pull-up"; + pcfg_pull_down = "/pinctrl/pcfg-pull-down"; + pcfg_pull_none = "/pinctrl/pcfg-pull-none"; + pcfg_pull_none_drv_level_0 = "/pinctrl/pcfg-pull-none-drv-level-0"; + pcfg_pull_none_drv_level_1 = "/pinctrl/pcfg-pull-none-drv-level-1"; + pcfg_pull_none_drv_level_2 = "/pinctrl/pcfg-pull-none-drv-level-2"; + pcfg_pull_none_drv_level_3 = "/pinctrl/pcfg-pull-none-drv-level-3"; + pcfg_pull_none_drv_level_4 = "/pinctrl/pcfg-pull-none-drv-level-4"; + pcfg_pull_none_drv_level_5 = "/pinctrl/pcfg-pull-none-drv-level-5"; + pcfg_pull_none_drv_level_6 = "/pinctrl/pcfg-pull-none-drv-level-6"; + pcfg_pull_up_drv_level_0 = "/pinctrl/pcfg-pull-up-drv-level-0"; + pcfg_pull_up_drv_level_1 = "/pinctrl/pcfg-pull-up-drv-level-1"; + pcfg_pull_up_drv_level_2 = "/pinctrl/pcfg-pull-up-drv-level-2"; + pcfg_pull_up_drv_level_3 = "/pinctrl/pcfg-pull-up-drv-level-3"; + pcfg_pull_up_drv_level_4 = "/pinctrl/pcfg-pull-up-drv-level-4"; + pcfg_pull_up_drv_level_5 = "/pinctrl/pcfg-pull-up-drv-level-5"; + pcfg_pull_up_drv_level_6 = "/pinctrl/pcfg-pull-up-drv-level-6"; + pcfg_pull_down_drv_level_0 = "/pinctrl/pcfg-pull-down-drv-level-0"; + pcfg_pull_down_drv_level_1 = "/pinctrl/pcfg-pull-down-drv-level-1"; + pcfg_pull_down_drv_level_2 = "/pinctrl/pcfg-pull-down-drv-level-2"; + pcfg_pull_down_drv_level_3 = "/pinctrl/pcfg-pull-down-drv-level-3"; + pcfg_pull_down_drv_level_4 = "/pinctrl/pcfg-pull-down-drv-level-4"; + pcfg_pull_down_drv_level_5 = "/pinctrl/pcfg-pull-down-drv-level-5"; + pcfg_pull_down_drv_level_6 = "/pinctrl/pcfg-pull-down-drv-level-6"; + pcfg_pull_up_smt = "/pinctrl/pcfg-pull-up-smt"; + pcfg_pull_down_smt = "/pinctrl/pcfg-pull-down-smt"; + pcfg_pull_none_smt = "/pinctrl/pcfg-pull-none-smt"; + pcfg_pull_none_drv_level_0_smt = "/pinctrl/pcfg-pull-none-drv-level-0-smt"; + pcfg_pull_none_drv_level_1_smt = "/pinctrl/pcfg-pull-none-drv-level-1-smt"; + pcfg_pull_none_drv_level_2_smt = "/pinctrl/pcfg-pull-none-drv-level-2-smt"; + pcfg_pull_none_drv_level_3_smt = "/pinctrl/pcfg-pull-none-drv-level-3-smt"; + pcfg_pull_none_drv_level_4_smt = "/pinctrl/pcfg-pull-none-drv-level-4-smt"; + pcfg_pull_none_drv_level_5_smt = "/pinctrl/pcfg-pull-none-drv-level-5-smt"; + pcfg_pull_none_drv_level_6_smt = "/pinctrl/pcfg-pull-none-drv-level-6-smt"; + pcfg_output_high = "/pinctrl/pcfg-output-high"; + pcfg_output_high_pull_up = "/pinctrl/pcfg-output-high-pull-up"; + pcfg_output_high_pull_down = "/pinctrl/pcfg-output-high-pull-down"; + pcfg_output_high_pull_none = "/pinctrl/pcfg-output-high-pull-none"; + pcfg_output_low = "/pinctrl/pcfg-output-low"; + pcfg_output_low_pull_up = "/pinctrl/pcfg-output-low-pull-up"; + pcfg_output_low_pull_down = "/pinctrl/pcfg-output-low-pull-down"; + pcfg_output_low_pull_none = "/pinctrl/pcfg-output-low-pull-none"; + auddsm_pins = "/pinctrl/auddsm/auddsm-pins"; + bt1120_pins = "/pinctrl/bt1120/bt1120-pins"; + can0m0_pins = "/pinctrl/can0/can0m0-pins"; + can0m1_pins = "/pinctrl/can0/can0m1-pins"; + can1m0_pins = "/pinctrl/can1/can1m0-pins"; + can1m1_pins = "/pinctrl/can1/can1m1-pins"; + can2m0_pins = "/pinctrl/can2/can2m0-pins"; + can2m1_pins = "/pinctrl/can2/can2m1-pins"; + cif_clk = "/pinctrl/cif/cif-clk"; + cif_dvp_clk = "/pinctrl/cif/cif-dvp-clk"; + cif_dvp_bus16 = "/pinctrl/cif/cif-dvp-bus16"; + cif_dvp_bus8 = "/pinctrl/cif/cif-dvp-bus8"; + clk32k_in = "/pinctrl/clk32k/clk32k-in"; + clk32k_out0 = "/pinctrl/clk32k/clk32k-out0"; + clk32k_out1 = "/pinctrl/clk32k/clk32k-out1"; + cpu_pins = "/pinctrl/cpu/cpu-pins"; + ddrphych0_pins = "/pinctrl/ddrphych0/ddrphych0-pins"; + ddrphych1_pins = "/pinctrl/ddrphych1/ddrphych1-pins"; + ddrphych2_pins = "/pinctrl/ddrphych2/ddrphych2-pins"; + ddrphych3_pins = "/pinctrl/ddrphych3/ddrphych3-pins"; + dp0m0_pins = "/pinctrl/dp0/dp0m0-pins"; + dp0m1_pins = "/pinctrl/dp0/dp0m1-pins"; + dp0m2_pins = "/pinctrl/dp0/dp0m2-pins"; + dp1m0_pins = "/pinctrl/dp1/dp1m0-pins"; + dp1m1_pins = "/pinctrl/dp1/dp1m1-pins"; + dp1m2_pins = "/pinctrl/dp1/dp1m2-pins"; + emmc_rstnout = "/pinctrl/emmc/emmc-rstnout"; + emmc_bus8 = "/pinctrl/emmc/emmc-bus8"; + emmc_clk = "/pinctrl/emmc/emmc-clk"; + emmc_cmd = "/pinctrl/emmc/emmc-cmd"; + emmc_data_strobe = "/pinctrl/emmc/emmc-data-strobe"; + eth1_pins = "/pinctrl/eth1/eth1-pins"; + fspim0_pins = "/pinctrl/fspi/fspim0-pins"; + fspim0_cs1 = "/pinctrl/fspi/fspim0-cs1"; + fspim2_pins = "/pinctrl/fspi/fspim2-pins"; + fspim2_cs1 = "/pinctrl/fspi/fspim2-cs1"; + fspim1_pins = "/pinctrl/fspi/fspim1-pins"; + fspim1_cs1 = "/pinctrl/fspi/fspim1-cs1"; + gmac1_miim = "/pinctrl/gmac1/gmac1-miim"; + gmac1_clkinout = "/pinctrl/gmac1/gmac1-clkinout"; + gmac1_rx_bus2 = "/pinctrl/gmac1/gmac1-rx-bus2"; + gmac1_tx_bus2 = "/pinctrl/gmac1/gmac1-tx-bus2"; + gmac1_rgmii_clk = "/pinctrl/gmac1/gmac1-rgmii-clk"; + gmac1_rgmii_bus = "/pinctrl/gmac1/gmac1-rgmii-bus"; + gmac1_ppsclk = "/pinctrl/gmac1/gmac1-ppsclk"; + gmac1_ppstrig = "/pinctrl/gmac1/gmac1-ppstrig"; + gmac1_ptp_ref_clk = "/pinctrl/gmac1/gmac1-ptp-ref-clk"; + gmac1_txer = "/pinctrl/gmac1/gmac1-txer"; + gpu_pins = "/pinctrl/gpu/gpu-pins"; + hdmim0_rx_cec = "/pinctrl/hdmi/hdmim0-rx-cec"; + hdmim0_rx_hpdin = "/pinctrl/hdmi/hdmim0-rx-hpdin"; + hdmim0_rx_scl = "/pinctrl/hdmi/hdmim0-rx-scl"; + hdmim0_rx_sda = "/pinctrl/hdmi/hdmim0-rx-sda"; + hdmim0_tx0_cec = "/pinctrl/hdmi/hdmim0-tx0-cec"; + hdmim0_tx0_hpd = "/pinctrl/hdmi/hdmim0-tx0-hpd"; + hdmim0_tx0_scl = "/pinctrl/hdmi/hdmim0-tx0-scl"; + hdmim0_tx0_sda = "/pinctrl/hdmi/hdmim0-tx0-sda"; + hdmim0_tx1_hpd = "/pinctrl/hdmi/hdmim0-tx1-hpd"; + hdmim1_rx = "/pinctrl/hdmi/hdmim1-rx"; + hdmim1_rx_cec = "/pinctrl/hdmi/hdmim1-rx-cec"; + hdmim1_rx_hpdin = "/pinctrl/hdmi/hdmim1-rx-hpdin"; + hdmim1_rx_scl = "/pinctrl/hdmi/hdmim1-rx-scl"; + hdmim1_rx_sda = "/pinctrl/hdmi/hdmim1-rx-sda"; + hdmim1_tx0_cec = "/pinctrl/hdmi/hdmim1-tx0-cec"; + hdmim1_tx0_hpd = "/pinctrl/hdmi/hdmim1-tx0-hpd"; + hdmim1_tx0_scl = "/pinctrl/hdmi/hdmim1-tx0-scl"; + hdmim1_tx0_sda = "/pinctrl/hdmi/hdmim1-tx0-sda"; + hdmim1_tx1_cec = "/pinctrl/hdmi/hdmim1-tx1-cec"; + hdmim1_tx1_hpd = "/pinctrl/hdmi/hdmim1-tx1-hpd"; + hdmim1_tx1_scl = "/pinctrl/hdmi/hdmim1-tx1-scl"; + hdmim1_tx1_sda = "/pinctrl/hdmi/hdmim1-tx1-sda"; + hdmim2_rx_cec = "/pinctrl/hdmi/hdmim2-rx-cec"; + hdmim2_rx_hpdin = "/pinctrl/hdmi/hdmim2-rx-hpdin"; + hdmim2_rx_scl = "/pinctrl/hdmi/hdmim2-rx-scl"; + hdmim2_rx_sda = "/pinctrl/hdmi/hdmim2-rx-sda"; + hdmim2_tx0_scl = "/pinctrl/hdmi/hdmim2-tx0-scl"; + hdmim2_tx0_sda = "/pinctrl/hdmi/hdmim2-tx0-sda"; + hdmim2_tx1_cec = "/pinctrl/hdmi/hdmim2-tx1-cec"; + hdmim2_tx1_scl = "/pinctrl/hdmi/hdmim2-tx1-scl"; + hdmim2_tx1_sda = "/pinctrl/hdmi/hdmim2-tx1-sda"; + hdmi_debug0 = "/pinctrl/hdmi/hdmi-debug0"; + hdmi_debug1 = "/pinctrl/hdmi/hdmi-debug1"; + hdmi_debug2 = "/pinctrl/hdmi/hdmi-debug2"; + hdmi_debug3 = "/pinctrl/hdmi/hdmi-debug3"; + hdmi_debug4 = "/pinctrl/hdmi/hdmi-debug4"; + hdmi_debug5 = "/pinctrl/hdmi/hdmi-debug5"; + hdmi_debug6 = "/pinctrl/hdmi/hdmi-debug6"; + hdmim0_tx1_cec = "/pinctrl/hdmi/hdmim0-tx1-cec"; + hdmim0_tx1_scl = "/pinctrl/hdmi/hdmim0-tx1-scl"; + hdmim0_tx1_sda = "/pinctrl/hdmi/hdmim0-tx1-sda"; + hdmirx_det = "/pinctrl/hdmi/hdmirx-det"; + i2c0m0_xfer = "/pinctrl/i2c0/i2c0m0-xfer"; + i2c0m2_xfer = "/pinctrl/i2c0/i2c0m2-xfer"; + i2c0m1_xfer = "/pinctrl/i2c0/i2c0m1-xfer"; + i2c1m0_xfer = "/pinctrl/i2c1/i2c1m0-xfer"; + i2c1m1_xfer = "/pinctrl/i2c1/i2c1m1-xfer"; + i2c1m2_xfer = "/pinctrl/i2c1/i2c1m2-xfer"; + i2c1m3_xfer = "/pinctrl/i2c1/i2c1m3-xfer"; + i2c1m4_xfer = "/pinctrl/i2c1/i2c1m4-xfer"; + i2c2m0_xfer = "/pinctrl/i2c2/i2c2m0-xfer"; + i2c2m2_xfer = "/pinctrl/i2c2/i2c2m2-xfer"; + i2c2m3_xfer = "/pinctrl/i2c2/i2c2m3-xfer"; + i2c2m4_xfer = "/pinctrl/i2c2/i2c2m4-xfer"; + i2c2m1_xfer = "/pinctrl/i2c2/i2c2m1-xfer"; + i2c3m0_xfer = "/pinctrl/i2c3/i2c3m0-xfer"; + i2c3m1_xfer = "/pinctrl/i2c3/i2c3m1-xfer"; + i2c3m2_xfer = "/pinctrl/i2c3/i2c3m2-xfer"; + i2c3m4_xfer = "/pinctrl/i2c3/i2c3m4-xfer"; + i2c3m3_xfer = "/pinctrl/i2c3/i2c3m3-xfer"; + i2c4m0_xfer = "/pinctrl/i2c4/i2c4m0-xfer"; + i2c4m2_xfer = "/pinctrl/i2c4/i2c4m2-xfer"; + i2c4m3_xfer = "/pinctrl/i2c4/i2c4m3-xfer"; + i2c4m4_xfer = "/pinctrl/i2c4/i2c4m4-xfer"; + i2c4m1_xfer = "/pinctrl/i2c4/i2c4m1-xfer"; + i2c5m0_xfer = "/pinctrl/i2c5/i2c5m0-xfer"; + i2c5m1_xfer = "/pinctrl/i2c5/i2c5m1-xfer"; + i2c5m2_xfer = "/pinctrl/i2c5/i2c5m2-xfer"; + i2c5m3_xfer = "/pinctrl/i2c5/i2c5m3-xfer"; + i2c5m4_xfer = "/pinctrl/i2c5/i2c5m4-xfer"; + i2c6m0_xfer = "/pinctrl/i2c6/i2c6m0-xfer"; + i2c6m1_xfer = "/pinctrl/i2c6/i2c6m1-xfer"; + i2c6m3_xfer = "/pinctrl/i2c6/i2c6m3-xfer"; + i2c6m4_xfer = "/pinctrl/i2c6/i2c6m4-xfer"; + i2c6m2_xfer = "/pinctrl/i2c6/i2c6m2-xfer"; + i2c7m0_xfer = "/pinctrl/i2c7/i2c7m0-xfer"; + i2c7m2_xfer = "/pinctrl/i2c7/i2c7m2-xfer"; + i2c7m3_xfer = "/pinctrl/i2c7/i2c7m3-xfer"; + i2c7m1_xfer = "/pinctrl/i2c7/i2c7m1-xfer"; + i2c8m0_xfer = "/pinctrl/i2c8/i2c8m0-xfer"; + i2c8m2_xfer = "/pinctrl/i2c8/i2c8m2-xfer"; + i2c8m3_xfer = "/pinctrl/i2c8/i2c8m3-xfer"; + i2c8m4_xfer = "/pinctrl/i2c8/i2c8m4-xfer"; + i2c8m1_xfer = "/pinctrl/i2c8/i2c8m1-xfer"; + i2s0_idle = "/pinctrl/i2s0/i2s0-idle"; + i2s0_lrck = "/pinctrl/i2s0/i2s0-lrck"; + i2s0_mclk = "/pinctrl/i2s0/i2s0-mclk"; + i2s0_sclk = "/pinctrl/i2s0/i2s0-sclk"; + i2s0_sdi0 = "/pinctrl/i2s0/i2s0-sdi0"; + i2s0_sdi1 = "/pinctrl/i2s0/i2s0-sdi1"; + i2s0_sdi2 = "/pinctrl/i2s0/i2s0-sdi2"; + i2s0_sdi3 = "/pinctrl/i2s0/i2s0-sdi3"; + i2s0_sdo0 = "/pinctrl/i2s0/i2s0-sdo0"; + i2s0_sdo1 = "/pinctrl/i2s0/i2s0-sdo1"; + i2s0_sdo2 = "/pinctrl/i2s0/i2s0-sdo2"; + i2s0_sdo3 = "/pinctrl/i2s0/i2s0-sdo3"; + i2s1m0_lrck = "/pinctrl/i2s1/i2s1m0-lrck"; + i2s1m0_mclk = "/pinctrl/i2s1/i2s1m0-mclk"; + i2s1m0_sclk = "/pinctrl/i2s1/i2s1m0-sclk"; + i2s1m0_sdi0 = "/pinctrl/i2s1/i2s1m0-sdi0"; + i2s1m0_sdi1 = "/pinctrl/i2s1/i2s1m0-sdi1"; + i2s1m0_sdi2 = "/pinctrl/i2s1/i2s1m0-sdi2"; + i2s1m0_sdi3 = "/pinctrl/i2s1/i2s1m0-sdi3"; + i2s1m0_sdo0 = "/pinctrl/i2s1/i2s1m0-sdo0"; + i2s1m0_sdo1 = "/pinctrl/i2s1/i2s1m0-sdo1"; + i2s1m0_sdo2 = "/pinctrl/i2s1/i2s1m0-sdo2"; + i2s1m0_sdo3 = "/pinctrl/i2s1/i2s1m0-sdo3"; + i2s1m1_lrck = "/pinctrl/i2s1/i2s1m1-lrck"; + i2s1m1_mclk = "/pinctrl/i2s1/i2s1m1-mclk"; + i2s1m1_sclk = "/pinctrl/i2s1/i2s1m1-sclk"; + i2s1m1_sdi0 = "/pinctrl/i2s1/i2s1m1-sdi0"; + i2s1m1_sdi1 = "/pinctrl/i2s1/i2s1m1-sdi1"; + i2s1m1_sdi2 = "/pinctrl/i2s1/i2s1m1-sdi2"; + i2s1m1_sdi3 = "/pinctrl/i2s1/i2s1m1-sdi3"; + i2s1m1_sdo0 = "/pinctrl/i2s1/i2s1m1-sdo0"; + i2s1m1_sdo1 = "/pinctrl/i2s1/i2s1m1-sdo1"; + i2s1m1_sdo2 = "/pinctrl/i2s1/i2s1m1-sdo2"; + i2s1m1_sdo3 = "/pinctrl/i2s1/i2s1m1-sdo3"; + i2s2m1_idle = "/pinctrl/i2s2/i2s2m1-idle"; + i2s2m1_lrck = "/pinctrl/i2s2/i2s2m1-lrck"; + i2s2m1_mclk = "/pinctrl/i2s2/i2s2m1-mclk"; + i2s2m1_sclk = "/pinctrl/i2s2/i2s2m1-sclk"; + i2s2m1_sdi = "/pinctrl/i2s2/i2s2m1-sdi"; + i2s2m1_sdo = "/pinctrl/i2s2/i2s2m1-sdo"; + i2s2m0_idle = "/pinctrl/i2s2/i2s2m0-idle"; + i2s2m0_lrck = "/pinctrl/i2s2/i2s2m0-lrck"; + i2s2m0_mclk = "/pinctrl/i2s2/i2s2m0-mclk"; + i2s2m0_sclk = "/pinctrl/i2s2/i2s2m0-sclk"; + i2s2m0_sdi = "/pinctrl/i2s2/i2s2m0-sdi"; + i2s2m0_sdo = "/pinctrl/i2s2/i2s2m0-sdo"; + i2s3_idle = "/pinctrl/i2s3/i2s3-idle"; + i2s3_lrck = "/pinctrl/i2s3/i2s3-lrck"; + i2s3_mclk = "/pinctrl/i2s3/i2s3-mclk"; + i2s3_sclk = "/pinctrl/i2s3/i2s3-sclk"; + i2s3_sdi = "/pinctrl/i2s3/i2s3-sdi"; + i2s3_sdo = "/pinctrl/i2s3/i2s3-sdo"; + jtagm0_pins = "/pinctrl/jtag/jtagm0-pins"; + jtagm1_pins = "/pinctrl/jtag/jtagm1-pins"; + jtagm2_pins = "/pinctrl/jtag/jtagm2-pins"; + litcpu_pins = "/pinctrl/litcpu/litcpu-pins"; + mcum0_pins = "/pinctrl/mcu/mcum0-pins"; + mcum1_pins = "/pinctrl/mcu/mcum1-pins"; + mipim0_camera0_clk = "/pinctrl/mipi/mipim0-camera0-clk"; + mipim0_camera1_clk = "/pinctrl/mipi/mipim0-camera1-clk"; + mipim0_camera2_clk = "/pinctrl/mipi/mipim0-camera2-clk"; + mipim0_camera3_clk = "/pinctrl/mipi/mipim0-camera3-clk"; + mipim0_camera4_clk = "/pinctrl/mipi/mipim0-camera4-clk"; + mipim1_camera0_clk = "/pinctrl/mipi/mipim1-camera0-clk"; + mipim1_camera1_clk = "/pinctrl/mipi/mipim1-camera1-clk"; + mipim1_camera2_clk = "/pinctrl/mipi/mipim1-camera2-clk"; + mipim1_camera3_clk = "/pinctrl/mipi/mipim1-camera3-clk"; + mipim1_camera4_clk = "/pinctrl/mipi/mipim1-camera4-clk"; + mipi_te0 = "/pinctrl/mipi/mipi-te0"; + mipi_te1 = "/pinctrl/mipi/mipi-te1"; + npu_pins = "/pinctrl/npu/npu-pins"; + pcie20x1m0_pins = "/pinctrl/pcie20x1/pcie20x1m0-pins"; + pcie20x1m1_pins = "/pinctrl/pcie20x1/pcie20x1m1-pins"; + pcie20x1_2_button_rstn = "/pinctrl/pcie20x1/pcie20x1-2-button-rstn"; + pcie30phy_pins = "/pinctrl/pcie30phy/pcie30phy-pins"; + pcie30x1m0_pins = "/pinctrl/pcie30x1/pcie30x1m0-pins"; + pcie30x1m1_pins = "/pinctrl/pcie30x1/pcie30x1m1-pins"; + pcie30x1m2_pins = "/pinctrl/pcie30x1/pcie30x1m2-pins"; + pcie30x1_0_button_rstn = "/pinctrl/pcie30x1/pcie30x1-0-button-rstn"; + pcie30x1_1_button_rstn = "/pinctrl/pcie30x1/pcie30x1-1-button-rstn"; + pcie30x2m0_pins = "/pinctrl/pcie30x2/pcie30x2m0-pins"; + pcie30x2m1_pins = "/pinctrl/pcie30x2/pcie30x2m1-pins"; + pcie30x2m2_pins = "/pinctrl/pcie30x2/pcie30x2m2-pins"; + pcie30x2m3_pins = "/pinctrl/pcie30x2/pcie30x2m3-pins"; + pcie30x2_button_rstn = "/pinctrl/pcie30x2/pcie30x2-button-rstn"; + pcie30x4m0_pins = "/pinctrl/pcie30x4/pcie30x4m0-pins"; + pcie30x4m1_pins = "/pinctrl/pcie30x4/pcie30x4m1-pins"; + pcie30x4m2_pins = "/pinctrl/pcie30x4/pcie30x4m2-pins"; + pcie30x4m3_pins = "/pinctrl/pcie30x4/pcie30x4m3-pins"; + pcie30x4_button_rstn = "/pinctrl/pcie30x4/pcie30x4-button-rstn"; + pdm0m0_clk = "/pinctrl/pdm0/pdm0m0-clk"; + pdm0m0_clk1 = "/pinctrl/pdm0/pdm0m0-clk1"; + pdm0m0_idle = "/pinctrl/pdm0/pdm0m0-idle"; + pdm0m0_sdi0 = "/pinctrl/pdm0/pdm0m0-sdi0"; + pdm0m0_sdi1 = "/pinctrl/pdm0/pdm0m0-sdi1"; + pdm0m0_sdi2 = "/pinctrl/pdm0/pdm0m0-sdi2"; + pdm0m0_sdi3 = "/pinctrl/pdm0/pdm0m0-sdi3"; + pdm0m1_clk = "/pinctrl/pdm0/pdm0m1-clk"; + pdm0m1_clk1 = "/pinctrl/pdm0/pdm0m1-clk1"; + pdm0m1_idle = "/pinctrl/pdm0/pdm0m1-idle"; + pdm0m1_sdi0 = "/pinctrl/pdm0/pdm0m1-sdi0"; + pdm0m1_sdi1 = "/pinctrl/pdm0/pdm0m1-sdi1"; + pdm0m1_sdi2 = "/pinctrl/pdm0/pdm0m1-sdi2"; + pdm0m1_sdi3 = "/pinctrl/pdm0/pdm0m1-sdi3"; + pdm1m0_clk = "/pinctrl/pdm1/pdm1m0-clk"; + pdm1m0_clk1 = "/pinctrl/pdm1/pdm1m0-clk1"; + pdm1m0_idle = "/pinctrl/pdm1/pdm1m0-idle"; + pdm1m0_sdi0 = "/pinctrl/pdm1/pdm1m0-sdi0"; + pdm1m0_sdi1 = "/pinctrl/pdm1/pdm1m0-sdi1"; + pdm1m0_sdi2 = "/pinctrl/pdm1/pdm1m0-sdi2"; + pdm1m0_sdi3 = "/pinctrl/pdm1/pdm1m0-sdi3"; + pdm1m1_clk = "/pinctrl/pdm1/pdm1m1-clk"; + pdm1m1_clk1 = "/pinctrl/pdm1/pdm1m1-clk1"; + pdm1m1_idle = "/pinctrl/pdm1/pdm1m1-idle"; + pdm1m1_sdi0 = "/pinctrl/pdm1/pdm1m1-sdi0"; + pdm1m1_sdi1 = "/pinctrl/pdm1/pdm1m1-sdi1"; + pdm1m1_sdi2 = "/pinctrl/pdm1/pdm1m1-sdi2"; + pdm1m1_sdi3 = "/pinctrl/pdm1/pdm1m1-sdi3"; + pmic_pins = "/pinctrl/pmic/pmic-pins"; + pmu_pins = "/pinctrl/pmu/pmu-pins"; + pwm0m0_pins = "/pinctrl/pwm0/pwm0m0-pins"; + pwm0m1_pins = "/pinctrl/pwm0/pwm0m1-pins"; + pwm0m2_pins = "/pinctrl/pwm0/pwm0m2-pins"; + pwm1m0_pins = "/pinctrl/pwm1/pwm1m0-pins"; + pwm1m1_pins = "/pinctrl/pwm1/pwm1m1-pins"; + pwm1m2_pins = "/pinctrl/pwm1/pwm1m2-pins"; + pwm2m0_pins = "/pinctrl/pwm2/pwm2m0-pins"; + pwm2m1_pins = "/pinctrl/pwm2/pwm2m1-pins"; + pwm2m2_pins = "/pinctrl/pwm2/pwm2m2-pins"; + pwm3m0_pins = "/pinctrl/pwm3/pwm3m0-pins"; + pwm3m1_pins = "/pinctrl/pwm3/pwm3m1-pins"; + pwm3m2_pins = "/pinctrl/pwm3/pwm3m2-pins"; + pwm3m3_pins = "/pinctrl/pwm3/pwm3m3-pins"; + pwm4m0_pins = "/pinctrl/pwm4/pwm4m0-pins"; + pwm4m1_pins = "/pinctrl/pwm4/pwm4m1-pins"; + pwm5m0_pins = "/pinctrl/pwm5/pwm5m0-pins"; + pwm5m1_pins = "/pinctrl/pwm5/pwm5m1-pins"; + pwm5m2_pins = "/pinctrl/pwm5/pwm5m2-pins"; + pwm6m0_pins = "/pinctrl/pwm6/pwm6m0-pins"; + pwm6m1_pins = "/pinctrl/pwm6/pwm6m1-pins"; + pwm6m2_pins = "/pinctrl/pwm6/pwm6m2-pins"; + pwm7m0_pins = "/pinctrl/pwm7/pwm7m0-pins"; + pwm7m1_pins = "/pinctrl/pwm7/pwm7m1-pins"; + pwm7m2_pins = "/pinctrl/pwm7/pwm7m2-pins"; + pwm7m3_pins = "/pinctrl/pwm7/pwm7m3-pins"; + pwm8m0_pins = "/pinctrl/pwm8/pwm8m0-pins"; + pwm8m1_pins = "/pinctrl/pwm8/pwm8m1-pins"; + pwm8m2_pins = "/pinctrl/pwm8/pwm8m2-pins"; + pwm9m0_pins = "/pinctrl/pwm9/pwm9m0-pins"; + pwm9m1_pins = "/pinctrl/pwm9/pwm9m1-pins"; + pwm9m2_pins = "/pinctrl/pwm9/pwm9m2-pins"; + pwm10m0_pins = "/pinctrl/pwm10/pwm10m0-pins"; + pwm10m1_pins = "/pinctrl/pwm10/pwm10m1-pins"; + pwm10m2_pins = "/pinctrl/pwm10/pwm10m2-pins"; + pwm11m0_pins = "/pinctrl/pwm11/pwm11m0-pins"; + pwm11m1_pins = "/pinctrl/pwm11/pwm11m1-pins"; + pwm11m2_pins = "/pinctrl/pwm11/pwm11m2-pins"; + pwm11m3_pins = "/pinctrl/pwm11/pwm11m3-pins"; + pwm12m0_pins = "/pinctrl/pwm12/pwm12m0-pins"; + pwm12m1_pins = "/pinctrl/pwm12/pwm12m1-pins"; + pwm13m0_pins = "/pinctrl/pwm13/pwm13m0-pins"; + pwm13m1_pins = "/pinctrl/pwm13/pwm13m1-pins"; + pwm13m2_pins = "/pinctrl/pwm13/pwm13m2-pins"; + pwm14m0_pins = "/pinctrl/pwm14/pwm14m0-pins"; + pwm14m1_pins = "/pinctrl/pwm14/pwm14m1-pins"; + pwm14m2_pins = "/pinctrl/pwm14/pwm14m2-pins"; + pwm15m0_pins = "/pinctrl/pwm15/pwm15m0-pins"; + pwm15m1_pins = "/pinctrl/pwm15/pwm15m1-pins"; + pwm15m2_pins = "/pinctrl/pwm15/pwm15m2-pins"; + pwm15m3_pins = "/pinctrl/pwm15/pwm15m3-pins"; + refclk_pins = "/pinctrl/refclk/refclk-pins"; + sata_pins = "/pinctrl/sata/sata-pins"; + sata0m0_pins = "/pinctrl/sata0/sata0m0-pins"; + sata0m1_pins = "/pinctrl/sata0/sata0m1-pins"; + sata1m0_pins = "/pinctrl/sata1/sata1m0-pins"; + sata1m1_pins = "/pinctrl/sata1/sata1m1-pins"; + sata2m0_pins = "/pinctrl/sata2/sata2m0-pins"; + sata2m1_pins = "/pinctrl/sata2/sata2m1-pins"; + sdiom1_pins = "/pinctrl/sdio/sdiom1-pins"; + sdiom0_pins = "/pinctrl/sdio/sdiom0-pins"; + sdmmc_bus4 = "/pinctrl/sdmmc/sdmmc-bus4"; + sdmmc_clk = "/pinctrl/sdmmc/sdmmc-clk"; + sdmmc_cmd = "/pinctrl/sdmmc/sdmmc-cmd"; + sdmmc_det = "/pinctrl/sdmmc/sdmmc-det"; + sdmmc_pwren = "/pinctrl/sdmmc/sdmmc-pwren"; + sd_s0_pwr = "/pinctrl/sdmmc/sd-s0-pwr"; + spdif0m0_tx = "/pinctrl/spdif0/spdif0m0-tx"; + spdif0m1_tx = "/pinctrl/spdif0/spdif0m1-tx"; + spdif1m0_tx = "/pinctrl/spdif1/spdif1m0-tx"; + spdif1m1_tx = "/pinctrl/spdif1/spdif1m1-tx"; + spdif1m2_tx = "/pinctrl/spdif1/spdif1m2-tx"; + spi0m0_pins = "/pinctrl/spi0/spi0m0-pins"; + spi0m0_cs0 = "/pinctrl/spi0/spi0m0-cs0"; + spi0m0_cs1 = "/pinctrl/spi0/spi0m0-cs1"; + spi0m1_pins = "/pinctrl/spi0/spi0m1-pins"; + spi0m1_cs0 = "/pinctrl/spi0/spi0m1-cs0"; + spi0m1_cs1 = "/pinctrl/spi0/spi0m1-cs1"; + spi0m2_pins = "/pinctrl/spi0/spi0m2-pins"; + spi0m2_cs0 = "/pinctrl/spi0/spi0m2-cs0"; + spi0m2_cs1 = "/pinctrl/spi0/spi0m2-cs1"; + spi0m3_pins = "/pinctrl/spi0/spi0m3-pins"; + spi0m3_cs0 = "/pinctrl/spi0/spi0m3-cs0"; + spi0m3_cs1 = "/pinctrl/spi0/spi0m3-cs1"; + spi1m1_pins = "/pinctrl/spi1/spi1m1-pins"; + spi1m1_cs0 = "/pinctrl/spi1/spi1m1-cs0"; + spi1m1_cs1 = "/pinctrl/spi1/spi1m1-cs1"; + spi1m2_pins = "/pinctrl/spi1/spi1m2-pins"; + spi1m2_cs0 = "/pinctrl/spi1/spi1m2-cs0"; + spi1m2_cs1 = "/pinctrl/spi1/spi1m2-cs1"; + spi1m0_pins = "/pinctrl/spi1/spi1m0-pins"; + spi1m0_cs0 = "/pinctrl/spi1/spi1m0-cs0"; + spi1m0_cs1 = "/pinctrl/spi1/spi1m0-cs1"; + spi2m0_pins = "/pinctrl/spi2/spi2m0-pins"; + spi2m0_cs0 = "/pinctrl/spi2/spi2m0-cs0"; + spi2m0_cs1 = "/pinctrl/spi2/spi2m0-cs1"; + spi2m1_pins = "/pinctrl/spi2/spi2m1-pins"; + spi2m1_cs0 = "/pinctrl/spi2/spi2m1-cs0"; + spi2m1_cs1 = "/pinctrl/spi2/spi2m1-cs1"; + spi2m2_pins = "/pinctrl/spi2/spi2m2-pins"; + spi2m2_cs0 = "/pinctrl/spi2/spi2m2-cs0"; + spi2m2_cs1 = "/pinctrl/spi2/spi2m2-cs1"; + spi3m1_pins = "/pinctrl/spi3/spi3m1-pins"; + spi3m1_cs0 = "/pinctrl/spi3/spi3m1-cs0"; + spi3m1_cs1 = "/pinctrl/spi3/spi3m1-cs1"; + spi3m2_pins = "/pinctrl/spi3/spi3m2-pins"; + spi3m2_cs0 = "/pinctrl/spi3/spi3m2-cs0"; + spi3m2_cs1 = "/pinctrl/spi3/spi3m2-cs1"; + spi3m3_pins = "/pinctrl/spi3/spi3m3-pins"; + spi3m3_cs0 = "/pinctrl/spi3/spi3m3-cs0"; + spi3m3_cs1 = "/pinctrl/spi3/spi3m3-cs1"; + spi3m0_pins = "/pinctrl/spi3/spi3m0-pins"; + spi3m0_cs0 = "/pinctrl/spi3/spi3m0-cs0"; + spi3m0_cs1 = "/pinctrl/spi3/spi3m0-cs1"; + spi4m0_pins = "/pinctrl/spi4/spi4m0-pins"; + spi4m0_cs0 = "/pinctrl/spi4/spi4m0-cs0"; + spi4m0_cs1 = "/pinctrl/spi4/spi4m0-cs1"; + spi4m1_pins = "/pinctrl/spi4/spi4m1-pins"; + spi4m1_cs0 = "/pinctrl/spi4/spi4m1-cs0"; + spi4m1_cs1 = "/pinctrl/spi4/spi4m1-cs1"; + spi4m2_pins = "/pinctrl/spi4/spi4m2-pins"; + spi4m2_cs0 = "/pinctrl/spi4/spi4m2-cs0"; + tsadcm1_shut = "/pinctrl/tsadc/tsadcm1-shut"; + tsadc_shut = "/pinctrl/tsadc/tsadc-shut"; + tsadc_shut_org = "/pinctrl/tsadc/tsadc-shut-org"; + uart0m0_xfer = "/pinctrl/uart0/uart0m0-xfer"; + uart0m1_xfer = "/pinctrl/uart0/uart0m1-xfer"; + uart0m2_xfer = "/pinctrl/uart0/uart0m2-xfer"; + uart0_ctsn = "/pinctrl/uart0/uart0-ctsn"; + uart0_rtsn = "/pinctrl/uart0/uart0-rtsn"; + uart1m1_xfer = "/pinctrl/uart1/uart1m1-xfer"; + uart1m1_ctsn = "/pinctrl/uart1/uart1m1-ctsn"; + uart1m1_rtsn = "/pinctrl/uart1/uart1m1-rtsn"; + uart1m2_xfer = "/pinctrl/uart1/uart1m2-xfer"; + uart1m2_ctsn = "/pinctrl/uart1/uart1m2-ctsn"; + uart1m2_rtsn = "/pinctrl/uart1/uart1m2-rtsn"; + uart1m0_xfer = "/pinctrl/uart1/uart1m0-xfer"; + uart1m0_ctsn = "/pinctrl/uart1/uart1m0-ctsn"; + uart1m0_rtsn = "/pinctrl/uart1/uart1m0-rtsn"; + uart2m0_xfer = "/pinctrl/uart2/uart2m0-xfer"; + uart2m1_xfer = "/pinctrl/uart2/uart2m1-xfer"; + uart2m2_xfer = "/pinctrl/uart2/uart2m2-xfer"; + uart2_ctsn = "/pinctrl/uart2/uart2-ctsn"; + uart2_rtsn = "/pinctrl/uart2/uart2-rtsn"; + uart3m0_xfer = "/pinctrl/uart3/uart3m0-xfer"; + uart3m1_xfer = "/pinctrl/uart3/uart3m1-xfer"; + uart3m2_xfer = "/pinctrl/uart3/uart3m2-xfer"; + uart3_ctsn = "/pinctrl/uart3/uart3-ctsn"; + uart3_rtsn = "/pinctrl/uart3/uart3-rtsn"; + uart4m0_xfer = "/pinctrl/uart4/uart4m0-xfer"; + uart4m1_xfer = "/pinctrl/uart4/uart4m1-xfer"; + uart4m2_xfer = "/pinctrl/uart4/uart4m2-xfer"; + uart4_ctsn = "/pinctrl/uart4/uart4-ctsn"; + uart4_rtsn = "/pinctrl/uart4/uart4-rtsn"; + uart5m0_xfer = "/pinctrl/uart5/uart5m0-xfer"; + uart5m0_ctsn = "/pinctrl/uart5/uart5m0-ctsn"; + uart5m0_rtsn = "/pinctrl/uart5/uart5m0-rtsn"; + uart5m1_xfer = "/pinctrl/uart5/uart5m1-xfer"; + uart5m1_ctsn = "/pinctrl/uart5/uart5m1-ctsn"; + uart5m1_rtsn = "/pinctrl/uart5/uart5m1-rtsn"; + uart5m2_xfer = "/pinctrl/uart5/uart5m2-xfer"; + uart6m1_xfer = "/pinctrl/uart6/uart6m1-xfer"; + uart6m1_ctsn = "/pinctrl/uart6/uart6m1-ctsn"; + uart6m1_rtsn = "/pinctrl/uart6/uart6m1-rtsn"; + uart6m2_xfer = "/pinctrl/uart6/uart6m2-xfer"; + uart6m0_xfer = "/pinctrl/uart6/uart6m0-xfer"; + uart6m0_ctsn = "/pinctrl/uart6/uart6m0-ctsn"; + uart6m0_rtsn = "/pinctrl/uart6/uart6m0-rtsn"; + uart7m1_xfer = "/pinctrl/uart7/uart7m1-xfer"; + uart7m1_ctsn = "/pinctrl/uart7/uart7m1-ctsn"; + uart7m1_rtsn = "/pinctrl/uart7/uart7m1-rtsn"; + uart7m2_xfer = "/pinctrl/uart7/uart7m2-xfer"; + uart7m0_xfer = "/pinctrl/uart7/uart7m0-xfer"; + uart7m0_ctsn = "/pinctrl/uart7/uart7m0-ctsn"; + uart7m0_rtsn = "/pinctrl/uart7/uart7m0-rtsn"; + uart8m0_xfer = "/pinctrl/uart8/uart8m0-xfer"; + uart8m0_ctsn = "/pinctrl/uart8/uart8m0-ctsn"; + uart8m0_rtsn = "/pinctrl/uart8/uart8m0-rtsn"; + uart8m1_xfer = "/pinctrl/uart8/uart8m1-xfer"; + uart8m1_ctsn = "/pinctrl/uart8/uart8m1-ctsn"; + uart8m1_rtsn = "/pinctrl/uart8/uart8m1-rtsn"; + uart8_xfer = "/pinctrl/uart8/uart8-xfer"; + uart9m1_xfer = "/pinctrl/uart9/uart9m1-xfer"; + uart9m1_ctsn = "/pinctrl/uart9/uart9m1-ctsn"; + uart9m1_rtsn = "/pinctrl/uart9/uart9m1-rtsn"; + uart9m2_xfer = "/pinctrl/uart9/uart9m2-xfer"; + uart9m2_ctsn = "/pinctrl/uart9/uart9m2-ctsn"; + uart9m2_rtsn = "/pinctrl/uart9/uart9m2-rtsn"; + uart9m0_xfer = "/pinctrl/uart9/uart9m0-xfer"; + uart9m0_ctsn = "/pinctrl/uart9/uart9m0-ctsn"; + uart9m0_rtsn = "/pinctrl/uart9/uart9m0-rtsn"; + vop_pins = "/pinctrl/vop/vop-pins"; + bt656_pins = "/pinctrl/bt656/bt656-pins"; + tsadc_gpio_func = "/pinctrl/gpio-func/tsadc-gpio-func"; + pcfg_pull_none_drv_level_7 = "/pinctrl/pcfg-pull-none-drv-level-7"; + pcfg_pull_none_drv_level_8 = "/pinctrl/pcfg-pull-none-drv-level-8"; + pcfg_pull_none_drv_level_9 = "/pinctrl/pcfg-pull-none-drv-level-9"; + pcfg_pull_none_drv_level_10 = "/pinctrl/pcfg-pull-none-drv-level-10"; + pcfg_pull_none_drv_level_11 = "/pinctrl/pcfg-pull-none-drv-level-11"; + pcfg_pull_none_drv_level_12 = "/pinctrl/pcfg-pull-none-drv-level-12"; + pcfg_pull_none_drv_level_13 = "/pinctrl/pcfg-pull-none-drv-level-13"; + pcfg_pull_none_drv_level_14 = "/pinctrl/pcfg-pull-none-drv-level-14"; + pcfg_pull_none_drv_level_15 = "/pinctrl/pcfg-pull-none-drv-level-15"; + pcfg_pull_up_drv_level_7 = "/pinctrl/pcfg-pull-up-drv-level-7"; + pcfg_pull_up_drv_level_8 = "/pinctrl/pcfg-pull-up-drv-level-8"; + pcfg_pull_up_drv_level_9 = "/pinctrl/pcfg-pull-up-drv-level-9"; + pcfg_pull_up_drv_level_10 = "/pinctrl/pcfg-pull-up-drv-level-10"; + pcfg_pull_up_drv_level_11 = "/pinctrl/pcfg-pull-up-drv-level-11"; + pcfg_pull_up_drv_level_12 = "/pinctrl/pcfg-pull-up-drv-level-12"; + pcfg_pull_up_drv_level_13 = "/pinctrl/pcfg-pull-up-drv-level-13"; + pcfg_pull_up_drv_level_14 = "/pinctrl/pcfg-pull-up-drv-level-14"; + pcfg_pull_up_drv_level_15 = "/pinctrl/pcfg-pull-up-drv-level-15"; + pcfg_pull_down_drv_level_7 = "/pinctrl/pcfg-pull-down-drv-level-7"; + pcfg_pull_down_drv_level_8 = "/pinctrl/pcfg-pull-down-drv-level-8"; + pcfg_pull_down_drv_level_9 = "/pinctrl/pcfg-pull-down-drv-level-9"; + pcfg_pull_down_drv_level_10 = "/pinctrl/pcfg-pull-down-drv-level-10"; + pcfg_pull_down_drv_level_11 = "/pinctrl/pcfg-pull-down-drv-level-11"; + pcfg_pull_down_drv_level_12 = "/pinctrl/pcfg-pull-down-drv-level-12"; + pcfg_pull_down_drv_level_13 = "/pinctrl/pcfg-pull-down-drv-level-13"; + pcfg_pull_down_drv_level_14 = "/pinctrl/pcfg-pull-down-drv-level-14"; + pcfg_pull_down_drv_level_15 = "/pinctrl/pcfg-pull-down-drv-level-15"; + eth0_pins = "/pinctrl/eth0/eth0-pins"; + gmac0_miim = "/pinctrl/gmac0/gmac0-miim"; + gmac0_clkinout = "/pinctrl/gmac0/gmac0-clkinout"; + gmac0_rx_bus2 = "/pinctrl/gmac0/gmac0-rx-bus2"; + gmac0_tx_bus2 = "/pinctrl/gmac0/gmac0-tx-bus2"; + gmac0_rgmii_clk = "/pinctrl/gmac0/gmac0-rgmii-clk"; + gmac0_rgmii_bus = "/pinctrl/gmac0/gmac0-rgmii-bus"; + gmac0_ppsclk = "/pinctrl/gmac0/gmac0-ppsclk"; + gmac0_ppstring = "/pinctrl/gmac0/gmac0-ppstring"; + gmac0_ptp_refclk = "/pinctrl/gmac0/gmac0-ptp-refclk"; + gmac0_txer = "/pinctrl/gmac0/gmac0-txer"; + mipicsi0_pwr = "/pinctrl/cam/mipicsi0-pwr"; + mipicsi1_pwr = "/pinctrl/cam/mipicsi1-pwr"; + mipidcphy0_pwr = "/pinctrl/cam/mipidcphy0-pwr"; + mipidphy0_pwr = "/pinctrl/cam/mipidphy0-pwr"; + hp_det = "/pinctrl/headphone/hp-det"; + hym8563_int = "/pinctrl/hym8563/hym8563-int"; + lcd_rst_gpio = "/pinctrl/lcd/lcd-rst-gpio"; + work_leds_gpio = "/pinctrl/leds/work-leds-gpio"; + wifi_enable_h = "/pinctrl/sdio-pwrseq/wifi-enable-h"; + touch_gpio = "/pinctrl/touch/touch-gpio"; + ts_int_active = "/pinctrl/touch/ts_int_active"; + ts_reset_active = "/pinctrl/touch/ts_reset_active"; + ts_int_suspend = "/pinctrl/touch/ts_int_suspend"; + ts_reset_suspend = "/pinctrl/touch/ts_reset_suspend"; + vcc5v0_host_en = "/pinctrl/usb/vcc5v0-host-en"; + usbc0_int = "/pinctrl/usb-typec/usbc0-int"; + typec5v_pwren = "/pinctrl/usb-typec/typec5v-pwren"; + uart9_gpios = "/pinctrl/wireless-bluetooth/uart9-gpios"; + bt_reset_gpio = "/pinctrl/wireless-bluetooth/bt-reset-gpio"; + bt_wake_gpio = "/pinctrl/wireless-bluetooth/bt-wake-gpio"; + bt_irq_gpio = "/pinctrl/wireless-bluetooth/bt-irq-gpio"; + wifi_host_wake_irq = "/pinctrl/wireless-wlan/wifi-host-wake-irq"; + pcie20x1_0_clkreqn_m1 = "/pinctrl/pcie/pcie20x1-0-clkreqn-m1"; + usbdrd3_1 = "/usbdrd3_1"; + usbdrd_dwc3_1 = "/usbdrd3_1/usb@fc400000"; + pcie30_phy_grf = "/syscon@fd5b8000"; + pipe_phy1_grf = "/syscon@fd5c0000"; + usbdpphy1_grf = "/syscon@fd5cc000"; + usb2phy1_grf = "/syscon@fd5d4000"; + u2phy1 = "/syscon@fd5d4000/usb2-phy@4000"; + u2phy1_otg = "/syscon@fd5d4000/usb2-phy@4000/otg-port"; + hdptxphy1_grf = "/syscon@fd5e4000"; + spdif_tx5 = "/spdif-tx@fddb8000"; + i2s8_8ch = "/i2s@fddc8000"; + spdif_tx4 = "/spdif-tx@fdde8000"; + i2s6_8ch = "/i2s@fddf4000"; + i2s7_8ch = "/i2s@fddf8000"; + i2s10_8ch = "/i2s@fde00000"; + spdif_rx1 = "/spdif-rx@fde10000"; + spdif_rx2 = "/spdif-rx@fde18000"; + dp1 = "/dp@fde60000"; + dp1_in_vp0 = "/dp@fde60000/ports/port@0/endpoint@0"; + dp1_in_vp1 = "/dp@fde60000/ports/port@0/endpoint@1"; + dp1_in_vp2 = "/dp@fde60000/ports/port@0/endpoint@2"; + dp1_out = "/dp@fde60000/ports/port@1/endpoint"; + hdmi1 = "/hdmi@fdea0000"; + hdmi1_in = "/hdmi@fdea0000/ports/port@0"; + hdmi1_in_vp0 = "/hdmi@fdea0000/ports/port@0/endpoint@0"; + hdmi1_in_vp1 = "/hdmi@fdea0000/ports/port@0/endpoint@1"; + hdmi1_in_vp2 = "/hdmi@fdea0000/ports/port@0/endpoint@2"; + edp1 = "/edp@fded0000"; + edp1_in_vp0 = "/edp@fded0000/ports/port@0/endpoint@0"; + edp1_in_vp1 = "/edp@fded0000/ports/port@0/endpoint@1"; + edp1_in_vp2 = "/edp@fded0000/ports/port@0/endpoint@2"; + edp1_out = "/edp@fded0000/ports/port@1/endpoint"; + hdmirx_ctrler = "/hdmirx-controller@fdee0000"; + pcie3x4 = "/pcie@fe150000"; + pcie3x4_intc = "/pcie@fe150000/legacy-interrupt-controller"; + pcie3x2 = "/pcie@fe160000"; + pcie3x2_intc = "/pcie@fe160000/legacy-interrupt-controller"; + pcie2x1l0 = "/pcie@fe170000"; + pcie2x1l0_intc = "/pcie@fe170000/legacy-interrupt-controller"; + gmac_uio0 = "/uio@fe1b0000"; + gmac0 = "/ethernet@fe1b0000"; + mdio0 = "/ethernet@fe1b0000/mdio"; + gmac0_stmmac_axi_setup = "/ethernet@fe1b0000/stmmac-axi-config"; + gmac0_mtl_rx_setup = "/ethernet@fe1b0000/rx-queues-config"; + gmac0_mtl_tx_setup = "/ethernet@fe1b0000/tx-queues-config"; + sata1 = "/sata@fe220000"; + hdptxphy1 = "/phy@fed70000"; + hdptxphy_hdmi1 = "/hdmiphy@fed70000"; + usbdp_phy1 = "/phy@fed90000"; + usbdp_phy1_dp = "/phy@fed90000/dp-port"; + usbdp_phy1_u3 = "/phy@fed90000/u3-port"; + combphy1_ps = "/phy@fee10000"; + pcie30phy = "/phy@fee80000"; + adc_keys = "/adc-keys"; + backlight = "/backlight"; + bt_sco = "/bt-sco"; + bt_sound = "/bt-sound"; + edp0_sound = "/edp0-sound"; + edp1_sound = "/edp1-sound"; + hdmi0_sound = "/hdmi0-sound"; + hdmi1_sound = "/hdmi1-sound"; + dp0_sound = "/dp0-sound"; + dp1_sound = "/dp1-sound"; + leds = "/leds"; + work_led = "/leds/work"; + spdif_tx0_dc = "/spdif-tx0-dc"; + spdif_tx0_sound = "/spdif-tx0-sound"; + spdif_tx1_dc = "/spdif-tx1-dc"; + spdif_tx1_sound = "/spdif-tx1-sound"; + vcc12v_dcin = "/vcc12v-dcin"; + vcc5v0_sys = "/vcc5v0-sys"; + vcc5v0_usbdcin = "/vcc5v0-usbdcin"; + vcc5v0_usb = "/vcc5v0-usb"; + drm_logo = "/reserved-memory/drm-logo@0"; + drm_cubic_lut = "/reserved-memory/drm-cubic-lut@0"; + ramoops = "/reserved-memory/ramoops@110000"; + minidump_smem = "/reserved-memory/minidump-smem@1f0000"; + minidump_mem = "/reserved-memory/minidump-mem@c000000"; + es8388_sound = "/es8388-sound"; + fan = "/pwm-fan"; + pcie20_avdd0v85 = "/pcie20-avdd0v85"; + pcie20_avdd1v8 = "/pcie20-avdd1v8"; + pcie30_avdd0v75 = "/pcie30-avdd0v75"; + pcie30_avdd1v8 = "/pcie30-avdd1v8"; + sdio_pwrseq = "/sdio-pwrseq"; + rk_headset = "/rk-headset"; + vcc_1v1_nldo_s3 = "/vcc-1v1-nldo-s3"; + vbus5v0_typec = "/vbus5v0-typec"; + vcc3v3_lcd_n = "/vcc3v3-lcd0-n"; + vcc3v3_pcie30 = "/vcc3v3-pcie30"; + vcc5v0_host = "/vcc5v0-host"; + vcc_mipicsi0 = "/vcc-mipicsi0-regulator"; + vcc_mipicsi1 = "/vcc-mipicsi1-regulator"; + vcc_mipidphy0 = "/vcc-mipidcphy0-regulator"; + vcc_mipidcphy0 = "/vcc-mipidcphy0-regulator"; + vcc_3v3_sd_s0 = "/vcc-3v3-sd-s0-regulator"; + wireless_bluetooth = "/wireless-bluetooth"; + wireless_wlan = "/wireless-wlan"; + chosen = "/chosen"; + cspmu = "/cspmu@fd10c000"; + debug = "/debug@fd104000"; + fiq_debugger = "/fiq-debugger"; + minidump = "/minidump"; + }; +}; + +/ { + hvisor_virtio_device { + compatible = "hvisor"; + interrupt-parent = <0x1>; + interrupts = <0x00 0x20 0x01>; + power-domains = <0x06 0x09>, <0x06 0x0a>, <0x06 0x0b>, + <0x06 0x0c>, + <0x06 0x18>, <0x06 0x1a>; + clocks = <0x0f 0x06>, <0x02 0x12d>, <0x02 0x122>, <0x02 0x124>, + <0x02 0x12e>, <0x02 0x123>, <0x02 0x125>, <0x02 0x131>, + <0x0f 0x05>, <0x02 0x115>, <0x02 0x116>, <0x02 0x114>, + <0x02 0x270>, /* VOP: aclk_vop */ + <0x02 0x26f>, /* VOP: hclk_vop */ + <0x02 0x274>, /* VOP+DISP: dclk_vp0 */ + <0x02 0x275>, /* VOP+DISP: dclk_vp1 */ + <0x02 0x276>, /* VOP+DISP: dclk_vp2 */ + <0x02 0x277>, /* VOP+DISP: dclk_vp3 */ + <0x02 0x26e>, /* VOP: pclk_vop */ + <0x02 0x271>, /* VOP: dclk_src_vp0 */ + <0x02 0x272>, /* VOP: dclk_src_vp1 */ + <0x02 0x273>, /* VOP: dclk_src_vp2 */ + <0x02 0x27d>, /* VOP: aclk_dovi */ + <0x02 0x27e>, /* VOP: aclk_vop_div2 */ + <0x02 0x26b>, /* VOP: aclk_vop_root */ + <0x02 0x221>, /* HDMI0: pclk */ + <0x02 0x265>, /* HDMI0: hpd */ + <0x02 0x222>, /* HDMI0: earc */ + <0x02 0x223>, /* HDMI0: hdmitx_ref */ + <0x02 0x246>, /* HDMI0: aud */ + <0x02 0x224>, /* HDMI1: pclk */ + <0x02 0x266>, /* HDMI1: hpd */ + <0x02 0x225>, /* HDMI1: earc */ + <0x02 0x226>, /* HDMI1: hdmitx_ref */ + <0x02 0x24c>, /* HDMI1: aud */ + <0x02 0x2b5>, /* HDPHY0+1: ref */ + <0x02 0x267>, /* HDPHY0: apb */ + <0x02 0x268>; /* HDPHY1: apb */ + clock-names = "clk_npu", "aclk0", "aclk1", "aclk2", + "hclk0", "hclk1", "hclk2", "pclk", + "clk_gpu", "clk_gpu_coregroup", + "clk_gpu_stacks", "clk_mali", + "aclk_vop", "hclk_vop", + "dclk_vp0", "dclk_vp1", + "dclk_vp2", "dclk_vp3", + "pclk_vop", "dclk_src_vp0", + "dclk_src_vp1", "dclk_src_vp2", + "aclk_dovi", "aclk_vop_div2", + "aclk_vop_root", + "hdmi0_pclk", "hdmi0_hpd", + "hdmi0_earc", "hdmi0_hdmitx_ref", + "hdmi0_aud", + "hdmi1_pclk", "hdmi1_hpd", + "hdmi1_earc", "hdmi1_hdmitx_ref", + "hdmi1_aud", + "hdphy_ref", "hdphy0_apb", + "hdphy1_apb"; + resets = <0x02 0x1e6>, <0x02 0x1b0>, <0x02 0x1c0>, + <0x02 0x1e8>, <0x02 0x1b2>, <0x02 0x1c2>, + <0x02 0x349>, /* VOP: axi */ + <0x02 0x348>, /* VOP: ahb */ + <0x02 0x34d>, /* VOP: dclk_vp0 */ + <0x02 0x350>, /* VOP: dclk_vp1 */ + <0x02 0x351>, /* VOP: dclk_vp2 */ + <0x02 0x352>, /* VOP: dclk_vp3 */ + <0x02 0x3d0>, /* HDMI0: ref */ + <0x02 0x49c>, /* HDMI0: hdp */ + <0x02 0x3d7>, /* HDMI1: ref */ + <0x02 0x49d>, /* HDMI1: hdp */ + <0x02 0x48e>, <0x02 0x485>, <0x02 0xc003b>, + <0x02 0xc003c>, <0x02 0xc003d>, <0x02 0x48c>, + <0x02 0x48d>, + <0x02 0x491>, <0x02 0x486>, <0x02 0xc003f>, + <0x02 0xc0040>, <0x02 0xc0041>, <0x02 0x48f>, + <0x02 0x490>; + reset-names = "srst_a0", "srst_a1", "srst_a2", + "srst_h0", "srst_h1", "srst_h2", + "vop_axi", "vop_ahb", "vop_dclk0", + "vop_dclk1", "vop_dclk2", "vop_dclk3", + "hdmi0_ref", "hdmi0_hdp", + "hdmi1_ref", "hdmi1_hdp", + "hdmiphy0_phy", "hdmiphy0_apb", + "hdmiphy0_init", "hdmiphy0_cmn", + "hdmiphy0_lane", "hdmiphy0_ropll", + "hdmiphy0_lcpll", + "hdmiphy1_phy", "hdmiphy1_apb", + "hdmiphy1_init", "hdmiphy1_cmn", + "hdmiphy1_lane", "hdmiphy1_ropll", + "hdmiphy1_lcpll"; + }; + + // reserve memory for hvisor and GuestOS + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + + hvisor@500000 { + no-map; + reg = <0x00 0x00500000 0x00 0x04600000>; + }; + + linux-bootmisc@30000000 { + no-map; + reg = <0x00 0x30000000 0x00 0x10000000>; + // [0x3000_0000, 0x3040_0000), 4 MiB, device-tree-blob + // [0x3040_0000, 0x3340_0000), 48 MiB, kernel + // [0x3340_0000, 0x5000_0000), 204 MiB, free + }; + + linux-memory@100000000 { + no-map; + reg = <0x01 0x00000000 0x01 0xfc000000>; + }; + + zone2-gpu-memory@58000000 { + no-map; + reg = <0x00 0x58000000 0x00 0x80000000>; + }; + }; +}; + +&{/gpu@fb000000} { + status = "disabled"; +}; + +&{/vop@fdd90000} { + status = "disabled"; +}; + +&{/iommu@fdd97e00} { + status = "disabled"; +}; + +&{/syscon@fd5a4000} { + status = "disabled"; +}; + +&{/dmc} { + status = "disabled"; +}; diff --git a/platform/aarch64/sysoul_x3300-scmi/image/dts/zone1-linux-npu.dts b/platform/aarch64/sysoul_x3300-scmi/image/dts/zone1-linux-npu.dts new file mode 100644 index 000000000..72781af39 --- /dev/null +++ b/platform/aarch64/sysoul_x3300-scmi/image/dts/zone1-linux-npu.dts @@ -0,0 +1,366 @@ +/dts-v1/; + +/ { + compatible = "rockchip,xiuos_rk3588\0rockchip,rk3588"; + interrupt-parent = <0x01>; + #address-cells = <0x02>; + #size-cells = <0x02>; + model = "Rockchip RK3588 XIUOS Board (Zone1-Linux with NPU + VirtIO-SCMI)"; + + memory { + reg = <0x00 0x30000000 0x00 0x10000000>, + <0x01 0x00000000 0x01 0xfc000000>; + device_type = "memory"; + }; + + reserved-memory { + #address-cells = <0x02>; + #size-cells = <0x02>; + ranges; + + npu_reserved: npu-memory@38000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x38000000 0x00 0x04000000>; + }; + }; + + cpus { + #address-cells = <0x1>; + #size-cells = <0x0>; + + cpu-map { + cluster0 { + core0 { + cpu = <0x06>; + }; + + core1 { + cpu = <0x07>; + }; + }; + }; + + cpu@600 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x600>; + enable-method = "psci"; + capacity-dmips-mhz = <0x400>; + cpu-idle-states = <0x10>; + i-cache-size = <0x10000>; + i-cache-line-size = <0x40>; + i-cache-sets = <0x100>; + d-cache-size = <0x10000>; + d-cache-line-size = <0x40>; + d-cache-sets = <0x100>; + next-level-cache = <0x1b>; + phandle = <0x06>; + }; + + cpu@700 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x700>; + enable-method = "psci"; + capacity-dmips-mhz = <0x400>; + cpu-idle-states = <0x10>; + i-cache-size = <0x10000>; + i-cache-line-size = <0x40>; + i-cache-sets = <0x100>; + d-cache-size = <0x10000>; + d-cache-line-size = <0x40>; + d-cache-sets = <0x100>; + next-level-cache = <0x1d>; + phandle = <0x07>; + }; + + idle-states { + entry-method = "psci"; + + cpu-sleep { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x10000>; + entry-latency-us = <0x64>; + exit-latency-us = <0x78>; + min-residency-us = <0x3e8>; + phandle = <0x10>; + }; + }; + + l2-cache-l0 { + compatible = "cache"; + cache-size = <0x20000>; + cache-line-size = <0x40>; + cache-sets = <0x200>; + next-level-cache = <0x1e>; + phandle = <0x11>; + }; + + l2-cache-l1 { + compatible = "cache"; + cache-size = <0x20000>; + cache-line-size = <0x40>; + cache-sets = <0x200>; + next-level-cache = <0x1e>; + phandle = <0x13>; + }; + + l2-cache-b0 { + compatible = "cache"; + cache-size = <0x80000>; + cache-line-size = <0x40>; + cache-sets = <0x400>; + next-level-cache = <0x1e>; + phandle = <0x17>; + }; + + l2-cache-b1 { + compatible = "cache"; + cache-size = <0x80000>; + cache-line-size = <0x40>; + cache-sets = <0x400>; + next-level-cache = <0x1e>; + phandle = <0x19>; + }; + + l2-cache-b2 { + compatible = "cache"; + cache-size = <0x80000>; + cache-line-size = <0x40>; + cache-sets = <0x400>; + next-level-cache = <0x1e>; + phandle = <0x1b>; + }; + + l2-cache-b3 { + compatible = "cache"; + cache-size = <0x80000>; + cache-line-size = <0x40>; + cache-sets = <0x400>; + next-level-cache = <0x1e>; + phandle = <0x1d>; + }; + + l3-cache { + compatible = "cache"; + cache-size = <0x300000>; + cache-line-size = <0x40>; + cache-sets = <0x1000>; + phandle = <0x1e>; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + arm-pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <0x01 0x07 0x08>; + interrupt-affinity = <0x06 0x07>; + phandle = <0x220>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <0x01 0x0d 0xf04 0x01 0x0e 0xf04 0x01 0x0b 0xf04 0x01 0x0a 0xf04>; + }; + + interrupt-controller@fe600000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <0x03>; + #address-cells = <0x02>; + #size-cells = <0x02>; + ranges; + interrupt-controller; + reg = <0x00 0xfe600000 0x00 0x10000 0x00 0xfe680000 0x00 0x100000>; + interrupts = <0x01 0x09 0x04>; + phandle = <0x01>; + }; + + aliases { + }; + + // ========== VirtIO-SCMI (Clock, Reset & Power via VirtIO) ========== + firmware { + scmi { + compatible = "arm,scmi-virtio"; + #address-cells = <0x01>; + #size-cells = <0x00>; + phandle = <0x1000>; + + scmi_clk: protocol@14 { // clock protocol + reg = <0x14>; + #clock-cells = <0x01>; + }; + + scmi_rst: protocol@16 { // reset protocol + reg = <0x16>; + #reset-cells = <0x01>; + }; + + scmi_pwr: protocol@11 { // power domain protocol + reg = <0x11>; + #power-domain-cells = <0x01>; + }; + }; + }; + + // virtio-mmio for SCMI + virtio_mmio@ff9c0000 { + dma-coherent; + interrupt-parent = <0x01>; + interrupts = <0x0 0x24 0x1>; + reg = <0x0 0xff9c0000 0x0 0x200>; + compatible = "virtio,mmio"; + }; + + // virtio-mmio for blk + virtio_mmio@ff9d0000 { + dma-coherent; + interrupt-parent = <0x01>; + interrupts = <0x0 0x21 0x1>; + reg = <0x0 0xff9d0000 0x0 0x200>; + compatible = "virtio,mmio"; + }; + + // virtio-mmio for serial/console + virtio_mmio@ff9e0000 { + dma-coherent; + interrupt-parent = <0x01>; + interrupts = <0x0 0x22 0x1>; + reg = <0x0 0xff9e0000 0x0 0x200>; + compatible = "virtio,mmio"; + }; + + // virtio-mmio for net + virtio_mmio@ffa00000 { + dma-coherent; + interrupt-parent = <0x01>; + interrupts = <0x0 0x25 0x1>; + reg = <0x0 0xffa00000 0x0 0x200>; + compatible = "virtio,mmio"; + }; + + // ========== NPU OPP Table ========== + + npu-opp-table { + compatible = "operating-points-v2"; + phandle = <0x70>; + + opp-300000000 { + opp-hz = <0x00 0x11e1a300>; + opp-microvolt = <0xa4cb8>; + }; + + opp-500000000 { + opp-hz = <0x00 0x1dcd6500>; + opp-microvolt = <0xa4cb8>; + }; + + opp-700000000 { + opp-hz = <0x00 0x29b92700>; + opp-microvolt = <0xaae60>; + }; + + opp-900000000 { + opp-hz = <0x00 0x35a4e900>; + opp-microvolt = <0xc3500>; + }; + }; + + // ========== GPU OPP Table ========== + + + // ========== GPU ========== + + + // ========== Display Dependencies (GRF) ========== + + pmu0_grf: syscon@fd588000 { + compatible = "rockchip,rk3588-pmu0-grf", "syscon", "simple-mfd"; + reg = <0x00 0xfd588000 0x00 0x1000>; + }; + + /* sys_grf (0xfd58c000) intentionally NOT exposed to this zone: + * system-wide GRF; zone1 has no consumer for it, and probing it as a + * syscon would generate unmapped MMIO accesses (hvisor shuts the zone + * down on unhandled MMIO faults). */ + + + + + + // ========== HDMIPHYs ========== + + + + // ========== VOP + VOP MMU ========== + + + + // ========== HDMI Fixed Clocks ========== + + hclk_vo1_fixed: hclk-vo1-fixed { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <400000000>; + }; + + // ========== HDMI0 ========== + + + // ========== HDMI1 ========== + + + + // ========== NPU (no IOMMU mode) ========== + + rknpu: npu@fdab0000 { + compatible = "rockchip,rk3588-rknpu"; + reg = <0x00 0xfdab0000 0x00 0x10000>, + <0x00 0xfdac0000 0x00 0x10000>, + <0x00 0xfdad0000 0x00 0x10000>; + interrupts = <0x00 0x6e 0x04>, + <0x00 0x6f 0x04>, + <0x00 0x70 0x04>; + interrupt-names = "npu0_irq", "npu1_irq", "npu2_irq"; + // All clocks via SCMI (virtual IDs 0-7, mapped by hvisor DT order) + clocks = <&scmi_clk 0>, + <&scmi_clk 1>, + <&scmi_clk 2>, + <&scmi_clk 3>, + <&scmi_clk 4>, + <&scmi_clk 5>, + <&scmi_clk 6>, + <&scmi_clk 7>; + clock-names = "clk_npu", "aclk0", "aclk1", "aclk2", + "hclk0", "hclk1", "hclk2", "pclk"; + // All resets via SCMI (virtual IDs 0-5) + resets = <&scmi_rst 0>, + <&scmi_rst 1>, + <&scmi_rst 2>, + <&scmi_rst 3>, + <&scmi_rst 4>, + <&scmi_rst 5>; + reset-names = "srst_a0", "srst_a1", "srst_a2", + "srst_h0", "srst_h1", "srst_h2"; + // Power domains via SCMI (virtual IDs 0-2) + power-domains = <&scmi_pwr 0>, + <&scmi_pwr 1>, + <&scmi_pwr 2>; + power-domain-names = "npu0", "npu1", "npu2"; + // Operating points (via SCMI clock) + operating-points-v2 = <0x70>; + // Reserved memory for DMA (non-IOMMU mode) + memory-region = <&npu_reserved>; + status = "okay"; + }; + + chosen { + bootargs = "earlycon=virtio,mmio,0xff9e0000 console=hvc0 root=/dev/vda rootwait rw"; + stdout-path = "/virtio_mmio@0xff9e0000"; + }; +}; diff --git a/platform/aarch64/sysoul_x3300-scmi/image/dts/zone2-linux-gpu-hdmi.dts b/platform/aarch64/sysoul_x3300-scmi/image/dts/zone2-linux-gpu-hdmi.dts new file mode 100644 index 000000000..96a2f56fb --- /dev/null +++ b/platform/aarch64/sysoul_x3300-scmi/image/dts/zone2-linux-gpu-hdmi.dts @@ -0,0 +1,549 @@ +/dts-v1/; + +/ { + compatible = "rockchip,xiuos_rk3588\0rockchip,rk3588"; + interrupt-parent = <0x01>; + #address-cells = <0x02>; + #size-cells = <0x02>; + model = "Rockchip RK3588 XIUOS Board (Zone2-Linux with GPU + VirtIO-SCMI)"; + + memory { + reg = <0x00 0x58000000 0x00 0x80000000>; + device_type = "memory"; + }; + + cpus { + #address-cells = <0x1>; + #size-cells = <0x0>; + + cpu-map { + cluster0 { + core0 { + cpu = <0x04>; + }; + core1 { + cpu = <0x05>; + }; + }; + }; + + cpu@400 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x400>; + enable-method = "psci"; + capacity-dmips-mhz = <0x400>; + cpu-idle-states = <0x10>; + i-cache-size = <0x10000>; + i-cache-line-size = <0x40>; + i-cache-sets = <0x100>; + d-cache-size = <0x10000>; + d-cache-line-size = <0x40>; + d-cache-sets = <0x100>; + next-level-cache = <0x1b>; + phandle = <0x04>; + }; + + cpu@500 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x500>; + enable-method = "psci"; + capacity-dmips-mhz = <0x400>; + cpu-idle-states = <0x10>; + i-cache-size = <0x10000>; + i-cache-line-size = <0x40>; + i-cache-sets = <0x100>; + d-cache-size = <0x10000>; + d-cache-line-size = <0x40>; + d-cache-sets = <0x100>; + next-level-cache = <0x1d>; + phandle = <0x05>; + }; + + idle-states { + entry-method = "psci"; + + cpu-sleep { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x10000>; + entry-latency-us = <0x64>; + exit-latency-us = <0x78>; + min-residency-us = <0x3e8>; + phandle = <0x10>; + }; + }; + + l2-cache-b0 { + compatible = "cache"; + cache-size = <0x80000>; + cache-line-size = <0x40>; + cache-sets = <0x400>; + next-level-cache = <0x1e>; + phandle = <0x1b>; + }; + + l2-cache-b1 { + compatible = "cache"; + cache-size = <0x80000>; + cache-line-size = <0x40>; + cache-sets = <0x400>; + next-level-cache = <0x1e>; + phandle = <0x1d>; + }; + + l3-cache { + compatible = "cache"; + cache-size = <0x300000>; + cache-line-size = <0x40>; + cache-sets = <0x1000>; + phandle = <0x1e>; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + arm-pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <0x01 0x07 0x08>; + interrupt-affinity = <0x04 0x05>; + phandle = <0x220>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <0x01 0x0d 0xf04 0x01 0x0e 0xf04 0x01 0x0b 0xf04 0x01 0x0a 0xf04>; + }; + + interrupt-controller@fe600000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <0x03>; + #address-cells = <0x02>; + #size-cells = <0x02>; + ranges; + interrupt-controller; + reg = <0x00 0xfe600000 0x00 0x10000 0x00 0xfe680000 0x00 0x100000>; + interrupts = <0x01 0x09 0x04>; + phandle = <0x01>; + }; + + aliases { + }; + + // ========== VirtIO-SCMI ========== + firmware { + scmi { + compatible = "arm,scmi-virtio"; + #address-cells = <0x01>; + #size-cells = <0x00>; + phandle = <0x1000>; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <0x01>; + }; + + scmi_rst: protocol@16 { + reg = <0x16>; + #reset-cells = <0x01>; + }; + + scmi_pwr: protocol@11 { + reg = <0x11>; + #power-domain-cells = <0x01>; + }; + }; + }; + + // virtio-mmio for SCMI (zone2 IPA, mapped by hvisor) + virtio_mmio@ffa10000 { + dma-coherent; + interrupt-parent = <0x01>; + interrupts = <0x0 0x46 0x1>; + reg = <0x0 0xffa10000 0x0 0x200>; + compatible = "virtio,mmio"; + }; + + // virtio-mmio for blk + virtio_mmio@ffa20000 { + dma-coherent; + interrupt-parent = <0x01>; + interrupts = <0x0 0x47 0x1>; + reg = <0x0 0xffa20000 0x0 0x200>; + compatible = "virtio,mmio"; + }; + + // virtio-mmio for serial/console + virtio_mmio@ffa30000 { + dma-coherent; + interrupt-parent = <0x01>; + interrupts = <0x0 0x48 0x1>; + reg = <0x0 0xffa30000 0x0 0x200>; + compatible = "virtio,mmio"; + }; + + // virtio-mmio for net + virtio_mmio@ffa50000 { + dma-coherent; + interrupt-parent = <0x01>; + interrupts = <0x0 0x49 0x1>; + reg = <0x0 0xffa50000 0x0 0x200>; + compatible = "virtio,mmio"; + }; + + + // ========== VOP/HDMI Dependencies ========== + // + // IMPORTANT: SYS_GRF (0xfd58c000) and PMU_GRF (0xfd588000) are + // intentionally NOT exposed to this zone. They are system-wide GRFs: + // GPIO0/GPIO1 IOMUX lives in PMU_GRF, and zone0's SPI2 (PMIC rk806) + // uses GPIO0 pins — passing these GRFs through let a guest driver + // clobber the SPI2 pinmux, breaking PMIC communication. + // + // VOP/HDMI drivers access "rockchip,grf" / "rockchip,pmu" / + // "rockchip,ioc-grf" regmaps unconditionally (vop2_grf_readl has no + // NULL guard), so instead of removing the properties we point them at + // VO1_GRF (0xfd5a8000), which IS passed through. VO1_GRF is + // display-only: its valid registers live at low offsets (0x0004-0x0024) + // while the drivers' sys-grf offsets (0x0304/0x0308/0x0384) land in + // undefined space inside the VO1_GRF block — reads return 0, writes + // are dropped by the hardware. GRF blocks are decoded at block + // granularity, so these accesses cannot hang the bus. + + vop_grf: syscon@fd5a4000 { + compatible = "rockchip,rk3588-vop-grf", "syscon"; + reg = <0x00 0xfd5a4000 0x00 0x2000>; + }; + + vo1_grf: syscon@fd5a8000 { + compatible = "rockchip,rk3588-vo-grf", "syscon"; + reg = <0x00 0xfd5a8000 0x00 0x1000>; + }; + + hdptx_grf: syscon@fd5e0000 { + compatible = "rockchip,rk3588-hdptxphy-grf", "syscon"; + reg = <0x00 0xfd5e0000 0x00 0x1000>; + }; + + ioc: syscon@fd5f0000 { + compatible = "rockchip,rk3588-ioc", "syscon"; + reg = <0x00 0xfd5f0000 0x00 0x10000>; + }; + + sys_grf: syscon@fd58c000 { + compatible = "rockchip,rk3588-sys-grf", "syscon"; + reg = <0x00 0xfd58c000 0x00 0x1000>; + }; + + pinctrl: pinctrl { + compatible = "rockchip,rk3588-pinctrl"; + rockchip,grf = <&ioc>; + #address-cells = <0x02>; + #size-cells = <0x02>; + ranges; + + hdmi { + hdmim0_tx0_cec: hdmim0-tx0-cec { + rockchip,pins = <4 17 5 &pcfg_pull_none>; + }; + hdmim0_tx0_hpd: hdmim0-tx0-hpd { + rockchip,pins = <1 5 5 &pcfg_pull_none>; + }; + hdmim0_tx0_scl: hdmim0-tx0-scl { + rockchip,pins = <4 15 5 &pcfg_pull_none_drv_level_5_smt>; + }; + hdmim0_tx0_sda: hdmim0-tx0-sda { + rockchip,pins = <4 16 5 &pcfg_pull_none_drv_level_1_smt>; + }; + }; + + pcfg_pull_none: pcfg-pull-none { + bias-disable; + }; + pcfg_pull_none_drv_level_5_smt: pcfg-pull-none-drv-level-5-smt { + bias-disable; + drive-strength = <5>; + input-schmitt-enable; + }; + pcfg_pull_none_drv_level_1_smt: pcfg-pull-none-drv-level-1-smt { + bias-disable; + drive-strength = <1>; + input-schmitt-enable; + }; + }; + + /* + * VOP IOMMU (rk_iommu, passthrough). Without it the VOP has no + * scatter-gather support: rockchip_gem_prime_import_sg_table then + * requires physically contiguous buffers, which the Mali GPU (own + * MMU) does not provide -> gbm front buffer import fails. With the + * IOMMU the DRM core uses the iommu map path instead. + */ + vop_mmu: iommu@fdd97e00 { + compatible = "rockchip,iommu-v2"; + reg = <0x00 0xfdd97e00 0x00 0x100>, + <0x00 0xfdd97f00 0x00 0x100>; + interrupts = <0x00 0x9c 0x04>; + interrupt-names = "vop_mmu"; + clocks = <&scmi_clk 4>, <&scmi_clk 5>; + clock-names = "aclk", "iface"; + #iommu-cells = <0x00>; + rockchip,disable-device-link-resume; + rockchip,shootdown-entire; + status = "okay"; + }; + + display_subsystem: display-subsystem { + compatible = "rockchip,display-subsystem"; + ports = <&vop_out>; + /* + * hdmi0_phy_pll = clk_hdmiphy_pixel0, the HDPTX PLL output + * clock registered LOCALLY by this zone's phy driver + * (fed60000 is passed through). NOT an SCMI virtual clock: + * the PLL registers live in this zone. vop2_extend_clk_init + * looks it up on the DRM master device (this node) by name, + * which lets mode_valid accept HDMI modes without the v0pll + * parent check. fw_devlink (clocks phandle) makes sure the + * phy probes before this master. + */ + clocks = <&hdmiphy0>; + clock-names = "hdmi0_phy_pll"; + status = "okay"; + }; + + vop@fdd90000 { + compatible = "rockchip,rk3588-vop"; + reg = <0x00 0xfdd90000 0x00 0x4200>, + <0x00 0xfdd95000 0x00 0x1000>; + reg-names = "regs", "gamma_lut"; + interrupts = <0x00 0x9c 0x04>; + clocks = <&scmi_clk 4>, <&scmi_clk 5>, + <&scmi_clk 6>, <&scmi_clk 7>, + <&scmi_clk 8>, <&scmi_clk 9>, + <&scmi_clk 10>, <&scmi_clk 11>, + <&scmi_clk 12>, <&scmi_clk 13>, + <&scmi_clk 14>, <&scmi_clk 15>, + <&scmi_clk 16>; + clock-names = "aclk_vop", "hclk_vop", + "dclk_vp0", "dclk_vp1", + "dclk_vp2", "dclk_vp3", + "pclk_vop", "dclk_src_vp0", + "dclk_src_vp1", "dclk_src_vp2", + "aclk_dovi", "aclk_vop_div2_src", + "aclk_vop_root"; + resets = <&scmi_rst 0>, <&scmi_rst 1>, + <&scmi_rst 2>, <&scmi_rst 3>, + <&scmi_rst 4>, <&scmi_rst 5>; + reset-names = "axi", "ahb", "dclk_vp0", + "dclk_vp1", "dclk_vp2", "dclk_vp3"; + power-domains = <&scmi_pwr 1>; + iommus = <&vop_mmu>; + /* sys_grf/pmu/ioc redirected to vo1_grf — see note above */ + rockchip,grf = <&vo1_grf>; + rockchip,vop-grf = <&vop_grf>; + rockchip,vo1-grf = <&vo1_grf>; + rockchip,pmu = <&vo1_grf>; + rockchip,ioc-grf = <&vo1_grf>; + status = "okay"; + + vop_out: ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + /* + * Plane assignment strategy (rk3588 win phys ids: + * Cluster0=0 Cluster1=1 Esmart0=2 Esmart1=3 + * Cluster2=6 Cluster3=7 Esmart2=8 Esmart3=9). + * + * ALL windows are assigned to VP0 (0x3cf) - the only + * VP that has a connector and ever gets driven. + * VP1/VP2/VP3 are left with mask 0 and are never + * registered as CRTCs. + * + * The vop2 driver requires every window to be + * assigned to exactly one VP (the plane masks must + * sum to 0x3cf), otherwise it discards the DTS + * assignment and uses its default (VP0 = 0x145, + * which adds Cluster0/2 + Esmart2 to VP0). + * + * Why everything on VP0: u-boot leaves the VOP + * hardware in a dirty state - it drives the HDMI + * logo on VP0 and enables arbitrary windows (seen: + * Esmart1/Esmart3 with a stale DMA address + * 0xedeb8000). Those stale windows are only + * disabled by vop2_disable_all_planes_for_crtc(), + * which iterates vp->win_mask (= plane mask) and is + * only invoked when the new mode differs from the + * current hardware mode (vop2_crtc_mode_update). + * If a stale window is NOT in VP0's mask it can + * never be disabled: it keeps scanning the stale + * address through the IOMMU, faults, and shows a + * green screen. Putting every window on VP0 makes + * any mode switch clean all of them. + */ + vp0: port@0 { + reg = <0x00>; + #address-cells = <0x01>; + #size-cells = <0x00>; + rockchip,plane-mask = <0x3cf>; /* all 12 windows */ + rockchip,primary-plane = <0x02>; /* Esmart0 */ + + vp0_out_hdmi0: endpoint@0 { + reg = <0x00>; + remote-endpoint = <&hdmi0_in>; + }; + }; + vp1: port@1 { + reg = <0x01>; + #address-cells = <0x01>; + #size-cells = <0x00>; + rockchip,plane-mask = <0x00>; + }; + vp2: port@2 { + reg = <0x02>; + #address-cells = <0x01>; + #size-cells = <0x00>; + rockchip,plane-mask = <0x00>; + }; + }; + }; + + hdmiphy0: hdmiphy@fed60000 { + compatible = "rockchip,rk3588-hdptx-phy-hdmi"; + reg = <0x00 0xfed60000 0x00 0x2000>; + clocks = <&scmi_clk 22>, <&scmi_clk 23>; + clock-names = "ref", "apb"; + clock-output-names = "clk_hdmiphy_pixel0"; + #clock-cells = <0x00>; + resets = <&scmi_rst 8>, <&scmi_rst 9>, <&scmi_rst 10>, + <&scmi_rst 11>, <&scmi_rst 12>, <&scmi_rst 13>, + <&scmi_rst 14>; + reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", + "lcpll"; + rockchip,grf = <&hdptx_grf>; + #phy-cells = <0x00>; + status = "okay"; + }; + + hdmi@fde80000 { + compatible = "rockchip,rk3588-dw-hdmi"; + reg = <0x00 0xfde80000 0x00 0x10000>, + <0x00 0xfde90000 0x00 0x10000>; + interrupts = <0x00 0xa9 0x04>, <0x00 0xaa 0x04>, + <0x00 0xab 0x04>, <0x00 0xac 0x04>, + <0x00 0x168 0x04>; + clocks = <&scmi_clk 17>, <&scmi_clk 18>, + <&scmi_clk 19>, <&scmi_clk 20>, + <&scmi_clk 21>, <&scmi_clk 7>, + <&scmi_clk 8>, <&scmi_clk 9>, + <&scmi_clk 10>, <&hdmiphy0>; + clock-names = "pclk", "hpd", "earc", + "hdmitx_ref", "aud", + "dclk_vp0", "dclk_vp1", + "dclk_vp2", "dclk_vp3", + "link_clk"; + resets = <&scmi_rst 6>, <&scmi_rst 7>; + reset-names = "ref", "hdp"; + power-domains = <&scmi_pwr 2>; + reg-io-width = <0x04>; + rockchip,grf = <&sys_grf>; + rockchip,vo1_grf = <&vo1_grf>; + phys = <&hdmiphy0>; + phy-names = "hdmi"; + #sound-dai-cells = <0x00>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd &hdmim0_tx0_scl &hdmim0_tx0_sda>; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + port@0 { + reg = <0x00>; + #address-cells = <0x01>; + #size-cells = <0x00>; + + hdmi0_in: endpoint@0 { + reg = <0x00>; + remote-endpoint = <&vp0_out_hdmi0>; + }; + }; + }; + }; + + // ========== GPU Dependencies ========== + + syscon@fd5a0000 { + compatible = "rockchip,rk3588-gpu-grf\0syscon"; + reg = <0x00 0xfd5a0000 0x00 0x100>; + phandle = <0x66>; + }; + + pvtm@fdb30000 { + compatible = "rockchip,rk3588-gpu-pvtm"; + reg = <0x00 0xfdb30000 0x00 0x100>; + #address-cells = <0x01>; + #size-cells = <0x00>; + }; + + // ========== GPU OPP Table ========== + + gpu-opp-table { + compatible = "operating-points-v2"; + phandle = <0x71>; + + opp-300000000 { + opp-hz = <0x00 0x11e1a300>; + opp-microvolt = <0xa4cb8>; + }; + opp-500000000 { + opp-hz = <0x00 0x1dcd6500>; + opp-microvolt = <0xa4cb8>; + }; + opp-800000000 { + opp-hz = <0x00 0x2faf0800>; + opp-microvolt = <0xb71b0>; + }; + opp-1000000000 { + opp-hz = <0x00 0x3b9aca00>; + opp-microvolt = <0xcf850>; + }; + }; + + // ========== GPU ========== + + gpu@fb000000 { + compatible = "arm,mali-valhall"; + reg = <0x00 0xfb000000 0x00 0x200000>; + interrupts = <0x00 0x5e 0x04>, + <0x00 0x5d 0x04>, + <0x00 0x5c 0x04>; + interrupt-names = "GPU", "MMU", "JOB"; + /* + * SCMI virtual IDs 0-3 mapped via clock_ids [8,9,10,11]: + * 0 → hvisor clock[8] = clk_gpu + * 1 → hvisor clock[9] = clk_gpu_coregroup + * 2 → hvisor clock[10] = clk_gpu_stacks + * 3 → hvisor clock[11] = clk_mali + */ + clocks = <&scmi_clk 0>, <&scmi_clk 1>, + <&scmi_clk 2>, <&scmi_clk 3>; + clock-names = "clk_mali", "clk_gpu_coregroup", + "clk_gpu_stacks", "clk_gpu"; + operating-points-v2 = <0x71>; + /* + * SCMI virtual ID 0 → power_ids[0] = 3 → hvisor power[3] = 0x0c + */ + power-domains = <&scmi_pwr 0>; + status = "okay"; + }; + + chosen { + bootargs = "earlycon=virtio,mmio,0xffa30000 console=hvc0 root=/dev/vda rootwait rw"; + stdout-path = "/virtio_mmio@0xffa30000"; + }; +}; diff --git a/platform/aarch64/sysoul_x3300-scmi/kconfig/defconfig b/platform/aarch64/sysoul_x3300-scmi/kconfig/defconfig new file mode 100644 index 000000000..242faa328 --- /dev/null +++ b/platform/aarch64/sysoul_x3300-scmi/kconfig/defconfig @@ -0,0 +1,3 @@ +CONFIG_ARCH_AARCH64=y +CONFIG_IRQ_GICV3=y +CONFIG_UART_16550=y diff --git a/platform/aarch64/sysoul_x3300-scmi/linker.ld b/platform/aarch64/sysoul_x3300-scmi/linker.ld new file mode 100644 index 000000000..b287362b6 --- /dev/null +++ b/platform/aarch64/sysoul_x3300-scmi/linker.ld @@ -0,0 +1,68 @@ +ENTRY(arch_entry) +BASE_ADDRESS = 0x500000; +CPU_NUM = 8; + +SECTIONS +{ + . = BASE_ADDRESS; + skernel = .; + + .boot : { + *(.text.boot) + *(.data.boot) + } + + stext = .; + .text : { + *(.text.entry) + *(.text .text.*) + } + + . = ALIGN(4K); + etext = .; + srodata = .; + .rodata : { + *(.rodata .rodata.*) + *(.srodata .srodata.*) + } + + . = ALIGN(4K); + erodata = .; + sdata = .; + .data : { + *(.data .data.*) + *(.sdata .sdata.*) + } + + . = ALIGN(4K); + edata = .; + .bss : { + *(.bss.stack) + sbss = .; + *(.bss .bss.*) + *(.sbss .sbss.*) + } + + . = ALIGN(4K); + _percpu_start = .; + _percpu_end = _percpu_start + SIZEOF(.percpu); + .percpu 0x0 (NOLOAD) : AT(_percpu_start) { + _percpu_load_start = .; + *(.percpu .percpu.*) + _percpu_load_end = .; + . = _percpu_load_start + ALIGN(64) * CPU_NUM; + } + . = _percpu_end; + + . = ALIGN(4K); + ebss = .; + ekernel = .; + + /DISCARD/ : { + *(.eh_frame) + } + . = ALIGN(4K); + __core_end = .; +} + +__hv_end = __core_end + HV_EXTENDED_SIZE; diff --git a/platform/aarch64/sysoul_x3300-scmi/platform.mk b/platform/aarch64/sysoul_x3300-scmi/platform.mk new file mode 100644 index 000000000..e68880956 --- /dev/null +++ b/platform/aarch64/sysoul_x3300-scmi/platform.mk @@ -0,0 +1,8 @@ +$(hvisor_bin): elf + @if ! command -v mkimage > /dev/null; then \ + sudo apt update && sudo apt install u-boot-tools; \ + fi && \ + $(OBJCOPY) $(hvisor_elf) --strip-all -O binary $(hvisor_bin).tmp && \ + mkimage -n hvisor_img -A arm64 -O linux -C none -T kernel -a 0x00500000 \ + -e 0x00500000 -d $(hvisor_bin).tmp $(hvisor_bin) && \ + rm -rf $(hvisor_bin).tmp \ No newline at end of file diff --git a/platform/aarch64/sysoul_x3300/board.rs b/platform/aarch64/sysoul_x3300/board.rs index 0e396f88c..47cc1c959 100644 --- a/platform/aarch64/sysoul_x3300/board.rs +++ b/platform/aarch64/sysoul_x3300/board.rs @@ -18,7 +18,7 @@ use crate::pci_dev; use crate::{ arch::{ mmu::MemoryType, - zone::{GicConfig, Gicv3Config, HvArchZoneConfig}, + zone::{GicConfig, Gicv3Config, HvArchZoneConfig, UefiConfig}, }, config::*, pci::vpci_dev::VpciDevType, @@ -41,6 +41,9 @@ pub static BOARD_MPIDR_MAPPINGS: [u64; BOARD_NCPUS] = [ 0x700, // cpu7 ]; +/// Early boot cache invalidate mask (per CPU): bit0->L1(D), bit1->L2, bit2->L3. +pub static BOARD_EARLY_CACHE_INVALIDATE_MASKS: [u64; BOARD_NCPUS] = [0b111; BOARD_NCPUS]; + /// The physical memory layout of the board. /// Each address should align to 2M (0x20_0000). /// Addresses must be in ascending order. @@ -211,6 +214,7 @@ pub const ROOT_ARCH_ZONE_CONFIG: HvArchZoneConfig = HvArchZoneConfig { gits_base: 0x0, gits_size: 0x0, }), + uefi_config: UefiConfig::NoUefi }; pub const ROOT_ZONE_IVC_CONFIG: [HvIvcConfig; 0] = []; diff --git a/platform/aarch64/sysoul_x3300/cargo/features b/platform/aarch64/sysoul_x3300/cargo/features deleted file mode 100644 index afa594897..000000000 --- a/platform/aarch64/sysoul_x3300/cargo/features +++ /dev/null @@ -1,2 +0,0 @@ -gicv3 -uart_16550 diff --git a/platform/aarch64/sysoul_x3300/configs/zone1-android.json b/platform/aarch64/sysoul_x3300/configs/zone1-android.json index 5865f62fa..c4a9fa3a3 100644 --- a/platform/aarch64/sysoul_x3300/configs/zone1-android.json +++ b/platform/aarch64/sysoul_x3300/configs/zone1-android.json @@ -314,5 +314,6 @@ "gicr_size": "0x100000", "gits_base": "0x0", "gits_size": "0x0" - } -} \ No newline at end of file + }, + "pci_config": [] +} diff --git a/platform/aarch64/sysoul_x3300/kconfig/defconfig b/platform/aarch64/sysoul_x3300/kconfig/defconfig new file mode 100644 index 000000000..242faa328 --- /dev/null +++ b/platform/aarch64/sysoul_x3300/kconfig/defconfig @@ -0,0 +1,3 @@ +CONFIG_ARCH_AARCH64=y +CONFIG_IRQ_GICV3=y +CONFIG_UART_16550=y diff --git a/platform/aarch64/zcu102/board.rs b/platform/aarch64/zcu102/board.rs index a26626935..6eb12a41f 100644 --- a/platform/aarch64/zcu102/board.rs +++ b/platform/aarch64/zcu102/board.rs @@ -17,7 +17,7 @@ use crate::config::HvConfigMemoryRegion; use crate::{ arch::{ mmu::MemoryType, - zone::{GicConfig, Gicv2Config, HvArchZoneConfig}, + zone::{GicConfig, Gicv2Config, HvArchZoneConfig, UefiConfig}, }, config::*, }; @@ -35,6 +35,9 @@ pub static BOARD_MPIDR_MAPPINGS: [u64; BOARD_NCPUS] = [ 0x3, // cpu3 ]; +/// Early boot cache invalidate mask (per CPU): bit0->L1(D), bit1->L2, bit2->L3. +pub static BOARD_EARLY_CACHE_INVALIDATE_MASKS: [u64; BOARD_NCPUS] = [0b011; BOARD_NCPUS]; + /// The physical memory layout of the board. /// Each address should align to 2M (0x200000). /// Addresses must be in ascending order. @@ -133,6 +136,7 @@ pub const ROOT_ARCH_ZONE_CONFIG: HvArchZoneConfig = HvArchZoneConfig { gicv_base: 0xf9060000, gicv_size: 0x20000, }), + uefi_config: UefiConfig::NoUefi }; pub const ROOT_ZONE_IVC_CONFIG: [HvIvcConfig; 0] = []; diff --git a/platform/aarch64/zcu102/cargo/features b/platform/aarch64/zcu102/cargo/features deleted file mode 100644 index 4189d1494..000000000 --- a/platform/aarch64/zcu102/cargo/features +++ /dev/null @@ -1,2 +0,0 @@ -gicv2 -xuartps diff --git a/platform/aarch64/zcu102/kconfig/defconfig b/platform/aarch64/zcu102/kconfig/defconfig new file mode 100644 index 000000000..b3563178f --- /dev/null +++ b/platform/aarch64/zcu102/kconfig/defconfig @@ -0,0 +1,3 @@ +CONFIG_ARCH_AARCH64=y +CONFIG_IRQ_GICV2=y +CONFIG_XUARTPS=y diff --git a/platform/loongarch64/ls3a5000/board.rs b/platform/loongarch64/ls3a5000/board.rs index 541d73a87..a69db3726 100644 --- a/platform/loongarch64/ls3a5000/board.rs +++ b/platform/loongarch64/ls3a5000/board.rs @@ -77,8 +77,11 @@ pub const ROOT_ZONE_MEMORY_REGIONS: &[HvConfigMemoryRegion] = &[ mem_type: MEM_TYPE_IO, physical_start: 0x1fe00000, virtual_start: 0x1fe00000, - size: 0x1000, - }, // uart0 + size: 0x3000, + }, // IOCSR MMIO: uart0, IPI, EXTIOI. + // Reference: + // IPI: + // EXTIOI: HvConfigMemoryRegion { mem_type: MEM_TYPE_IO, physical_start: 0x10080000, @@ -151,7 +154,7 @@ pub const ROOT_ZONE_MEMORY_REGIONS: &[HvConfigMemoryRegion] = &[ }, // SHARD_MEM ]; -pub const IRQ_WAKEUP_VIRTIO_DEVICE: usize = 32 + 0x20; +pub const IRQ_WAKEUP_VIRTIO_DEVICE: usize = 4; pub const ROOT_ZONE_IRQS_BITMAP: &[BitmapWord] = &get_irqs_bitmap(&[]); pub const ROOT_ARCH_ZONE_CONFIG: HvArchZoneConfig = HvArchZoneConfig { dummy: 0 }; pub const ROOT_ZONE_IVC_CONFIG: [HvIvcConfig; 0] = []; @@ -183,32 +186,41 @@ pub const ROOT_PCI_CONFIG: [HvPciConfig; 1] = [HvPciConfig { /* BUS 6 on X4 slot */ /* 06:00.0, 06:00.1, 06:00.2, 06:00.3 net */ pub const ROOT_PCI_DEVS: &[HvPciDevConfig] = &[ - pci_dev!(0x0, 0x0, 0x0, 0x0, VpciDevType::Physical), // 00:00.0 - pci_dev!(0x0, 0x0, 0x0, 0x1, VpciDevType::Physical), // 00:00.1 - pci_dev!(0x0, 0x0, 0x0, 0x2, VpciDevType::Physical), // 00:00.2 - pci_dev!(0x0, 0x0, 0x0, 0x3, VpciDevType::Physical), // 00:00.3 - pci_dev!(0x0, 0x0, 0x4, 0x0, VpciDevType::Physical), // 00:04.0 - pci_dev!(0x0, 0x0, 0x4, 0x1, VpciDevType::Physical), // 00:04.1 - pci_dev!(0x0, 0x0, 0x5, 0x0, VpciDevType::Physical), // 00:05.0 - pci_dev!(0x0, 0x0, 0x5, 0x1, VpciDevType::Physical), // 00:05.1 - // pci_dev!(0x0, 0x0, 0x6, 0x0, VpciDevType::Physical), // 00:06.0 - // pci_dev!(0x0, 0x0, 0x6, 0x1, VpciDevType::Physical), // 00:06.1 - // pci_dev!(0x0, 0x0, 0x6, 0x2, VpciDevType::Physical), // 00:06.2 - pci_dev!(0x0, 0x0, 0x7, 0x0, VpciDevType::Physical), // 00:07.0 - pci_dev!(0x0, 0x0, 0x8, 0x0, VpciDevType::Physical), // 00:08.0 - pci_dev!(0x0, 0x0, 0x9, 0x0, VpciDevType::Physical), // 00:09.0 - pci_dev!(0x0, 0x0, 0xa, 0x0, VpciDevType::Physical), // 00:0a.0 - pci_dev!(0x0, 0x0, 0xb, 0x0, VpciDevType::Physical), // 00:0b.0 - pci_dev!(0x0, 0x0, 0xc, 0x0, VpciDevType::Physical), // 00:0c.0 - pci_dev!(0x0, 0x0, 0xd, 0x0, VpciDevType::Physical), // 00:0d.0 - pci_dev!(0x0, 0x0, 0xf, 0x0, VpciDevType::Physical), // 00:0f.0 - pci_dev!(0x0, 0x0, 0x10, 0x0, VpciDevType::Physical), // 00:10.0 - pci_dev!(0x0, 0x0, 0x13, 0x0, VpciDevType::Physical), // 00:13.0 - pci_dev!(0x0, 0x0, 0x16, 0x0, VpciDevType::Physical), // 00:16.0 - pci_dev!(0x0, 0x0, 0x19, 0x0, VpciDevType::Physical), // 00:19.0 - pci_dev!(0x0, 0x2, 0x0, 0x0, VpciDevType::Physical), // 02:00.0 - pci_dev!(0x0, 0x5, 0x0, 0x0, VpciDevType::Physical), // 05:00.0 - pci_dev!(0x0, 0x6, 0x0, 0x0, VpciDevType::Physical), // 06:00.0 + pci_dev!(0x0, 0x0, 0x0, 0x0 => 0x0, 0x0, 0x0, VpciDevType::Physical), // 00:00.0 + pci_dev!(0x0, 0x0, 0x0, 0x1 => 0x0, 0x0, 0x1, VpciDevType::Physical), // 00:00.1 + pci_dev!(0x0, 0x0, 0x0, 0x2 => 0x0, 0x0, 0x2, VpciDevType::Physical), // 00:00.2 + pci_dev!(0x0, 0x0, 0x0, 0x3 => 0x0, 0x0, 0x3, VpciDevType::Physical), // 00:00.3 + pci_dev!(0x0, 0x0, 0x4, 0x0 => 0x0, 0x4, 0x0, VpciDevType::Physical), // 00:04.0 + pci_dev!(0x0, 0x0, 0x4, 0x1 => 0x0, 0x4, 0x1, VpciDevType::Physical), // 00:04.1 + pci_dev!(0x0, 0x0, 0x5, 0x0 => 0x0, 0x5, 0x0, VpciDevType::Physical), // 00:05.0 + pci_dev!(0x0, 0x0, 0x5, 0x1 => 0x0, 0x5, 0x1, VpciDevType::Physical), // 00:05.1 + // pci_dev!(0x0, 0x0, 0x6, 0x0 => 0x0, 0x6, 0x0, VpciDevType::Physical), // 00:06.0 + // pci_dev!(0x0, 0x0, 0x6, 0x1 => 0x0, 0x6, 0x1, VpciDevType::Physical), // 00:06.1 + // pci_dev!(0x0, 0x0, 0x6, 0x2 => 0x0, 0x6, 0x2, VpciDevType::Physical), // 00:06.2 + pci_dev!(0x0, 0x0, 0x7, 0x0 => 0x0, 0x7, 0x0, VpciDevType::Physical), // 00:07.0 + pci_dev!(0x0, 0x0, 0x8, 0x0 => 0x0, 0x8, 0x0, VpciDevType::Physical), // 00:08.0 + pci_dev!(0x0, 0x0, 0x9, 0x0 => 0x0, 0x9, 0x0, VpciDevType::Physical), // 00:09.0 + pci_dev!(0x0, 0x0, 0xa, 0x0 => 0x0, 0xa, 0x0, VpciDevType::Physical), // 00:0a.0 + pci_dev!(0x0, 0x0, 0xb, 0x0 => 0x0, 0xb, 0x0, VpciDevType::Physical), // 00:0b.0 + pci_dev!(0x0, 0x0, 0xc, 0x0 => 0x0, 0xc, 0x0, VpciDevType::Physical), // 00:0c.0 + pci_dev!(0x0, 0x0, 0xd, 0x0 => 0x0, 0xd, 0x0, VpciDevType::Physical), // 00:0d.0 + pci_dev!(0x0, 0x0, 0xf, 0x0 => 0x0, 0xf, 0x0, VpciDevType::Physical), // 00:0f.0 + pci_dev!(0x0, 0x0, 0x10, 0x0 => 0x0, 0x10, 0x0, VpciDevType::Physical), // 00:10.0 + pci_dev!(0x0, 0x0, 0x13, 0x0 => 0x0, 0x13, 0x0, VpciDevType::Physical), // 00:13.0 + pci_dev!(0x0, 0x0, 0x16, 0x0 => 0x0, 0x16, 0x0, VpciDevType::Physical), // 00:16.0 + pci_dev!(0x0, 0x0, 0x19, 0x0 => 0x0, 0x19, 0x0, VpciDevType::Physical), // 00:19.0 + pci_dev!(0x0, 0x2, 0x0, 0x0 => 0x2, 0x0, 0x0, VpciDevType::Physical), // 02:00.0 + pci_dev!(0x0, 0x5, 0x0, 0x0 => 0x5, 0x0, 0x0, VpciDevType::Physical), // 05:00.0 + pci_dev!(0x0, 0x6, 0x0, 0x0 => 0x6, 0x0, 0x0, VpciDevType::Physical), // 06:00.0 + // VFs BELONGS TO 06:00.0 + // pci_dev!(0x0, 0x7, 0x10, 0x0 => 0x7, 0x10, 0x0, VpciDevType::Physical), // 07:10.0 + // pci_dev!(0x0, 0x7, 0x10, 0x4 => 0x7, 0x10, 0x4, VpciDevType::Physical), // 07:10.4 + // pci_dev!(0x0, 0x7, 0x11, 0x0 => 0x7, 0x11, 0x0, VpciDevType::Physical), // 07:11.0 + // pci_dev!(0x0, 0x7, 0x11, 0x4 => 0x7, 0x11, 0x4, VpciDevType::Physical), // 07:11.4 + // pci_dev!(0x0, 0x7, 0x12, 0x0 => 0x7, 0x12, 0x0, VpciDevType::Physical), // 07:12.0 + // pci_dev!(0x0, 0x7, 0x12, 0x4 => 0x7, 0x12, 0x4, VpciDevType::Physical), // 07:12.4 + // pci_dev!(0x0, 0x7, 0x13, 0x0 => 0x7, 0x13, 0x0, VpciDevType::Physical), // 07:13.0 + // pci_dev!(0x0, 0x7, 0x13, 0x4 => 0x7, 0x13, 0x4, VpciDevType::Physical), // 07:13.4 ]; // bus << 8 | dev << 5 | func << 3 diff --git a/platform/loongarch64/ls3a5000/cargo/features b/platform/loongarch64/ls3a5000/cargo/features deleted file mode 100644 index 442505f46..000000000 --- a/platform/loongarch64/ls3a5000/cargo/features +++ /dev/null @@ -1,7 +0,0 @@ -loongson_3a5000 -loongson_7a2000 -loongson_uart - -pci -loongarch64_pcie -no_pcie_bar_realloc \ No newline at end of file diff --git a/platform/loongarch64/ls3a5000/configs/zone1-linux.json b/platform/loongarch64/ls3a5000/configs/zone1-linux.json index cbfbf9728..fa90f802d 100644 --- a/platform/loongarch64/ls3a5000/configs/zone1-linux.json +++ b/platform/loongarch64/ls3a5000/configs/zone1-linux.json @@ -111,28 +111,35 @@ "arch_config": { "dummy": "0x1234" }, - "pci_config": [{ - "ecam_base": "0xfe00000000", - "ecam_size": "0x20000000", - "io_base": "0x18408000", - "io_size": "0x8000", - "pci_io_base": "0x00008000", - "mem32_base": "0x0", - "mem32_size": "0x0", - "pci_mem32_base": "0x0", - "mem64_base": "0x60000000", - "mem64_size": "0x20000000", - "pci_mem64_base": "0x60000000", - "bus_range_begin": "0x0", - "bus_range_end": "0x1f", - "domain": "0x0" - }], + "pci_config": [ + { + "ecam_base": "0xfe00000000", + "ecam_size": "0x20000000", + "io_base": "0x18408000", + "io_size": "0x8000", + "pci_io_base": "0x00008000", + "mem32_base": "0x0", + "mem32_size": "0x0", + "pci_mem32_base": "0x0", + "mem64_base": "0x60000000", + "mem64_size": "0x20000000", + "pci_mem64_base": "0x60000000", + "bus_range_begin": "0x0", + "bus_range_end": "0x1f", + "domain": "0x0" + } + ], "num_pci_devs": 1, - "alloc_pci_devs": [{ - "domain": "0x0", - "bus": "0x6", - "device": "0x1", - "function": "0x0", - "dev_type": "0" - }] + "alloc_pci_devs": [ + { + "domain": "0x0", + "bus": "0x7", + "device": "0x10", + "function": "0x0", + "v_bus": "0x6", + "v_device": "0x0", + "v_function": "0x0", + "dev_type": "0" + } + ] } \ No newline at end of file diff --git a/platform/loongarch64/ls3a5000/configs/zone2-linux.json b/platform/loongarch64/ls3a5000/configs/zone2-linux.json index 54ed3e2bd..c2e5f87f5 100644 --- a/platform/loongarch64/ls3a5000/configs/zone2-linux.json +++ b/platform/loongarch64/ls3a5000/configs/zone2-linux.json @@ -99,28 +99,35 @@ "arch_config": { "dummy": "0x1234" }, - "pci_config": [{ - "ecam_base": "0xfe00000000", - "ecam_size": "0x20000000", - "io_base": "0x18408000", - "io_size": "0x8000", - "pci_io_base": "0x00008000", - "mem32_base": "0x0", - "mem32_size": "0x0", - "pci_mem32_base": "0x0", - "mem64_base": "0x60000000", - "mem64_size": "0x20000000", - "pci_mem64_base": "0x60000000", - "bus_range_begin": "0x0", - "bus_range_end": "0x1f", - "domain": "0x0" - }], + "pci_config": [ + { + "ecam_base": "0xfe00000000", + "ecam_size": "0x20000000", + "io_base": "0x18408000", + "io_size": "0x8000", + "pci_io_base": "0x00008000", + "mem32_base": "0x0", + "mem32_size": "0x0", + "pci_mem32_base": "0x0", + "mem64_base": "0x60000000", + "mem64_size": "0x20000000", + "pci_mem64_base": "0x60000000", + "bus_range_begin": "0x0", + "bus_range_end": "0x1f", + "domain": "0x0" + } + ], "num_pci_devs": 1, - "alloc_pci_devs": [{ - "domain": "0x0", - "bus": "0x6", - "device": "0x2", - "function": "0x0", - "dev_type": "0" - }] + "alloc_pci_devs": [ + { + "domain": "0x0", + "bus": "0x7", + "device": "0x10", + "function": "0x4", + "v_bus": "0x6", + "v_device": "0x0", + "v_function": "0x0", + "dev_type": "0" + } + ] } \ No newline at end of file diff --git a/platform/loongarch64/ls3a5000/configs/zone3-linux.json b/platform/loongarch64/ls3a5000/configs/zone3-linux.json index 4f8e39b77..ee15bf60b 100644 --- a/platform/loongarch64/ls3a5000/configs/zone3-linux.json +++ b/platform/loongarch64/ls3a5000/configs/zone3-linux.json @@ -99,28 +99,35 @@ "arch_config": { "dummy": "0x1234" }, - "pci_config": [{ - "ecam_base": "0xfe00000000", - "ecam_size": "0x20000000", - "io_base": "0x18408000", - "io_size": "0x8000", - "pci_io_base": "0x00008000", - "mem32_base": "0x0", - "mem32_size": "0x0", - "pci_mem32_base": "0x0", - "mem64_base": "0x60000000", - "mem64_size": "0x20000000", - "pci_mem64_base": "0x60000000", - "bus_range_begin": "0x0", - "bus_range_end": "0x1f", - "domain": "0x0" - }], + "pci_config": [ + { + "ecam_base": "0xfe00000000", + "ecam_size": "0x20000000", + "io_base": "0x18408000", + "io_size": "0x8000", + "pci_io_base": "0x00008000", + "mem32_base": "0x0", + "mem32_size": "0x0", + "pci_mem32_base": "0x0", + "mem64_base": "0x60000000", + "mem64_size": "0x20000000", + "pci_mem64_base": "0x60000000", + "bus_range_begin": "0x0", + "bus_range_end": "0x1f", + "domain": "0x0" + } + ], "num_pci_devs": 1, - "alloc_pci_devs": [{ - "domain": "0x0", - "bus": "0x6", - "device": "0x3", - "function": "0x0", - "dev_type": "0" - }] + "alloc_pci_devs": [ + { + "domain": "0x0", + "bus": "0x7", + "device": "0x11", + "function": "0x0", + "v_bus": "0x6", + "v_device": "0x0", + "v_function": "0x0", + "dev_type": "0" + } + ] } \ No newline at end of file diff --git a/platform/loongarch64/ls3a5000/kconfig/defconfig b/platform/loongarch64/ls3a5000/kconfig/defconfig new file mode 100644 index 000000000..c061a0fd3 --- /dev/null +++ b/platform/loongarch64/ls3a5000/kconfig/defconfig @@ -0,0 +1,7 @@ +CONFIG_ARCH_LOONGARCH64=y +CONFIG_LOONGSON_3A5000=y +CONFIG_LOONGSON_7A2000=y +CONFIG_LOONGSON_UART=y +CONFIG_NO_PCIE_BAR_REALLOC=y +CONFIG_PCI=y +CONFIG_PCIE_LOONGARCH64=y diff --git a/platform/loongarch64/ls3a6000/board.rs b/platform/loongarch64/ls3a6000/board.rs index 6bd74afa7..171c3ca9e 100644 --- a/platform/loongarch64/ls3a6000/board.rs +++ b/platform/loongarch64/ls3a6000/board.rs @@ -17,68 +17,127 @@ use crate::pci_dev; use crate::{arch::zone::HvArchZoneConfig, config::*, pci::vpci_dev::VpciDevType}; -pub const BOARD_NAME: &str = "ls3a5000"; +pub const BOARD_NAME: &str = "ls3a6000"; pub const BOARD_NCPUS: usize = 4; pub const ROOT_ZONE_DTB_ADDR: u64 = 0x10000f000; pub const ROOT_ZONE_KERNEL_ADDR: u64 = 0x200000; -pub const ROOT_ZONE_ENTRY: u64 = 0x9000000000d8c000; -pub const ROOT_ZONE_CPUS: u64 = 1 << 0; +pub const ROOT_ZONE_ENTRY: u64 = 0x9000000000dc6000; +pub const ROOT_ZONE_CPUS: u64 = (1 << 0) | (1 << 1); pub const ROOT_ZONE_NAME: &str = "root-linux-la64"; pub const ROOT_ZONE_MEMORY_REGIONS: &[HvConfigMemoryRegion] = &[ - /* memory regions */ + /* Legacy low RAM used during early boot. */ + HvConfigMemoryRegion { + mem_type: MEM_TYPE_RAM, + physical_start: 0x1000, + virtual_start: 0x0, + size: 0x10000, + }, + HvConfigMemoryRegion { + mem_type: MEM_TYPE_RAM, + physical_start: 0x10000, + virtual_start: 0x10000, + size: 0x1f0000, + }, + /* Keep these banks aligned with the root Linux device tree. */ HvConfigMemoryRegion { mem_type: MEM_TYPE_RAM, physical_start: 0x00200000, virtual_start: 0x00200000, - size: 0x0ee00000, - }, // ram + size: 0x0ec00000, + }, + HvConfigMemoryRegion { + mem_type: MEM_TYPE_RAM, + physical_start: 0x90400000, + virtual_start: 0x90400000, + size: 0x67b60000, + }, + HvConfigMemoryRegion { + mem_type: MEM_TYPE_RAM, + physical_start: 0xf7f70000, + virtual_start: 0xf7f70000, + size: 0x05f10000, + }, + HvConfigMemoryRegion { + mem_type: MEM_TYPE_RAM, + physical_start: 0xfe440000, + virtual_start: 0xfe440000, + size: 0xf1bc0000, + }, + /* Shared-memory and non-root banks reserved by the root device tree. */ + HvConfigMemoryRegion { + mem_type: MEM_TYPE_RAM, + physical_start: 0x2_00c0_0000, + virtual_start: 0x2_00c0_0000, + size: 0x0400_0000, + }, + HvConfigMemoryRegion { + mem_type: MEM_TYPE_RAM, + physical_start: 0x2_04c0_0000, + virtual_start: 0x2_04c0_0000, + size: 0x0400_0000, + }, + HvConfigMemoryRegion { + mem_type: MEM_TYPE_RAM, + physical_start: 0x2_08c0_0000, + virtual_start: 0x2_08c0_0000, + size: 0x0400_0000, + }, + HvConfigMemoryRegion { + mem_type: MEM_TYPE_RAM, + physical_start: 0x2_0cc0_0000, + virtual_start: 0x2_0cc0_0000, + size: 0x0400_0000, + }, HvConfigMemoryRegion { mem_type: MEM_TYPE_RAM, - physical_start: 0x90000000, - virtual_start: 0x90000000, - size: 0x10000000, - }, // ram + physical_start: 0x2_1cc0_0000, + virtual_start: 0x2_1cc0_0000, + size: 0x1_0000_0000, + }, HvConfigMemoryRegion { mem_type: MEM_TYPE_RAM, - physical_start: 0xf000_0000, - virtual_start: 0xf000_0000, - size: 0x1000_0000, - }, // ram + physical_start: 0x3_1cc0_0000, + virtual_start: 0x3_1cc0_0000, + size: 0x1_0000_0000, + }, HvConfigMemoryRegion { mem_type: MEM_TYPE_RAM, - physical_start: 0x1_6000_0000, - virtual_start: 0x1_6000_0000, - size: 0x1000_0000, - }, // linux0 + physical_start: 0x4_1cc0_0000, + virtual_start: 0x4_1cc0_0000, + size: 0x1_0000_0000, + }, HvConfigMemoryRegion { mem_type: MEM_TYPE_RAM, - physical_start: 0xc000_0000, - virtual_start: 0xc000_0000, - size: 0x3000_0000, - }, // linux1 + physical_start: 0x5_1cc0_0000, + virtual_start: 0x5_1cc0_0000, + size: 0x1_0000_0000, + }, HvConfigMemoryRegion { mem_type: MEM_TYPE_RAM, - physical_start: 0xa000_0000, - virtual_start: 0xa000_0000, - size: 0x2000_0000, - }, // linux2 + physical_start: 0x6_1cc0_0000, + virtual_start: 0x6_1cc0_0000, + size: 0x1_0000_0000, + }, HvConfigMemoryRegion { mem_type: MEM_TYPE_RAM, - physical_start: 0x1_0000_0000, - virtual_start: 0x1_0000_0000, - size: 0x2000_0000, - }, // linux3 + physical_start: 0x7_1cc0_0000, + virtual_start: 0x7_1cc0_0000, + size: 0x1_0000_0000, + }, /* devices and controllers */ HvConfigMemoryRegion { mem_type: MEM_TYPE_IO, physical_start: 0x1fe00000, virtual_start: 0x1fe00000, - size: 0x1000, - }, // uart0 + size: 0x3000, + }, // IOCSR MMIO: uart0, IPI, EXTIOI. + // Reference: + // IPI: + // EXTIOI: HvConfigMemoryRegion { mem_type: MEM_TYPE_IO, physical_start: 0x10080000, @@ -97,6 +156,18 @@ pub const ROOT_ZONE_MEMORY_REGIONS: &[HvConfigMemoryRegion] = &[ virtual_start: 0x10000000, size: 0x1000, }, // pch-pic irq controller + HvConfigMemoryRegion { + mem_type: MEM_TYPE_IO, + physical_start: 0x100A_0000, + virtual_start: 0x100A_0000, + size: 0x1000, + }, // LS7A PWM0-3 + HvConfigMemoryRegion { + mem_type: MEM_TYPE_IO, + physical_start: 0x0E0010000000, + virtual_start: 0x0E0010000000, + size: 0x1000, + }, // ACPI thermal sensor /* PCI related stuffs ... */ // HvConfigMemoryRegion { // mem_type: MEM_TYPE_IO, @@ -115,50 +186,35 @@ pub const ROOT_ZONE_MEMORY_REGIONS: &[HvConfigMemoryRegion] = &[ // physical_start: 0x18408000, // virtual_start: 0x18408000, // size: 0x00008000, - // }, // pci io resource - // HvConfigMemoryRegion { - // mem_type: MEM_TYPE_IO, - // physical_start: 0x60000000, - // virtual_start: 0x60000000, - // size: 0x20000000, - // }, // pci mem resource + // }, // pci config space (HT) HvConfigMemoryRegion { mem_type: MEM_TYPE_IO, physical_start: 0x1001_0000, virtual_start: 0x1001_0000, size: 0x0001_0000, - }, // ? - /* map special regions - 2024.4.12 */ - // linux's strscpy called gpa at 0x9000_0000_0000_0000 which is ldx x, 0x9000_0000_0000_0000(a1) + 0x0(a0) why ? - // __memcpy_fromio 0xf0000 why? + }, // PCH/LS7A miscellaneous registers HvConfigMemoryRegion { - mem_type: MEM_TYPE_RAM, - physical_start: 0x1000, - virtual_start: 0x0, - size: 0x10000, - }, // 0x0 - HvConfigMemoryRegion { - mem_type: MEM_TYPE_RAM, - physical_start: 0xf0000, - virtual_start: 0xf0000, - size: 0x10000, - }, // 0xf0000 + mem_type: MEM_TYPE_IO, + physical_start: 0x18408000, + virtual_start: 0x18408000, + size: 0x00008000, + }, // PCI IO resource HvConfigMemoryRegion { - mem_type: MEM_TYPE_RAM, - physical_start: 0x1_4000_0000, - virtual_start: 0x1_4000_0000, - size: 0x80_0000, // linux1-root - }, // SHARD_MEM + mem_type: MEM_TYPE_IO, + physical_start: 0x60000000, + virtual_start: 0x60000000, + size: 0x20000000, + }, // PCI memory resource ]; -pub const IRQ_WAKEUP_VIRTIO_DEVICE: usize = 32 + 0x20; +pub const IRQ_WAKEUP_VIRTIO_DEVICE: usize = 4; pub const ROOT_ZONE_IRQS_BITMAP: &[BitmapWord] = &get_irqs_bitmap(&[]); pub const ROOT_ARCH_ZONE_CONFIG: HvArchZoneConfig = HvArchZoneConfig { dummy: 0 }; pub const ROOT_ZONE_IVC_CONFIG: [HvIvcConfig; 0] = []; pub const ROOT_PCI_CONFIG: [HvPciConfig; 1] = [HvPciConfig { bus_range_begin: 0x0, - bus_range_end: 0x1f, + bus_range_end: 0xff, ecam_base: 0xfe00000000, ecam_size: 0x20000000, io_base: 0x18408000, @@ -183,32 +239,32 @@ pub const ROOT_PCI_CONFIG: [HvPciConfig; 1] = [HvPciConfig { /* BUS 6 on X4 slot */ /* 06:00.0, 06:00.1, 06:00.2, 06:00.3 net */ pub const ROOT_PCI_DEVS: [HvPciDevConfig; 26] = [ - pci_dev!(0x0, 0x0, 0x0, 0x0, VpciDevType::Physical), // 00:00.0 - pci_dev!(0x0, 0x0, 0x0, 0x1, VpciDevType::Physical), // 00:00.1 - pci_dev!(0x0, 0x0, 0x0, 0x2, VpciDevType::Physical), // 00:00.2 - pci_dev!(0x0, 0x0, 0x0, 0x3, VpciDevType::Physical), // 00:00.3 - pci_dev!(0x0, 0x0, 0x4, 0x0, VpciDevType::Physical), // 00:04.0 - pci_dev!(0x0, 0x0, 0x4, 0x1, VpciDevType::Physical), // 00:04.1 - pci_dev!(0x0, 0x0, 0x5, 0x0, VpciDevType::Physical), // 00:05.0 - pci_dev!(0x0, 0x0, 0x5, 0x1, VpciDevType::Physical), // 00:05.1 - pci_dev!(0x0, 0x0, 0x6, 0x0, VpciDevType::Physical), // 00:06.0 - pci_dev!(0x0, 0x0, 0x6, 0x1, VpciDevType::Physical), // 00:06.1 - pci_dev!(0x0, 0x0, 0x6, 0x2, VpciDevType::Physical), // 00:06.2 - pci_dev!(0x0, 0x0, 0x7, 0x0, VpciDevType::Physical), // 00:07.0 - pci_dev!(0x0, 0x0, 0x8, 0x0, VpciDevType::Physical), // 00:08.0 - pci_dev!(0x0, 0x0, 0x9, 0x0, VpciDevType::Physical), // 00:09.0 - pci_dev!(0x0, 0x0, 0xa, 0x0, VpciDevType::Physical), // 00:0a.0 - pci_dev!(0x0, 0x0, 0xb, 0x0, VpciDevType::Physical), // 00:0b.0 - pci_dev!(0x0, 0x0, 0xc, 0x0, VpciDevType::Physical), // 00:0c.0 - pci_dev!(0x0, 0x0, 0xd, 0x0, VpciDevType::Physical), // 00:0d.0 - pci_dev!(0x0, 0x0, 0xf, 0x0, VpciDevType::Physical), // 00:0f.0 - pci_dev!(0x0, 0x0, 0x10, 0x0, VpciDevType::Physical), // 00:10.0 - pci_dev!(0x0, 0x0, 0x13, 0x0, VpciDevType::Physical), // 00:13.0 - pci_dev!(0x0, 0x0, 0x16, 0x0, VpciDevType::Physical), // 00:16.0 - pci_dev!(0x0, 0x0, 0x19, 0x0, VpciDevType::Physical), // 00:19.0 - pci_dev!(0x0, 0x2, 0x0, 0x0, VpciDevType::Physical), // 02:00.0 - pci_dev!(0x0, 0x5, 0x0, 0x0, VpciDevType::Physical), // 05:00.0 - pci_dev!(0x0, 0x6, 0x0, 0x0, VpciDevType::Physical), // 06:00.0 + pci_dev!(0x0, 0x0, 0x0, 0x0 => 0x0, 0x0, 0x0, VpciDevType::Physical), // 00:00.0 + pci_dev!(0x0, 0x0, 0x0, 0x1 => 0x0, 0x0, 0x1, VpciDevType::Physical), // 00:00.1 + pci_dev!(0x0, 0x0, 0x0, 0x2 => 0x0, 0x0, 0x2, VpciDevType::Physical), // 00:00.2 + pci_dev!(0x0, 0x0, 0x0, 0x3 => 0x0, 0x0, 0x3, VpciDevType::Physical), // 00:00.3 + pci_dev!(0x0, 0x0, 0x4, 0x0 => 0x0, 0x4, 0x0, VpciDevType::Physical), // 00:04.0 + pci_dev!(0x0, 0x0, 0x4, 0x1 => 0x0, 0x4, 0x1, VpciDevType::Physical), // 00:04.1 + pci_dev!(0x0, 0x0, 0x5, 0x0 => 0x0, 0x5, 0x0, VpciDevType::Physical), // 00:05.0 + pci_dev!(0x0, 0x0, 0x5, 0x1 => 0x0, 0x5, 0x1, VpciDevType::Physical), // 00:05.1 + pci_dev!(0x0, 0x0, 0x6, 0x0 => 0x0, 0x6, 0x0, VpciDevType::Physical), // 00:06.0 + pci_dev!(0x0, 0x0, 0x6, 0x1 => 0x0, 0x6, 0x1, VpciDevType::Physical), // 00:06.1 + pci_dev!(0x0, 0x0, 0x6, 0x2 => 0x0, 0x6, 0x2, VpciDevType::Physical), // 00:06.2 + pci_dev!(0x0, 0x0, 0x7, 0x0 => 0x0, 0x7, 0x0, VpciDevType::Physical), // 00:07.0 + pci_dev!(0x0, 0x0, 0x8, 0x0 => 0x0, 0x8, 0x0, VpciDevType::Physical), // 00:08.0 + pci_dev!(0x0, 0x0, 0x9, 0x0 => 0x0, 0x9, 0x0, VpciDevType::Physical), // 00:09.0 + pci_dev!(0x0, 0x0, 0xa, 0x0 => 0x0, 0xa, 0x0, VpciDevType::Physical), // 00:0a.0 + pci_dev!(0x0, 0x0, 0xb, 0x0 => 0x0, 0xb, 0x0, VpciDevType::Physical), // 00:0b.0 + pci_dev!(0x0, 0x0, 0xc, 0x0 => 0x0, 0xc, 0x0, VpciDevType::Physical), // 00:0c.0 + pci_dev!(0x0, 0x0, 0xd, 0x0 => 0x0, 0xd, 0x0, VpciDevType::Physical), // 00:0d.0 + pci_dev!(0x0, 0x0, 0xf, 0x0 => 0x0, 0xf, 0x0, VpciDevType::Physical), // 00:0f.0 + pci_dev!(0x0, 0x0, 0x10, 0x0 => 0x0, 0x10, 0x0, VpciDevType::Physical), // 00:10.0 + pci_dev!(0x0, 0x0, 0x13, 0x0 => 0x0, 0x13, 0x0, VpciDevType::Physical), // 00:13.0 + pci_dev!(0x0, 0x0, 0x16, 0x0 => 0x0, 0x16, 0x0, VpciDevType::Physical), // 00:16.0 + pci_dev!(0x0, 0x0, 0x19, 0x0 => 0x0, 0x19, 0x0, VpciDevType::Physical), // 00:19.0 + pci_dev!(0x0, 0x2, 0x0, 0x0 => 0x2, 0x0, 0x0, VpciDevType::Physical), // 02:00.0 + pci_dev!(0x0, 0x5, 0x0, 0x0 => 0x5, 0x0, 0x0, VpciDevType::Physical), // 05:00.0 + pci_dev!(0x0, 0x6, 0x0, 0x0 => 0x6, 0x0, 0x0, VpciDevType::Physical), // 06:00.0 ]; // bus << 8 | dev << 5 | func << 3 diff --git a/platform/loongarch64/ls3a6000/cargo/features b/platform/loongarch64/ls3a6000/cargo/features deleted file mode 100644 index 86cd7a5c3..000000000 --- a/platform/loongarch64/ls3a6000/cargo/features +++ /dev/null @@ -1,7 +0,0 @@ -loongson_3a6000 -loongson_7a2000 -loongson_uart - -pci -loongarch64_pcie -no_pcie_bar_realloc \ No newline at end of file diff --git a/platform/loongarch64/ls3a6000/configs/zone1-linux.json b/platform/loongarch64/ls3a6000/configs/zone1-linux.json index cbfbf9728..08f21c7fb 100644 --- a/platform/loongarch64/ls3a6000/configs/zone1-linux.json +++ b/platform/loongarch64/ls3a6000/configs/zone1-linux.json @@ -3,32 +3,15 @@ "name": "linux1", "zone_id": 1, "cpus": [ - 1 + 2, + 3 ], "memory_regions": [ { "type": "ram", - "physical_start": "0xc0000000", - "virtual_start": "0xc0000000", - "size": "0x10000000" - }, - { - "type": "ram", - "physical_start": "0xd0000000", - "virtual_start": "0xd0000000", - "size": "0x10000000" - }, - { - "type": "io", - "physical_start": "0x1fe00000", - "virtual_start": "0x1fe00000", - "size": "0x1000" - }, - { - "type": "io", - "physical_start": "0x10080000", - "virtual_start": "0x10080000", - "size": "0x1000" + "physical_start": "0x21cc00000", + "virtual_start": "0x21cc00000", + "size": "0x200000000" }, { "type": "virtio", @@ -42,30 +25,6 @@ "virtual_start": "0x30002000", "size": "0x200" }, - { - "type": "io", - "physical_start": "0xffffffff0000", - "virtual_start": "0xffffffff0000", - "size": "0x1000" - }, - { - "type": "io", - "physical_start": "0x10000000", - "virtual_start": "0x10000000", - "size": "0x1000" - }, - { - "type": "io", - "physical_start": "0x100d0000", - "virtual_start": "0x100d0000", - "size": "0x1000" - }, - { - "type": "io", - "physical_start": "0x10010000", - "virtual_start": "0x10010000", - "size": "0x00010000" - }, { "type": "ram", "physical_start": "0x1000", @@ -80,34 +39,49 @@ }, { "type": "ram", - "physical_start": "0x140000000", - "virtual_start": "0x140000000", - "size": "0x800000" + "physical_start": "0x200c00000", + "virtual_start": "0x200c00000", + "size": "0x04000000" }, { "type": "ram", - "physical_start": "0x140800000", - "virtual_start": "0x140800000", - "size": "0x800000" + "physical_start": "0x204c00000", + "virtual_start": "0x204c00000", + "size": "0x04000000" }, { "type": "ram", - "physical_start": "0x141000000", - "virtual_start": "0x141000000", - "size": "0x800000" + "physical_start": "0x210c00000", + "virtual_start": "0x210c00000", + "size": "0x04000000" + }, + { + "type": "ram", + "physical_start": "0x214c00000", + "virtual_start": "0x214c00000", + "size": "0x04000000" } ], "interrupts": [ 4, 5 ], - "ivc_configs": [], + "ivc_configs": [{ + "ivc_id": 0, + "peer_id": 1, + "control_table_ipa": "0x200be0000", + "shared_mem_ipa": "0x200be1000", + "rw_sec_size": 0, + "out_sec_size": "0x1000", + "interrupt_num": 148, + "max_peers": 2 + }], "kernel_args": "NOT_USED_YET", "kernel_filepath": "/tool/nonroot/vmlinux-linux1.bin", "dtb_filepath": "/tool/test.bin", - "kernel_load_paddr": "0xc0200000", - "dtb_load_paddr": "0xc0000000", - "entry_point": "0x90000000c0dff000", + "kernel_load_paddr": "0x21ce00000", + "dtb_load_paddr": "0x21cc00000", + "entry_point": "0x900000021da22000", "arch_config": { "dummy": "0x1234" }, @@ -120,19 +94,22 @@ "mem32_base": "0x0", "mem32_size": "0x0", "pci_mem32_base": "0x0", - "mem64_base": "0x60000000", - "mem64_size": "0x20000000", - "pci_mem64_base": "0x60000000", - "bus_range_begin": "0x0", - "bus_range_end": "0x1f", + "mem64_base": "0x75300000", + "mem64_size": "0x1000000", + "pci_mem64_base": "0x75300000", + "bus_range_begin": "0x6", + "bus_range_end": "0x6", "domain": "0x0" }], "num_pci_devs": 1, "alloc_pci_devs": [{ "domain": "0x0", "bus": "0x6", - "device": "0x1", - "function": "0x0", + "device": "0x0", + "function": "0x1", + "v_bus": "0x6", + "v_device": "0x0", + "v_function": "0x1", "dev_type": "0" }] -} \ No newline at end of file +} diff --git a/platform/loongarch64/ls3a6000/configs/zone2-linux.json b/platform/loongarch64/ls3a6000/configs/zone2-linux.json index 54ed3e2bd..523a4ff70 100644 --- a/platform/loongarch64/ls3a6000/configs/zone2-linux.json +++ b/platform/loongarch64/ls3a6000/configs/zone2-linux.json @@ -121,6 +121,9 @@ "bus": "0x6", "device": "0x2", "function": "0x0", + "v_bus": "0x6", + "v_device": "0x2", + "v_function": "0x0", "dev_type": "0" }] -} \ No newline at end of file +} diff --git a/platform/loongarch64/ls3a6000/configs/zone3-linux.json b/platform/loongarch64/ls3a6000/configs/zone3-linux.json index 4f8e39b77..46856f5a8 100644 --- a/platform/loongarch64/ls3a6000/configs/zone3-linux.json +++ b/platform/loongarch64/ls3a6000/configs/zone3-linux.json @@ -121,6 +121,9 @@ "bus": "0x6", "device": "0x3", "function": "0x0", + "v_bus": "0x6", + "v_device": "0x3", + "v_function": "0x0", "dev_type": "0" }] -} \ No newline at end of file +} diff --git a/platform/loongarch64/ls3a6000/image/dts/include/loongson-3a5000.dtsi b/platform/loongarch64/ls3a6000/image/dts/include/loongson-3a5000.dtsi index 3880aca0a..05fef3973 100644 --- a/platform/loongarch64/ls3a6000/image/dts/include/loongson-3a5000.dtsi +++ b/platform/loongarch64/ls3a6000/image/dts/include/loongson-3a5000.dtsi @@ -21,6 +21,14 @@ next-level-cache = <&scache0>; numa-node-id = <0>; }; + cpu@1 { + compatible = "loongson,loongson3"; + device_type = "cpu"; + reg = <0x1>; + l2-cache = <&vcache1>; + next-level-cache = <&scache0>; + numa-node-id = <0>; + }; vcache0: l2-cache0 { compatible = "cache"; next-level-cache = <&scache0>; diff --git a/platform/loongarch64/ls3a6000/kconfig/defconfig b/platform/loongarch64/ls3a6000/kconfig/defconfig new file mode 100644 index 000000000..ef0a73e99 --- /dev/null +++ b/platform/loongarch64/ls3a6000/kconfig/defconfig @@ -0,0 +1,7 @@ +CONFIG_ARCH_LOONGARCH64=y +CONFIG_LOONGSON_3A6000=y +CONFIG_LOONGSON_7A2000=y +CONFIG_LOONGSON_UART=y +CONFIG_NO_PCIE_BAR_REALLOC=y +CONFIG_PCI=y +CONFIG_PCIE_LOONGARCH64=y diff --git a/platform/riscv64/hifive-premier-p550/cargo/features b/platform/riscv64/hifive-premier-p550/cargo/features deleted file mode 100644 index d72ea9ac9..000000000 --- a/platform/riscv64/hifive-premier-p550/cargo/features +++ /dev/null @@ -1,4 +0,0 @@ -eic770x_soc -plic -eic7700_sysreg -sifive_ccache diff --git a/platform/riscv64/hifive-premier-p550/configs/zone1-linux.json b/platform/riscv64/hifive-premier-p550/configs/zone1-linux.json index 0e8bc05b2..c23613bbd 100644 --- a/platform/riscv64/hifive-premier-p550/configs/zone1-linux.json +++ b/platform/riscv64/hifive-premier-p550/configs/zone1-linux.json @@ -59,5 +59,6 @@ "plic_size": "0x4000000", "aplic_base": "0xd000000", "aplic_size": "0x8000" - } -} \ No newline at end of file + }, + "pci_config": [] +} diff --git a/platform/riscv64/hifive-premier-p550/kconfig/defconfig b/platform/riscv64/hifive-premier-p550/kconfig/defconfig new file mode 100644 index 000000000..769ea39d6 --- /dev/null +++ b/platform/riscv64/hifive-premier-p550/kconfig/defconfig @@ -0,0 +1,5 @@ +CONFIG_ARCH_RISCV64=y +CONFIG_EIC7700_SYSREG=y +CONFIG_HYPERVISOR_V0_6=y +CONFIG_PLIC=y +CONFIG_SIFIVE_CCACHE=y diff --git a/platform/riscv64/k3-com260/README.md b/platform/riscv64/k3-com260/README.md new file mode 100644 index 000000000..1f9aeafe4 --- /dev/null +++ b/platform/riscv64/k3-com260/README.md @@ -0,0 +1,37 @@ +# SpaceMiT K3 (k3-com260) + +## Software + +- Linux source: +- Linux configuration: `k3_bianbu_defconfig` +- Cross-compilation toolchain: + +## Device support + +- zone0 supports passthrough assignment of network and block devices. +- zone1 currently supports only virtio devices. Passthrough of physical devices + is not yet supported because their dependency relationships are complex. + +## Reproduction steps + +1. Prepare `hvisor.bin`, the zone0 Linux `Image`, and `zone0.dtb` on the TFTP + server. +2. Place the following files in the zone0 filesystem, in the same working + directory: + - The zone1 Linux `Image`, `zone1-linux.dtb`, and `rootfs2.ext4`. + - The `hvisor` executable and `hvisor.ko` from hvisor-tool. + - `configs/virtio-backend.json`, `configs/zone1-linux-virtio.json`, and + `scripts/boot_zone1.sh` from this directory. +3. Power on the board and press `s` during U-Boot startup to stop autoboot. + Enter the commands in [boot.txt](boot.txt) to load hvisor and the zone0 + kernel and DTB. The final `bootm` command starts hvisor, which then starts + zone0. +4. After zone0 has booted, follow the commands in + [scripts/boot_zone1.sh](scripts/boot_zone1.sh) to load `hvisor.ko`, start the + virtio backend, and start zone1. +5. Run `screen /dev/pts/0` in zone0 to connect to the zone1 serial console. + +> **Note:** SD-card support requires the MPXY extension introduced by SBI 3.0 +> and is left for future work. To enable it, hvisor must report SBI version 3.0 +> to the guest and forward MPXY calls to OpenSBI. hvisor does not currently +> provide this passthrough. diff --git a/platform/riscv64/k3-com260/board.rs b/platform/riscv64/k3-com260/board.rs new file mode 100644 index 000000000..61f36d6e7 --- /dev/null +++ b/platform/riscv64/k3-com260/board.rs @@ -0,0 +1,147 @@ +// Copyright (c) 2025 Syswonder +// hvisor is licensed under Mulan PSL v2. +// You can use this software according to the terms and conditions of the Mulan PSL v2. +// You may obtain a copy of Mulan PSL v2 at: +// http://license.coscl.org.cn/MulanPSL2 +// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR +// FIT FOR A PARTICULAR PURPOSE. +// See the Mulan PSL v2 for more details. +// +// Syswonder Website: +// https://www.syswonder.org +// +// Authors: +// Jingyu Liu +// +use crate::{arch::zone::HvArchZoneConfig, config::*}; + +pub const BOARD_NAME: &str = "k3-com260"; +// Here only contains X100 cores, not including A100 cores. +pub const BOARD_NCPUS: usize = 8; +#[rustfmt::skip] +pub static BOARD_HARTID_MAP: [usize; BOARD_NCPUS] = [ + 0x0, // X100 core0 + 0x1, // X100 core1 + 0x2, // X100 core2 + 0x3, // X100 core3 + 0x4, // X100 core4 + 0x5, // X100 core5 + 0x6, // X100 core6 + 0x7, // X100 core7 +]; +pub const TIMEBASE_FREQ: u64 = 0x16e3600; // 24MHz + +pub const APLIC_S_BASE: usize = 0xe0804000; +pub const APLIC_S_SIZE: usize = 0x4000; +pub const BOARD_APLIC_INTERRUPTS_NUM: usize = 512; +pub const IMSIC_S_BASE: usize = 0xe0400000; +pub const IMSIC_GUEST_NUM: usize = 63; +pub const IMSIC_GUEST_INDEX: usize = 1; +pub const IMSIC_NUM_IDS: usize = 0x1FF; + +pub const ROOT_ZONE_DTB_ADDR: u64 = 0x1_0f00_0000; +pub const ROOT_ZONE_KERNEL_ADDR: u64 = 0x1_1000_0000; +pub const ROOT_ZONE_ENTRY: u64 = 0x1_1000_0000; +pub const ROOT_ZONE_CPUS: u64 = 0xF; // core0 ~ core3 +pub const ROOT_ZONE_NAME: &str = "root-linux"; + +pub const ROOT_ZONE_MEMORY_REGIONS: &[HvConfigMemoryRegion] = &[ + HvConfigMemoryRegion { + mem_type: MEM_TYPE_RAM, + physical_start: 0x107000000, // 0x1_0200_0000 + 0x500_0000 + virtual_start: 0x107000000, + size: 0x100000000, + }, // ram + HvConfigMemoryRegion { + mem_type: MEM_TYPE_IO, + physical_start: 0xd4017000, + virtual_start: 0xd4017000, + size: 0x1000, + }, // serial@d4017000 + HvConfigMemoryRegion { + mem_type: MEM_TYPE_IO, + physical_start: 0xd4050000, + virtual_start: 0xd4050000, + size: 0x10000, + }, // system-controller@d4050000 + HvConfigMemoryRegion { + mem_type: MEM_TYPE_IO, + physical_start: 0xd4015000, + virtual_start: 0xd4015000, + size: 0x1000, + }, // system-controller@d4015000 + HvConfigMemoryRegion { + mem_type: MEM_TYPE_IO, + physical_start: 0xd4090000, + virtual_start: 0xd4090000, + size: 0x10000, + }, // clock-controller@d4090000 + HvConfigMemoryRegion { + mem_type: MEM_TYPE_IO, + physical_start: 0xd401e000, + virtual_start: 0xd401e000, + size: 0x1000, + }, // pinctrl@d401e000 + HvConfigMemoryRegion { + mem_type: MEM_TYPE_IO, + physical_start: 0xd4282000, + virtual_start: 0xd4282000, + size: 0x1000, + }, // system-controller@d4282800 + HvConfigMemoryRegion { + mem_type: MEM_TYPE_IO, + physical_start: 0xc0e00000, + virtual_start: 0xc0e00000, + size: 0x40000, + }, // ufshc@0xc0e00000 + HvConfigMemoryRegion { + mem_type: MEM_TYPE_IO, + physical_start: 0xd4019000, + virtual_start: 0xd4019000, + size: 0x1000, + }, // gpio@d4019000 + HvConfigMemoryRegion { + mem_type: MEM_TYPE_IO, + physical_start: 0xd4280000, + virtual_start: 0xd4280000, + size: 0x1000, + }, // mmc@d4280000 + HvConfigMemoryRegion { + mem_type: MEM_TYPE_IO, + physical_start: 0xcac82000, + virtual_start: 0xcac82000, + size: 0x2000, + }, // ethernet@cac82000 +]; + +pub const IRQ_WAKEUP_VIRTIO_DEVICE: usize = 0x20; +pub const HW_IRQS: &[u32] = &[ + 42, // serial@d4017000 + 58, // gpio@d4019000 + 60, // pinctrl@d401e000 + 99, // mmc@d4280000 + 135, // ufshc@0xc0e00000 + 133, 277, // ethernet@cac82000 +]; +pub const ROOT_ZONE_IRQS_BITMAP: &[BitmapWord] = &get_irqs_bitmap(&[ + 42, // serial@d4017000 + 58, // gpio@d4019000 + 60, // pinctrl@d401e000 + 99, // mmc@d4280000 + 135, // ufshc@0xc0e00000 + 133, 277, // ethernet@cac82000 +]); + +pub const ROOT_ARCH_ZONE_CONFIG: HvArchZoneConfig = HvArchZoneConfig { + plic_base: 0x0, + plic_size: 0x0, + aplic_base: APLIC_S_BASE, + aplic_size: APLIC_S_SIZE, +}; + +pub const ROOT_PCI_CONFIG: [HvPciConfig; 0] = []; + +pub const ROOT_ZONE_IVC_CONFIG: &[HvIvcConfig] = &[]; + +pub const ROOT_PCI_DEVS: &[HvPciDevConfig] = &[]; diff --git a/platform/riscv64/k3-com260/boot.txt b/platform/riscv64/k3-com260/boot.txt new file mode 100644 index 000000000..139ef5d72 --- /dev/null +++ b/platform/riscv64/k3-com260/boot.txt @@ -0,0 +1,14 @@ +setenv serverip 192.168.137.1; +setenv ipaddr 192.168.137.200; +setenv netmask 255.255.255.0; + +setenv hvisor_fit_addr 0x122200000; +tftpboot ${hvisor_fit_addr} ${serverip}:hvisor.bin; + +setenv zone0_fdt_addr 0x10f000000; +tftpboot ${zone0_fdt_addr} ${serverip}:zone0.dtb; + +setenv zone0_kernel_addr 0x110000000; +tftpboot ${zone0_kernel_addr} ${serverip}:Image; + +bootm ${hvisor_fit_addr} - ${zone0_fdt_addr}; diff --git a/platform/riscv64/k3-com260/cargo/config.template.toml b/platform/riscv64/k3-com260/cargo/config.template.toml new file mode 100644 index 000000000..f5d5b55c3 --- /dev/null +++ b/platform/riscv64/k3-com260/cargo/config.template.toml @@ -0,0 +1,6 @@ +[target.riscv64gc-unknown-none-elf] +runner = "platform/__ARCH__/__BOARD__/test/runner.sh" +rustflags = [ + "-Clink-arg=-Tplatform/__ARCH__/__BOARD__/linker.ld", + "-Cforce-frame-pointers=yes", +] \ No newline at end of file diff --git a/platform/riscv64/k3-com260/configs/virtio-backend.json b/platform/riscv64/k3-com260/configs/virtio-backend.json new file mode 100644 index 000000000..c0db6059f --- /dev/null +++ b/platform/riscv64/k3-com260/configs/virtio-backend.json @@ -0,0 +1,31 @@ +{ + "zones": [ + { + "id": 1, + "memory_region": [ + { + "zone0_ipa": "0x180000000", + "zonex_ipa": "0x180000000", + "size": "0x80000000" + } + ], + "devices": [ + { + "type": "blk", + "addr": "0x10006000", + "len": "0x1000", + "irq": 6, + "img": "rootfs2.ext4", + "status": "enable" + }, + { + "type": "console", + "addr": "0x10007000", + "len": "0x1000", + "irq": 7, + "status": "enable" + } + ] + } + ] +} \ No newline at end of file diff --git a/platform/riscv64/k3-com260/configs/zone1-linux-virtio.json b/platform/riscv64/k3-com260/configs/zone1-linux-virtio.json new file mode 100644 index 000000000..d53def2ea --- /dev/null +++ b/platform/riscv64/k3-com260/configs/zone1-linux-virtio.json @@ -0,0 +1,48 @@ +{ + "arch": "riscv", + "name": "linux2", + "zone_id": 1, + "cpus": [4, 5, 6, 7], + "memory_regions": [ + { + "type": "ram", + "physical_start": "0x180000000", + "virtual_start": "0x180000000", + "size": "0x80000000" + }, + { + "type": "io", + "physical_start": "0xd4282000", + "virtual_start": "0xd4282000", + "size": "0x1000" + }, + { + "type": "virtio", + "physical_start": "0x10006000", + "virtual_start": "0x10006000", + "size": "0x1000" + }, + { + "type": "virtio", + "physical_start": "0x10007000", + "virtual_start": "0x10007000", + "size": "0x1000" + } + ], + "interrupts": [6, 7], + "ivc_configs": [], + "kernel_filepath": "./Image", + "dtb_filepath": "./zone1-linux.dtb", + "kernel_load_paddr": "0x181000000", + "dtb_load_paddr": "0x180000000", + "entry_point": "0x181000000", + "arch_config": { + "plic_base": "0x0", + "plic_size": "0x0", + "aplic_base": "0xe0804000", + "aplic_size": "0x4000" + }, + "pci_config": [], + "num_pci_devs": 0, + "alloc_pci_devs": [] +} \ No newline at end of file diff --git a/platform/riscv64/k3-com260/hvisor.its b/platform/riscv64/k3-com260/hvisor.its new file mode 100644 index 000000000..31a98a1c3 --- /dev/null +++ b/platform/riscv64/k3-com260/hvisor.its @@ -0,0 +1,28 @@ +/dts-v1/; + +/ { + description = "Hypervisor FIT Image"; + #address-cells = <2>; + + images { + hvisor { + description = "Hypervisor Kernel"; + data = /incbin/("hvisor.bin.tmp"); + type = "kernel"; + arch = "riscv"; + os = "linux"; + compression = "none"; + + load = <0x1 0x02200000>; + entry = <0x1 0x02200000>; + }; + }; + + configurations { + default = "config_1"; + config_1 { + description = "Boot Hypervisor with External FDT"; + kernel = "hvisor"; + }; + }; +}; \ No newline at end of file diff --git a/platform/riscv64/k3-com260/image/dts/Makefile b/platform/riscv64/k3-com260/image/dts/Makefile new file mode 100644 index 000000000..2f795e7fe --- /dev/null +++ b/platform/riscv64/k3-com260/image/dts/Makefile @@ -0,0 +1,8 @@ +DTS_FILES := $(wildcard *.dts) +DTB_FILES := $(DTS_FILES:.dts=.dtb) + +all: $(DTB_FILES) +%.dtb: %.dts + dtc -I dts -O dtb $< -o $@ +clean: + rm -f $(DTB_FILES) \ No newline at end of file diff --git a/platform/riscv64/k3-com260/image/dts/k3_com260_ifx.dts b/platform/riscv64/k3-com260/image/dts/k3_com260_ifx.dts new file mode 100644 index 000000000..5eca0cd83 --- /dev/null +++ b/platform/riscv64/k3-com260/image/dts/k3_com260_ifx.dts @@ -0,0 +1,9178 @@ +/dts-v1/; + +/ { + #address-cells = <0x02>; + #size-cells = <0x02>; + model = "SpacemiT K3 Com260 IFX"; + compatible = "spacemit,k3-com260-ifx"; + + cpus { + #address-cells = <0x01>; + #size-cells = <0x00>; + timebase-frequency = <0x16e3600>; + + cpu@0 { + device_type = "cpu"; + reg = <0x00>; + model = "Spacemit(R) X100"; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdcvh"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i\0m\0a\0f\0d\0c\0v\0h\0smaia\0smstateen\0ssaia\0sscofpmf\0sstc\0svinval\0svnapot\0svpbmt\0zawrs\0zba\0zbb\0zbc\0zbs\0zcb\0zca\0zcmop\0zfa\0zfh\0zfhmin\0zkt\0zicbom\0zicbop\0zicboz\0zicntr\0zicond\0zicsr\0zifencei\0zihintpause\0zihintntl\0zihpm\0zimop\0zvbb\0zvbc\0zvfh\0zvfhmin\0zvkb\0zvkg\0zvkn\0zvknc\0zvkned\0zvkng\0zvknha\0zvknhb\0zvks\0zvksc\0zvksed\0zvksh\0zvksg\0zvkt\0zcd\0sdtrig"; + riscv,cbom-block-size = <0x40>; + riscv,cboz-block-size = <0x40>; + riscv,cbop-block-size = <0x40>; + i-cache-block-size = <0x40>; + i-cache-size = <0x10000>; + i-cache-sets = <0x100>; + d-cache-block-size = <0x40>; + d-cache-size = <0x10000>; + d-cache-sets = <0x100>; + next-level-cache = <0x01>; + cpu-idle-states = <0x02 0x03>; + mmu-type = "riscv,sv39"; + #cooling-cells = <0x02>; + clst-supply = <0x04>; + clocks = <0x05 0x04 0x05 0x05>; + clock-names = "cls0\0cls1"; + operating-points-v2 = <0x06>; + phandle = <0x0b>; + + interrupt-controller { + #interrupt-cells = <0x01>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + phandle = <0x69>; + }; + + debug { + compatible = "riscv,debug-v1.0.0"; + + trigger-module { + mcontext-present; + hcontext-present; + scontext-present; + }; + }; + }; + + cpu@1 { + device_type = "cpu"; + reg = <0x01>; + model = "Spacemit(R) X100"; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdcvh"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i\0m\0a\0f\0d\0c\0v\0h\0smaia\0smstateen\0ssaia\0sscofpmf\0sstc\0svinval\0svnapot\0svpbmt\0zawrs\0zba\0zbb\0zbc\0zbs\0zcb\0zca\0zcmop\0zfa\0zfh\0zfhmin\0zkt\0zicbom\0zicbop\0zicboz\0zicntr\0zicond\0zicsr\0zifencei\0zihintpause\0zihintntl\0zihpm\0zimop\0zvbb\0zvbc\0zvfh\0zvfhmin\0zvkb\0zvkg\0zvkn\0zvknc\0zvkned\0zvkng\0zvknha\0zvknhb\0zvks\0zvksc\0zvksed\0zvksh\0zvksg\0zvkt\0zcd\0sdtrig"; + riscv,cbom-block-size = <0x40>; + riscv,cboz-block-size = <0x40>; + riscv,cbop-block-size = <0x40>; + i-cache-block-size = <0x40>; + i-cache-size = <0x10000>; + i-cache-sets = <0x100>; + d-cache-block-size = <0x40>; + d-cache-size = <0x10000>; + d-cache-sets = <0x100>; + next-level-cache = <0x01>; + cpu-idle-states = <0x02 0x03>; + mmu-type = "riscv,sv39"; + #cooling-cells = <0x02>; + clst-supply = <0x04>; + clocks = <0x05 0x04 0x05 0x05>; + clock-names = "cls0\0cls1"; + operating-points-v2 = <0x06>; + phandle = <0x0c>; + + interrupt-controller { + #interrupt-cells = <0x01>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + phandle = <0x6a>; + }; + + debug { + compatible = "riscv,debug-v1.0.0"; + + trigger-module { + mcontext-present; + hcontext-present; + scontext-present; + }; + }; + }; + + cpu@2 { + device_type = "cpu"; + reg = <0x02>; + model = "Spacemit(R) X100"; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdcvh"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i\0m\0a\0f\0d\0c\0v\0h\0smaia\0smstateen\0ssaia\0sscofpmf\0sstc\0svinval\0svnapot\0svpbmt\0zawrs\0zba\0zbb\0zbc\0zbs\0zcb\0zca\0zcmop\0zfa\0zfh\0zfhmin\0zkt\0zicbom\0zicbop\0zicboz\0zicntr\0zicond\0zicsr\0zifencei\0zihintpause\0zihintntl\0zihpm\0zimop\0zvbb\0zvbc\0zvfh\0zvfhmin\0zvkb\0zvkg\0zvkn\0zvknc\0zvkned\0zvkng\0zvknha\0zvknhb\0zvks\0zvksc\0zvksed\0zvksh\0zvksg\0zvkt\0zcd\0sdtrig"; + riscv,cbom-block-size = <0x40>; + riscv,cboz-block-size = <0x40>; + riscv,cbop-block-size = <0x40>; + i-cache-block-size = <0x40>; + i-cache-size = <0x10000>; + i-cache-sets = <0x100>; + d-cache-block-size = <0x40>; + d-cache-size = <0x10000>; + d-cache-sets = <0x100>; + next-level-cache = <0x01>; + cpu-idle-states = <0x02 0x03>; + mmu-type = "riscv,sv39"; + #cooling-cells = <0x02>; + clst-supply = <0x04>; + clocks = <0x05 0x04 0x05 0x05>; + clock-names = "cls0\0cls1"; + operating-points-v2 = <0x06>; + phandle = <0x0d>; + + interrupt-controller { + #interrupt-cells = <0x01>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + phandle = <0x6b>; + }; + + debug { + compatible = "riscv,debug-v1.0.0"; + + trigger-module { + mcontext-present; + hcontext-present; + scontext-present; + }; + }; + }; + + cpu@3 { + device_type = "cpu"; + reg = <0x03>; + model = "Spacemit(R) X100"; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdcvh"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i\0m\0a\0f\0d\0c\0v\0h\0smaia\0smstateen\0ssaia\0sscofpmf\0sstc\0svinval\0svnapot\0svpbmt\0zawrs\0zba\0zbb\0zbc\0zbs\0zcb\0zca\0zcmop\0zfa\0zfh\0zfhmin\0zkt\0zicbom\0zicbop\0zicboz\0zicntr\0zicond\0zicsr\0zifencei\0zihintpause\0zihintntl\0zihpm\0zimop\0zvbb\0zvbc\0zvfh\0zvfhmin\0zvkb\0zvkg\0zvkn\0zvknc\0zvkned\0zvkng\0zvknha\0zvknhb\0zvks\0zvksc\0zvksed\0zvksh\0zvksg\0zvkt\0zcd\0sdtrig"; + riscv,cbom-block-size = <0x40>; + riscv,cboz-block-size = <0x40>; + riscv,cbop-block-size = <0x40>; + i-cache-block-size = <0x40>; + i-cache-size = <0x10000>; + i-cache-sets = <0x100>; + d-cache-block-size = <0x40>; + d-cache-size = <0x10000>; + d-cache-sets = <0x100>; + next-level-cache = <0x01>; + cpu-idle-states = <0x02 0x03>; + mmu-type = "riscv,sv39"; + #cooling-cells = <0x02>; + clst-supply = <0x04>; + clocks = <0x05 0x04 0x05 0x05>; + clock-names = "cls0\0cls1"; + operating-points-v2 = <0x06>; + phandle = <0x0e>; + + interrupt-controller { + #interrupt-cells = <0x01>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + phandle = <0x6c>; + }; + + debug { + compatible = "riscv,debug-v1.0.0"; + + trigger-module { + mcontext-present; + hcontext-present; + scontext-present; + }; + }; + }; + + cpu@4 { + device_type = "cpu"; + reg = <0x04>; + model = "Spacemit(R) X100"; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdcvh"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i\0m\0a\0f\0d\0c\0v\0h\0smaia\0smstateen\0ssaia\0sscofpmf\0sstc\0svinval\0svnapot\0svpbmt\0zawrs\0zba\0zbb\0zbc\0zbs\0zcb\0zca\0zcmop\0zfa\0zfh\0zfhmin\0zkt\0zicbom\0zicbop\0zicboz\0zicntr\0zicond\0zicsr\0zifencei\0zihintpause\0zihintntl\0zihpm\0zimop\0zvbb\0zvbc\0zvfh\0zvfhmin\0zvkb\0zvkg\0zvkn\0zvknc\0zvkned\0zvkng\0zvknha\0zvknhb\0zvks\0zvksc\0zvksed\0zvksh\0zvksg\0zvkt\0zcd\0sdtrig"; + riscv,cbom-block-size = <0x40>; + riscv,cboz-block-size = <0x40>; + riscv,cbop-block-size = <0x40>; + i-cache-block-size = <0x40>; + i-cache-size = <0x10000>; + i-cache-sets = <0x100>; + d-cache-block-size = <0x40>; + d-cache-size = <0x10000>; + d-cache-sets = <0x100>; + next-level-cache = <0x07>; + cpu-idle-states = <0x02 0x03>; + mmu-type = "riscv,sv39"; + #cooling-cells = <0x02>; + clst-supply = <0x04>; + clocks = <0x05 0x04 0x05 0x05>; + clock-names = "cls0\0cls1"; + operating-points-v2 = <0x06>; + phandle = <0x0f>; + + interrupt-controller { + #interrupt-cells = <0x01>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + phandle = <0x6d>; + }; + + debug { + compatible = "riscv,debug-v1.0.0"; + + trigger-module { + mcontext-present; + hcontext-present; + scontext-present; + }; + }; + }; + + cpu@5 { + device_type = "cpu"; + reg = <0x05>; + model = "Spacemit(R) X100"; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdcvh"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i\0m\0a\0f\0d\0c\0v\0h\0smaia\0smstateen\0ssaia\0sscofpmf\0sstc\0svinval\0svnapot\0svpbmt\0zawrs\0zba\0zbb\0zbc\0zbs\0zcb\0zca\0zcmop\0zfa\0zfh\0zfhmin\0zkt\0zicbom\0zicbop\0zicboz\0zicntr\0zicond\0zicsr\0zifencei\0zihintpause\0zihintntl\0zihpm\0zimop\0zvbb\0zvbc\0zvfh\0zvfhmin\0zvkb\0zvkg\0zvkn\0zvknc\0zvkned\0zvkng\0zvknha\0zvknhb\0zvks\0zvksc\0zvksed\0zvksh\0zvksg\0zvkt\0zcd\0sdtrig"; + riscv,cbom-block-size = <0x40>; + riscv,cboz-block-size = <0x40>; + riscv,cbop-block-size = <0x40>; + i-cache-block-size = <0x40>; + i-cache-size = <0x10000>; + i-cache-sets = <0x100>; + d-cache-block-size = <0x40>; + d-cache-size = <0x10000>; + d-cache-sets = <0x100>; + next-level-cache = <0x07>; + cpu-idle-states = <0x02 0x03>; + mmu-type = "riscv,sv39"; + #cooling-cells = <0x02>; + clst-supply = <0x04>; + clocks = <0x05 0x04 0x05 0x05>; + clock-names = "cls0\0cls1"; + operating-points-v2 = <0x06>; + phandle = <0x10>; + + interrupt-controller { + #interrupt-cells = <0x01>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + phandle = <0x6e>; + }; + + debug { + compatible = "riscv,debug-v1.0.0"; + + trigger-module { + mcontext-present; + hcontext-present; + scontext-present; + }; + }; + }; + + cpu@6 { + device_type = "cpu"; + reg = <0x06>; + model = "Spacemit(R) X100"; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdcvh"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i\0m\0a\0f\0d\0c\0v\0h\0smaia\0smstateen\0ssaia\0sscofpmf\0sstc\0svinval\0svnapot\0svpbmt\0zawrs\0zba\0zbb\0zbc\0zbs\0zcb\0zca\0zcmop\0zfa\0zfh\0zfhmin\0zkt\0zicbom\0zicbop\0zicboz\0zicntr\0zicond\0zicsr\0zifencei\0zihintpause\0zihintntl\0zihpm\0zimop\0zvbb\0zvbc\0zvfh\0zvfhmin\0zvkb\0zvkg\0zvkn\0zvknc\0zvkned\0zvkng\0zvknha\0zvknhb\0zvks\0zvksc\0zvksed\0zvksh\0zvksg\0zvkt\0zcd\0sdtrig"; + riscv,cbom-block-size = <0x40>; + riscv,cboz-block-size = <0x40>; + riscv,cbop-block-size = <0x40>; + i-cache-block-size = <0x40>; + i-cache-size = <0x10000>; + i-cache-sets = <0x100>; + d-cache-block-size = <0x40>; + d-cache-size = <0x10000>; + d-cache-sets = <0x100>; + next-level-cache = <0x07>; + cpu-idle-states = <0x02 0x03>; + mmu-type = "riscv,sv39"; + #cooling-cells = <0x02>; + clst-supply = <0x04>; + clocks = <0x05 0x04 0x05 0x05>; + clock-names = "cls0\0cls1"; + operating-points-v2 = <0x06>; + phandle = <0x11>; + + interrupt-controller { + #interrupt-cells = <0x01>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + phandle = <0x6f>; + }; + + debug { + compatible = "riscv,debug-v1.0.0"; + + trigger-module { + mcontext-present; + hcontext-present; + scontext-present; + }; + }; + }; + + cpu@7 { + device_type = "cpu"; + reg = <0x07>; + model = "Spacemit(R) X100"; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdcvh"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i\0m\0a\0f\0d\0c\0v\0h\0smaia\0smstateen\0ssaia\0sscofpmf\0sstc\0svinval\0svnapot\0svpbmt\0zawrs\0zba\0zbb\0zbc\0zbs\0zcb\0zca\0zcmop\0zfa\0zfh\0zfhmin\0zkt\0zicbom\0zicbop\0zicboz\0zicntr\0zicond\0zicsr\0zifencei\0zihintpause\0zihintntl\0zihpm\0zimop\0zvbb\0zvbc\0zvfh\0zvfhmin\0zvkb\0zvkg\0zvkn\0zvknc\0zvkned\0zvkng\0zvknha\0zvknhb\0zvks\0zvksc\0zvksed\0zvksh\0zvksg\0zvkt\0zcd\0sdtrig"; + riscv,cbom-block-size = <0x40>; + riscv,cboz-block-size = <0x40>; + riscv,cbop-block-size = <0x40>; + i-cache-block-size = <0x40>; + i-cache-size = <0x10000>; + i-cache-sets = <0x100>; + d-cache-block-size = <0x40>; + d-cache-size = <0x10000>; + d-cache-sets = <0x100>; + next-level-cache = <0x07>; + cpu-idle-states = <0x02 0x03>; + mmu-type = "riscv,sv39"; + #cooling-cells = <0x02>; + clst-supply = <0x04>; + clocks = <0x05 0x04 0x05 0x05>; + clock-names = "cls0\0cls1"; + operating-points-v2 = <0x06>; + phandle = <0x12>; + + interrupt-controller { + #interrupt-cells = <0x01>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + phandle = <0x70>; + }; + + debug { + compatible = "riscv,debug-v1.0.0"; + + trigger-module { + mcontext-present; + hcontext-present; + scontext-present; + }; + }; + }; + + cpu@8 { + device_type = "cpu"; + reg = <0x08>; + model = "Spacemit(R) A100"; + status = "okay"; + compatible = "riscv"; + cpu-ai = "true"; + riscv,isa = "rv64imafdcv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i\0m\0a\0f\0d\0c\0v\0smaia\0smstateen\0ssaia\0sscofpmf\0sstc\0svinval\0svnapot\0svpbmt\0zawrs\0zba\0zbb\0zbc\0zbs\0zcb\0zca\0zcmop\0zfa\0zfh\0zfhmin\0zkt\0zicbom\0zicbop\0zicboz\0zicntr\0zicond\0zicsr\0zifencei\0zihintpause\0zihintntl\0zihpm\0zimop\0zvbb\0zvbc\0zvfh\0zvfhmin\0zvkb\0zvkg\0zvkn\0zvknc\0zvkned\0zvkng\0zvknha\0zvknhb\0zvks\0zvksc\0zvksed\0zvksh\0zvksg\0zvkt\0zcd\0sdtrig"; + riscv,cbom-block-size = <0x40>; + riscv,cboz-block-size = <0x40>; + riscv,cbop-block-size = <0x40>; + i-cache-block-size = <0x40>; + i-cache-size = <0x10000>; + i-cache-sets = <0x100>; + d-cache-block-size = <0x40>; + d-cache-size = <0x10000>; + d-cache-sets = <0x100>; + next-level-cache = <0x08>; + cpu-idle-states = <0x02 0x03>; + mmu-type = "riscv,sv39"; + #cooling-cells = <0x02>; + clocks = <0x05 0x06 0x05 0x07>; + clock-names = "cls0\0cls1"; + operating-points-v2 = <0x09>; + phandle = <0x13>; + + interrupt-controller { + #interrupt-cells = <0x01>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + phandle = <0x71>; + }; + + debug { + compatible = "riscv,debug-v1.0.0"; + + trigger-module { + mcontext-present; + hcontext-present; + scontext-present; + }; + }; + }; + + cpu@9 { + device_type = "cpu"; + reg = <0x09>; + model = "Spacemit(R) A100"; + status = "okay"; + compatible = "riscv"; + cpu-ai = "true"; + riscv,isa = "rv64imafdcv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i\0m\0a\0f\0d\0c\0v\0smaia\0smstateen\0ssaia\0sscofpmf\0sstc\0svinval\0svnapot\0svpbmt\0zawrs\0zba\0zbb\0zbc\0zbs\0zcb\0zca\0zcmop\0zfa\0zfh\0zfhmin\0zkt\0zicbom\0zicbop\0zicboz\0zicntr\0zicond\0zicsr\0zifencei\0zihintpause\0zihintntl\0zihpm\0zimop\0zvbb\0zvbc\0zvfh\0zvfhmin\0zvkb\0zvkg\0zvkn\0zvknc\0zvkned\0zvkng\0zvknha\0zvknhb\0zvks\0zvksc\0zvksed\0zvksh\0zvksg\0zvkt\0zcd\0sdtrig"; + riscv,cbom-block-size = <0x40>; + riscv,cboz-block-size = <0x40>; + riscv,cbop-block-size = <0x40>; + i-cache-block-size = <0x40>; + i-cache-size = <0x10000>; + i-cache-sets = <0x100>; + d-cache-block-size = <0x40>; + d-cache-size = <0x10000>; + d-cache-sets = <0x100>; + next-level-cache = <0x08>; + cpu-idle-states = <0x02 0x03>; + mmu-type = "riscv,sv39"; + #cooling-cells = <0x02>; + clocks = <0x05 0x06 0x05 0x07>; + clock-names = "cls0\0cls1"; + operating-points-v2 = <0x09>; + phandle = <0x14>; + + interrupt-controller { + #interrupt-cells = <0x01>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + phandle = <0x72>; + }; + + debug { + compatible = "riscv,debug-v1.0.0"; + + trigger-module { + mcontext-present; + hcontext-present; + scontext-present; + }; + }; + }; + + cpu@10 { + device_type = "cpu"; + reg = <0x0a>; + model = "Spacemit(R) A100"; + status = "okay"; + compatible = "riscv"; + cpu-ai = "true"; + riscv,isa = "rv64imafdcv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i\0m\0a\0f\0d\0c\0v\0smaia\0smstateen\0ssaia\0sscofpmf\0sstc\0svinval\0svnapot\0svpbmt\0zawrs\0zba\0zbb\0zbc\0zbs\0zcb\0zca\0zcmop\0zfa\0zfh\0zfhmin\0zkt\0zicbom\0zicbop\0zicboz\0zicntr\0zicond\0zicsr\0zifencei\0zihintpause\0zihintntl\0zihpm\0zimop\0zvbb\0zvbc\0zvfh\0zvfhmin\0zvkb\0zvkg\0zvkn\0zvknc\0zvkned\0zvkng\0zvknha\0zvknhb\0zvks\0zvksc\0zvksed\0zvksh\0zvksg\0zvkt\0zcd\0sdtrig"; + riscv,cbom-block-size = <0x40>; + riscv,cboz-block-size = <0x40>; + riscv,cbop-block-size = <0x40>; + i-cache-block-size = <0x40>; + i-cache-size = <0x10000>; + i-cache-sets = <0x100>; + d-cache-block-size = <0x40>; + d-cache-size = <0x10000>; + d-cache-sets = <0x100>; + next-level-cache = <0x08>; + cpu-idle-states = <0x02 0x03>; + mmu-type = "riscv,sv39"; + #cooling-cells = <0x02>; + clocks = <0x05 0x06 0x05 0x07>; + clock-names = "cls0\0cls1"; + operating-points-v2 = <0x09>; + phandle = <0x15>; + + interrupt-controller { + #interrupt-cells = <0x01>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + phandle = <0x73>; + }; + + debug { + compatible = "riscv,debug-v1.0.0"; + + trigger-module { + mcontext-present; + hcontext-present; + scontext-present; + }; + }; + }; + + cpu@11 { + device_type = "cpu"; + reg = <0x0b>; + model = "Spacemit(R) A100"; + status = "okay"; + compatible = "riscv"; + cpu-ai = "true"; + riscv,isa = "rv64imafdcv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i\0m\0a\0f\0d\0c\0v\0smaia\0smstateen\0ssaia\0sscofpmf\0sstc\0svinval\0svnapot\0svpbmt\0zawrs\0zba\0zbb\0zbc\0zbs\0zcb\0zca\0zcmop\0zfa\0zfh\0zfhmin\0zkt\0zicbom\0zicbop\0zicboz\0zicntr\0zicond\0zicsr\0zifencei\0zihintpause\0zihintntl\0zihpm\0zimop\0zvbb\0zvbc\0zvfh\0zvfhmin\0zvkb\0zvkg\0zvkn\0zvknc\0zvkned\0zvkng\0zvknha\0zvknhb\0zvks\0zvksc\0zvksed\0zvksh\0zvksg\0zvkt\0zcd\0sdtrig"; + riscv,cbom-block-size = <0x40>; + riscv,cboz-block-size = <0x40>; + riscv,cbop-block-size = <0x40>; + i-cache-block-size = <0x40>; + i-cache-size = <0x10000>; + i-cache-sets = <0x100>; + d-cache-block-size = <0x40>; + d-cache-size = <0x10000>; + d-cache-sets = <0x100>; + next-level-cache = <0x08>; + cpu-idle-states = <0x02 0x03>; + mmu-type = "riscv,sv39"; + #cooling-cells = <0x02>; + clocks = <0x05 0x06 0x05 0x07>; + clock-names = "cls0\0cls1"; + operating-points-v2 = <0x09>; + phandle = <0x16>; + + interrupt-controller { + #interrupt-cells = <0x01>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + phandle = <0x74>; + }; + + debug { + compatible = "riscv,debug-v1.0.0"; + + trigger-module { + mcontext-present; + hcontext-present; + scontext-present; + }; + }; + }; + + cpu@12 { + device_type = "cpu"; + reg = <0x0c>; + model = "Spacemit(R) A100"; + status = "okay"; + compatible = "riscv"; + cpu-ai = "true"; + riscv,isa = "rv64imafdcv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i\0m\0a\0f\0d\0c\0v\0smaia\0smstateen\0ssaia\0sscofpmf\0sstc\0svinval\0svnapot\0svpbmt\0zawrs\0zba\0zbb\0zbc\0zbs\0zcb\0zca\0zcmop\0zfa\0zfh\0zfhmin\0zkt\0zicbom\0zicbop\0zicboz\0zicntr\0zicond\0zicsr\0zifencei\0zihintpause\0zihintntl\0zihpm\0zimop\0zvbb\0zvbc\0zvfh\0zvfhmin\0zvkb\0zvkg\0zvkn\0zvknc\0zvkned\0zvkng\0zvknha\0zvknhb\0zvks\0zvksc\0zvksed\0zvksh\0zvksg\0zvkt\0zcd\0sdtrig"; + riscv,cbom-block-size = <0x40>; + riscv,cboz-block-size = <0x40>; + riscv,cbop-block-size = <0x40>; + i-cache-block-size = <0x40>; + i-cache-size = <0x10000>; + i-cache-sets = <0x100>; + d-cache-block-size = <0x40>; + d-cache-size = <0x10000>; + d-cache-sets = <0x100>; + next-level-cache = <0x0a>; + cpu-idle-states = <0x02 0x03>; + mmu-type = "riscv,sv39"; + #cooling-cells = <0x02>; + clocks = <0x05 0x06 0x05 0x07>; + clock-names = "cls0\0cls1"; + operating-points-v2 = <0x09>; + phandle = <0x17>; + + interrupt-controller { + #interrupt-cells = <0x01>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + phandle = <0x75>; + }; + + debug { + compatible = "riscv,debug-v1.0.0"; + + trigger-module { + mcontext-present; + hcontext-present; + scontext-present; + }; + }; + }; + + cpu@13 { + device_type = "cpu"; + reg = <0x0d>; + model = "Spacemit(R) A100"; + status = "okay"; + compatible = "riscv"; + cpu-ai = "true"; + riscv,isa = "rv64imafdcv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i\0m\0a\0f\0d\0c\0v\0smaia\0smstateen\0ssaia\0sscofpmf\0sstc\0svinval\0svnapot\0svpbmt\0zawrs\0zba\0zbb\0zbc\0zbs\0zcb\0zca\0zcmop\0zfa\0zfh\0zfhmin\0zkt\0zicbom\0zicbop\0zicboz\0zicntr\0zicond\0zicsr\0zifencei\0zihintpause\0zihintntl\0zihpm\0zimop\0zvbb\0zvbc\0zvfh\0zvfhmin\0zvkb\0zvkg\0zvkn\0zvknc\0zvkned\0zvkng\0zvknha\0zvknhb\0zvks\0zvksc\0zvksed\0zvksh\0zvksg\0zvkt\0zcd\0sdtrig"; + riscv,cbom-block-size = <0x40>; + riscv,cboz-block-size = <0x40>; + riscv,cbop-block-size = <0x40>; + i-cache-block-size = <0x40>; + i-cache-size = <0x10000>; + i-cache-sets = <0x100>; + d-cache-block-size = <0x40>; + d-cache-size = <0x10000>; + d-cache-sets = <0x100>; + next-level-cache = <0x0a>; + cpu-idle-states = <0x02 0x03>; + mmu-type = "riscv,sv39"; + #cooling-cells = <0x02>; + clocks = <0x05 0x06 0x05 0x07>; + clock-names = "cls0\0cls1"; + operating-points-v2 = <0x09>; + phandle = <0x18>; + + interrupt-controller { + #interrupt-cells = <0x01>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + phandle = <0x76>; + }; + + debug { + compatible = "riscv,debug-v1.0.0"; + + trigger-module { + mcontext-present; + hcontext-present; + scontext-present; + }; + }; + }; + + cpu@14 { + device_type = "cpu"; + reg = <0x0e>; + model = "Spacemit(R) A100"; + status = "okay"; + compatible = "riscv"; + cpu-ai = "true"; + riscv,isa = "rv64imafdcv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i\0m\0a\0f\0d\0c\0v\0smaia\0smstateen\0ssaia\0sscofpmf\0sstc\0svinval\0svnapot\0svpbmt\0zawrs\0zba\0zbb\0zbc\0zbs\0zcb\0zca\0zcmop\0zfa\0zfh\0zfhmin\0zkt\0zicbom\0zicbop\0zicboz\0zicntr\0zicond\0zicsr\0zifencei\0zihintpause\0zihintntl\0zihpm\0zimop\0zvbb\0zvbc\0zvfh\0zvfhmin\0zvkb\0zvkg\0zvkn\0zvknc\0zvkned\0zvkng\0zvknha\0zvknhb\0zvks\0zvksc\0zvksed\0zvksh\0zvksg\0zvkt\0zcd\0sdtrig"; + riscv,cbom-block-size = <0x40>; + riscv,cboz-block-size = <0x40>; + riscv,cbop-block-size = <0x40>; + i-cache-block-size = <0x40>; + i-cache-size = <0x10000>; + i-cache-sets = <0x100>; + d-cache-block-size = <0x40>; + d-cache-size = <0x10000>; + d-cache-sets = <0x100>; + next-level-cache = <0x0a>; + cpu-idle-states = <0x02 0x03>; + mmu-type = "riscv,sv39"; + #cooling-cells = <0x02>; + clocks = <0x05 0x06 0x05 0x07>; + clock-names = "cls0\0cls1"; + operating-points-v2 = <0x09>; + phandle = <0x19>; + + interrupt-controller { + #interrupt-cells = <0x01>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + phandle = <0x77>; + }; + + debug { + compatible = "riscv,debug-v1.0.0"; + + trigger-module { + mcontext-present; + hcontext-present; + scontext-present; + }; + }; + }; + + cpu@15 { + device_type = "cpu"; + reg = <0x0f>; + model = "Spacemit(R) A100"; + status = "okay"; + compatible = "riscv"; + cpu-ai = "true"; + riscv,isa = "rv64imafdcv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i\0m\0a\0f\0d\0c\0v\0smaia\0smstateen\0ssaia\0sscofpmf\0sstc\0svinval\0svnapot\0svpbmt\0zawrs\0zba\0zbb\0zbc\0zbs\0zcb\0zca\0zcmop\0zfa\0zfh\0zfhmin\0zkt\0zicbom\0zicbop\0zicboz\0zicntr\0zicond\0zicsr\0zifencei\0zihintpause\0zihintntl\0zihpm\0zimop\0zvbb\0zvbc\0zvfh\0zvfhmin\0zvkb\0zvkg\0zvkn\0zvknc\0zvkned\0zvkng\0zvknha\0zvknhb\0zvks\0zvksc\0zvksed\0zvksh\0zvksg\0zvkt\0zcd\0sdtrig"; + riscv,cbom-block-size = <0x40>; + riscv,cboz-block-size = <0x40>; + riscv,cbop-block-size = <0x40>; + i-cache-block-size = <0x40>; + i-cache-size = <0x10000>; + i-cache-sets = <0x100>; + d-cache-block-size = <0x40>; + d-cache-size = <0x10000>; + d-cache-sets = <0x100>; + next-level-cache = <0x0a>; + cpu-idle-states = <0x02 0x03>; + mmu-type = "riscv,sv39"; + #cooling-cells = <0x02>; + clocks = <0x05 0x06 0x05 0x07>; + clock-names = "cls0\0cls1"; + operating-points-v2 = <0x09>; + phandle = <0x1a>; + + interrupt-controller { + #interrupt-cells = <0x01>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + phandle = <0x78>; + }; + + debug { + compatible = "riscv,debug-v1.0.0"; + + trigger-module { + mcontext-present; + hcontext-present; + scontext-present; + }; + }; + }; + + l2-cache1 { + compatible = "cache"; + cache-block-size = <0x40>; + cache-level = <0x02>; + cache-size = <0x400000>; + cache-sets = <0x1000>; + cache-unified; + phandle = <0x01>; + }; + + l2-cache2 { + compatible = "cache"; + cache-block-size = <0x40>; + cache-level = <0x02>; + cache-size = <0x400000>; + cache-sets = <0x1000>; + cache-unified; + phandle = <0x07>; + }; + + l2-cache3 { + compatible = "cache"; + cache-block-size = <0x40>; + cache-level = <0x02>; + cache-size = <0x100000>; + cache-sets = <0x400>; + cache-unified; + phandle = <0x08>; + }; + + l2-cache4 { + compatible = "cache"; + cache-block-size = <0x40>; + cache-level = <0x02>; + cache-size = <0x100000>; + cache-sets = <0x400>; + cache-unified; + phandle = <0x0a>; + }; + + cpu-map { + + cluster0 { + + core0 { + cpu = <0x0b>; + }; + + core1 { + cpu = <0x0c>; + }; + + core2 { + cpu = <0x0d>; + }; + + core3 { + cpu = <0x0e>; + }; + }; + + cluster1 { + + core0 { + cpu = <0x0f>; + }; + + core1 { + cpu = <0x10>; + }; + + core2 { + cpu = <0x11>; + }; + + core3 { + cpu = <0x12>; + }; + }; + + cluster2 { + + core0 { + cpu = <0x13>; + }; + + core1 { + cpu = <0x14>; + }; + + core2 { + cpu = <0x15>; + }; + + core3 { + cpu = <0x16>; + }; + }; + + cluster3 { + + core0 { + cpu = <0x17>; + }; + + core1 { + cpu = <0x18>; + }; + + core2 { + cpu = <0x19>; + }; + + core3 { + cpu = <0x1a>; + }; + }; + }; + + opp_table0_x100 { + compatible = "operating-points-v2"; + opp-shared; + clocks = <0x1b 0x02 0x1b 0x03 0x1b 0x22 0x05 0x02>; + clock-names = "pll_clst0\0pll_clst1\0pll_src\0clt_pll_src"; + phandle = <0x06>; + + opp2400000000 { + opp-hz = <0x00 0x8f0d1800 0x00 0x8f0d1800>; + opp-microvolt = <0xf4240 0xf4240 0xf51e0>; + clock-latency-ns = <0x30d40>; + }; + + opp2300000000 { + opp-hz = <0x00 0x89173700 0x00 0x89173700>; + opp-microvolt = <0xd6d80 0xd6d80 0xd7d20>; + clock-latency-ns = <0x30d40>; + }; + + opp2200000000 { + opp-hz = <0x00 0x83215600 0x00 0x83215600>; + opp-microvolt = <0xd6d80 0xd6d80 0xd7d20>; + clock-latency-ns = <0x30d40>; + }; + + opp2150000000 { + opp-hz = <0x00 0x80266580 0x00 0x80266580>; + opp-microvolt = <0xd6d80 0xd6d80 0xd7d20>; + clock-latency-ns = <0x30d40>; + }; + + opp2100000000 { + opp-hz = <0x00 0x7d2b7500 0x00 0x7d2b7500>; + opp-microvolt = <0xd6d80 0xd6d80 0xd7d20>; + clock-latency-ns = <0x30d40>; + }; + + opp2000000000 { + opp-hz = <0x00 0x77359400 0x00 0x77359400>; + opp-microvolt = <0xd6d80 0xd6d80 0xd7d20>; + clock-latency-ns = <0x30d40>; + }; + + opp1900000000 { + opp-hz = <0x00 0x713fb300 0x00 0x713fb300>; + opp-microvolt = <0xd6d80 0xd6d80 0xd7d20>; + clock-latency-ns = <0x30d40>; + }; + + opp1850000000 { + opp-hz = <0x00 0x6e44c280 0x00 0x6e44c280>; + opp-microvolt = <0xd6d80 0xd6d80 0xd7d20>; + clock-latency-ns = <0x30d40>; + }; + + opp1800000000 { + opp-hz = <0x00 0x6b49d200 0x00 0x6b49d200>; + opp-microvolt = <0xd6d80 0xd6d80 0xd7d20>; + clock-latency-ns = <0x30d40>; + }; + + opp1700000000 { + opp-hz = <0x00 0x6553f100 0x00 0x6553f100>; + opp-microvolt = <0xd6d80 0xd6d80 0xd7d20>; + clock-latency-ns = <0x30d40>; + }; + + opp1600000000 { + opp-hz = <0x00 0x5f5e1000 0x00 0x5f5e1000>; + opp-microvolt = <0xd6d80 0xd6d80 0xd7d20>; + clock-latency-ns = <0x30d40>; + }; + + opp1500000000 { + opp-hz = <0x00 0x59682f00 0x00 0x59682f00>; + opp-microvolt = <0xcf850 0xcf850 0xd07f0>; + clock-latency-ns = <0x30d40>; + }; + + opp1400000000 { + opp-hz = <0x00 0x53724e00 0x00 0x53724e00>; + opp-microvolt = <0xcf850 0xcf850 0xd07f0>; + clock-latency-ns = <0x30d40>; + }; + + opp1300000000 { + opp-hz = <0x00 0x4d7c6d00 0x00 0x4d7c6d00>; + opp-microvolt = <0xcf850 0xcf850 0xd07f0>; + clock-latency-ns = <0x30d40>; + }; + + opp1200000000 { + opp-hz = <0x00 0x47868c00 0x00 0x47868c00>; + opp-microvolt = <0xcf850 0xcf850 0xd07f0>; + clock-latency-ns = <0x30d40>; + }; + + opp1100000000 { + opp-hz = <0x00 0x4190ab00 0x00 0x4190ab00>; + opp-microvolt = <0xcf850 0xcf850 0xd07f0>; + clock-latency-ns = <0x30d40>; + }; + + opp1000000000 { + opp-hz = <0x00 0x3b9aca00 0x00 0x3b9aca00>; + opp-microvolt = <0xc3500 0xc3500 0xc44a0>; + clock-latency-ns = <0x30d40>; + }; + + opp819000000 { + opp-hz = <0x00 0x30d40000 0x00 0x30d40000>; + opp-microvolt = <0xc3500 0xc3500 0xc44a0>; + clock-latency-ns = <0x30d40>; + }; + + opp614400000 { + opp-hz = <0x00 0x249f0000 0x00 0x249f0000>; + opp-microvolt = <0xc3500 0xc3500 0xc44a0>; + clock-latency-ns = <0x30d40>; + }; + }; + + opp_table0_a100 { + compatible = "operating-points-v2"; + opp-shared; + clocks = <0x1b 0x04 0x1b 0x07 0x1b 0x32 0x05 0x03>; + clock-names = "pll_clst0\0pll_clst1\0pll_src\0clt_pll_src"; + phandle = <0x09>; + + opp2000000000 { + opp-hz = <0x00 0x77359400 0x00 0x77359400>; + clock-latency-ns = <0x30d40>; + }; + + opp1900000000 { + opp-hz = <0x00 0x713fb300 0x00 0x713fb300>; + clock-latency-ns = <0x30d40>; + }; + + opp1850000000 { + opp-hz = <0x00 0x6e44c280 0x00 0x6e44c280>; + clock-latency-ns = <0x30d40>; + }; + + opp1800000000 { + opp-hz = <0x00 0x6b49d200 0x00 0x6b49d200>; + clock-latency-ns = <0x30d40>; + }; + + opp1700000000 { + opp-hz = <0x00 0x6553f100 0x00 0x6553f100>; + clock-latency-ns = <0x30d40>; + }; + + opp1600000000 { + opp-hz = <0x00 0x5f5e1000 0x00 0x5f5e1000>; + clock-latency-ns = <0x30d40>; + }; + + opp1500000000 { + opp-hz = <0x00 0x59682f00 0x00 0x59682f00>; + clock-latency-ns = <0x30d40>; + }; + + opp1400000000 { + opp-hz = <0x00 0x53724e00 0x00 0x53724e00>; + clock-latency-ns = <0x30d40>; + }; + + opp1300000000 { + opp-hz = <0x00 0x4d7c6d00 0x00 0x4d7c6d00>; + clock-latency-ns = <0x30d40>; + }; + + opp1200000000 { + opp-hz = <0x00 0x47868c00 0x00 0x47868c00>; + clock-latency-ns = <0x30d40>; + }; + + opp1100000000 { + opp-hz = <0x00 0x4190ab00 0x00 0x4190ab00>; + clock-latency-ns = <0x30d40>; + }; + + opp1000000000 { + opp-hz = <0x00 0x3b9aca00 0x00 0x3b9aca00>; + clock-latency-ns = <0x30d40>; + }; + + opp819000000 { + opp-hz = <0x00 0x30d40000 0x00 0x30d40000>; + clock-latency-ns = <0x30d40>; + }; + + opp614400000 { + opp-hz = <0x00 0x249f0000 0x00 0x249f0000>; + clock-latency-ns = <0x30d40>; + }; + }; + }; + + riscv-timer { + compatible = "riscv,timer"; + riscv,timer-cannot-wake-cpu; + }; + + idle-states { + + cpu-nonret { + compatible = "riscv,idle-state"; + idle-state-name = "riscv,cpu-nonret"; + riscv,sbi-suspend-param = <0x90000000>; + local-timer-stop; + entry-latency-us = <0xc8>; + exit-latency-us = <0x1f4>; + min-residency-us = <0x3b6>; + phandle = <0x02>; + }; + + cluster-nonret { + compatible = "riscv,idle-state"; + idle-state-name = "riscv,cluster-nonret"; + riscv,sbi-suspend-param = <0x91000000>; + local-timer-stop; + entry-latency-us = <0x258>; + exit-latency-us = <0x44c>; + min-residency-us = <0xa8c>; + wakeup-latency-us = <0x5dc>; + phandle = <0x03>; + }; + }; + + soc { + #address-cells = <0x02>; + #size-cells = <0x02>; + compatible = "simple-bus"; + dma-noncoherent; + ranges; + + encoder@d9002000 { + compatible = "riscv,trace-encoder"; + reg = <0x00 0xd9002000 0x00 0x1000>; + cpus = <0x0b>; + + out-ports { + + port { + + endpoint { + remote-endpoint = <0x1c>; + phandle = <0x1e>; + }; + }; + }; + }; + + bridge@d9003000 { + compatible = "riscv,trace-atbbridge"; + reg = <0x00 0xd9003000 0x00 0x1000>; + cpus = <0x0b>; + + out-ports { + + port { + + endpoint { + remote-endpoint = <0x1d>; + phandle = <0x4d>; + }; + }; + }; + + in-ports { + + port { + + endpoint { + remote-endpoint = <0x1e>; + phandle = <0x1c>; + }; + }; + }; + }; + + encoder@d9004000 { + compatible = "riscv,trace-encoder"; + reg = <0x00 0xd9004000 0x00 0x1000>; + cpus = <0x0c>; + + out-ports { + + port { + + endpoint { + remote-endpoint = <0x1f>; + phandle = <0x21>; + }; + }; + }; + }; + + bridge@d9005000 { + compatible = "riscv,trace-atbbridge"; + reg = <0x00 0xd9005000 0x00 0x1000>; + cpus = <0x0c>; + + out-ports { + + port { + + endpoint { + remote-endpoint = <0x20>; + phandle = <0x4e>; + }; + }; + }; + + in-ports { + + port { + + endpoint { + remote-endpoint = <0x21>; + phandle = <0x1f>; + }; + }; + }; + }; + + encoder@d9006000 { + compatible = "riscv,trace-encoder"; + reg = <0x00 0xd9006000 0x00 0x1000>; + cpus = <0x0d>; + + out-ports { + + port { + + endpoint { + remote-endpoint = <0x22>; + phandle = <0x24>; + }; + }; + }; + }; + + bridge@d9007000 { + compatible = "riscv,trace-atbbridge"; + reg = <0x00 0xd9007000 0x00 0x1000>; + cpus = <0x0d>; + + out-ports { + + port { + + endpoint { + remote-endpoint = <0x23>; + phandle = <0x4f>; + }; + }; + }; + + in-ports { + + port { + + endpoint { + remote-endpoint = <0x24>; + phandle = <0x22>; + }; + }; + }; + }; + + encoder@d9008000 { + compatible = "riscv,trace-encoder"; + reg = <0x00 0xd9008000 0x00 0x1000>; + cpus = <0x0e>; + + out-ports { + + port { + + endpoint { + remote-endpoint = <0x25>; + phandle = <0x27>; + }; + }; + }; + }; + + bridge@d9009000 { + compatible = "riscv,trace-atbbridge"; + reg = <0x00 0xd9009000 0x00 0x1000>; + cpus = <0x0e>; + + out-ports { + + port { + + endpoint { + remote-endpoint = <0x26>; + phandle = <0x50>; + }; + }; + }; + + in-ports { + + port { + + endpoint { + remote-endpoint = <0x27>; + phandle = <0x25>; + }; + }; + }; + }; + + encoder@d9012000 { + compatible = "riscv,trace-encoder"; + reg = <0x00 0xd9012000 0x00 0x1000>; + cpus = <0x0f>; + + out-ports { + + port { + + endpoint { + remote-endpoint = <0x28>; + phandle = <0x2a>; + }; + }; + }; + }; + + bridge@d9013000 { + compatible = "riscv,trace-atbbridge"; + reg = <0x00 0xd9013000 0x00 0x1000>; + cpus = <0x0f>; + + out-ports { + + port { + + endpoint { + remote-endpoint = <0x29>; + phandle = <0x52>; + }; + }; + }; + + in-ports { + + port { + + endpoint { + remote-endpoint = <0x2a>; + phandle = <0x28>; + }; + }; + }; + }; + + encoder@d9014000 { + compatible = "riscv,trace-encoder"; + reg = <0x00 0xd9014000 0x00 0x1000>; + cpus = <0x10>; + + out-ports { + + port { + + endpoint { + remote-endpoint = <0x2b>; + phandle = <0x2d>; + }; + }; + }; + }; + + bridge@d9015000 { + compatible = "riscv,trace-atbbridge"; + reg = <0x00 0xd9015000 0x00 0x1000>; + cpus = <0x10>; + + out-ports { + + port { + + endpoint { + remote-endpoint = <0x2c>; + phandle = <0x53>; + }; + }; + }; + + in-ports { + + port { + + endpoint { + remote-endpoint = <0x2d>; + phandle = <0x2b>; + }; + }; + }; + }; + + encoder@d9016000 { + compatible = "riscv,trace-encoder"; + reg = <0x00 0xd9016000 0x00 0x1000>; + cpus = <0x11>; + + out-ports { + + port { + + endpoint { + remote-endpoint = <0x2e>; + phandle = <0x30>; + }; + }; + }; + }; + + bridge@d9017000 { + compatible = "riscv,trace-atbbridge"; + reg = <0x00 0xd9017000 0x00 0x1000>; + cpus = <0x11>; + + out-ports { + + port { + + endpoint { + remote-endpoint = <0x2f>; + phandle = <0x54>; + }; + }; + }; + + in-ports { + + port { + + endpoint { + remote-endpoint = <0x30>; + phandle = <0x2e>; + }; + }; + }; + }; + + encoder@d9018000 { + compatible = "riscv,trace-encoder"; + reg = <0x00 0xd9018000 0x00 0x1000>; + cpus = <0x12>; + + out-ports { + + port { + + endpoint { + remote-endpoint = <0x31>; + phandle = <0x33>; + }; + }; + }; + }; + + bridge@d9019000 { + compatible = "riscv,trace-atbbridge"; + reg = <0x00 0xd9019000 0x00 0x1000>; + cpus = <0x12>; + + out-ports { + + port { + + endpoint { + remote-endpoint = <0x32>; + phandle = <0x55>; + }; + }; + }; + + in-ports { + + port { + + endpoint { + remote-endpoint = <0x33>; + phandle = <0x31>; + }; + }; + }; + }; + + encoder@d9022000 { + compatible = "riscv,trace-encoder"; + reg = <0x00 0xd9022000 0x00 0x1000>; + cpus = <0x13>; + + out-ports { + + port { + + endpoint { + remote-endpoint = <0x34>; + phandle = <0x36>; + }; + }; + }; + }; + + bridge@d9023000 { + compatible = "riscv,trace-atbbridge"; + reg = <0x00 0xd9023000 0x00 0x1000>; + cpus = <0x13>; + + out-ports { + + port { + + endpoint { + remote-endpoint = <0x35>; + phandle = <0x57>; + }; + }; + }; + + in-ports { + + port { + + endpoint { + remote-endpoint = <0x36>; + phandle = <0x34>; + }; + }; + }; + }; + + encoder@d9024000 { + compatible = "riscv,trace-encoder"; + reg = <0x00 0xd9024000 0x00 0x1000>; + cpus = <0x14>; + + out-ports { + + port { + + endpoint { + remote-endpoint = <0x37>; + phandle = <0x39>; + }; + }; + }; + }; + + bridge@d9025000 { + compatible = "riscv,trace-atbbridge"; + reg = <0x00 0xd9025000 0x00 0x1000>; + cpus = <0x14>; + + out-ports { + + port { + + endpoint { + remote-endpoint = <0x38>; + phandle = <0x58>; + }; + }; + }; + + in-ports { + + port { + + endpoint { + remote-endpoint = <0x39>; + phandle = <0x37>; + }; + }; + }; + }; + + encoder@d9026000 { + compatible = "riscv,trace-encoder"; + reg = <0x00 0xd9026000 0x00 0x1000>; + cpus = <0x15>; + + out-ports { + + port { + + endpoint { + remote-endpoint = <0x3a>; + phandle = <0x3c>; + }; + }; + }; + }; + + bridge@d9027000 { + compatible = "riscv,trace-atbbridge"; + reg = <0x00 0xd9027000 0x00 0x1000>; + cpus = <0x15>; + + out-ports { + + port { + + endpoint { + remote-endpoint = <0x3b>; + phandle = <0x59>; + }; + }; + }; + + in-ports { + + port { + + endpoint { + remote-endpoint = <0x3c>; + phandle = <0x3a>; + }; + }; + }; + }; + + encoder@d9028000 { + compatible = "riscv,trace-encoder"; + reg = <0x00 0xd9028000 0x00 0x1000>; + cpus = <0x16>; + + out-ports { + + port { + + endpoint { + remote-endpoint = <0x3d>; + phandle = <0x3f>; + }; + }; + }; + }; + + bridge@d9029000 { + compatible = "riscv,trace-atbbridge"; + reg = <0x00 0xd9029000 0x00 0x1000>; + cpus = <0x16>; + + out-ports { + + port { + + endpoint { + remote-endpoint = <0x3e>; + phandle = <0x5a>; + }; + }; + }; + + in-ports { + + port { + + endpoint { + remote-endpoint = <0x3f>; + phandle = <0x3d>; + }; + }; + }; + }; + + encoder@d9032000 { + compatible = "riscv,trace-encoder"; + reg = <0x00 0xd9032000 0x00 0x1000>; + cpus = <0x17>; + + out-ports { + + port { + + endpoint { + remote-endpoint = <0x40>; + phandle = <0x42>; + }; + }; + }; + }; + + bridge@d9033000 { + compatible = "riscv,trace-atbbridge"; + reg = <0x00 0xd9033000 0x00 0x1000>; + cpus = <0x17>; + + out-ports { + + port { + + endpoint { + remote-endpoint = <0x41>; + phandle = <0x5c>; + }; + }; + }; + + in-ports { + + port { + + endpoint { + remote-endpoint = <0x42>; + phandle = <0x40>; + }; + }; + }; + }; + + encoder@d9034000 { + compatible = "riscv,trace-encoder"; + reg = <0x00 0xd9034000 0x00 0x1000>; + cpus = <0x18>; + + out-ports { + + port { + + endpoint { + remote-endpoint = <0x43>; + phandle = <0x45>; + }; + }; + }; + }; + + bridge@d9035000 { + compatible = "riscv,trace-atbbridge"; + reg = <0x00 0xd9035000 0x00 0x1000>; + cpus = <0x18>; + + out-ports { + + port { + + endpoint { + remote-endpoint = <0x44>; + phandle = <0x5d>; + }; + }; + }; + + in-ports { + + port { + + endpoint { + remote-endpoint = <0x45>; + phandle = <0x43>; + }; + }; + }; + }; + + encoder@d9036000 { + compatible = "riscv,trace-encoder"; + reg = <0x00 0xd9036000 0x00 0x1000>; + cpus = <0x19>; + + out-ports { + + port { + + endpoint { + remote-endpoint = <0x46>; + phandle = <0x48>; + }; + }; + }; + }; + + bridge@d9037000 { + compatible = "riscv,trace-atbbridge"; + reg = <0x00 0xd9037000 0x00 0x1000>; + cpus = <0x19>; + + out-ports { + + port { + + endpoint { + remote-endpoint = <0x47>; + phandle = <0x5e>; + }; + }; + }; + + in-ports { + + port { + + endpoint { + remote-endpoint = <0x48>; + phandle = <0x46>; + }; + }; + }; + }; + + encoder@d9038000 { + compatible = "riscv,trace-encoder"; + reg = <0x00 0xd9038000 0x00 0x1000>; + cpus = <0x1a>; + + out-ports { + + port { + + endpoint { + remote-endpoint = <0x49>; + phandle = <0x4b>; + }; + }; + }; + }; + + bridge@d9039000 { + compatible = "riscv,trace-atbbridge"; + reg = <0x00 0xd9039000 0x00 0x1000>; + cpus = <0x1a>; + + out-ports { + + port { + + endpoint { + remote-endpoint = <0x4a>; + phandle = <0x5f>; + }; + }; + }; + + in-ports { + + port { + + endpoint { + remote-endpoint = <0x4b>; + phandle = <0x49>; + }; + }; + }; + }; + + funnel@d9000000 { + compatible = "riscv,trace-funnel"; + reg = <0x00 0xd9000000 0x00 0x1000>; + cpus = <0x0b 0x0c 0x0d 0x0e>; + riscv,timestamp-present; + + out-ports { + + port { + + endpoint { + remote-endpoint = <0x4c>; + phandle = <0x62>; + }; + }; + }; + + in-ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint { + remote-endpoint = <0x4d>; + phandle = <0x1d>; + }; + }; + + port@1 { + reg = <0x01>; + + endpoint { + remote-endpoint = <0x4e>; + phandle = <0x20>; + }; + }; + + port@2 { + reg = <0x02>; + + endpoint { + remote-endpoint = <0x4f>; + phandle = <0x23>; + }; + }; + + port@3 { + reg = <0x03>; + + endpoint { + remote-endpoint = <0x50>; + phandle = <0x26>; + }; + }; + }; + }; + + funnel@d9010000 { + compatible = "riscv,trace-funnel"; + reg = <0x00 0xd9010000 0x00 0x1000>; + cpus = <0x0f 0x10 0x11 0x12>; + riscv,timestamp-present; + + out-ports { + + port { + + endpoint { + remote-endpoint = <0x51>; + phandle = <0x63>; + }; + }; + }; + + in-ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint { + remote-endpoint = <0x52>; + phandle = <0x29>; + }; + }; + + port@1 { + reg = <0x01>; + + endpoint { + remote-endpoint = <0x53>; + phandle = <0x2c>; + }; + }; + + port@2 { + reg = <0x02>; + + endpoint { + remote-endpoint = <0x54>; + phandle = <0x2f>; + }; + }; + + port@3 { + reg = <0x03>; + + endpoint { + remote-endpoint = <0x55>; + phandle = <0x32>; + }; + }; + }; + }; + + funnel@d9020000 { + compatible = "riscv,trace-funnel"; + reg = <0x00 0xd9020000 0x00 0x1000>; + cpus = <0x13 0x14 0x15 0x16>; + riscv,timestamp-present; + + out-ports { + + port { + + endpoint { + remote-endpoint = <0x56>; + phandle = <0x64>; + }; + }; + }; + + in-ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint { + remote-endpoint = <0x57>; + phandle = <0x35>; + }; + }; + + port@1 { + reg = <0x01>; + + endpoint { + remote-endpoint = <0x58>; + phandle = <0x38>; + }; + }; + + port@2 { + reg = <0x02>; + + endpoint { + remote-endpoint = <0x59>; + phandle = <0x3b>; + }; + }; + + port@3 { + reg = <0x03>; + + endpoint { + remote-endpoint = <0x5a>; + phandle = <0x3e>; + }; + }; + }; + }; + + funnel@d9030000 { + compatible = "riscv,trace-funnel"; + reg = <0x00 0xd9030000 0x00 0x1000>; + cpus = <0x17 0x18 0x19 0x1a>; + riscv,timestamp-present; + + out-ports { + + port { + + endpoint { + remote-endpoint = <0x5b>; + phandle = <0x65>; + }; + }; + }; + + in-ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint { + remote-endpoint = <0x5c>; + phandle = <0x41>; + }; + }; + + port@1 { + reg = <0x01>; + + endpoint { + remote-endpoint = <0x5d>; + phandle = <0x44>; + }; + }; + + port@2 { + reg = <0x02>; + + endpoint { + remote-endpoint = <0x5e>; + phandle = <0x47>; + }; + }; + + port@3 { + reg = <0x03>; + + endpoint { + remote-endpoint = <0x5f>; + phandle = <0x4a>; + }; + }; + }; + }; + + funnel@d9042000 { + compatible = "arm,coresight-dynamic-funnel\0arm,primecell"; + reg = <0x00 0xd9042000 0x00 0x1000>; + clocks = <0x60>; + clock-names = "apb_pclk"; + + out-ports { + + port { + + endpoint { + remote-endpoint = <0x61>; + phandle = <0x67>; + }; + }; + }; + + in-ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint { + remote-endpoint = <0x62>; + phandle = <0x4c>; + }; + }; + + port@1 { + reg = <0x01>; + + endpoint { + remote-endpoint = <0x63>; + phandle = <0x51>; + }; + }; + + port@2 { + reg = <0x02>; + + endpoint { + remote-endpoint = <0x64>; + phandle = <0x56>; + }; + }; + + port@3 { + reg = <0x03>; + + endpoint { + remote-endpoint = <0x65>; + phandle = <0x5b>; + }; + }; + }; + }; + + etf@d9043000 { + compatible = "arm,coresight-tmc\0arm,primecell"; + reg = <0x00 0xd9043000 0x00 0x1000>; + clocks = <0x60>; + clock-names = "apb_pclk"; + + out-ports { + + port { + + endpoint { + remote-endpoint = <0x66>; + phandle = <0x68>; + }; + }; + }; + + in-ports { + + port { + + endpoint { + remote-endpoint = <0x67>; + phandle = <0x61>; + }; + }; + }; + }; + + etr@d9044000 { + compatible = "arm,coresight-tmc\0arm,primecell"; + reg = <0x00 0xd9044000 0x00 0x1000>; + clocks = <0x60>; + clock-names = "apb_pclk"; + arm,scatter-gather; + + in-ports { + + port { + + endpoint { + remote-endpoint = <0x68>; + phandle = <0x66>; + }; + }; + }; + }; + + clint@e081c000 { + compatible = "riscv,clint0"; + interrupts-extended = <0x69 0x03 0x69 0x07 0x6a 0x03 0x6a 0x07 0x6b 0x03 0x6b 0x07 0x6c 0x03 0x6c 0x07 0x6d 0x03 0x6d 0x07 0x6e 0x03 0x6e 0x07 0x6f 0x03 0x6f 0x07 0x70 0x03 0x70 0x07 0x71 0x03 0x71 0x07 0x72 0x03 0x72 0x07 0x73 0x03 0x73 0x07 0x74 0x03 0x74 0x07 0x75 0x03 0x75 0x07 0x76 0x03 0x76 0x07 0x77 0x03 0x77 0x07 0x78 0x03 0x78 0x07>; + reg = <0x00 0xe081c000 0x00 0x4000>; + }; + + interrupt-controller@e0400000 { + compatible = "riscv,imsics"; + interrupts-extended = <0x69 0x09 0x6a 0x09 0x6b 0x09 0x6c 0x09 0x6d 0x09 0x6e 0x09 0x6f 0x09 0x70 0x09 0x71 0x09 0x72 0x09 0x73 0x09 0x74 0x09 0x75 0x09 0x76 0x09 0x77 0x09 0x78 0x09>; + reg = <0x00 0xe0400000 0x00 0x400000>; + interrupt-controller; + #interrupt-cells = <0x00>; + #msi-cells = <0x00>; + msi-controller; + riscv,num-ids = <0x1ff>; + riscv,num-guest-ids = <0x1ff>; + riscv,hart-index-bits = <0x04>; + riscv,guest-index-bits = <0x06>; + status = "okay"; + phandle = <0x79>; + }; + + interrupt-controller@e0804000 { + compatible = "riscv,aplic"; + reg = <0x00 0xe0804000 0x00 0x4000>; + msi-parent = <0x79>; + #interrupt-cells = <0x02>; + interrupt-controller; + riscv,num-sources = <0x200>; + status = "okay"; + phandle = <0x82>; + }; + + system-controller@d4050000 { + compatible = "spacemit,k3-syscon-mpmu"; + reg = <0x00 0xd4050000 0x00 0x10000>; + clocks = <0x7a 0x7b 0x7c 0x7d 0x7e 0x7f>; + clock-names = "osc_32k\0vctcxo_1m\0vctcxo_3m\0vctcxo_24m\0reserved_clk\0external_clk"; + #clock-cells = <0x01>; + #reset-cells = <0x01>; + phandle = <0x80>; + }; + + clock-controller@d4090000 { + compatible = "spacemit,k3-pll"; + reg = <0x00 0xd4090000 0x00 0x10000>; + clocks = <0x7d>; + spacemit,mpmu = <0x80>; + #clock-cells = <0x01>; + phandle = <0x1b>; + }; + + system-controller@d4282800 { + compatible = "spacemit,k3-syscon-apmu"; + reg = <0x00 0xd4282800 0x00 0x400>; + clocks = <0x7a 0x7b 0x7c 0x7d 0x7e 0x7f>; + clock-names = "osc_32k\0vctcxo_1m\0vctcxo_3m\0vctcxo_24m\0reserved_clk\0external_clk"; + #clock-cells = <0x01>; + #power-domain-cells = <0x01>; + #reset-cells = <0x01>; + phandle = <0x05>; + }; + + system-controller@d4015000 { + compatible = "spacemit,k3-syscon-apbc"; + reg = <0x00 0xd4015000 0x00 0x1000>; + clocks = <0x7a 0x7b 0x7c 0x7d 0x7e 0x7f>; + clock-names = "osc_32k\0vctcxo_1m\0vctcxo_3m\0vctcxo_24m\0reserved_clk\0external_clk"; + #clock-cells = <0x01>; + #reset-cells = <0x01>; + phandle = <0x81>; + }; + + system-controller@f0610000 { + compatible = "spacemit,k3-syscon-apbc2"; + reg = <0x00 0xf0610000 0x00 0x2000>; + clocks = <0x7a 0x7b 0x7c 0x7d 0x7e 0x7f>; + clock-names = "osc_32k\0vctcxo_1m\0vctcxo_3m\0vctcxo_24m\0reserved_clk\0external_clk"; + #clock-cells = <0x01>; + #reset-cells = <0x01>; + phandle = <0x87>; + }; + + system-controller@d8440000 { + compatible = "spacemit,k3-syscon-dciu"; + reg = <0x00 0xd8440000 0x00 0xc000>; + #clock-cells = <0x01>; + #reset-cells = <0x01>; + phandle = <0xd6>; + }; + + system-controller@c0880000 { + compatible = "spacemit,k3-syscon-rcpu-sysctrl"; + reg = <0x00 0xc0880000 0x00 0x1000>; + clocks = <0x7d 0x7f>; + clock-names = "vctcxo_24m\0external_clk"; + #clock-cells = <0x01>; + #reset-cells = <0x01>; + phandle = <0xd0>; + }; + + system-controller@c0881f00 { + compatible = "spacemit,k3-syscon-rcpu-uartctrl"; + reg = <0x00 0xc0881f00 0x00 0x100>; + #clock-cells = <0x01>; + #reset-cells = <0x01>; + phandle = <0xe2>; + }; + + system-controller@c0882000 { + compatible = "spacemit,k3-syscon-rcpu-i2sctrl"; + reg = <0x00 0xc0882000 0x00 0x1000>; + #clock-cells = <0x01>; + #reset-cells = <0x01>; + phandle = <0xe5>; + }; + + system-controller@c0885f00 { + compatible = "spacemit,k3-syscon-rcpu-spictrl"; + reg = <0x00 0xc0885f00 0x00 0x100>; + #clock-cells = <0x01>; + #reset-cells = <0x01>; + phandle = <0xef>; + }; + + system-controller@c0886f00 { + compatible = "spacemit,k3-syscon-rcpu-i2cctrl"; + reg = <0x00 0xc0886f00 0x00 0x100>; + #clock-cells = <0x01>; + #reset-cells = <0x01>; + phandle = <0xe4>; + }; + + system-controller@c088c000 { + compatible = "spacemit,k3-syscon-rpmu"; + reg = <0x00 0xc088c000 0x00 0x800>; + #clock-cells = <0x01>; + #reset-cells = <0x01>; + }; + + system-controller@c088d000 { + compatible = "spacemit,k3-syscon-rcpu-pwmctrl"; + reg = <0x00 0xc088d000 0x00 0x100>; + #clock-cells = <0x01>; + #reset-cells = <0x01>; + phandle = <0xe3>; + }; + + syscon-gpio { + compatible = "syscon"; + reg = <0x00 0xd4019000 0x00 0x800>; + phandle = <0x83>; + }; + + syscon-gpio-edge { + compatible = "syscon"; + reg = <0x00 0xd4019800 0x00 0x10>; + phandle = <0x84>; + }; + + gpio@d4019000 { + compatible = "spacemit,k3-gpio"; + reg = <0x00 0xd4019000 0x00 0x100>; + clocks = <0x81 0x14 0x81 0x15>; + clock-names = "core\0bus"; + gpio-controller; + #gpio-cells = <0x03>; + interrupts = <0x3a 0x04>; + interrupt-parent = <0x82>; + interrupt-controller; + #interrupt-cells = <0x03>; + syscon-gpio-regs = <0x83>; + syscon-gpio-edge = <0x84>; + gpio-ranges = <0x85 0x00 0x00 0x00 0x20 0x85 0x01 0x00 0x20 0x20 0x85 0x02 0x00 0x40 0x20 0x85 0x03 0x00 0x60 0x20>; + phandle = <0x8b>; + }; + + pinctrl@d401e000 { + compatible = "spacemit,k3-pinctrl"; + reg = <0x00 0xd401e000 0x00 0x400 0x00 0xd401e800 0x00 0x34>; + clocks = <0x81 0x67 0x81 0x68>; + clock-names = "func\0bus"; + interrupt-controller; + #interrupt-cells = <0x02>; + interrupts = <0x3c 0x04>; + interrupt-parent = <0x82>; + spacemit,gpio-edge = <0x84>; + spacemit,apbc = <0x81 0x50>; + spacemit,apmu = <0x05>; + phandle = <0x85>; + + uart0-0-cfg { + phandle = <0x86>; + + uart0-0-pins { + pinmux = <0x950002 0x960002>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + uart0-1-cfg { + + uart0-0-pins { + pinmux = <0x840002 0x850002>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + uart0-2-cfg { + + uart0-0-pins { + pinmux = <0x910005 0x920005>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + uart0-3-cfg { + + uart0-0-pins { + pinmux = <0x2a0002 0x2b0002>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + uart0-4-cfg { + + uart0-0-pins { + pinmux = <0x5d0003 0x5e0003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + uart1-0-cfg { + + uart1-0-pins { + pinmux = <0x5f0002 0x600002 0x610002 0x620002>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + uart1-1-cfg { + + uart1-0-pins { + pinmux = <0x760001 0x770001 0x780001 0x790001>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + uart2-0-cfg { + + uart2-0-pins { + pinmux = <0x860002 0x870002 0x880002 0x890002>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + uart2-1-cfg { + + uart2-0-pins { + pinmux = <0x610001 0x620001>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + uart3-0-cfg { + + uart3-0-pins { + pinmux = <0x1a0002 0x1b0002 0x1c0002 0x1d0002>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + uart3-1-cfg { + + uart3-0-pins { + pinmux = <0x350002 0x360002 0x370002 0x380002>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + uart4-0-cfg { + + uart4-0-pins { + pinmux = <0x560003 0x570003 0x5a0003 0x5b0003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + uart4-1-cfg { + + uart4-0-pins { + pinmux = <0x630003 0x640003 0x650003 0x660003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + uart5-0-cfg { + + uart5-0-pins { + pinmux = <0x910004 0x920004>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + uart5-1-cfg { + + uart5-0-pins { + pinmux = <0x150002 0x160002 0x170002 0x180002>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + uart5-2-cfg { + + uart5-0-pins { + pinmux = <0x520004 0x530004>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + uart6-0-cfg { + + uart6-0-pins { + pinmux = <0x300002 0x310002 0x320002 0x330002>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + uart6-1-cfg { + + uart6-0-pins { + pinmux = <0x7a0003 0x7b0003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + uart7-0-cfg { + + uart7-0-pins { + pinmux = <0xb0002 0xc0002 0xd0002 0xe0002>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + uart7-1-cfg { + + uart7-0-pins { + pinmux = <0x170005 0x180005 0x190005 0x1a0005>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + uart8-0-cfg { + + uart8-0-pins { + pinmux = <0xb0005 0xc0005>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + uart8-1-cfg { + + uart8-0-pins { + pinmux = <0x4c0003 0x4d0003 0x4e0003 0x4f0003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + uart9-0-cfg { + + uart9-0-pins { + pinmux = <0x930004 0x940004>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + uart9-1-cfg { + + uart9-0-pins { + pinmux = <0x520003 0x530003 0x540003 0x550003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + uart10-0-cfg { + + uart10-0-pins { + pinmux = <0x1f0002 0x200002 0x210002 0x220002>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + uart10-1-cfg { + + uart10-0-pins { + pinmux = <0x2c0002 0x2d0002 0x2e0002 0x2f0002>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + ruart0-0-cfg { + + ruart0-0-pins { + pinmux = <0x840004 0x850004>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + ruart0-1-cfg { + + ruart0-0-pins { + pinmux = <0x910006 0x920006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + ruart0-2-cfg { + + ruart0-0-pins { + pinmux = <0x6d0003 0x6e0003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + ruart0-3-cfg { + + ruart0-0-pins { + pinmux = <0x7a0004 0x7b0004>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + ruart1_0-cfg { + + ruart1-0-pins { + pinmux = <0x8a0002 0x8b0002 0x8c0002 0x8d0002>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + ruart1-1-cfg { + + ruart1-0-pins { + pinmux = <0x110005 0x120005 0x130005 0x140005>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + ruart2-0-cfg { + + ruart2-0-pins { + pinmux = <0x390002 0x3a0002>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + ruart3-0-cfg { + + ruart3-0-pins { + pinmux = <0x370004 0x380004>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + ruart3-1-cfg { + + ruart3-0-pins { + pinmux = <0x580003 0x590003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + ruart4-0-cfg { + + ruart4-0-pins { + pinmux = <0x150005 0x160005>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + ruart4-1-cfg { + + ruart4-0-pins { + pinmux = <0x500003 0x510003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + ruart5-0-cfg { + + ruart5-0-pins { + pinmux = <0x3b0002 0x3c0002>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + i2c0-0-cfg { + phandle = <0x89>; + + i2c0-0-pins { + pinmux = <0x06 0x10006>; + bias-pull-up; + drive-strength = <0x19>; + power-source = <0xce4>; + }; + }; + + i2c0-1-cfg { + + i2c0-0-pins { + pinmux = <0x2a0005 0x2b0005>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + i2c0-2-cfg { + + i2c0-0-pins { + pinmux = <0x300005 0x310005>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + i2c0-3-cfg { + + i2c0-0-pins { + pinmux = <0x4c0006 0x4d0006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + i2c0-4-cfg { + + i2c0-0-pins { + pinmux = <0x730004 0x740004>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + i2c1-0-cfg { + + i2c1-0-pins { + pinmux = <0x20006 0x30006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + i2c1-1-cfg { + phandle = <0x8e>; + + i2c1-0-pins { + pinmux = <0x360005 0x370005>; + bias-pull-up; + drive-strength = <0x19>; + power-source = <0x708>; + }; + }; + + i2c1-2-cfg { + + i2c1-0-pins { + pinmux = <0x4e0006 0x4f0006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + i2c1-3-cfg { + + i2c1-0-pins { + pinmux = <0x660006 0x670006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + i2c2-0-cfg { + + i2c2-0-pins { + pinmux = <0x50006 0x60006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + i2c2-1-cfg { + phandle = <0x8f>; + + i2c2-0-pins { + pinmux = <0x2e0005 0x2f0005>; + bias-pull-up; + drive-strength = <0x19>; + power-source = <0x708>; + }; + }; + + i2c2-2-cfg { + + i2c2-0-pins { + pinmux = <0x500006 0x510006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + i2c2-3-cfg { + + i2c2-0-pins { + pinmux = <0x780002 0x790002>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + i2c3-0-cfg { + + i2c3-0-pins { + pinmux = <0x8e0005 0x8f0005>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + i2c3-1-cfg { + + i2c3-0-pins { + pinmux = <0x240004 0x250004>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + i2c3-2-cfg { + phandle = <0x90>; + + i2c3-0-pins { + pinmux = <0x520006 0x530006>; + bias-pull-up; + drive-strength = <0x19>; + power-source = <0xce4>; + }; + }; + + i2c3-3-cfg { + + i2c3-0-pins { + pinmux = <0x690004 0x6a0004>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + i2c4-0-cfg { + + i2c4-0-pins { + pinmux = <0x880006 0x890006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + i2c4-1-cfg { + + i2c4-0-pins { + pinmux = <0xb0006 0xc0006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + i2c4-2-cfg { + + i2c4-0-pins { + pinmux = <0x320005 0x330005>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + i2c4-3-cfg { + + i2c4-0-pins { + pinmux = <0x6f0004 0x700004>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + touchpad-int-cfg { + + touchpad-int-pins { + pinmux = <0x1a0000>; + bias-pull-up; + power-source = <0xce4>; + }; + }; + + i2c5-0-cfg { + + i2c5-0-pins { + pinmux = <0x190006 0x1a0006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + i2c5-1-cfg { + + i2c5-0-pins { + pinmux = <0x3f0005 0x400005>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + i2c5-2-cfg { + phandle = <0x92>; + + i2c5-0-pins { + pinmux = <0x5d0005 0x5e0005>; + bias-pull-up; + drive-strength = <0x19>; + power-source = <0x708>; + }; + }; + + i2c5-3-cfg { + + i2c5-0-pins { + pinmux = <0x7e0004 0x7f0004>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + i2c6-0-cfg { + + i2c6-0-pins { + pinmux = <0x970002 0x980002>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + i2c6-1-cfg { + phandle = <0x96>; + + i2c6-0-pins { + pinmux = <0x70006 0x80006>; + bias-pull-up; + drive-strength = <0x12>; + power-source = <0xce4>; + }; + }; + + i2c6-2-cfg { + + i2c6-0-pins { + pinmux = <0xe0006 0xf0006>; + bias-pull-up; + drive-strength = <0x12>; + }; + }; + + i2c6-3-cfg { + + i2c6-0-pins { + pinmux = <0x3d0005 0x3e0005>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + i2c8-cfg { + + i2c8-pins { + pinmux = <0x800000 0x810000>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + i2c8-cfg-rcpu { + phandle = <0xa9>; + + i2c8-pins-rcpu { + pinmux = <0x800001 0x810001>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + ri2c0-0-cfg { + + ri2c0-0-pins { + pinmux = <0x1b0006 0x1c0006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + ri2c0-1-cfg { + + ri2c0-0-pins { + pinmux = <0x390005 0x3a0005>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + ri2c0-2-cfg { + + ri2c0-0-pins { + pinmux = <0x4a0006 0x4b0006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + ri2c0-3-cfg { + + ri2c0-0-pins { + pinmux = <0x730006 0x740006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + ri2c1-0-cfg { + + ri2c1-0-pins { + pinmux = <0x210006 0x220006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + ri2c1-1-cfg { + + ri2c1-0-pins { + pinmux = <0x270004 0x280004>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + ri2c1-2-cfg { + + ri2c1-0-pins { + pinmux = <0x3b0005 0x3c0005>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + ri2c1-3-cfg { + + ri2c1-0-pins { + pinmux = <0x690003 0x6a0003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm0-0-cfg { + + pwm0-0-pins { + pinmux = <0x2b0006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm0-1-cfg { + + pwm0-0-pins { + pinmux = <0x2a0006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm1-0-cfg { + + pwm1-0-pins { + pinmux = <0x10003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm1-2-cfg { + + pwm1-0-pins { + pinmux = <0x5f0006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm2-0-cfg { + + pwm2-0-pins { + pinmux = <0x20003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm2-1-cfg { + + pwm2-0-pins { + pinmux = <0x2c0006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm2-2-cfg { + + pwm2-0-pins { + pinmux = <0x600006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm2-3-cfg { + + pwm2-0-pins { + pinmux = <0x860004>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm3-0-cfg { + + pwm3-0-pins { + pinmux = <0x30003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm3-1-cfg { + + pwm3-0-pins { + pinmux = <0x2d0006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm3-2-cfg { + + pwm3-0-pins { + pinmux = <0x610006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm3-3-cfg { + + pwm3-0-pins { + pinmux = <0x870004>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm4-0-cfg { + + pwm4-0-pins { + pinmux = <0x40003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm4-1-cfg { + + pwm4-0-pins { + pinmux = <0x2e0006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm4-2-cfg { + + pwm4-0-pins { + pinmux = <0x880004>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm5-0-cfg { + + pwm5-0-pins { + pinmux = <0x50003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm5-1-cfg { + + pwm5-0-pins { + pinmux = <0x2f0006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm5-2-cfg { + + pwm5-0-pins { + pinmux = <0x890004>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm6-0-cfg { + + pwm6-0-pins { + pinmux = <0x60003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm6-1-cfg { + + pwm6-0-pins { + pinmux = <0x910003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm6-2-cfg { + + pwm6-0-pins { + pinmux = <0x300006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm7-0-cfg { + + pwm7-0-pins { + pinmux = <0x70003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm7-1-cfg { + + pwm7-0-pins { + pinmux = <0x920003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm7-2-cfg { + + pwm7-0-pins { + pinmux = <0x310006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm8-0-cfg { + + pwm8-0-pins { + pinmux = <0x80003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm8-1-cfg { + + pwm8-0-pins { + pinmux = <0x930003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm8-2-cfg { + + pwm8-0-pins { + pinmux = <0x320006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm9-0-cfg { + + pwm9-0-pins { + pinmux = <0x90003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm9-1-cfg { + + pwm9-0-pins { + pinmux = <0x940003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm9-2-cfg { + + pwm9-0-pins { + pinmux = <0x330006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm10-0-cfg { + + pwm10-0-pins { + pinmux = <0xa0003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm10-1-cfg { + + pwm10-0-pins { + pinmux = <0x340006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm10-2-cfg { + + pwm10-0-pins { + pinmux = <0x8d0004>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm11-0-cfg { + + pwm11-0-pins { + pinmux = <0x350006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm11-1-cfg { + + pwm11-0-pins { + pinmux = <0x8c0004>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm12-0-cfg { + + pwm12-0-pins { + pinmux = <0x360006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm12-1-cfg { + + pwm12-0-pins { + pinmux = <0x8b0004>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm13-0-cfg { + + pwm13-0-pins { + pinmux = <0x370006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm13-1-cfg { + + pwm13-0-pins { + pinmux = <0x8a0004>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm13-2-cfg { + + pwm13-0-pins { + pinmux = <0xd0003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm14-0-cfg { + + pwm14-0-pins { + pinmux = <0x380006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm14-1-cfg { + + pwm14-0-pins { + pinmux = <0x900004>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm14-2-cfg { + + pwm14-0-pins { + pinmux = <0xe0003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm15-0-cfg { + + pwm15-0-pins { + pinmux = <0x390006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm15-1-cfg { + + pwm15-0-pins { + pinmux = <0x8e0004>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm15-2-cfg { + + pwm15-0-pins { + pinmux = <0x150003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm16-0-cfg { + + pwm16-0-pins { + pinmux = <0x3a0006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm16-1-cfg { + + pwm16-0-pins { + pinmux = <0x8f0004>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm16-2-cfg { + + pwm16-0-pins { + pinmux = <0x160003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm17-0-cfg { + + pwm17-0-pins { + pinmux = <0x170003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm17-1-cfg { + + pwm17-0-pins { + pinmux = <0x3b0006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm17-2-cfg { + + pwm17-0-pins { + pinmux = <0x690006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm18-0-cfg { + + pwm18-0-pins { + pinmux = <0x180003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm18-1-cfg { + + pwm18-0-pins { + pinmux = <0x3c0006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm18-2-cfg { + + pwm18-0-pins { + pinmux = <0x6a0006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm19-0-cfg { + + pwm19-0-pins { + pinmux = <0x190003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm19-1-cfg { + + pwm19-0-pins { + pinmux = <0x3d0006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm19-2-cfg { + + pwm19-0-pins { + pinmux = <0x6b0006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rpwm0-0-cfg { + + rpwm0-0-pins { + pinmux = <0xf0003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rpwm0-1-cfg { + + rpwm0-0-pins { + pinmux = <0x1b0003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rpwm0-2-cfg { + + rpwm0-0-pins { + pinmux = <0x400006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rpwm1-0-cfg { + + rpwm1-0-pins { + pinmux = <0x100003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rpwm1-1-cfg { + + rpwm1-0-pins { + pinmux = <0x1c0003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rpwm1-2-cfg { + + rpwm1-0-pins { + pinmux = <0x410006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rpwm2-0-cfg { + + rpwm2-0-pins { + pinmux = <0x110003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rpwm2-1-cfg { + + rpwm2-0-pins { + pinmux = <0x1d0003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rpwm2-2-cfg { + + rpwm2-0-pins { + pinmux = <0x420006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rpwm3-0-cfg { + + rpwm3-0-pins { + pinmux = <0x120003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rpwm3-1-cfg { + + rpwm3-0-pins { + pinmux = <0x1e0003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rpwm3-2-cfg { + + rpwm3-0-pins { + pinmux = <0x430006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rpwm4-0-cfg { + + rpwm4-0-pins { + pinmux = <0x130003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rpwm4-1-cfg { + + rpwm4-0-pins { + pinmux = <0x1f0003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rpwm4-2-cfg { + + rpwm4-0-pins { + pinmux = <0x5d0006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rpwm5-0-cfg { + + rpwm5-0-pins { + pinmux = <0x140003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rpwm5-1-cfg { + + rpwm5-0-pins { + pinmux = <0x200003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rpwm5-2-cfg { + + rpwm5-0-pins { + pinmux = <0x5c0005>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rpwm6-0-cfg { + + rpwm6-0-pins { + pinmux = <0x210003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rpwm6-1-cfg { + + rpwm6-0-pins { + pinmux = <0x5e0006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rpwm6-2-cfg { + + rpwm6-0-pins { + pinmux = <0x6d0006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rpwm7-0-cfg { + + rpwm7-0-pins { + pinmux = <0x220003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rpwm7-1-cfg { + + rpwm7-0-pins { + pinmux = <0x6e0006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rpwm8-0-cfg { + + rpwm8-0-pins { + pinmux = <0x230003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rpwm8-1-cfg { + + rpwm8-0-pins { + pinmux = <0x6f0006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rpwm9-0-cfg { + + rpwm9-0-pins { + pinmux = <0x240003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rpwm9-1-cfg { + + rpwm9-0-pins { + pinmux = <0x700006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + ir0-0-cfg { + + ir0-0-pins { + pinmux = <0x290005>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + ir0-1-cfg { + + ir0-0-pins { + pinmux = <0x6c0004>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + ir1-0-cfg { + + ir1-0-pins { + pinmux = <0x04>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + ir1-1-cfg { + + ir1-0-pins { + pinmux = <0x460004>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rir0-0-cfg { + + rir0-0-pins { + pinmux = <0x280005>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rir0-1-cfg { + + rir0-0-pins { + pinmux = <0x470004>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rir1-0-cfg { + + rir1-0-pins { + pinmux = <0x10004>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rir1-1-cfg { + + rir1-0-pins { + pinmux = <0x490004>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + can0-0-cfg { + + can0-0-pins { + pinmux = <0xb0003 0xc0003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + can0-1-cfg { + + can0-0-pins { + pinmux = <0x2c0003 0x2d0003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + can0-2-cfg { + + can0-0-pins { + pinmux = <0x4c0004 0x4d0004>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + can1-0-cfg { + + can1-0-pins { + pinmux = <0x300003 0x310003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + can1-1-cfg { + + can1-0-pins { + pinmux = <0x580006 0x590006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + can1-2-cfg { + + can1-0-pins { + pinmux = <0x6d0004 0x6e0004>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + can2-0-cfg { + + can2-0-pins { + pinmux = <0x320003 0x330003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + can2-1-cfg { + phandle = <0xa0>; + + can2-0-pins { + pinmux = <0x560004 0x570004>; + bias-pull-up; + drive-strength = <0x19>; + power-source = <0xce4>; + }; + }; + + can3-0-cfg { + + can3-0-pins { + pinmux = <0x500004 0x510004>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + can3-1-cfg { + + can3-0-pins { + pinmux = <0x670004 0x680004>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + can4-0-cfg { + + can4-0-pins { + pinmux = <0x280006 0x290006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + can4-1-cfg { + + can4-0-pins { + pinmux = <0x650004 0x660004>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + can4-2-cfg { + + can4-0-pins { + pinmux = <0x780004 0x790004>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rcan0-0-cfg { + + rcan0-0-pins { + pinmux = <0x390003 0x3a0003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rcan0-1-cfg { + + rcan0-0-pins { + pinmux = <0x5a0006 0x5b0006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rcan1-0-cfg { + + rcan1-0-pins { + pinmux = <0x8e0002 0x900002>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rcan2-0-cfg { + + rcan2-0-pins { + pinmux = <0x630004 0x640004>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rcan3-0-cfg { + + rcan3-0-pins { + pinmux = <0x780003 0x790003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rcan4-0-cfg { + + rcan4-0-pins { + pinmux = <0x6b0003 0x6c0003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + sspa0-0-cfg { + + sspa0-0-pins { + pinmux = <0x510002 0x520002 0x530002 0x540002 0x550002>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + sspa0-1-cfg { + + sspa0-0-pins { + pinmux = <0x6f0002 0x700002 0x710002 0x720002 0x730002>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + sspa1-0-cfg { + + sspa1-0-pins { + pinmux = <0xf0002 0x100002 0x110002 0x120002 0x130002>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + sspa1-1-cfg { + + sspa1-0-pins { + pinmux = <0x7a0002 0x7b0002 0x7c0002 0x7d0002 0x7e0002>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + sspa2-0-cfg { + + sspa2-0-pins { + pinmux = <0x4c0002 0x4d0002 0x4e0002 0x4f0002 0x500002>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + sspa3-0-cfg { + + sspa3-0-pins { + pinmux = <0x630002 0x640002 0x650002 0x660002 0x670002>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + sspa4-0-cfg { + + sspa4-0-pins { + pinmux = <0x450002 0x460002 0x470002 0x480002 0x490002>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + sspa5-0-cfg { + + sspa5-0-pins { + pinmux = <0x02 0x10002 0x20002 0x30002 0x40002>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rsspa0-0-cfg { + + rsspa0-0-pins { + pinmux = <0x60002 0x70002 0x80002 0x90002 0xa0002>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rsspa0-1-cfg { + + rsspa0-0-pins { + pinmux = <0x4c0001 0x4d0001 0x4e0001 0x4f0001 0x500001>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rsspa1-0-cfg { + + rsspa1-0-pins { + pinmux = <0x240002 0x250002 0x260002 0x270002 0x280002>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pcie0-0-cfg { + + pcie0-0-pins { + pinmux = <0x2a0004 0x2b0004 0x2c0004>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + pcie0-1-cfg { + phandle = <0xd8>; + + pcie0-0-pins { + pinmux = <0x4f0005 0x510005>; + bias-disable; + drive-strength = <0x26>; + power-source = <0xce4>; + bias-pull-up; + }; + }; + + pcie0-2-cfg { + + pcie0-0-pins { + pinmux = <0x6c0005 0x6d0005 0x6e0005>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + pcie1-0-cfg { + + pcie1-0-pins { + pinmux = <0x150004 0x160004 0x170004>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + pcie1-1-cfg { + + pcie1-0-pins { + pinmux = <0x580004 0x590004 0x5a0004>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + pcie1-2-cfg { + + pcie1-0-pins { + pinmux = <0x710005 0x720005 0x730005>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + pcie2-0-cfg { + + pcie2-0-pins { + pinmux = <0xc0004 0xd0004 0xe0004>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + pcie2-1-cfg { + + pcie2-0-pins { + pinmux = <0x190004 0x1a0004 0x1b0004>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + pcie2-2-cfg { + + pcie2-0-pins { + pinmux = <0x3a0004 0x3b0004 0x3c0004>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + pcie3-0-cfg { + phandle = <0xdb>; + + pcie3-0-pins { + pinmux = <0x30004 0x50004>; + bias-disable; + drive-strength = <0x26>; + bias-pull-up; + power-source = <0xce4>; + }; + }; + + pcie3-1-cfg { + + pcie3-0-pins { + pinmux = <0x690005 0x6a0005 0x6b0005>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + pcie3-2-cfg { + + pcie3-0-pins { + pinmux = <0x7c0003 0x7d0003 0x7e0003>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + pcie4-0-cfg { + + pcie4-0-pins { + pinmux = <0x1f0004 0x200004 0x210004>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + pcie4-1-cfg { + phandle = <0xdd>; + + pcie4-0-pins { + pinmux = <0x4c0005 0x500005 0x4e0005>; + bias-disable; + drive-strength = <0x26>; + bias-pull-up; + power-source = <0xce4>; + }; + }; + + gmac0-cfg { + + gmac0-0-pins { + pinmux = <0x01 0x10001 0x20001 0x30001 0x60001 0x70001 0xb0001 0xc0001 0xd0001>; + bias-disable; + drive-strength = <0x19>; + }; + + gmac0-1-pins { + pinmux = <0x40001 0x50001 0x80001 0x90001 0xa0001>; + bias-disable; + drive-strength = <0x19>; + }; + + gmac0-2-pins { + pinmux = <0xf0001 0x100001 0x110001 0x120001>; + bias-disable; + drive-strength = <0x19>; + }; + + gmac0-3-pins { + pinmux = <0xe0001>; + bias-disable; + drive-strength = <0x19>; + }; + + gmac0-4-pins { + pinmux = <0x130001>; + bias-disable; + drive-strength = <0x19>; + }; + + gmac0-5-pins { + pinmux = <0x140001>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + gmac1-cfg { + phandle = <0xce>; + + gmac1-0-pins { + pinmux = <0x150001 0x160001 0x170001 0x180001 0x1b0001 0x1c0001 0x200001 0x210001 0x220001>; + bias-disable; + drive-strength = <0x19>; + power-source = <0x708>; + }; + + gmac1-1-pins { + pinmux = <0x190001 0x1a0001 0x1d0001 0x1e0001 0x1f0001>; + bias-disable; + drive-strength = <0x19>; + power-source = <0x708>; + }; + + gmac1-3-pins { + pinmux = <0x230001>; + bias-disable; + drive-strength = <0x19>; + power-source = <0x708>; + }; + + gmac1-6-pins { + pinmux = <0x250000>; + bias-disable; + drive-strength = <0x19>; + power-source = <0x708>; + }; + }; + + gmac2-cfg { + + gmac2-0-pins { + pinmux = <0x2a0001 0x2b0001 0x2c0001 0x2d0001 0x300001 0x310001 0x350001 0x360001 0x370001>; + bias-disable; + drive-strength = <0x19>; + }; + + gmac2-1-pins { + pinmux = <0x2e0001 0x2f0001 0x320001 0x330001 0x340001>; + bias-disable; + drive-strength = <0x19>; + }; + + gmac2-2-pins { + pinmux = <0x380001>; + bias-disable; + drive-strength = <0x19>; + }; + + gmac2-3-pins { + pinmux = <0x3a0001>; + bias-disable; + drive-strength = <0x19>; + }; + + gmac2-4-pins { + pinmux = <0x390001>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + gmac3-cfg { + + gmac3-0-pins { + pinmux = <0x3b0001 0x3c0001 0x3d0001 0x3e0001 0x410001 0x420001 0x460001 0x470001 0x480001>; + bias-disable; + drive-strength = <0x19>; + }; + + gmac3-1-pins { + pinmux = <0x3f0001 0x400001 0x430001 0x440001 0x450001>; + bias-disable; + drive-strength = <0x19>; + }; + + gmac3-2-pins { + pinmux = <0x490001>; + bias-disable; + drive-strength = <0x19>; + }; + + gmac3-3-pins { + pinmux = <0x4b0001>; + bias-disable; + drive-strength = <0x19>; + }; + + gmac3-4-pins { + pinmux = <0x4a0001>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + ssp0-0-cfg { + + ssp0-0-pins { + pinmux = <0x350003 0x360003 0x370003>; + bias-disable; + drive-strength = <0x19>; + }; + + ssp0-1-pins { + pinmux = <0x380003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + ssp0-1-cfg { + + ssp0-0-pins { + pinmux = <0x510001 0x520001 0x530001>; + bias-disable; + drive-strength = <0x19>; + }; + + ssp0-1-pins { + pinmux = <0x540001>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + ssp0-2-cfg { + + ssp0-0-pins { + pinmux = <0x680001 0x690001 0x6a0001>; + bias-disable; + drive-strength = <0x19>; + }; + + ssp0-1-pins { + pinmux = <0x6b0001>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + ssp1-0-cfg { + + ssp1-0-pins { + pinmux = <0x200005 0x210005 0x220005>; + bias-disable; + drive-strength = <0x19>; + }; + + ssp1-1-pins { + pinmux = <0x230005>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + ssp1-1-cfg { + + ssp1-0-pins { + pinmux = <0x6f0001 0x700001 0x710001>; + bias-disable; + drive-strength = <0x19>; + }; + + ssp1-1-pins { + pinmux = <0x720001>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + ssp2-0-cfg { + + ssp2-0-pins { + pinmux = <0x1c0005 0x1d0005 0x1e0005>; + bias-disable; + drive-strength = <0x19>; + }; + + ssp2-1-pins { + pinmux = <0x1f0005>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + ssp2-1-cfg { + + ssp2-0-pins { + pinmux = <0x680002 0x690002 0x6a0002>; + bias-disable; + drive-strength = <0x19>; + }; + + ssp2-1-pins { + pinmux = <0x6b0002>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + ssp3-0-cfg { + + ssp3-0-pins { + pinmux = <0x440006 0x450006 0x460006>; + bias-disable; + drive-strength = <0x19>; + }; + + ssp3-1-pins { + pinmux = <0x470006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + ssp3-1-cfg { + + ssp3-0-pins { + pinmux = <0x630001 0x640001 0x650001>; + bias-disable; + drive-strength = <0x19>; + }; + + ssp3-1-pins { + pinmux = <0x660001>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rssp0-0-cfg { + + rssp0-0-pins { + pinmux = <0x3c0003 0x3d0003 0x3e0003>; + bias-disable; + drive-strength = <0x19>; + }; + + rssp0-1-pins { + pinmux = <0x3f0003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rssp0-1-cfg { + + rssp0-0-pins { + pinmux = <0x560001 0x570001 0x580001>; + bias-disable; + drive-strength = <0x19>; + }; + + rssp0-1-pins { + pinmux = <0x590001>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rssp1-0-cfg { + + rssp1-0-pins { + pinmux = <0x400003 0x410003 0x420003>; + bias-disable; + drive-strength = <0x19>; + }; + + rssp1-1-pins { + pinmux = <0x430003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rssp1-1-cfg { + + rssp1-0-pins { + pinmux = <0x6c0001 0x6d0001 0x740001>; + bias-disable; + drive-strength = <0x19>; + }; + + rssp1-1-pins { + pinmux = <0x750001>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwr_ssp-cfg { + + pwr_ssp-0-pins { + pinmux = <0x970000 0x980000 0x950000>; + bias-disable; + drive-strength = <0x19>; + }; + + pwr_ssp-1-pins { + pinmux = <0x960000>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + qspi-cfg { + phandle = <0x98>; + + qspi-0-pins { + pinmux = <0x8a0000 0x8b0000 0x8c0000 0x8d0000 0x900000>; + bias-disable; + drive-strength = <0x19>; + power-source = <0x708>; + }; + }; + + espi0-0-cfg { + + espi0-0-pins { + pinmux = <0x05 0x10005 0x20005 0x30005 0x40005 0x60005 0x70005>; + bias-pull-up; + drive-strength = <0x19>; + }; + + espi0-1-pins { + pinmux = <0x50005>; + bias-pull-down; + drive-strength = <0x19>; + }; + }; + + espi0-1-cfg { + + espi0-0-pins { + pinmux = <0x440003 0x450003 0x460003 0x470003 0x480003 0x4a0003 0x4b0003>; + bias-pull-up; + drive-strength = <0x19>; + }; + + espi0-1-pins { + pinmux = <0x490003>; + bias-pull-down; + drive-strength = <0x19>; + }; + }; + + espi0-2-cfg { + + espi0-0-pins { + pinmux = <0x5b0004 0x5c0004 0x5d0004 0x5e0004 0x5f0004 0x610004 0x620004>; + bias-pull-up; + drive-strength = <0x19>; + power-source = <0x708>; + }; + + espi0-1-pins { + pinmux = <0x600004>; + bias-pull-down; + drive-strength = <0x19>; + power-source = <0x708>; + }; + }; + + respi0-cfg { + + respi0-0-pins { + pinmux = <0x560002 0x570002 0x580002 0x590002 0x5a0002 0x5c0002 0x5d0002>; + bias-pull-up; + drive-strength = <0x19>; + }; + + respi0-1-pins { + pinmux = <0x5b0002>; + bias-pull-down; + drive-strength = <0x19>; + }; + }; + + mmc1-cfg { + phandle = <0xd1>; + + mmc1-0-pins { + pinmux = <0x840000 0x850000 0x860000 0x870000 0x880000>; + bias-pull-up; + drive-strength = <0x08>; + power-source = <0xce4>; + }; + + mmc1-1-pins { + pinmux = <0x890000>; + bias-pull-down; + drive-strength = <0x08>; + power-source = <0xce4>; + }; + }; + + mmc1-uhs-cfg { + phandle = <0xd3>; + + mmc1-0-pins { + pinmux = <0x840000 0x850000 0x860000 0x870000 0x880000>; + bias-pull-up; + drive-strength = <0x07>; + power-source = <0x708>; + }; + + mmc1-1-pins { + pinmux = <0x890000>; + bias-pull-down; + drive-strength = <0x06>; + power-source = <0x708>; + }; + }; + + mmc1-debug-cfg { + + mmc1-0-pins { + pinmux = <0x840002 0x850002 0x860000 0x870000 0x880000>; + bias-pull-up; + drive-strength = <0x08>; + power-source = <0xce4>; + }; + + mmc1-1-pins { + pinmux = <0x890000>; + bias-pull-down; + drive-strength = <0x08>; + power-source = <0xce4>; + }; + }; + + mmc2-cfg { + + mmc2-0-pins { + pinmux = <0x7a0001 0x7b0001 0x7c0001 0x7d0001 0x7e0001>; + bias-pull-up; + drive-strength = <0x19>; + }; + + mmc2-1-pins { + pinmux = <0x7f0001>; + bias-pull-down; + drive-strength = <0x19>; + }; + }; + + cam0-0-cfg { + + cam0-0-pins { + pinmux = <0xd0005>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + cam0-1-cfg { + + cam0-0-pins { + pinmux = <0x2e0003>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + cam0-2-cfg { + phandle = <0x95>; + + cam1-0-pins { + pinmux = <0x4b0002>; + bias-disable; + drive-strength = <0x19>; + power-source = <0x708>; + }; + }; + + cam1-0-cfg { + + cam1-0-pins { + pinmux = <0x220004>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + cam1-1-cfg { + + cam1-0-pins { + pinmux = <0x2f0003>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + cam1-2-cfg { + + cam0-0-pins { + pinmux = <0x4a0002>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + cam2-0-cfg { + + cam2-0-pins { + pinmux = <0x230004>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + cam2-1-cfg { + + cam2-0-pins { + pinmux = <0x340005>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + cam2-2-cfg { + + cam2-0-pins { + pinmux = <0x550001>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + cam3-0-cfg { + + cam3-0-pins { + pinmux = <0x2b0003>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + cam3-1-cfg { + + cam3-0-pins { + pinmux = <0x430004>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + cam3-2-cfg { + + cam3-0-pins { + pinmux = <0x630006>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + dsi-0-cfg { + + dsi-0-pins { + pinmux = <0xd0006>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + dsi-1-cfg { + + dsi-0-pins { + pinmux = <0x260006>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + dsi-2-cfg { + + dsi-0-pins { + pinmux = <0x450005>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + dsi-3-cfg { + + dsi-0-pins { + pinmux = <0x480005>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + dsi-4-cfg { + + dsi-0-pins { + pinmux = <0x540006>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + dsi-5-cfg { + + dsi-0-pins { + pinmux = <0x5a0001>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + dsi-6-cfg { + + dsi-0-pins { + pinmux = <0x5c0006>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + edp0-0-cfg { + + edp0-0-pins { + pinmux = <0x1e0006>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + edp0-1-cfg { + + edp0-0-pins { + pinmux = <0x390004>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + edp1-0-cfg { + + edp1-0-pins { + pinmux = <0x1f0006>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + dp0-0-cfg { + + dp0-0-pins { + pinmux = <0x90006>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + dp0-1-cfg { + + dp0-0-pins { + pinmux = <0x170006>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + dp0-2-cfg { + + dp0-0-pins { + pinmux = <0x610005>; + bias-disable; + drive-strength = <0x19>; + power-source = <0xce4>; + }; + }; + + dp0-3-cfg { + + dp0-0-pins { + pinmux = <0x7c0004>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + dp1-0-cfg { + + dp1-0-pins { + pinmux = <0xa0006>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + dp1-1-cfg { + + dp1-0-pins { + pinmux = <0x180006>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + dp1-2-cfg { + + dp1-0-pins { + pinmux = <0x450004>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + dp1-3-cfg { + phandle = <0xff>; + + dp1-0-pins { + pinmux = <0x480004>; + bias-disable; + drive-strength = <0x19>; + power-source = <0xce4>; + }; + }; + + dp1-4-cfg { + + dp1-0-pins { + pinmux = <0x620005>; + bias-disable; + drive-strength = <0x19>; + power-source = <0xce4>; + }; + }; + + dp1-5-cfg { + + dp1-0-pins { + pinmux = <0x7d0004>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + usb20_host_drv-0-cfg { + + usb20_host_drv-pins { + pinmux = <0x100006>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + usb20_host_drv-1-cfg { + + usb20_host_drv-pins { + pinmux = <0x270005>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + usb20_host_drv-2-cfg { + + usb20_host_drv-pins { + pinmux = <0x490005>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + usb20_host_drv-3-cfg { + + usb20_host_drv-pins { + pinmux = <0x670003>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + usb20_host_drv-4-cfg { + + usb20_host_drv-pins { + pinmux = <0x6c0002>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + usb30_drd-0-cfg { + + usb30_drd-pins { + pinmux = <0x110006 0x120006 0x130006>; + bias-pull-down; + drive-strength = <0x19>; + }; + }; + + usb30_drd-1-cfg { + + usb30_drd-pins { + pinmux = <0x5f0003 0x600003 0x610003>; + bias-pull-down; + drive-strength = <0x19>; + }; + }; + + usb30_drd-2-cfg { + + usb30_drd-pins { + pinmux = <0x740002 0x750002 0x760002>; + bias-pull-down; + drive-strength = <0x19>; + }; + }; + + usb30_drd_int-0-cfg { + + usb30_drd_int-pins { + pinmux = <0x6f0005>; + bias-pull-down; + drive-strength = <0x19>; + }; + }; + + usb30_drd_int-1-cfg { + + usb30_drd_int-pins { + pinmux = <0x770002>; + bias-pull-down; + drive-strength = <0x19>; + }; + }; + + usb30_b_drv-0-cfg { + + usb30_c_drv-pins { + pinmux = <0x540004>; + bias-pull-down; + drive-strength = <0x19>; + }; + }; + + usb30_c_drv-0-cfg { + + usb30_c_drv-pins { + pinmux = <0x550004>; + bias-pull-down; + drive-strength = <0x19>; + }; + }; + + usb30_c_drv-1-cfg { + + usb30_c_drv-pins { + pinmux = <0x7f0006>; + bias-pull-down; + drive-strength = <0x19>; + }; + }; + + usb30_d_drv-0-cfg { + + usb30_d_drv-pins { + pinmux = <0x140006>; + bias-pull-down; + drive-strength = <0x19>; + }; + }; + + usb30_d_drv-1-cfg { + + usb30_d_drv-pins { + pinmux = <0x1b0005>; + bias-pull-down; + drive-strength = <0x19>; + }; + }; + + usb30_d_drv-2-cfg { + + usb30_d_drv-pins { + pinmux = <0x700005>; + bias-pull-down; + drive-strength = <0x19>; + }; + }; + + usb30h1_drv-0-cfg { + + usb30h1_drv-pins { + pinmux = <0x4a0005>; + bias-pull-down; + drive-strength = <0x19>; + }; + }; + + usb30h1_drv-1-cfg { + + usb30h1_drv-pins { + pinmux = <0x680003>; + bias-pull-down; + drive-strength = <0x19>; + }; + }; + + usb30h2_drv-0-cfg { + + usb30h2_drv-pins { + pinmux = <0x4b0005>; + bias-pull-down; + drive-strength = <0x19>; + }; + }; + + usb30_drd_dir-0-cfg { + + usb30_drd_dir-pins { + pinmux = <0x560006>; + bias-pull-down; + drive-strength = <0x19>; + }; + }; + + usb30_drd_dir-1-cfg { + + usb30_drd_dir-pins { + pinmux = <0x6b0004>; + bias-pull-down; + drive-strength = <0x19>; + }; + }; + + fusb301-cfg { + phandle = <0x8a>; + + fusb301-0-pins { + pinmux = <0x3a0000>; + bias-pull-up; + drive-strength = <0x19>; + power-source = <0x708>; + }; + }; + + m2-wdis1-cfg { + phandle = <0x101>; + + m2-wdis1-pins { + pinmux = <0x490000>; + bias-pull-up; + drive-strength = <0x26>; + power-source = <0xce4>; + }; + }; + + m2-wdis2-cfg { + phandle = <0x102>; + + m2-wdis2-pins { + pinmux = <0x390000>; + bias-pull-up; + drive-strength = <0x26>; + power-source = <0xce4>; + }; + }; + + cam-mux-cfg { + phandle = <0x94>; + + cam-mux-pins { + pinmux = <0x670000>; + bias-pull-up; + drive-strength = <0x19>; + power-source = <0x708>; + }; + }; + + mmc1-cd-cfg { + phandle = <0xd2>; + + mmc1-cd-pins { + pinmux = <0x40000>; + bias-pull-up = <0x01>; + drive-strength = <0x08>; + power-source = <0xce4>; + }; + }; + }; + + pdma@d4000000 { + compatible = "spacemit,k1-pdma"; + reg = <0x00 0xd4000000 0x00 0x4000>; + interrupt-parent = <0x82>; + interrupts = <0x48 0x04>; + clocks = <0x05 0x27>; + resets = <0x05 0x17>; + #dma-cells = <0x01>; + #dma-channels = <0x10>; + max-burst-size = <0x40>; + status = "okay"; + phandle = <0x97>; + }; + + pdma@f0600000 { + compatible = "spacemit,k1-pdma"; + reg = <0x00 0xf0600000 0x00 0x4000>; + interrupt-parent = <0x82>; + interrupts = <0x96 0x04>; + #dma-cells = <0x01>; + #dma-channels = <0x10>; + max-burst-size = <0x40>; + status = "disabled"; + }; + + udma { + compatible = "spacemit,udma"; + status = "okay"; + }; + + serial@d4017000 { + compatible = "spacemit,k1-uart\0intel,xscale-uart"; + reg = <0x00 0xd4017000 0x00 0x100>; + clocks = <0x81 0x00 0x81 0x0a 0x80 0x19>; + clock-names = "core\0bus\0gate"; + resets = <0x81 0x00>; + reg-shift = <0x02>; + reg-io-width = <0x04>; + fifo-size = <0x100>; + tx-threshold = <0x20>; + interrupt-parent = <0x82>; + interrupts = <0x2a 0x04>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <0x86>; + }; + + serial@f0612000 { + compatible = "spacemit,k1-uart\0intel,xscale-uart"; + reg = <0x00 0xf0612000 0x00 0x100>; + clocks = <0x87 0x00 0x87 0x01 0x80 0x19>; + clock-names = "core\0bus\0gate"; + resets = <0x87 0x00>; + reg-shift = <0x02>; + reg-io-width = <0x04>; + fifo-size = <0x100>; + tx-threshold = <0x20>; + interrupt-parent = <0x82>; + interrupts = <0x2b 0x04>; + status = "disabled"; + }; + + serial@d4017100 { + compatible = "spacemit,k1-uart\0intel,xscale-uart"; + reg = <0x00 0xd4017100 0x00 0x100>; + clocks = <0x81 0x01 0x81 0x0b 0x80 0x19>; + clock-names = "core\0bus\0gate"; + resets = <0x81 0x01>; + reg-shift = <0x02>; + reg-io-width = <0x04>; + fifo-size = <0x100>; + tx-threshold = <0x20>; + interrupt-parent = <0x82>; + interrupts = <0x2c 0x04>; + status = "disabled"; + }; + + serial@d4017200 { + compatible = "spacemit,k1-uart\0intel,xscale-uart"; + reg = <0x00 0xd4017200 0x00 0x100>; + clocks = <0x81 0x02 0x81 0x0c 0x80 0x19>; + clock-names = "core\0bus\0gate"; + resets = <0x81 0x02>; + reg-shift = <0x02>; + reg-io-width = <0x04>; + fifo-size = <0x100>; + tx-threshold = <0x20>; + interrupt-parent = <0x82>; + interrupts = <0x2d 0x04>; + status = "disabled"; + }; + + serial@d4017300 { + compatible = "spacemit,k1-uart\0intel,xscale-uart"; + reg = <0x00 0xd4017300 0x00 0x100>; + clocks = <0x81 0x03 0x81 0x0d 0x80 0x19>; + clock-names = "core\0bus\0gate"; + resets = <0x81 0x03>; + reg-shift = <0x02>; + reg-io-width = <0x04>; + fifo-size = <0x100>; + tx-threshold = <0x20>; + interrupt-parent = <0x82>; + interrupts = <0x2e 0x04>; + status = "disabled"; + }; + + serial@d4017400 { + compatible = "spacemit,k1-uart\0intel,xscale-uart"; + reg = <0x00 0xd4017400 0x00 0x100>; + clocks = <0x81 0x04 0x81 0x0e 0x80 0x19>; + clock-names = "core\0bus\0gate"; + resets = <0x81 0x04>; + reg-shift = <0x02>; + reg-io-width = <0x04>; + fifo-size = <0x100>; + tx-threshold = <0x20>; + interrupt-parent = <0x82>; + interrupts = <0x2f 0x04>; + status = "disabled"; + }; + + serial@d4017500 { + compatible = "spacemit,k1-uart\0intel,xscale-uart"; + reg = <0x00 0xd4017500 0x00 0x100>; + clocks = <0x81 0x05 0x81 0x0f 0x80 0x19>; + clock-names = "core\0bus\0gate"; + resets = <0x81 0x05>; + reg-shift = <0x02>; + reg-io-width = <0x04>; + fifo-size = <0x100>; + tx-threshold = <0x20>; + interrupt-parent = <0x82>; + interrupts = <0x30 0x04>; + status = "disabled"; + }; + + serial@d4017600 { + compatible = "spacemit,k1-uart\0intel,xscale-uart"; + reg = <0x00 0xd4017600 0x00 0x100>; + clocks = <0x81 0x06 0x81 0x10 0x80 0x19>; + clock-names = "core\0bus\0gate"; + resets = <0x81 0x06>; + reg-shift = <0x02>; + reg-io-width = <0x04>; + fifo-size = <0x100>; + tx-threshold = <0x20>; + interrupt-parent = <0x82>; + interrupts = <0x31 0x04>; + status = "disabled"; + }; + + serial@d4017700 { + compatible = "spacemit,k1-uart\0intel,xscale-uart"; + reg = <0x00 0xd4017700 0x00 0x100>; + clocks = <0x81 0x07 0x81 0x11 0x80 0x19>; + clock-names = "core\0bus\0gate"; + resets = <0x81 0x07>; + reg-shift = <0x02>; + reg-io-width = <0x04>; + fifo-size = <0x100>; + tx-threshold = <0x20>; + interrupt-parent = <0x82>; + interrupts = <0x32 0x04>; + status = "disabled"; + }; + + serial@d4017800 { + compatible = "spacemit,k1-uart\0intel,xscale-uart"; + reg = <0x00 0xd4017800 0x00 0x100>; + clocks = <0x81 0x08 0x81 0x12 0x80 0x19>; + clock-names = "core\0bus\0gate"; + resets = <0x81 0x08>; + reg-shift = <0x02>; + reg-io-width = <0x04>; + fifo-size = <0x100>; + tx-threshold = <0x20>; + interrupt-parent = <0x82>; + interrupts = <0x33 0x04>; + status = "disabled"; + }; + + serial@d401f000 { + compatible = "spacemit,k1-uart\0intel,xscale-uart"; + reg = <0x00 0xd401f000 0x00 0x100>; + clocks = <0x81 0x09 0x81 0x13 0x80 0x19>; + clock-names = "core\0bus\0gate"; + resets = <0x81 0x09>; + reg-shift = <0x02>; + reg-io-width = <0x04>; + fifo-size = <0x100>; + tx-threshold = <0x20>; + interrupt-parent = <0x82>; + interrupts = <0x119 0x04>; + status = "disabled"; + }; + + i2c@d4010800 { + compatible = "spacemit,k1-i2c"; + reg = <0x00 0xd4010800 0x00 0x38>; + #address-cells = <0x01>; + #size-cells = <0x00>; + interrupt-parent = <0x82>; + interrupts = <0x24 0x04>; + clocks = <0x81 0x49 0x81 0x50>; + clock-names = "func\0bus"; + clock-frequency = <0x61a80>; + resets = <0x81 0x23>; + power-domains = <0x88 0x05>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <0x89>; + + tcpc@25 { + compatible = "onsemi,fusb301"; + reg = <0x25>; + pinctrl-names = "default"; + pinctrl-0 = <0x8a>; + irq-gpios = <0x8b 0x01 0x1a 0x01>; + suspend-vbus-off; + status = "okay"; + + connector@0 { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + typec-power-opmode = "default"; + pd-disable; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint { + remote-endpoint = <0x8c>; + phandle = <0xbf>; + }; + }; + + port@1 { + reg = <0x01>; + + endpoint { + remote-endpoint = <0x8d>; + phandle = <0xbc>; + }; + }; + }; + }; + }; + }; + + i2c@d4011000 { + compatible = "spacemit,k1-i2c"; + reg = <0x00 0xd4011000 0x00 0x38>; + #address-cells = <0x01>; + #size-cells = <0x00>; + interrupt-parent = <0x82>; + interrupts = <0x25 0x04>; + clocks = <0x81 0x4a 0x81 0x51>; + clock-names = "func\0bus"; + clock-frequency = <0x61a80>; + resets = <0x81 0x24>; + power-domains = <0x88 0x05>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <0x8e>; + + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + read-only; + status = "okay"; + + nvmem-layout { + compatible = "onie,tlv-layout"; + + product-name { + }; + }; + }; + }; + + i2c@d4012000 { + compatible = "spacemit,k1-i2c"; + reg = <0x00 0xd4012000 0x00 0x38>; + #address-cells = <0x01>; + #size-cells = <0x00>; + interrupt-parent = <0x82>; + interrupts = <0x26 0x04>; + clocks = <0x81 0x4b 0x81 0x52>; + clock-names = "func\0bus"; + clock-frequency = <0x61a80>; + resets = <0x81 0x25>; + power-domains = <0x88 0x05>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <0x8f>; + }; + + i2c@f0614000 { + compatible = "spacemit,k1-i2c"; + reg = <0x00 0xf0614000 0x00 0x38>; + #address-cells = <0x01>; + #size-cells = <0x00>; + interrupt-parent = <0x82>; + interrupts = <0x27 0x04>; + clocks = <0x87 0x05 0x87 0x06>; + clock-names = "func\0bus"; + clock-frequency = <0x61a80>; + resets = <0x87 0x02>; + power-domains = <0x88 0x05>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <0x90>; + + raspits-panel@45 { + status = "okay"; + compatible = "raspberrypi,7inch-touchscreen-panel"; + reg = <0x45>; + + port { + + endpoint { + remote-endpoint = <0x91>; + phandle = <0xf8>; + }; + }; + }; + + raspits-touch-ft5426@38 { + status = "okay"; + compatible = "raspits_ft5426"; + reg = <0x38>; + }; + }; + + i2c@d4012800 { + compatible = "spacemit,k1-i2c"; + reg = <0x00 0xd4012800 0x00 0x38>; + #address-cells = <0x01>; + #size-cells = <0x00>; + interrupt-parent = <0x82>; + interrupts = <0x28 0x04>; + clocks = <0x81 0x4c 0x81 0x53>; + clock-names = "func\0bus"; + clock-frequency = <0x61a80>; + resets = <0x81 0x26>; + power-domains = <0x88 0x05>; + status = "disabled"; + }; + + i2c@d4013800 { + compatible = "spacemit,k1-i2c"; + reg = <0x00 0xd4013800 0x00 0x38>; + #address-cells = <0x01>; + #size-cells = <0x00>; + interrupt-parent = <0x82>; + interrupts = <0x29 0x04>; + clocks = <0x81 0x4d 0x81 0x54>; + clock-names = "func\0bus"; + clock-frequency = <0x61a80>; + resets = <0x81 0x27>; + power-domains = <0x88 0x05>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <0x92>; + + imx219@10 { + compatible = "sony,imx219"; + reg = <0x10>; + csi-id = <0x01>; + vdd-supply = <0x93>; + pwdn-gpios = <0x8b 0x01 0x0d 0x00>; + status = "okay"; + }; + + ov5647@36 { + compatible = "ovti,ov5647"; + reg = <0x36>; + csi-id = <0x02>; + vdd-supply = <0x93>; + pinctrl-names = "default"; + pinctrl-0 = <0x94>; + i2c-mux-gpios = <0x8b 0x03 0x07 0x00>; + pwdn-gpios = <0x8b 0x01 0x0c 0x00>; + status = "okay"; + }; + + ov5640@3c { + compatible = "spacemit,ov5640-max96724-max9295"; + reg = <0x3c>; + csi-id = <0x00>; + vdd-supply = <0x93>; + clock-names = "xclk"; + clocks = <0x05 0x5d>; + pinctrl-names = "default"; + pinctrl-0 = <0x95>; + pwdn-gpios = <0x8b 0x01 0x0c 0x00>; + deserializer-addr = <0x27>; + serializer-base-addr = <0x41>; + status = "okay"; + }; + + imx415@37 { + compatible = "sony,imx415"; + reg = <0x37>; + csi-id = <0x02>; + vdd-supply = <0x93>; + pinctrl-names = "default"; + pinctrl-0 = <0x94>; + i2c-mux-gpios = <0x8b 0x03 0x07 0x00>; + pwdn-gpios = <0x8b 0x01 0x0c 0x00>; + status = "disabled"; + }; + }; + + i2c@d4018800 { + compatible = "spacemit,k1-i2c"; + reg = <0x00 0xd4018800 0x00 0x38>; + #address-cells = <0x01>; + #size-cells = <0x00>; + interrupt-parent = <0x82>; + interrupts = <0x46 0x04>; + clocks = <0x81 0x4e 0x81 0x55>; + clock-names = "func\0bus"; + clock-frequency = <0x61a80>; + resets = <0x81 0x28>; + power-domains = <0x88 0x05>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <0x96>; + + ctf2301@4c { + compatible = "sensylink,ctf2301"; + reg = <0x4c>; + #cooling-cells = <0x02>; + phandle = <0xb0>; + }; + }; + + i2c@d401d800 { + compatible = "spacemit,k1-i2c"; + reg = <0x00 0xd401d800 0x00 0x38>; + #address-cells = <0x01>; + #size-cells = <0x00>; + interrupt-parent = <0x82>; + interrupts = <0x13 0x04>; + clocks = <0x81 0x4f 0x81 0x56>; + clock-names = "func\0bus"; + clock-frequency = <0x61a80>; + resets = <0x81 0x29>; + power-domains = <0x88 0x05>; + status = "disabled"; + }; + + pwm@d401a000 { + compatible = "spacemit,k1-pwm\0marvell,pxa910-pwm"; + reg = <0x00 0xd401a000 0x00 0x10>; + clocks = <0x81 0x16 0x81 0x2a>; + clock-names = "func\0bus"; + resets = <0x81 0x0b>; + #pwm-cells = <0x03>; + k1,pwm-disable-fd; + status = "disabled"; + }; + + pwm@d401a400 { + compatible = "spacemit,k1-pwm\0marvell,pxa910-pwm"; + reg = <0x00 0xd401a400 0x00 0x10>; + clocks = <0x81 0x17 0x81 0x2b>; + clock-names = "func\0bus"; + resets = <0x81 0x0c>; + #pwm-cells = <0x03>; + k1,pwm-disable-fd; + status = "disabled"; + }; + + pwm@d401a800 { + compatible = "spacemit,k1-pwm\0marvell,pxa910-pwm"; + reg = <0x00 0xd401a800 0x00 0x10>; + clocks = <0x81 0x18 0x81 0x2c>; + clock-names = "func\0bus"; + resets = <0x81 0x0d>; + #pwm-cells = <0x03>; + k1,pwm-disable-fd; + status = "disabled"; + }; + + pwm@d401ac00 { + compatible = "spacemit,k1-pwm\0marvell,pxa910-pwm"; + reg = <0x00 0xd401ac00 0x00 0x10>; + clocks = <0x81 0x19 0x81 0x2d>; + clock-names = "func\0bus"; + resets = <0x81 0x0e>; + #pwm-cells = <0x03>; + k1,pwm-disable-fd; + status = "disabled"; + }; + + pwm@d401b000 { + compatible = "spacemit,k1-pwm\0marvell,pxa910-pwm"; + reg = <0x00 0xd401b000 0x00 0x10>; + clocks = <0x81 0x1a 0x81 0x2e>; + clock-names = "func\0bus"; + resets = <0x81 0x0f>; + #pwm-cells = <0x03>; + k1,pwm-disable-fd; + status = "disabled"; + }; + + pwm@d401b400 { + compatible = "spacemit,k1-pwm\0marvell,pxa910-pwm"; + reg = <0x00 0xd401b400 0x00 0x10>; + clocks = <0x81 0x1b 0x81 0x2f>; + clock-names = "func\0bus"; + resets = <0x81 0x10>; + #pwm-cells = <0x03>; + k1,pwm-disable-fd; + status = "disabled"; + }; + + pwm@d401b800 { + compatible = "spacemit,k1-pwm\0marvell,pxa910-pwm"; + reg = <0x00 0xd401b800 0x00 0x10>; + clocks = <0x81 0x1c 0x81 0x30>; + clock-names = "func\0bus"; + resets = <0x81 0x11>; + #pwm-cells = <0x03>; + k1,pwm-disable-fd; + status = "disabled"; + }; + + pwm@d401bc00 { + compatible = "spacemit,k1-pwm\0marvell,pxa910-pwm"; + reg = <0x00 0xd401bc00 0x00 0x10>; + clocks = <0x81 0x1d 0x81 0x31>; + clock-names = "func\0bus"; + resets = <0x81 0x12>; + #pwm-cells = <0x03>; + k1,pwm-disable-fd; + status = "disabled"; + }; + + pwm@d4020000 { + compatible = "spacemit,k1-pwm\0marvell,pxa910-pwm"; + reg = <0x00 0xd4020000 0x00 0x10>; + clocks = <0x81 0x1e 0x81 0x32>; + clock-names = "func\0bus"; + resets = <0x81 0x13>; + #pwm-cells = <0x03>; + k1,pwm-disable-fd; + status = "disabled"; + }; + + pwm@d4020400 { + compatible = "spacemit,k1-pwm\0marvell,pxa910-pwm"; + reg = <0x00 0xd4020400 0x00 0x10>; + clocks = <0x81 0x1f 0x81 0x33>; + clock-names = "func\0bus"; + resets = <0x81 0x14>; + #pwm-cells = <0x03>; + k1,pwm-disable-fd; + status = "disabled"; + }; + + pwm@d4020800 { + compatible = "spacemit,k1-pwm\0marvell,pxa910-pwm"; + reg = <0x00 0xd4020800 0x00 0x10>; + clocks = <0x81 0x20 0x81 0x34>; + clock-names = "func\0bus"; + resets = <0x81 0x15>; + #pwm-cells = <0x03>; + k1,pwm-disable-fd; + status = "disabled"; + }; + + pwm@d4020c00 { + compatible = "spacemit,k1-pwm\0marvell,pxa910-pwm"; + reg = <0x00 0xd4020c00 0x00 0x10>; + clocks = <0x81 0x21 0x81 0x35>; + clock-names = "func\0bus"; + resets = <0x81 0x16>; + #pwm-cells = <0x03>; + k1,pwm-disable-fd; + status = "disabled"; + }; + + pwm@d4021000 { + compatible = "spacemit,k1-pwm\0marvell,pxa910-pwm"; + reg = <0x00 0xd4021000 0x00 0x10>; + clocks = <0x81 0x22 0x81 0x36>; + clock-names = "func\0bus"; + resets = <0x81 0x17>; + #pwm-cells = <0x03>; + k1,pwm-disable-fd; + status = "disabled"; + }; + + pwm@d4021400 { + compatible = "spacemit,k1-pwm\0marvell,pxa910-pwm"; + reg = <0x00 0xd4021400 0x00 0x10>; + clocks = <0x81 0x23 0x81 0x37>; + clock-names = "func\0bus"; + resets = <0x81 0x18>; + #pwm-cells = <0x03>; + k1,pwm-disable-fd; + status = "disabled"; + }; + + pwm@d4021800 { + compatible = "spacemit,k1-pwm\0marvell,pxa910-pwm"; + reg = <0x00 0xd4021800 0x00 0x10>; + clocks = <0x81 0x24 0x81 0x38>; + clock-names = "func\0bus"; + resets = <0x81 0x19>; + #pwm-cells = <0x03>; + k1,pwm-disable-fd; + status = "disabled"; + }; + + pwm@d4021c00 { + compatible = "spacemit,k1-pwm\0marvell,pxa910-pwm"; + reg = <0x00 0xd4021c00 0x00 0x10>; + clocks = <0x81 0x25 0x81 0x39>; + clock-names = "func\0bus"; + resets = <0x81 0x1a>; + #pwm-cells = <0x03>; + k1,pwm-disable-fd; + status = "disabled"; + }; + + pwm@d4022000 { + compatible = "spacemit,k1-pwm\0marvell,pxa910-pwm"; + reg = <0x00 0xd4022000 0x00 0x10>; + clocks = <0x81 0x26 0x81 0x3a>; + clock-names = "func\0bus"; + resets = <0x81 0x1b>; + #pwm-cells = <0x03>; + k1,pwm-disable-fd; + status = "disabled"; + }; + + pwm@d4022400 { + compatible = "spacemit,k1-pwm\0marvell,pxa910-pwm"; + reg = <0x00 0xd4022400 0x00 0x10>; + clocks = <0x81 0x27 0x81 0x3b>; + clock-names = "func\0bus"; + resets = <0x81 0x1c>; + #pwm-cells = <0x03>; + k1,pwm-disable-fd; + status = "disabled"; + }; + + pwm@d4022800 { + compatible = "spacemit,k1-pwm\0marvell,pxa910-pwm"; + reg = <0x00 0xd4022800 0x00 0x10>; + clocks = <0x81 0x28 0x81 0x3c>; + clock-names = "func\0bus"; + resets = <0x81 0x1d>; + #pwm-cells = <0x03>; + k1,pwm-disable-fd; + status = "disabled"; + }; + + pwm@d4022c00 { + compatible = "spacemit,k1-pwm\0marvell,pxa910-pwm"; + reg = <0x00 0xd4022c00 0x00 0x10>; + clocks = <0x81 0x29 0x81 0x3d>; + clock-names = "func\0bus"; + resets = <0x81 0x1e>; + #pwm-cells = <0x03>; + k1,pwm-disable-fd; + status = "disabled"; + }; + + spi@d4040000 { + compatible = "spacemit,k3-spi"; + reg = <0x00 0xd4040000 0x00 0x30>; + dmas = <0x97 0x40 0x97 0x41>; + dma-names = "tx\0rx"; + interrupt-parent = <0x82>; + interrupts = <0x11b 0x04>; + clocks = <0x81 0x41 0x81 0x44>; + clock-names = "func\0bus"; + resets = <0x81 0x1f>; + spi-max-frequency = <0x30d4000>; + #address-cells = <0x01>; + #size-cells = <0x00>; + status = "disabled"; + }; + + spi@d4040800 { + compatible = "spacemit,k3-spi"; + reg = <0x00 0xd4040800 0x00 0x30>; + dmas = <0x97 0x42 0x97 0x43>; + dma-names = "tx\0rx"; + interrupt-parent = <0x82>; + interrupts = <0x11a 0x04>; + clocks = <0x81 0x42 0x81 0x45>; + clock-names = "func\0bus"; + resets = <0x81 0x20>; + spi-max-frequency = <0x30d4000>; + #address-cells = <0x01>; + #size-cells = <0x00>; + status = "disabled"; + }; + + spi@f0613000 { + compatible = "spacemit,k3-spi"; + reg = <0x00 0xf0613000 0x00 0x30>; + interrupt-parent = <0x82>; + interrupts = <0x36 0x04>; + clocks = <0x87 0x03 0x87 0x04>; + clock-names = "func\0bus"; + resets = <0x87 0x01>; + spi-max-frequency = <0x30d4000>; + #address-cells = <0x01>; + #size-cells = <0x00>; + status = "disabled"; + }; + + spi@d401c000 { + compatible = "spacemit,k3-spi"; + reg = <0x00 0xd401c000 0x00 0x30>; + dmas = <0x97 0x13 0x97 0x14>; + dma-names = "tx\0rx"; + interrupt-parent = <0x82>; + interrupts = <0x37 0x04>; + clocks = <0x81 0x43 0x81 0x46>; + clock-names = "func\0bus"; + resets = <0x81 0x21>; + spi-max-frequency = <0x30d4000>; + #address-cells = <0x01>; + #size-cells = <0x00>; + status = "disabled"; + }; + + spi@d420c000 { + compatible = "spacemit,k3-qspi"; + #address-cells = <0x01>; + #size-cells = <0x00>; + reg = <0x00 0xd420c000 0x00 0x1000 0x00 0xb8000000 0x00 0xc00000>; + reg-names = "QuadSPI\0QuadSPI-memory"; + clocks = <0x05 0x25 0x05 0x26>; + clock-names = "qspi\0qspi_en"; + resets = <0x05 0x15 0x05 0x16>; + reset-names = "qspi_reset\0qspi_bus_reset"; + interrupts = <0x75 0x04>; + interrupt-parent = <0x82>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <0x98>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x00>; + spi-max-frequency = <0x1945ba0>; + m25p,fast-read; + broken-flash-reset; + status = "okay"; + }; + }; + + v2d@c0100000 { + compatible = "spacemit,v2d"; + reg = <0x00 0xc0100000 0x00 0x1000>; + reg-names = "v2dreg"; + clocks = <0x05 0x18 0x05 0x13>; + clock-names = "v2d-io\0v2d-core"; + resets = <0x05 0x06>; + reset-names = "v2d_reset"; + interrupt-parent = <0x82>; + interrupts = <0x56 0x04>; + status = "okay"; + }; + + mailbox0@cac90000 { + compatible = "spacemit,k3-mailbox"; + reg = <0x00 0xcac90000 0x00 0x400>; + interrupt-parent = <0x82>; + interrupts = <0xd2 0x04>; + #mbox-cells = <0x01>; + status = "okay"; + }; + + mailbox1@cac90400 { + compatible = "spacemit,k3-mailbox"; + reg = <0x00 0xcac90400 0x00 0x400>; + interrupt-parent = <0x82>; + interrupts = <0xd4 0x04>; + #mbox-cells = <0x01>; + status = "okay"; + }; + + mailbox2@cac90800 { + compatible = "spacemit,k3-mailbox"; + reg = <0x00 0xcac90800 0x00 0x400>; + interrupt-parent = <0x82>; + interrupts = <0xd6 0x04>; + #mbox-cells = <0x01>; + status = "okay"; + }; + + mailbox3@cac90c00 { + compatible = "spacemit,k3-mailbox"; + reg = <0x00 0xcac90c00 0x00 0x400>; + interrupt-parent = <0x82>; + interrupts = <0xd8 0x04>; + #mbox-cells = <0x01>; + status = "okay"; + phandle = <0x99>; + }; + + mailbox4@cac91000 { + compatible = "spacemit,k3-mailbox"; + reg = <0x00 0xcac91000 0x00 0x400>; + interrupt-parent = <0x82>; + interrupts = <0xd9 0x04>; + #mbox-cells = <0x01>; + status = "okay"; + phandle = <0xa1>; + }; + + mailbox5@cac91400 { + compatible = "spacemit,k3-mailbox"; + reg = <0x00 0xcac91400 0x00 0x400>; + interrupt-parent = <0x82>; + interrupts = <0xe2 0x04>; + #mbox-cells = <0x01>; + status = "okay"; + }; + + mailbox6@cac91800 { + compatible = "spacemit,k3-mailbox"; + reg = <0x00 0xcac91800 0x00 0x400>; + interrupt-parent = <0x82>; + interrupts = <0xe3 0x04>; + #mbox-cells = <0x01>; + status = "okay"; + }; + + rcpu_rproc0@0 { + compatible = "spacemit,k3-rproc"; + reg = <0x00 0x00 0x00 0x00>; + mboxes = <0x99 0x01 0x99 0x02>; + mbox-names = "vq0\0vq1"; + firmware-name = "rt24_os0_rcpu.elf"; + memory-region = <0x9a 0x9b 0x9c 0x9d 0x9e 0x9f>; + status = "disabled"; + }; + + fdcan@d4028000 { + compatible = "spacemit,k1-flexcan"; + reg = <0x00 0xd4028000 0x00 0x4000>; + interrupts = <0xa1 0x04>; + interrupt-parent = <0x82>; + fsl,clk-source = <0x00>; + clocks = <0x81 0x84 0x81 0x89>; + clock-names = "per\0ipg"; + resets = <0x81 0x3f>; + status = "disabled"; + }; + + fdcan@d402c000 { + compatible = "spacemit,k1-flexcan"; + reg = <0x00 0xd402c000 0x00 0x4000>; + interrupts = <0xa3 0x04>; + interrupt-parent = <0x82>; + fsl,clk-source = <0x00>; + clocks = <0x81 0x85 0x81 0x8a>; + clock-names = "per\0ipg"; + resets = <0x81 0x40>; + status = "disabled"; + }; + + fdcan@d4034000 { + compatible = "spacemit,k1-flexcan"; + reg = <0x00 0xd4034000 0x00 0x4000>; + interrupts = <0xa5 0x04>; + interrupt-parent = <0x82>; + fsl,clk-source = <0x00>; + clocks = <0x81 0x86 0x81 0x8b>; + clock-names = "per\0ipg"; + resets = <0x81 0x41>; + status = "okay"; + clock-frequency = <0x4c4b400>; + pinctrl-names = "default"; + pinctrl-0 = <0xa0>; + }; + + fdcan@d4038000 { + compatible = "spacemit,k1-flexcan"; + reg = <0x00 0xd4038000 0x00 0x4000>; + interrupts = <0xa7 0x04>; + interrupt-parent = <0x82>; + fsl,clk-source = <0x00>; + clocks = <0x81 0x87 0x81 0x8c>; + clock-names = "per\0ipg"; + resets = <0x81 0x42>; + status = "disabled"; + }; + + fdcan@d403c000 { + compatible = "spacemit,k1-flexcan"; + reg = <0x00 0xd403c000 0x00 0x4000>; + interrupts = <0xa9 0x04>; + interrupt-parent = <0x82>; + fsl,clk-source = <0x00>; + clocks = <0x81 0x88 0x81 0x8d>; + clock-names = "per\0ipg"; + resets = <0x81 0x43>; + status = "disabled"; + }; + + rcpu_rproc1@1 { + compatible = "spacemit,k3-rproc"; + reg = <0x00 0x00 0x00 0x00>; + mboxes = <0xa1 0x00 0xa1 0x01>; + mbox-names = "vq0\0vq1"; + firmware-name = "rt24_os1_rcpu.elf"; + memory-region = <0xa2 0xa3 0xa4 0xa5 0xa6 0xa7>; + status = "okay"; + }; + + mpxy_mbox@0 { + compatible = "riscv,sbi-mpxy-mbox"; + #mbox-cells = <0x02>; + status = "okay"; + phandle = <0xa8>; + }; + + rpmi_regulator@0 { + compatible = "riscv,rpmi-regulator"; + mboxes = <0xa8 0x07 0x00>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <0xa9>; + + pvin { + regulator-min-microvolt = <0x4c4b40>; + regulator-max-microvolt = <0x4c4b40>; + regulator-always-on; + regulator-boot-on; + }; + + edcdc2 { + regulator-min-microvolt = <0x825f0>; + regulator-max-microvolt = <0xf55c8>; + regulator-always-on; + regulator-boot-on; + }; + + edcdc1 { + regulator-min-microvolt = <0x825f0>; + regulator-max-microvolt = <0xf55c8>; + regulator-always-on; + regulator-boot-on; + phandle = <0x04>; + }; + + p3v3 { + regulator-min-microvolt = <0x325aa0>; + regulator-max-microvolt = <0x325aa0>; + regulator-always-on; + regulator-boot-on; + phandle = <0xd4>; + }; + + p1v8 { + regulator-min-microvolt = <0x1b7740>; + regulator-max-microvolt = <0x1b7740>; + regulator-always-on; + regulator-boot-on; + }; + + dcdc1 { + regulator-min-microvolt = <0x100590>; + regulator-max-microvolt = <0x100590>; + regulator-always-on; + regulator-boot-on; + }; + + dcdc3 { + regulator-min-microvolt = "\0\f5"; + regulator-max-microvolt = "\0\f5"; + regulator-always-on; + regulator-boot-on; + }; + + dcdc4 { + regulator-min-microvolt = <0x200b20>; + regulator-max-microvolt = <0x200b20>; + regulator-always-on; + regulator-boot-on; + }; + + dcdc5 { + regulator-min-microvolt = <0x1b7740>; + regulator-max-microvolt = <0x1b7740>; + regulator-always-on; + regulator-boot-on; + }; + + dcdc6 { + regulator-min-microvolt = <0x7a120>; + regulator-max-microvolt = <0x927c0>; + regulator-always-on; + regulator-boot-on; + }; + + aldo1 { + regulator-min-microvolt = <0x1b7740>; + regulator-max-microvolt = <0x325aa0>; + regulator-always-on; + regulator-boot-on; + phandle = <0xd5>; + }; + + aldo2 { + regulator-min-microvolt = <0x1b7740>; + regulator-max-microvolt = <0x1b7740>; + regulator-always-on; + regulator-boot-on; + }; + + aldo3 { + regulator-min-microvolt = <0x7a120>; + regulator-max-microvolt = <0x33e140>; + phandle = <0x93>; + }; + + aldo4 { + regulator-min-microvolt = <0x325aa0>; + regulator-max-microvolt = <0x325aa0>; + regulator-always-on; + regulator-boot-on; + }; + + dldo1 { + regulator-min-microvolt = <0x124f80>; + regulator-max-microvolt = <0x124f80>; + regulator-always-on; + regulator-boot-on; + }; + + dldo2 { + regulator-min-microvolt = <0xdbba0>; + regulator-max-microvolt = <0xdbba0>; + regulator-always-on; + regulator-boot-on; + }; + + dldo3 { + regulator-min-microvolt = "\0\f5"; + regulator-max-microvolt = "\0\f5"; + regulator-always-on; + regulator-boot-on; + }; + + dldo4 { + regulator-min-microvolt = <0x1b7740>; + regulator-max-microvolt = <0x1b7740>; + regulator-always-on; + regulator-boot-on; + }; + + dldo5 { + regulator-min-microvolt = <0x1b7740>; + regulator-max-microvolt = <0x1b7740>; + regulator-always-on; + regulator-boot-on; + }; + + dldo6 { + regulator-min-microvolt = <0x1b7740>; + regulator-max-microvolt = <0x1b7740>; + regulator-always-on; + regulator-boot-on; + }; + + dldo7 { + regulator-min-microvolt = <0x1b7740>; + regulator-max-microvolt = <0x1b7740>; + regulator-always-on; + regulator-boot-on; + }; + + pwr_x100 { + regulator-min-microvolt = <0x325aa0>; + regulator-max-microvolt = <0x325aa0>; + regulator-always-on; + regulator-boot-on; + }; + + pwr_a100 { + regulator-min-microvolt = <0x325aa0>; + regulator-max-microvolt = <0x325aa0>; + regulator-always-on; + regulator-boot-on; + }; + + pwr_ext { + regulator-min-microvolt = <0x325aa0>; + regulator-max-microvolt = <0x325aa0>; + regulator-always-on; + regulator-boot-on; + }; + }; + + rpmi_rtc@0 { + compatible = "riscv,rpmi-rtc"; + mboxes = <0xa8 0x0e 0x00>; + interrupt-parent = <0x82>; + interrupts = <0x40 0x04>; + interrupt-names = "rpmi rtc"; + status = "okay"; + }; + + rpmi_pwrkey@0 { + compatible = "riscv,rpmi-pwrkey"; + mboxes = <0xa8 0x0f 0x00>; + interrupt-parent = <0x82>; + interrupts = <0x40 0x04>; + interrupt-names = "rpmi pwrkey"; + status = "okay"; + }; + + power-management@0 { + compatible = "simple-bus"; + #address-cells = <0x02>; + #size-cells = <0x02>; + ranges; + + power-controller { + compatible = "spacemit,power-controller"; + mboxes = <0xa8 0x09 0x00>; + #power-domain-cells = <0x01>; + #address-cells = <0x01>; + #size-cells = <0x00>; + status = "okay"; + phandle = <0x88>; + + vpu@0 { + #power-domain-cells = <0x00>; + }; + + gpu@1 { + #power-domain-cells = <0x00>; + }; + + audio@2 { + #power-domain-cells = <0x00>; + }; + + lcd@0 { + #power-domain-cells = <0x00>; + }; + + lcd@1 { + #power-domain-cells = <0x00>; + }; + + dummy@0 { + #power-domain-cells = <0x00>; + }; + }; + }; + + thermal@d4018000 { + compatible = "spacemit,k3-tsensor"; + reg = <0x00 0xd4018000 0x00 0x100>; + interrupt-parent = <0x82>; + interrupts = <0x3d 0x04>; + interrupt-names = "tsensor"; + clocks = <0x81 0x80 0x81 0x81>; + clock-names = "func\0bus"; + resets = <0x81 0x3d>; + sensor_range = <0x00 0x07>; + tsensor_map = <0x01 0x00 0x01 0x01 0x01 0x01 0x01 0x01>; + temperature_offset = <0x112>; + #thermal-sensor-cells = <0x01>; + status = "okay"; + phandle = <0xaa>; + }; + + thermal-zones { + + thermal_top { + polling-delay = <0x3e8>; + polling-delay-passive = <0xfa>; + thermal-sensors = <0xaa 0x00>; + + trips { + + thermal_top-trip0 { + temperature = <0x9c40>; + hysteresis = <0x1388>; + type = "passive"; + }; + }; + }; + + thermal_vpu { + polling-delay = <0x3e8>; + polling-delay-passive = <0xfa>; + thermal-sensors = <0xaa 0x02>; + + trips { + + thermal_vpu-trip0 { + temperature = <0x9c40>; + hysteresis = <0x1388>; + type = "passive"; + }; + }; + }; + + thermal_gpu { + polling-delay = <0x3e8>; + polling-delay-passive = <0x1f4>; + thermal-sensors = <0xaa 0x03>; + + trips { + + gpu-alert0 { + temperature = <0xfde8>; + hysteresis = <0x7d0>; + type = "passive"; + phandle = <0xab>; + }; + + gpu-alert1 { + temperature = <0x124f8>; + hysteresis = <0x7d0>; + type = "passive"; + phandle = <0xad>; + }; + + gpu-alert2 { + temperature = <0x14c08>; + hysteresis = <0x7d0>; + type = "passive"; + phandle = <0xae>; + }; + + gpu-crit { + temperature = <0x1c138>; + hysteresis = <0x7d0>; + type = "critical"; + }; + }; + + cooling-maps { + + map0 { + trip = <0xab>; + cooling-device = <0xac 0x00 0x01>; + }; + + map1 { + trip = <0xad>; + cooling-device = <0xac 0x02 0x03>; + }; + + map2 { + trip = <0xae>; + cooling-device = <0xac 0x04 0x05>; + }; + }; + }; + + thermal_cluster0 { + polling-delay = <0x3e8>; + polling-delay-passive = <0xfa>; + thermal-sensors = <0xaa 0x04>; + + trips { + + thermal_cluster0-trip0 { + temperature = <0x88b8>; + hysteresis = <0x1388>; + type = "active"; + phandle = <0xaf>; + }; + + thermal_cluster0-trip1 { + temperature = <0x9c40>; + hysteresis = <0x1388>; + type = "passive"; + phandle = <0xb1>; + }; + + thermal_cluster0-trip2 { + temperature = <0xc350>; + hysteresis = <0x1388>; + type = "passive"; + phandle = <0xb2>; + }; + + thermal_cluster0-trip3 { + temperature = <0xea60>; + hysteresis = <0x1388>; + type = "passive"; + phandle = <0xb3>; + }; + + thermal_cluster0-trip4 { + temperature = <0x11170>; + hysteresis = <0x1388>; + type = "passive"; + phandle = <0xb4>; + }; + }; + + cooling-maps { + + map0 { + trip = <0xaf>; + cooling-device = <0xb0 0x00 0x32>; + }; + + map1 { + trip = <0xb1>; + cooling-device = <0xb0 0x40 0x4b>; + }; + + map2 { + trip = <0xb2>; + cooling-device = <0xb0 0x66 0x80>; + }; + + map3 { + trip = <0xb3>; + cooling-device = <0xb0 0xb3 0xcc>; + }; + + map4 { + trip = <0xb4>; + cooling-device = <0xb0 0xff 0xff>; + }; + }; + }; + + thermal_cluster1 { + polling-delay = <0x3e8>; + polling-delay-passive = <0xfa>; + thermal-sensors = <0xaa 0x05>; + + trips { + + thermal_cluster1-trip0 { + temperature = <0x14c08>; + hysteresis = <0x7d0>; + type = "active"; + phandle = <0xb5>; + }; + + thermal_cluster1-trip1 { + temperature = <0x17318>; + hysteresis = <0x7d0>; + type = "passive"; + phandle = <0xb6>; + }; + + thermal_cluster1-trip2 { + temperature = <0x19a28>; + hysteresis = <0x7d0>; + type = "passive"; + phandle = <0xb7>; + }; + + thermal_cluster1-trip3 { + temperature = <0x1c138>; + hysteresis = <0x7d0>; + type = "critical"; + }; + }; + + cooling-maps { + + map0 { + trip = <0xb5>; + cooling-device = <0x0b 0x02 0x02 0x0c 0x02 0x02 0x0d 0x02 0x02 0x0e 0x02 0x02 0x0f 0x02 0x02 0x10 0x02 0x02 0x11 0x02 0x02 0x12 0x02 0x02>; + }; + + map1 { + trip = <0xb6>; + cooling-device = <0x0b 0x03 0x05 0x0c 0x03 0x05 0x0d 0x03 0x05 0x0e 0x03 0x05 0x0f 0x03 0x05 0x10 0x03 0x05 0x11 0x03 0x05 0x12 0x03 0x05>; + }; + + map2 { + trip = <0xb7>; + cooling-device = <0x0b 0x06 0x08 0x0c 0x06 0x08 0x0d 0x06 0x08 0x0e 0x06 0x08 0x0f 0x06 0x08 0x10 0x06 0x08 0x11 0x06 0x08 0x12 0x06 0x08>; + }; + }; + }; + + thermal_cluster2 { + polling-delay = <0x3e8>; + polling-delay-passive = <0xfa>; + thermal-sensors = <0xaa 0x06>; + + trips { + + thermal_cluster2-trip0 { + temperature = <0x14c08>; + hysteresis = <0x7d0>; + type = "active"; + phandle = <0xb8>; + }; + + thermal_cluster2-trip1 { + temperature = <0x17318>; + hysteresis = <0x7d0>; + type = "passive"; + phandle = <0xb9>; + }; + + thermal_cluster2-trip2 { + temperature = <0x19a28>; + hysteresis = <0x7d0>; + type = "passive"; + phandle = <0xba>; + }; + + thermal_cluster2-trip3 { + temperature = <0x1c138>; + hysteresis = <0x7d0>; + type = "critical"; + }; + }; + + cooling-maps { + + map0 { + trip = <0xb8>; + cooling-device = <0x13 0x03 0x03 0x14 0x03 0x03 0x15 0x03 0x03 0x16 0x03 0x03 0x17 0x03 0x03 0x18 0x03 0x03 0x19 0x03 0x03 0x1a 0x03 0x03>; + }; + + map1 { + trip = <0xb9>; + cooling-device = <0x13 0x04 0x05 0x14 0x04 0x05 0x15 0x04 0x05 0x16 0x04 0x05 0x17 0x04 0x05 0x18 0x04 0x05 0x19 0x04 0x05 0x1a 0x04 0x05>; + }; + + map2 { + trip = <0xba>; + cooling-device = <0x13 0x06 0x08 0x14 0x06 0x08 0x15 0x06 0x08 0x16 0x06 0x08 0x17 0x06 0x08 0x18 0x06 0x08 0x19 0x06 0x08 0x1a 0x06 0x08>; + }; + }; + }; + + thermal_cluster3 { + polling-delay = <0x3e8>; + polling-delay-passive = <0xfa>; + thermal-sensors = <0xaa 0x07>; + + trips { + + thermal_cluster7-trip0 { + temperature = <0x9c40>; + hysteresis = <0x1388>; + type = "passive"; + }; + }; + }; + }; + + timer@d4016000 { + compatible = "spacemit,soc-timer"; + reg = <0x00 0xd4016000 0x00 0xc8>; + spacemit,timer-id = <0x00>; + spacemit,timer-fastclk-frequency = <0xf4240>; + spacemit,timer-apb-frequency = <0x61a8000>; + spacemit,timer-frequency = <0xf4240>; + clocks = <0x81 0x58 0x81 0x60>; + clock-names = "func\0bus"; + resets = <0x81 0x2b>; + status = "okay"; + + counter0 { + compatible = "spacemit,timer-match"; + interrupts = <0x1a 0x04>; + interrupt-parent = <0x82>; + spacemit,timer-broadcast; + spacemit,timer-counter-id = <0x00>; + status = "okay"; + }; + }; + + rtc@d4010000 { + compatible = "mrvl,mmp-rtc"; + reg = <0x00 0xd4010000 0x00 0x100>; + interrupt-parent = <0x82>; + interrupts = <0x15 0x04 0x16 0x04>; + interrupt-names = "rtc 1Hz\0rtc alarm"; + resets = <0x81 0x22>; + status = "disabled"; + }; + + irc-rx0@d4017e00 { + compatible = "spacemit-k1,irc"; + reg = <0x00 0xd4017e00 0x00 0x100>; + interrupts = <0x45 0x04>; + interrupt-parent = <0x82>; + clocks = <0x81 0x7e>; + resets = <0x81 0x3b>; + clock-frequency = <0x61a8000>; + status = "disabled"; + }; + + irc-rx1@d4017f00 { + compatible = "spacemit-k1,irc"; + reg = <0x00 0xd4017f00 0x00 0x100>; + interrupts = <0x14 0x04>; + interrupt-parent = <0x82>; + clocks = <0x81 0x7f>; + resets = <0x81 0x3c>; + clock-frequency = <0x61a8000>; + status = "disabled"; + }; + + tcm@00000000 { + compatible = "spacemit,k1-tcm"; + reg = <0x00 0x00 0x00 0x4000000>; + #address-cells = <0x01>; + #size-cells = <0x01>; + ranges = <0x00 0x00 0x00 0x4000000>; + no-memory-wc; + + cluster0_tcm@0 { + reg = <0x00 0x60000>; + cpus = <0x13 0x14>; + pool; + }; + + cluster0_tcm@60000 { + reg = <0x60000 0x60000>; + cpus = <0x13 0x14>; + pool; + }; + + cluster0_tcm@c0000 { + reg = <0xc0000 0x60000>; + cpus = <0x15 0x16>; + pool; + }; + + cluster0_tcm@120000 { + reg = <0x120000 0x60000>; + cpus = <0x15 0x16>; + pool; + }; + + cluster1_tcm@2000000 { + reg = <0x2000000 0x60000>; + cpus = <0x17 0x18>; + pool; + }; + + cluster1_tcm@2060000 { + reg = <0x2060000 0x60000>; + cpus = <0x17 0x18>; + pool; + }; + + cluster1_tcm@20c0000 { + reg = <0x20c0000 0x60000>; + cpus = <0x19 0x1a>; + pool; + }; + + cluster1_tcm@2120000 { + reg = <0x2120000 0x60000>; + cpus = <0x19 0x1a>; + pool; + }; + }; + + phy@c0a20000 { + compatible = "spacemit,k3-usb2-phy"; + reg = <0x00 0xc0a20000 0x00 0x200>; + #phy-cells = <0x00>; + status = "okay"; + phandle = <0xbb>; + }; + + usb2@c0a00000 { + compatible = "spacemit,k1-dwc3"; + reg = <0x00 0xc0a00000 0x00 0x10000>; + spacemit,syscon-apmu = <0x05 0x7c>; + interrupts = <0x69 0x04 0x9b 0x04>; + interrupt-names = "dwc3\0wakeup"; + interrupt-parent = <0x82>; + clocks = <0x05 0x20>; + resets = <0x05 0x10>; + phys = <0xbb>; + phy-names = "usb2-phy"; + phy_type = "utmi"; + snps,dis_enblslpm_quirk; + snps,dis_u2_susphy_quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + dr_mode = "host"; + maximum-speed = "high-speed"; + status = "okay"; + }; + + phy@cad20000 { + compatible = "spacemit,k3-usb2-phy"; + reg = <0x00 0xcad20000 0x00 0x200>; + #phy-cells = <0x00>; + status = "okay"; + phandle = <0xbe>; + }; + + phy@cad30000 { + compatible = "spacemit,k3-usb3-phy\0spacemit,k3-typec-switch"; + spacemit,syscon-apmu = <0x05>; + spacemit,syscon-apb-spare = <0x1b>; + clocks = <0x05 0x21>; + reg = <0x00 0xcad30000 0x00 0x200 0x00 0xcad40000 0x00 0x200>; + #phy-cells = <0x00>; + status = "okay"; + orientation-switch; + phandle = <0xbd>; + + port { + + endpoint { + remote-endpoint = <0xbc>; + phandle = <0x8d>; + }; + }; + }; + + usb3@cad00000 { + compatible = "spacemit,k1-dwc3"; + reg = <0x00 0xcad00000 0x00 0x10000>; + spacemit,syscon-apmu = <0x05 0x3c4>; + interrupts = <0x76 0x04 0x9c 0x04>; + interrupt-names = "dwc3\0wakeup"; + interrupt-parent = <0x82>; + clocks = <0x05 0x21>; + resets = <0x05 0x11>; + phys = <0xbd 0xbe>; + phy-names = "usb3-phy\0usb2-phy"; + phy_type = "utmi"; + snps,dis_enblslpm_quirk; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + snps,parkmode-disable-ss-quirk; + status = "okay"; + dr_mode = "otg"; + usb-role-switch; + role-switch-default-mode = "peripheral"; + monitor-vbus; + reset-on-resume; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint { + remote-endpoint = <0xbf>; + phandle = <0x8c>; + }; + }; + }; + }; + + phy@81500000 { + compatible = "spacemit,k3-usb2-phy"; + reg = <0x00 0x81500000 0x00 0x200>; + #phy-cells = <0x00>; + status = "okay"; + phandle = <0xc0>; + }; + + phy@81f00000 { + compatible = "spacemit,k3-usb3-phy"; + spacemit,syscon-apmu = <0x05>; + spacemit,syscon-apb-spare = <0x1b>; + reg = <0x00 0x81f00000 0x00 0x200>; + combo-usb-bit = <0x02>; + #phy-cells = <0x00>; + status = "okay"; + phandle = <0xc1>; + }; + + usb3@81400000 { + compatible = "spacemit,k1-dwc3"; + reg = <0x00 0x81400000 0x00 0x10000>; + spacemit,syscon-apmu = <0x05 0x3c8>; + interrupts = <0x7d 0x04 0x9d 0x04>; + interrupt-names = "dwc3\0wakeup"; + interrupt-parent = <0x82>; + clocks = <0x05 0x22>; + resets = <0x05 0x12>; + phys = <0xc0 0xc1>; + phy-names = "usb2-phy\0usb3-phy"; + phy_type = "utmi"; + snps,dis_enblslpm_quirk; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + snps,parkmode-disable-ss-quirk; + dr_mode = "host"; + status = "okay"; + #address-cells = <0x01>; + #size-cells = <0x00>; + reset-on-resume; + + hub@1 { + compatible = "usb2109,2817"; + reg = <0x01>; + peer-hub = <0xc2>; + vdd-supply = <0xc3>; + phandle = <0xc4>; + }; + + hub@2 { + compatible = "usb2109,817"; + reg = <0x02>; + peer-hub = <0xc4>; + phandle = <0xc2>; + }; + }; + + phy@81800000 { + compatible = "spacemit,k3-usb2-phy"; + reg = <0x00 0x81800000 0x00 0x200>; + #phy-cells = <0x00>; + status = "disabled"; + phandle = <0xc5>; + }; + + phy@82000000 { + compatible = "spacemit,k3-usb3-phy"; + spacemit,syscon-apmu = <0x05>; + spacemit,syscon-apb-spare = <0x1b>; + reg = <0x00 0x82000000 0x00 0x200>; + combo-usb-bit = <0x01>; + #phy-cells = <0x00>; + status = "disabled"; + phandle = <0xc6>; + }; + + usb3@81700000 { + compatible = "spacemit,k1-dwc3"; + reg = <0x00 0x81700000 0x00 0x10000>; + spacemit,syscon-apmu = <0x05 0x3cc>; + interrupts = <0x94 0x04 0x9e 0x04>; + interrupt-names = "dwc3\0wakeup"; + interrupt-parent = <0x82>; + clocks = <0x05 0x23>; + resets = <0x05 0x13>; + phys = <0xc5 0xc6>; + phy-names = "usb2-phy\0usb3-phy"; + phy_type = "utmi"; + snps,dis_enblslpm_quirk; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + snps,parkmode-disable-ss-quirk; + dr_mode = "host"; + status = "disabled"; + }; + + phy@81b00000 { + compatible = "spacemit,k3-usb2-phy"; + reg = <0x00 0x81b00000 0x00 0x200>; + #phy-cells = <0x00>; + status = "disabled"; + phandle = <0xc7>; + }; + + phy@82100000 { + compatible = "spacemit,k3-usb3-phy"; + spacemit,syscon-apmu = <0x05>; + spacemit,syscon-apb-spare = <0x1b>; + reg = <0x00 0x82100000 0x00 0x200>; + combo-usb-bit = <0x00>; + #phy-cells = <0x00>; + status = "disabled"; + phandle = <0xc8>; + }; + + usb3@81a00000 { + compatible = "spacemit,k1-dwc3"; + reg = <0x00 0x81a00000 0x00 0x10000>; + spacemit,syscon-apmu = <0x05 0x3d0>; + interrupts = <0x95 0x04 0x9f 0x04>; + interrupt-names = "dwc3\0wakeup"; + interrupt-parent = <0x82>; + clocks = <0x05 0x24>; + resets = <0x05 0x14>; + phys = <0xc7 0xc8>; + phy-names = "usb2-phy\0usb3-phy"; + phy_type = "utmi"; + snps,dis_enblslpm_quirk; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + snps,parkmode-disable-ss-quirk; + dr_mode = "host"; + status = "disabled"; + }; + + stmmac-axi-config { + snps,wr_osr_lmt = <0x0f>; + snps,rd_osr_lmt = <0x0f>; + snps,blen = <0x100 0x80 0x40 0x20 0x10 0x00 0x00>; + phandle = <0xcb>; + }; + + imggpu@cac00000 { + compatible = "img,rgx"; + interrupt-names = "rgxirq"; + interrupt-parent = <0x82>; + interrupts = <0x4b 0x04>; + reg = <0x00 0xcac00000 0x00 0x80000>; + reg-names = "rgxregs"; + power-domains = <0x88 0x01>; + clocks = <0x05 0x2b>; + clock-names = "clk_rgx"; + resets = <0x05 0x1d>; + operating-points-v2 = <0xc9>; + #cooling-cells = <0x02>; + thermal-zone = "thermal_gpu"; + status = "okay"; + phandle = <0xac>; + + opp-table { + compatible = "operating-points-v2"; + phandle = <0xc9>; + + opp-409000000 { + opp-hz = <0x00 0x1860d840>; + opp-microvolt = "\0\f5"; + clock-latency-ns = <0x186a0>; + }; + + opp-491000000 { + opp-hz = <0x00 0x1d4410c0>; + opp-microvolt = "\0\f5"; + clock-latency-ns = <0x186a0>; + }; + + opp-614000000 { + opp-hz = <0x00 0x2498e580>; + opp-microvolt = <0xdbba0>; + clock-latency-ns = <0x186a0>; + }; + + opp-819000000 { + opp-hz = <0x00 0x30d0f2c0>; + opp-microvolt = <0xdbba0>; + clock-latency-ns = <0x186a0>; + }; + + opp-1000000000 { + opp-hz = <0x00 0x3b9aca00>; + opp-microvolt = <0xe7ef0>; + clock-latency-ns = <0x186a0>; + }; + + opp-1228000000 { + opp-hz = <0x00 0x4931cb00>; + opp-microvolt = <0xe7ef0>; + clock-latency-ns = <0x186a0>; + }; + }; + }; + + ethercat_master { + compatible = "spacemit,igh-ec-master"; + master-count = <0x01>; + status = "okay"; + + master0 { + main-device = <0xca>; + }; + }; + + rx-queues-config { + snps,rx-queues-to-use = <0x02>; + snps,rx-sched-sp; + phandle = <0xcc>; + + queue0 { + snps,dcb-algorithm; + snps,priority = <0x0f>; + snps,map-to-dma-channel = <0x00>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority = <0xf0>; + snps,map-to-dma-channel = <0x01>; + }; + }; + + tx-queues-config { + snps,tx-queues-to-use = <0x02>; + phandle = <0xcd>; + + queue0 { + snps,dcb-algorithm; + }; + + queue1 { + snps,dcb-algorithm; + }; + }; + + ethernet@cac80000 { + compatible = "spacemit,k3-gmac\0snps,dwmac-5.10a"; + reg = <0x00 0xcac80000 0x00 0x2000>; + spacemit,apmu = <0x05>; + spacemit,ctrl-offset = <0x3e4>; + spacemit,dline-offset = <0x3e8>; + clocks = <0x05 0x4a 0x05 0x4c>; + clock-names = "stmmaceth\0ptp_ref"; + resets = <0x05 0x4d>; + reset-names = "stmmaceth"; + interrupt-parent = <0x82>; + interrupts = <0x83 0x04 0x114 0x04>; + interrupt-names = "macirq\0eth_wake_irq"; + mac-address = [00 00 00 00 00 00]; + tx-fifo-depth = <0x2000>; + rx-fifo-depth = <0x2000>; + snps,tso; + snps,force_sf_dma_mode; + snps,axi-config = <0xcb>; + snps,mtl-rx-config = <0xcc>; + snps,mtl-tx-config = <0xcd>; + status = "disabled"; + }; + + ethernet@cac82000 { + compatible = "spacemit,k3-gmac\0snps,dwmac-5.10a"; + reg = <0x00 0xcac82000 0x00 0x2000>; + spacemit,apmu = <0x05>; + spacemit,ctrl-offset = <0x3ec>; + spacemit,dline-offset = <0x3f0>; + clocks = <0x05 0x4e 0x05 0x50>; + clock-names = "stmmaceth\0ptp_ref"; + resets = <0x05 0x4e>; + reset-names = "stmmaceth"; + interrupt-parent = <0x82>; + interrupts = <0x85 0x04 0x115 0x04>; + interrupt-names = "macirq\0eth_wake_irq"; + mac-address = [00 00 00 00 00 00]; + tx-fifo-depth = <0x2000>; + rx-fifo-depth = <0x2000>; + snps,tso; + snps,force_sf_dma_mode; + snps,axi-config = <0xcb>; + snps,mtl-rx-config = <0xcc>; + snps,mtl-tx-config = <0xcd>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <0xce>; + max-speed = <0x3e8>; + phy-mode = "rgmii"; + phy-handle = <0xcf>; + snps,reset-gpios = <0x8b 0x01 0x05 0x01>; + snps,reset-delays-us = <0x00 0x4e20 0x186a0>; + spacemit,wake-irq-enable; + spacemit,clk-tuning-enable; + spacemit,clk-tuning-by-delayline; + spacemit,tx-phase = <0x2f>; + spacemit,rx-phase = <0x35>; + phandle = <0xca>; + + mdio { + #address-cells = <0x01>; + #size-cells = <0x00>; + compatible = "snps,dwmac-mdio"; + + ethernet-phy@1 { + compatible = "ethernet-phy-id001c.c916\0ethernet-phy-ieee802.3-c22"; + reg = <0x01>; + phandle = <0xcf>; + + leds { + #address-cells = <0x01>; + #size-cells = <0x00>; + + led@1 { + reg = <0x01>; + function = "lan"; + color = <0x02>; + default-state = "keep"; + }; + + led@2 { + reg = <0x02>; + function = "lan"; + color = <0x06>; + default-state = "keep"; + }; + }; + }; + }; + }; + + ethernet@cac8e000 { + compatible = "spacemit,k3-gmac\0snps,dwmac-5.10a"; + reg = <0x00 0xcac8e000 0x00 0x2000>; + spacemit,apmu = <0x05>; + spacemit,ctrl-offset = <0x248>; + spacemit,dline-offset = <0x24c>; + clocks = <0x05 0x52 0x05 0x54>; + clock-names = "stmmaceth\0ptp_ref"; + resets = <0x05 0x4f>; + reset-names = "stmmaceth"; + interrupt-parent = <0x82>; + interrupts = <0x82 0x04 0x116 0x04>; + interrupt-names = "macirq\0eth_wake_irq"; + mac-address = [00 00 00 00 00 00]; + tx-fifo-depth = <0x2000>; + rx-fifo-depth = <0x2000>; + snps,tso; + snps,force_sf_dma_mode; + snps,axi-config = <0xcb>; + snps,mtl-rx-config = <0xcc>; + snps,mtl-tx-config = <0xcd>; + status = "disabled"; + }; + + ethernet@a0000000 { + compatible = "spacemit,k3-gmac\0snps,dwmac-5.10a"; + reg = <0x00 0xa0000000 0x00 0x2000>; + spacemit,apmu = <0xd0>; + spacemit,ctrl-offset = <0xe4>; + spacemit,dline-offset = <0xe8>; + clocks = <0xd0 0x0e 0xd0 0x10>; + clock-names = "stmmaceth\0ptp_ref"; + resets = <0xd0 0x07>; + reset-names = "stmmaceth"; + interrupt-parent = <0x82>; + interrupts = <0xed 0x04 0xec 0x04>; + interrupt-names = "macirq\0eth_wake_irq"; + mac-address = [00 00 00 00 00 00]; + tx-fifo-depth = <0x1000>; + rx-fifo-depth = <0x1000>; + snps,tso; + snps,force_sf_dma_mode; + snps,axi-config = <0xcb>; + status = "disabled"; + }; + + mmc@d4280000 { + compatible = "spacemit,k3-sdhci"; + reg = <0x00 0xd4280000 0x00 0x200>; + clocks = <0x05 0x1c 0x05 0x1d>; + clock-names = "core\0io"; + interrupt-parent = <0x82>; + interrupts = <0x63 0x04>; + resets = <0x05 0x0c 0x05 0x0d>; + reset-names = "sdh_axi\0sdh0"; + status = "okay"; + pinctrl-names = "default\0uhs"; + pinctrl-0 = <0xd1 0xd2>; + pinctrl-1 = <0xd3 0xd2>; + bus-width = <0x04>; + wp-inverted; + cd-gpios = <0x8b 0x00 0x04 0x00>; + vmmc-supply = <0xd4>; + vqmmc-supply = <0xd5>; + no-mmc; + no-sdio; + clock-frequency = "\f5\0"; + spacemit,tx_delaycode = <0x1f>; + }; + + mmc@d4280800 { + compatible = "spacemit,k3-sdhci"; + reg = <0x00 0xd4280800 0x00 0x200>; + clocks = <0x05 0x1c 0x05 0x1e>; + clock-names = "core\0io"; + interrupt-parent = <0x82>; + interrupts = <0x64 0x04>; + resets = <0x05 0x0c 0x05 0x0e>; + reset-names = "sdh_axi\0sdh1"; + status = "disabled"; + }; + + mmc@d4281000 { + compatible = "spacemit,k3-sdhci"; + reg = <0x00 0xd4281000 0x00 0x200>; + clocks = <0x05 0x1c 0x05 0x1f>; + clock-names = "core\0io"; + interrupt-parent = <0x82>; + interrupts = <0x65 0x04>; + resets = <0x05 0x0c 0x05 0x0f>; + reset-names = "sdh_axi\0sdh2"; + status = "disabled"; + }; + + i2s0@d4026000 { + compatible = "spacemit,k1-i2s"; + #sound-dai-cells = <0x00>; + reg = <0x00 0xd4026000 0x00 0x30>; + clocks = <0x80 0x2c 0x80 0x31 0x81 0x6b 0x81 0x77 0x81 0x71 0x80 0x22 0x80 0x24>; + clock-names = "sysclk_div\0sysclk\0bclk\0sspa_bus\0sspa\0c_sysclk\0c_bclk"; + resets = <0x81 0x34>; + assigned-clocks = <0x80 0x20 0x80 0x21 0x80 0x22 0x80 0x24 0x80 0x27>; + assigned-clock-rates = <0x124f8000 0x124f8000 0xbb8000 0x177000 0x249f0000>; + dmas = <0x97 0x16 0x97 0x15>; + dma-names = "rx\0tx"; + status = "disabled"; + }; + + i2s1@d4026800 { + compatible = "spacemit,k1-i2s"; + #sound-dai-cells = <0x00>; + reg = <0x00 0xd4026800 0x00 0x30>; + clocks = <0x80 0x26 0x81 0x6c 0x81 0x78 0x81 0x72 0x80 0x22 0x80 0x24>; + clock-names = "sysclk\0bclk\0sspa_bus\0sspa\0c_sysclk\0c_bclk"; + resets = <0x81 0x35>; + assigned-clocks = <0x80 0x20 0x80 0x21 0x80 0x22 0x80 0x24 0x80 0x25>; + assigned-clock-rates = <0x124f8000 0x124f8000 0xbb8000 0x177000 0x124f8000>; + dmas = <0x97 0x18 0x97 0x17>; + dma-names = "rx\0tx"; + status = "disabled"; + }; + + i2s2@d4027000 { + compatible = "spacemit,k1-i2s"; + #sound-dai-cells = <0x00>; + reg = <0x00 0xd4027000 0x00 0x30>; + clocks = <0x80 0x2d 0x80 0x32 0x81 0x6d 0x81 0x79 0x81 0x73 0x80 0x22 0x80 0x24>; + clock-names = "sysclk_div\0sysclk\0bclk\0sspa_bus\0sspa\0c_sysclk\0c_bclk"; + resets = <0x81 0x36>; + assigned-clocks = <0x80 0x20 0x80 0x21 0x80 0x22 0x80 0x24 0x80 0x28>; + assigned-clock-rates = <0x124f8000 0x124f8000 0xbb8000 0x177000 0x249f0000>; + dmas = <0x97 0x39 0x97 0x38>; + dma-names = "rx\0tx"; + status = "disabled"; + }; + + i2s3@d4027800 { + compatible = "spacemit,k1-i2s"; + #sound-dai-cells = <0x00>; + reg = <0x00 0xd4027800 0x00 0x30>; + clocks = <0x80 0x2e 0x80 0x33 0x81 0x6e 0x81 0x7a 0x81 0x74 0x80 0x22 0x80 0x24>; + clock-names = "sysclk_div\0sysclk\0bclk\0sspa_bus\0sspa\0c_sysclk\0c_bclk"; + resets = <0x81 0x37>; + assigned-clocks = <0x80 0x20 0x80 0x21 0x80 0x22 0x80 0x24 0x80 0x29>; + assigned-clock-rates = <0x124f8000 0x124f8000 0xbb8000 0x177000 0x249f0000>; + dmas = <0x97 0x3b 0x97 0x3a>; + dma-names = "rx\0tx"; + status = "disabled"; + }; + + i2s4@d4041000 { + compatible = "spacemit,k1-i2s"; + #sound-dai-cells = <0x00>; + reg = <0x00 0xd4041000 0x00 0x30>; + clocks = <0x80 0x2f 0x80 0x34 0x81 0x6f 0x81 0x7b 0x81 0x75 0x80 0x22 0x80 0x24>; + clock-names = "sysclk_div\0sysclk\0bclk\0sspa_bus\0sspa\0c_sysclk\0c_bclk"; + resets = <0x81 0x38>; + assigned-clocks = <0x80 0x20 0x80 0x21 0x80 0x22 0x80 0x24 0x80 0x2a>; + assigned-clock-rates = <0x124f8000 0x124f8000 0xbb8000 0x177000 0x249f0000>; + dmas = <0x97 0x3d 0x97 0x3c>; + dma-names = "rx\0tx"; + status = "disabled"; + }; + + i2s5@d4041800 { + compatible = "spacemit,k1-i2s"; + #sound-dai-cells = <0x00>; + reg = <0x00 0xd4041800 0x00 0x30>; + clocks = <0x80 0x30 0x80 0x35 0x81 0x70 0x81 0x7c 0x81 0x76 0x80 0x22 0x80 0x24>; + clock-names = "sysclk_div\0sysclk\0bclk\0sspa_bus\0sspa\0c_sysclk\0c_bclk"; + resets = <0x81 0x39>; + assigned-clocks = <0x80 0x20 0x80 0x21 0x80 0x22 0x80 0x24 0x80 0x2b>; + assigned-clock-rates = <0x124f8000 0x124f8000 0xbb8000 0x177000 0x249f0000>; + dmas = <0x97 0x3f 0x97 0x3e>; + dma-names = "rx\0tx"; + status = "disabled"; + }; + + sound-card@0 { + status = "disabled"; + compatible = "simple-audio-card"; + }; + + sound-card@1 { + status = "disabled"; + compatible = "simple-audio-card"; + }; + + hwspin@cac91c00 { + compatible = "spacemit,hwspinlock"; + reg = <0x00 0xcac91c00 0x00 0x100>; + status = "disabled"; + }; + + hdma0@d8804000 { + compatible = "spacemit-ai-dmac"; + reg = <0x00 0xd8804000 0x00 0x1000>; + interrupt-parent = <0x82>; + interrupts = <0x07 0x04>; + clocks = <0xd6 0x00>; + resets = <0xd6 0x00 0xd6 0x04>; + reset-names = "bus\0dma"; + dma-coherent; + status = "okay"; + }; + + hdma1@d8805000 { + compatible = "spacemit-ai-dmac"; + reg = <0x00 0xd8805000 0x00 0x1000>; + interrupt-parent = <0x82>; + interrupts = <0x08 0x04>; + clocks = <0xd6 0x00>; + resets = <0xd6 0x00 0xd6 0x05>; + reset-names = "bus\0dma"; + dma-coherent; + status = "okay"; + }; + + hdma2@d8806000 { + compatible = "spacemit-ai-dmac"; + reg = <0x00 0xd8806000 0x00 0x1000>; + interrupt-parent = <0x82>; + interrupts = <0x09 0x04>; + clocks = <0xd6 0x00>; + resets = <0xd6 0x00 0xd6 0x06>; + reset-names = "bus\0dma"; + dma-coherent; + status = "okay"; + }; + + hdma3@d8807000 { + compatible = "spacemit-ai-dmac"; + reg = <0x00 0xd8807000 0x00 0x1000>; + interrupt-parent = <0x82>; + interrupts = <0x0a 0x04>; + clocks = <0xd6 0x00>; + resets = <0xd6 0x00 0xd6 0x07>; + reset-names = "bus\0dma"; + dma-coherent; + status = "okay"; + }; + + hdma4@d8808000 { + compatible = "spacemit-ai-dmac"; + reg = <0x00 0xd8808000 0x00 0x1000>; + interrupt-parent = <0x82>; + interrupts = <0x0b 0x04>; + clocks = <0xd6 0x00>; + resets = <0xd6 0x00 0xd6 0x08>; + reset-names = "bus\0dma"; + dma-coherent; + status = "okay"; + }; + + hdma5@d8809000 { + compatible = "spacemit-ai-dmac"; + reg = <0x00 0xd8809000 0x00 0x1000>; + interrupt-parent = <0x82>; + interrupts = <0x0c 0x04>; + clocks = <0xd6 0x00>; + resets = <0xd6 0x00 0xd6 0x09>; + reset-names = "bus\0dma"; + dma-coherent; + status = "okay"; + }; + + hdma6@d880a000 { + compatible = "spacemit-ai-dmac"; + reg = <0x00 0xd880a000 0x00 0x1000>; + interrupt-parent = <0x82>; + interrupts = <0x0d 0x04>; + clocks = <0xd6 0x00>; + resets = <0xd6 0x00 0xd6 0x0a>; + reset-names = "bus\0dma"; + dma-coherent; + status = "okay"; + }; + + hdma7@d880b000 { + compatible = "spacemit-ai-dmac"; + reg = <0x00 0xd880b000 0x00 0x1000>; + interrupt-parent = <0x82>; + interrupts = <0x0e 0x04>; + clocks = <0xd6 0x00>; + resets = <0xd6 0x00 0xd6 0x0b>; + reset-names = "bus\0dma"; + dma-coherent; + status = "okay"; + }; + + aidma-dev@0 { + compatible = "ai-dma-dev"; + msi-parent = <0x79>; + status = "okay"; + }; + + phy-pcie@81d00000 { + compatible = "spacemit,k3-pcie-phy"; + reg = <0x00 0x81d00000 0x00 0x1000>; + spacemit,syscon-apb-spare = <0x1b>; + num-lanes = <0x02>; + spacemit,phy-id = <0x00>; + #phy-cells = <0x00>; + status = "okay"; + phandle = <0xd9>; + }; + + phy-pcie@81e00000 { + compatible = "spacemit,k3-pcie-phy"; + reg = <0x00 0x81e00000 0x00 0x1000>; + spacemit,syscon-apb-spare = <0x1b>; + num-lanes = <0x02>; + spacemit,phy-id = <0x01>; + #phy-cells = <0x00>; + status = "okay"; + phandle = <0xda>; + }; + + phy-pcie@81f00000 { + compatible = "spacemit,k3-pcie-phy"; + reg = <0x00 0x81f00000 0x00 0x1000>; + spacemit,syscon-apb-spare = <0x1b>; + num-lanes = <0x01>; + spacemit,phy-id = <0x02>; + #phy-cells = <0x00>; + status = "disabled"; + }; + + phy-pcie@82000000 { + compatible = "spacemit,k3-pcie-phy"; + reg = <0x00 0x82000000 0x00 0x1000>; + spacemit,syscon-apb-spare = <0x1b>; + num-lanes = <0x01>; + spacemit,phy-id = <0x03>; + #phy-cells = <0x00>; + status = "disabled"; + }; + + phy-pcie@82100000 { + compatible = "spacemit,k3-pcie-phy"; + reg = <0x00 0x82100000 0x00 0x1000>; + spacemit,syscon-apb-spare = <0x1b>; + num-lanes = <0x01>; + spacemit,phy-id = <0x04>; + #phy-cells = <0x00>; + status = "okay"; + phandle = <0xdc>; + }; + + phy-pcie@82200000 { + compatible = "spacemit,k3-pcie-phy"; + reg = <0x00 0x82200000 0x00 0x1000>; + spacemit,syscon-apb-spare = <0x1b>; + num-lanes = <0x01>; + spacemit,phy-id = <0x05>; + #phy-cells = <0x00>; + status = "okay"; + phandle = <0xde>; + }; + + iommu@c0f00000 { + compatible = "spacemit,k3-iommu"; + reg = <0x00 0xc0f00000 0x00 0x1000>; + interrupts = <0xea 0x04>; + interrupt-parent = <0x82>; + #iommu-cells = <0x01>; + clocks = <0x05 0x49>; + status = "disabled"; + phandle = <0xd7>; + }; + + pcie@80000000 { + compatible = "spacemit,k1-pcie"; + reg = <0x00 0x80000000 0x00 0x1000 0x00 0x80100000 0x00 0x1000 0x00 0x80300000 0x00 0x3f20 0x11 0x00 0x00 0x10000 0x00 0x82900000 0x00 0x1000>; + reg-names = "dbi\0dbi2\0atu\0config\0link"; + bus-range = <0x00 0xff>; + max-link-speed = <0x03>; + num-lanes = <0x04>; + device_type = "pci"; + #address-cells = <0x03>; + #size-cells = <0x02>; + ranges = <0x1000000 0x00 0x10000 0x11 0x10000 0x00 0x100000 0x2000000 0x00 0x110000 0x11 0x110000 0x00 0x7fef0000 0x43000000 0x18 0x00 0x18 0x00 0x01 0x00>; + interrupt-parent = <0x82>; + interrupts = <0x8d 0x04 0xdb 0x04>; + interrupt-names = "pcie_irq\0wakeup"; + clocks = <0x05 0x3c 0x05 0x3a 0x05 0x3b>; + clock-names = "dbi\0mstr\0slv"; + resets = <0x05 0x40 0x05 0x3e 0x05 0x3f>; + reset-names = "dbi\0mstr\0slv"; + linux,pci-domain = <0x00>; + msi-parent = <0x79>; + spacemit,apmu = <0x05 0x1f0>; + iommu-map = <0x00 0xd7 0x00 0x10000>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <0xd8>; + phys = <0xd9 0xda>; + phy-names = "phy0\0phy1"; + }; + + pcie@80400000 { + compatible = "spacemit,k1-pcie"; + reg = <0x00 0x80400000 0x00 0x1000 0x00 0x80500000 0x00 0x1000 0x00 0x80700000 0x00 0x3f20 0x11 0x80000000 0x00 0x10000 0x00 0x82c00000 0x00 0x1000>; + reg-names = "dbi\0dbi2\0atu\0config\0link"; + bus-range = <0x00 0xff>; + max-link-speed = <0x03>; + num-lanes = <0x02>; + device_type = "pci"; + #address-cells = <0x03>; + #size-cells = <0x02>; + ranges = <0x1000000 0x00 0x10000 0x11 0x80010000 0x00 0x100000 0x2000000 0x00 0x80110000 0x11 0x80110000 0x00 0x7fef0000 0x43000000 0x16 0x00 0x16 0x00 0x01 0x00>; + interrupt-parent = <0x82>; + interrupts = <0x8e 0x04 0xdc 0x04>; + interrupt-names = "pcie_irq\0wakeup"; + clocks = <0x05 0x3f 0x05 0x3d 0x05 0x3e>; + clock-names = "dbi\0mstr\0slv"; + resets = <0x05 0x43 0x05 0x41 0x05 0x42>; + reset-names = "dbi\0mstr\0slv"; + linux,pci-domain = <0x01>; + msi-parent = <0x79>; + spacemit,pcie-port = <0x01>; + spacemit,apmu = <0x05 0x1d0>; + iommu-map = <0x00 0xd7 0x10000 0x10000>; + status = "disabled"; + }; + + pcie@80800000 { + compatible = "spacemit,k1-pcie"; + reg = <0x00 0x80800000 0x00 0x1000 0x00 0x80900000 0x00 0x1000 0x00 0x80b00000 0x00 0x3f20 0x12 0x00 0x00 0x10000 0x00 0x82d00000 0x00 0x1000>; + reg-names = "dbi\0dbi2\0atu\0config\0link"; + bus-range = <0x00 0xff>; + max-link-speed = <0x03>; + num-lanes = <0x02>; + device_type = "pci"; + #address-cells = <0x03>; + #size-cells = <0x02>; + ranges = <0x1000000 0x00 0x00 0x12 0x10000 0x00 0x100000 0x2000000 0x00 0x110000 0x12 0x110000 0x00 0x7fef0000 0x43000000 0x15 0x00 0x15 0x00 0x01 0x00>; + interrupt-parent = <0x82>; + interrupts = <0x8f 0x04 0xdd 0x04>; + interrupt-names = "pcie_irq\0wakeup"; + clocks = <0x05 0x42 0x05 0x40 0x05 0x41>; + clock-names = "dbi\0mstr\0slv"; + resets = <0x05 0x46 0x05 0x44 0x05 0x45>; + reset-names = "dbi\0mstr\0slv"; + linux,pci-domain = <0x02>; + msi-parent = <0x79>; + spacemit,pcie-port = <0x02>; + spacemit,apmu = <0x05 0x1c8>; + iommu-map = <0x00 0xd7 0x20000 0x10000>; + status = "disabled"; + }; + + pcie@80c00000 { + compatible = "spacemit,k1-pcie"; + reg = <0x00 0x80c00000 0x00 0x1000 0x00 0x80d00000 0x00 0x1000 0x00 0x80f00000 0x00 0x3f20 0x12 0x80000000 0x00 0x10000 0x00 0x82a00000 0x00 0x1000>; + reg-names = "dbi\0dbi2\0atu\0config\0link"; + bus-range = <0x00 0xff>; + max-link-speed = <0x03>; + num-lanes = <0x01>; + device_type = "pci"; + #address-cells = <0x03>; + #size-cells = <0x02>; + ranges = <0x1000000 0x00 0x10000 0x12 0x80010000 0x00 0x100000 0x2000000 0x00 0x80110000 0x12 0x80110000 0x00 0x3fef0000 0x43000000 0x14 0x00 0x14 0x00 0x01 0x00>; + interrupt-parent = <0x82>; + interrupts = <0x91 0x04 0xde 0x04>; + interrupt-names = "pcie_irq\0wakeup"; + clocks = <0x05 0x45 0x05 0x43 0x05 0x44>; + clock-names = "dbi\0mstr\0slv"; + resets = <0x05 0x49 0x05 0x47 0x05 0x48>; + reset-names = "dbi\0mstr\0slv"; + linux,pci-domain = <0x03>; + msi-parent = <0x79>; + spacemit,pcie-port = <0x03>; + spacemit,apmu = <0x05 0x1e0>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <0xdb>; + phys = <0xdc>; + phy-names = "phy4"; + }; + + pcie@81000000 { + compatible = "spacemit,k1-pcie"; + reg = <0x00 0x81000000 0x00 0x1000 0x00 0x81100000 0x00 0x1000 0x00 0x81300000 0x00 0x3f20 0x12 0xc0000000 0x00 0x10000 0x00 0x82b00000 0x00 0x1000>; + reg-names = "dbi\0dbi2\0atu\0config\0link"; + bus-range = <0x00 0xff>; + max-link-speed = <0x03>; + num-lanes = <0x01>; + device_type = "pci"; + #address-cells = <0x03>; + #size-cells = <0x02>; + ranges = <0x1000000 0x00 0x00 0x12 0xc0010000 0x00 0x100000 0x2000000 0x00 0xc0110000 0x12 0xc0110000 0x00 0x3fef0000 0x43000000 0x13 0x00 0x13 0x00 0x01 0x00>; + interrupt-parent = <0x82>; + interrupts = <0x92 0x04 0xdf 0x04>; + interrupt-names = "pcie_irq\0wakeup"; + clocks = <0x05 0x48 0x05 0x46 0x05 0x47>; + clock-names = "dbi\0mstr\0slv"; + resets = <0x05 0x4c 0x05 0x4a 0x05 0x4b>; + reset-names = "dbi\0mstr\0slv"; + linux,pci-domain = <0x04>; + msi-parent = <0x79>; + spacemit,pcie-port = <0x04>; + spacemit,apmu = <0x05 0x1e8>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <0xdd>; + phys = <0xde>; + phy-names = "phy5"; + }; + + pcie_ep@80000000 { + compatible = "spacemit,k3-pcie-ep"; + reg = <0x00 0x80000000 0x00 0x100000 0x00 0x80100000 0x00 0x100000 0x00 0x80200000 0x00 0x1000 0x00 0x80300000 0x00 0x1000 0x00 0x80380000 0x00 0x1000 0x11 0x00 0x00 0x10000000 0x00 0x82900000 0x00 0x1000>; + reg-names = "dbi\0dbi2\0elbi\0atu\0dma\0addr_space\0link"; + interrupt-parent = <0x82>; + interrupts = <0x8d 0x04 0xdb 0x04>; + interrupt-names = "dma\0global"; + clocks = <0x05 0x3c 0x05 0x3a 0x05 0x3b>; + clock-names = "dbi\0mstr\0slv"; + resets = <0x05 0x40 0x05 0x3e 0x05 0x3f>; + reset-names = "dbi\0mstr\0slv"; + spacemit,pcie-port = <0x00>; + spacemit,apmu = <0x05 0x1f0>; + msi-parent = <0x79>; + max-link-speed = <0x03>; + num-lanes = <0x08>; + status = "disabled"; + }; + + ufshc@0xc0e00000 { + #address-cells = <0x02>; + #size-cells = <0x02>; + compatible = "spacemit,k3-ufshcd"; + reg = <0x00 0xc0e00000 0x00 0x40000>; + interrupt-parent = <0x82>; + interrupts = <0x87 0x04>; + clocks = <0x05 0x37>; + clock-names = "ufs-aclk"; + resets = <0x05 0x3b>; + reset-names = "ufs-aclk-rst"; + clock-freq = <0x1d4c0000>; + freq-table-hz = <0x1d4c0000 0x1d4c0000>; + lanes-per-direction = <0x02>; + ref-clk-freq = <0x124f800>; + status = "okay"; + }; + + espi@cac8c000 { + compatible = "spacemit,k3-espi"; + reg = <0x00 0xcac8c000 0x00 0x1000>; + #address-cells = <0x01>; + #size-cells = <0x01>; + ranges = <0x00 0x00 0x84000000 0x1000>; + pr-mem-base0 = <0x84000000>; + pr-mem-base1 = <0xcac8c000>; + clocks = <0x05 0x56 0x05 0x57 0x05 0x58>; + clock-names = "sclk_src\0sclk\0mclk"; + resets = <0x05 0x50 0x05 0x51>; + assigned-clocks = <0x05 0x57>; + assigned-clock-parents = <0x05 0x56>; + operating-frequency = <0x14>; + io-mode = "single"; + alert-mode = "io1"; + alert-type = "open-drain"; + watchdog-timeout = <0xffff>; + crc-enable; + auto-gating-enable; + peripheral-channel-enable; + vwire-channel-enable; + oob-channel-enable; + flash-channel-enable; + status = "disabled"; + + ec@0 { + compatible = "google,cros-ec-espi"; + reg = <0x00 0x1000>; + status = "disabled"; + }; + }; + + linlon-v5@c0500000 { + compatible = "arm china,linlon-v5"; + reg = <0x00 0xc0500000 0x00 0x200000>; + interrupt-parent = <0x82>; + interrupts = <0x4a 0x04>; + clocks = <0x05 0x29>; + clock-names = "vpu_clk"; + power-domains = <0x88 0x00>; + resets = <0x05 0x1b>; + status = "okay"; + }; + + cam_ccic@d420a000 { + status = "okay"; + compatible = "spacemit,ccic"; + cell-index = <0x00>; + spacemit,csiphy = <0xdf>; + reg = <0x00 0xd420a000 0x00 0x3ff>; + reg-names = "ccic-regs"; + interrupt-parent = <0x82>; + interrupts = <0x51 0x04>; + interrupt-names = "ccic-irq"; + clocks = <0x05 0x0a 0x05 0x19 0x05 0x1b 0x05 0x0b>; + clock-names = "csi_func\0ccic_func\0sc2_ahb\0sc2_axi"; + clock-rates = <0x3b9aca00 0x3b9aca00 0x186a0000 0x186a0000>; + resets = <0x05 0x00 0x05 0x0a 0x05 0x09 0x05 0x03>; + reset-names = "csi_reset\0ccic_4x_reset\0sc2_hclk_reset\0isp_cibus_reset"; + }; + + cam_ccic@d420a800 { + status = "okay"; + compatible = "spacemit,ccic"; + cell-index = <0x01>; + spacemit,csiphy = <0xe0>; + reg = <0x00 0xd420a800 0x00 0x3ff>; + reg-names = "ccic-regs"; + interrupt-parent = <0x82>; + interrupts = <0x52 0x04>; + interrupt-names = "ccic-irq"; + clocks = <0x05 0x0a 0x05 0x19 0x05 0x1b 0x05 0x0b>; + clock-names = "csi_func\0ccic_func\0sc2_ahb\0sc2_axi"; + clock-rates = <0x3b9aca00 0x3b9aca00 0x124f8000 0x186a0000>; + resets = <0x05 0x00 0x05 0x0a 0x05 0x09 0x05 0x03>; + reset-names = "csi_reset\0ccic_4x_reset\0sc2_hclk_reset\0isp_cibus_reset"; + }; + + cam_ccic@d4206000 { + status = "okay"; + compatible = "spacemit,ccic"; + cell-index = <0x02>; + spacemit,csiphy = <0xe1>; + reg = <0x00 0xd4206000 0x00 0x3ff>; + reg-names = "ccic-regs"; + interrupt-parent = <0x82>; + interrupts = <0x53 0x04>; + interrupt-names = "ccic-irq"; + clocks = <0x05 0x0a 0x05 0x19 0x05 0x1b 0x05 0x0b>; + clock-names = "csi_func\0ccic_func\0sc2_ahb\0sc2_axi"; + clock-rates = <0x3b9aca00 0x3b9aca00 0x124f8000 0x186a0000>; + resets = <0x05 0x00 0x05 0x0a 0x05 0x09 0x05 0x03>; + reset-names = "csi_reset\0ccic_4x_reset\0sc2_hclk_reset\0isp_cibus_reset"; + }; + + cam_ccic@d4206800 { + status = "disabled"; + compatible = "spacemit,ccic"; + cell-index = <0x03>; + spacemit,csiphy = <0xe1>; + reg = <0x00 0xd4206800 0x00 0x3ff>; + reg-names = "ccic-regs"; + interrupt-parent = <0x82>; + interrupts = <0x47 0x04>; + interrupt-names = "ccic-irq"; + clocks = <0x05 0x0a 0x05 0x19 0x05 0x1b 0x05 0x0b>; + clock-names = "csi_func\0ccic_func\0sc2_ahb\0sc2_axi"; + clock-rates = <0x3b9aca00 0x3b9aca00 0x124f8000 0x186a0000>; + resets = <0x05 0x00 0x05 0x0a 0x05 0x09 0x05 0x03>; + reset-names = "csi_reset\0ccic_4x_reset\0sc2_hclk_reset\0isp_cibus_reset"; + }; + + cam_ccic_dma@d420f000 { + status = "okay"; + compatible = "spacemit,ccic-dma"; + cell-index = <0x00>; + reg = <0x00 0xd420f000 0x00 0x1080>; + reg-names = "ccic-dma-regs"; + interrupt-parent = <0x82>; + interrupts = <0x5d 0x04 0x50 0x04>; + interrupt-names = "ccic-dma-irq\0ccic-dma-mmu-irq"; + }; + + watchdog@d4014000 { + compatible = "spacemit-k1,wdt"; + clocks = <0x81 0x57 0x81 0x5f>; + clock-names = "clk\0clk-bus"; + resets = <0x81 0x2a>; + reg = <0x00 0xd4014000 0x00 0xff 0x00 0xd4050000 0x00 0x1024>; + interrupts = <0x23 0x04>; + interrupt-parent = <0x82>; + spa,wdt-disabled; + spa,wdt-enable-restart-handler; + status = "okay"; + }; + + ddrqos@0xd4282c00 { + compatible = "spacemit,ddr-qos"; + reg = <0x00 0xd4282c00 0x00 0x200>; + status = "okay"; + }; + + reboot-mode-helper@c087c000 { + compatible = "spacemit,k3-reboot"; + reg = <0x00 0xc087c000 0x00 0x1000>; + }; + + irq-aff@0 { + compatible = "spacemit,irq-affinity-restore"; + msi-parent = <0x79>; + status = "okay"; + }; + + serial@c0881000 { + compatible = "spacemit,k1-uart\0intel,xscale-uart"; + reg = <0x00 0xc0881000 0x00 0x100>; + clocks = <0xe2 0x00 0xe2 0x06 0x80 0x19>; + clock-names = "core\0bus\0gate"; + spacemit,rcpu-uart; + resets = <0xe2 0x00>; + reg-shift = <0x02>; + reg-io-width = <0x04>; + fifo-size = <0x100>; + tx-threshold = <0x20>; + interrupt-parent = <0x82>; + interrupts = <0xfb 0x04>; + status = "disabled"; + }; + + serial@c0881100 { + compatible = "spacemit,k1-uart\0intel,xscale-uart"; + reg = <0x00 0xc0881100 0x00 0x100>; + clocks = <0xe2 0x01 0xe2 0x07 0x80 0x19>; + clock-names = "core\0bus\0gate"; + spacemit,rcpu-uart; + resets = <0xe2 0x01>; + reg-shift = <0x02>; + reg-io-width = <0x04>; + fifo-size = <0x100>; + tx-threshold = <0x20>; + interrupt-parent = <0x82>; + interrupts = <0xfc 0x04>; + status = "disabled"; + }; + + serial@c0881200 { + compatible = "spacemit,k1-uart\0intel,xscale-uart"; + reg = <0x00 0xc0881200 0x00 0x100>; + clocks = <0xe2 0x02 0xe2 0x08 0x80 0x19>; + clock-names = "core\0bus\0gate"; + spacemit,rcpu-uart; + resets = <0xe2 0x02>; + reg-shift = <0x02>; + reg-io-width = <0x04>; + fifo-size = <0x100>; + tx-threshold = <0x20>; + interrupt-parent = <0x82>; + interrupts = <0xfd 0x04>; + status = "disabled"; + }; + + serial@c0881300 { + compatible = "spacemit,k1-uart\0intel,xscale-uart"; + reg = <0x00 0xc0881300 0x00 0x100>; + clocks = <0xe2 0x03 0xe2 0x09 0x80 0x19>; + clock-names = "core\0bus\0gate"; + spacemit,rcpu-uart; + resets = <0xe2 0x03>; + reg-shift = <0x02>; + reg-io-width = <0x04>; + fifo-size = <0x100>; + tx-threshold = <0x20>; + interrupt-parent = <0x82>; + interrupts = <0xfe 0x04>; + status = "disabled"; + }; + + serial@c0881400 { + compatible = "spacemit,k1-uart\0intel,xscale-uart"; + reg = <0x00 0xc0881400 0x00 0x100>; + clocks = <0xe2 0x04 0xe2 0x0a 0x80 0x19>; + clock-names = "core\0bus\0gate"; + spacemit,rcpu-uart; + resets = <0xe2 0x04>; + reg-shift = <0x02>; + reg-io-width = <0x04>; + fifo-size = <0x100>; + tx-threshold = <0x20>; + interrupt-parent = <0x82>; + interrupts = <0xff 0x04>; + status = "disabled"; + }; + + serial@c0881500 { + compatible = "spacemit,k1-uart\0intel,xscale-uart"; + reg = <0x00 0xc0881500 0x00 0x100>; + clocks = <0xe2 0x05 0xe2 0x0b 0x80 0x19>; + clock-names = "core\0bus\0gate"; + spacemit,rcpu-uart; + resets = <0xe2 0x05>; + reg-shift = <0x02>; + reg-io-width = <0x04>; + fifo-size = <0x100>; + tx-threshold = <0x20>; + interrupt-parent = <0x82>; + interrupts = <0x100 0x04>; + status = "disabled"; + }; + + fdcan@c0710000 { + compatible = "spacemit,k1-flexcan"; + reg = <0x00 0xc0710000 0x00 0x4000>; + clocks = <0xd0 0x00 0xd0 0x05>; + clock-names = "per\0ipg"; + interrupts = <0xf1 0x04>; + interrupt-parent = <0x82>; + fsl,clk-source = <0x00>; + resets = <0xd0 0x00>; + status = "disabled"; + }; + + fdcan@c0720000 { + compatible = "spacemit,k1-flexcan"; + reg = <0x00 0xc0720000 0x00 0x4000>; + clocks = <0xd0 0x01 0xd0 0x06>; + clock-names = "per\0ipg"; + interrupts = <0xf3 0x04>; + interrupt-parent = <0x82>; + fsl,clk-source = <0x00>; + resets = <0xd0 0x01>; + status = "disabled"; + }; + + fdcan@c0730000 { + compatible = "spacemit,k1-flexcan"; + reg = <0x00 0xc0730000 0x00 0x4000>; + clocks = <0xd0 0x02 0xd0 0x07>; + clock-names = "per\0ipg"; + interrupts = <0xf5 0x04>; + interrupt-parent = <0x82>; + fsl,clk-source = <0x00>; + resets = <0xd0 0x02>; + status = "disabled"; + }; + + fdcan@c0740000 { + compatible = "spacemit,k1-flexcan"; + reg = <0x00 0xc0740000 0x00 0x4000>; + clocks = <0xd0 0x03 0xd0 0x08>; + clock-names = "per\0ipg"; + interrupts = <0xf7 0x04>; + interrupt-parent = <0x82>; + fsl,clk-source = <0x00>; + resets = <0xd0 0x03>; + status = "disabled"; + }; + + fdcan@c0750000 { + compatible = "spacemit,k1-flexcan"; + reg = <0x00 0xc0750000 0x00 0x4000>; + clocks = <0xd0 0x04 0xd0 0x09>; + clock-names = "per\0ipg"; + interrupts = <0xf9 0x04>; + interrupt-parent = <0x82>; + fsl,clk-source = <0x00>; + resets = <0xd0 0x04>; + status = "disabled"; + }; + + pwm@c088d100 { + compatible = "spacemit,k1-pwm\0marvell,pxa910-pwm"; + reg = <0x00 0xc088d100 0x00 0x10>; + clocks = <0xe3 0x00 0xe3 0x0a>; + clock-names = "func\0bus"; + resets = <0xe3 0x00>; + #pwm-cells = <0x03>; + k1,pwm-disable-fd; + status = "disabled"; + }; + + pwm@c088d200 { + compatible = "spacemit,k1-pwm\0marvell,pxa910-pwm"; + reg = <0x00 0xc088d200 0x00 0x10>; + clocks = <0xe3 0x01 0xe3 0x0b>; + clock-names = "func\0bus"; + resets = <0xe3 0x01>; + #pwm-cells = <0x03>; + k1,pwm-disable-fd; + status = "disabled"; + }; + + pwm@c088d300 { + compatible = "spacemit,k1-pwm\0marvell,pxa910-pwm"; + reg = <0x00 0xc088d300 0x00 0x10>; + clocks = <0xe3 0x02 0xe3 0x0c>; + clock-names = "func\0bus"; + resets = <0xe3 0x02>; + #pwm-cells = <0x03>; + k1,pwm-disable-fd; + status = "disabled"; + }; + + pwm@c088d400 { + compatible = "spacemit,k1-pwm\0marvell,pxa910-pwm"; + reg = <0x00 0xc088d400 0x00 0x10>; + clocks = <0xe3 0x03 0xe3 0x0d>; + clock-names = "func\0bus"; + resets = <0xe3 0x03>; + #pwm-cells = <0x03>; + k1,pwm-disable-fd; + status = "disabled"; + }; + + pwm@c088d500 { + compatible = "spacemit,k1-pwm\0marvell,pxa910-pwm"; + reg = <0x00 0xc088d500 0x00 0x10>; + clocks = <0xe3 0x04 0xe3 0x0e>; + clock-names = "func\0bus"; + resets = <0xe3 0x04>; + #pwm-cells = <0x03>; + k1,pwm-disable-fd; + status = "disabled"; + }; + + pwm@c088d600 { + compatible = "spacemit,k1-pwm\0marvell,pxa910-pwm"; + reg = <0x00 0xc088d600 0x00 0x10>; + clocks = <0xe3 0x05 0xe3 0x0f>; + clock-names = "func\0bus"; + resets = <0xe3 0x05>; + #pwm-cells = <0x03>; + k1,pwm-disable-fd; + status = "disabled"; + }; + + pwm@c088d700 { + compatible = "spacemit,k1-pwm\0marvell,pxa910-pwm"; + reg = <0x00 0xc088d700 0x00 0x10>; + clocks = <0xe3 0x06 0xe3 0x10>; + clock-names = "func\0bus"; + resets = <0xe3 0x06>; + #pwm-cells = <0x03>; + k1,pwm-disable-fd; + status = "disabled"; + }; + + pwm@c088d800 { + compatible = "spacemit,k1-pwm\0marvell,pxa910-pwm"; + reg = <0x00 0xc088d800 0x00 0x10>; + clocks = <0xe3 0x07 0xe3 0x11>; + clock-names = "func\0bus"; + resets = <0xe3 0x07>; + #pwm-cells = <0x03>; + k1,pwm-disable-fd; + status = "disabled"; + }; + + pwm@c088d900 { + compatible = "spacemit,k1-pwm\0marvell,pxa910-pwm"; + reg = <0x00 0xc088d900 0x00 0x10>; + clocks = <0xe3 0x08 0xe3 0x12>; + clock-names = "func\0bus"; + resets = <0xe3 0x08>; + #pwm-cells = <0x03>; + k1,pwm-disable-fd; + status = "disabled"; + }; + + pwm@c088da00 { + compatible = "spacemit,k1-pwm\0marvell,pxa910-pwm"; + reg = <0x00 0xc088da00 0x00 0x10>; + clocks = <0xe3 0x09 0xe3 0x13>; + clock-names = "func\0bus"; + resets = <0xe3 0x09>; + #pwm-cells = <0x03>; + k1,pwm-disable-fd; + status = "disabled"; + }; + + ri2c@c0886000 { + compatible = "spacemit,k1-i2c"; + reg = <0x00 0xc0886000 0x00 0x38>; + #address-cells = <0x01>; + #size-cells = <0x00>; + interrupt-parent = <0x82>; + interrupts = <0x110 0x04>; + clocks = <0xe4 0x00 0xe4 0x03>; + clock-names = "func\0bus"; + clock-frequency = <0x61a80>; + resets = <0xe4 0x00>; + status = "disabled"; + }; + + ri2c@c0886100 { + compatible = "spacemit,k1-i2c"; + reg = <0x00 0xc0886100 0x00 0x38>; + #address-cells = <0x01>; + #size-cells = <0x00>; + interrupt-parent = <0x82>; + interrupts = <0x111 0x04>; + clocks = <0xe4 0x01 0xe4 0x04>; + clock-names = "func\0bus"; + clock-frequency = <0x61a80>; + resets = <0xe4 0x01>; + status = "disabled"; + }; + + adma0@C0883000 { + compatible = "spacemit,k3-adma"; + reg = <0x00 0xc0883000 0x00 0x100 0x00 0xc08d0000 0x00 0x100>; + reg-names = "adma_reg\0buf_addr"; + interrupt-parent = <0x82>; + interrupts = <0x101 0x04 0x102 0x04>; + #dma-cells = <0x01>; + #dma-channels = <0x02>; + status = "disabled"; + phandle = <0xe6>; + }; + + adma1@C0883400 { + compatible = "spacemit,k3-adma"; + reg = <0x00 0xc0883400 0x00 0x100 0x00 0xc08d0100 0x00 0x100>; + reg-names = "adma_reg\0buf_addr"; + interrupt-parent = <0x82>; + interrupts = <0x104 0x04 0x105 0x04>; + #dma-cells = <0x01>; + #dma-channels = <0x02>; + status = "disabled"; + phandle = <0xe7>; + }; + + adma2@C0883800 { + compatible = "spacemit,k3-adma"; + reg = <0x00 0xc0883800 0x00 0x100 0x00 0xc08d0200 0x00 0x100>; + reg-names = "adma_reg\0buf_addr"; + interrupt-parent = <0x82>; + interrupts = <0x107 0x04 0x108 0x04>; + #dma-cells = <0x01>; + #dma-channels = <0x02>; + status = "disabled"; + phandle = <0xe8>; + }; + + adma3@C0883C00 { + compatible = "spacemit,k3-adma"; + reg = <0x00 0xc0883c00 0x00 0x100 0x00 0xc08d0300 0x00 0x100>; + reg-names = "adma_reg\0buf_addr"; + interrupt-parent = <0x82>; + interrupts = <0x10a 0x04 0x10b 0x04>; + #dma-cells = <0x01>; + #dma-channels = <0x02>; + status = "okay"; + phandle = <0xe9>; + }; + + ri2s0@c0883100 { + compatible = "spacemit,k3-ri2s"; + #sound-dai-cells = <0x00>; + reg = <0x00 0xc0883100 0x00 0x300 0x00 0xc08d0400 0x00 0x4000>; + clocks = <0xe5 0x00 0xe5 0x04 0xd0 0x12>; + clock-names = "func\0bus\0sysclk"; + resets = <0xe5 0x00 0xd0 0x09>; + reset-names = "reset\0reset-sys"; + dmas = <0xe6 0x01 0xe6 0x00>; + dma-names = "rx\0tx"; + status = "disabled"; + }; + + ri2s1@c0883500 { + compatible = "spacemit,k3-ri2s"; + #sound-dai-cells = <0x00>; + reg = <0x00 0xc0883500 0x00 0x300 0x00 0xc08d4400 0x00 0x4000>; + clocks = <0xe5 0x01 0xe5 0x05 0xd0 0x13>; + clock-names = "func\0bus\0sysclk"; + resets = <0xe5 0x01 0xd0 0x0a>; + reset-names = "reset\0reset-sys"; + dmas = <0xe7 0x01 0xe7 0x00>; + dma-names = "rx\0tx"; + status = "disabled"; + }; + + ri2s2@c0883900 { + compatible = "spacemit,k3-ri2s"; + #sound-dai-cells = <0x00>; + reg = <0x00 0xc0883900 0x00 0x300 0x00 0xc08d8400 0x00 0x4000>; + clocks = <0xe5 0x02 0xe5 0x06 0xe5 0x08>; + clock-names = "func\0bus\0sysclk"; + resets = <0xe5 0x02 0xe5 0x04>; + reset-names = "reset\0reset-sys"; + dmas = <0xe8 0x01 0xe8 0x00>; + dma-names = "rx\0tx"; + status = "disabled"; + phandle = <0xeb>; + }; + + ri2s3@c0883D00 { + compatible = "spacemit,k3-ri2s"; + #sound-dai-cells = <0x00>; + reg = <0x00 0xc0883d00 0x00 0x300 0x00 0xc08dc400 0x00 0x4000>; + clocks = <0xe5 0x03 0xe5 0x07 0xe5 0x09>; + clock-names = "func\0bus\0sysclk"; + resets = <0xe5 0x03 0xe5 0x05>; + reset-names = "reset\0reset-sys"; + dmas = <0xe9 0x01 0xe9 0x00>; + dma-names = "rx\0tx"; + status = "okay"; + phandle = <0xed>; + }; + + sound-card-dp0@0 { + compatible = "simple-audio-card"; + simple-audio-card,mclk-fs = <0x200>; + status = "disabled"; + + simple-audio-card,dai-link@0 { + format = "left_j"; + frame-master = <0xea>; + bitclock-master = <0xea>; + + cpu { + sound-dai = <0xeb>; + phandle = <0xea>; + }; + }; + }; + + sound-card-dp1@1 { + compatible = "simple-audio-card"; + simple-audio-card,mclk-fs = <0x200>; + status = "okay"; + simple-audio-card,name = "snd-dp1"; + + simple-audio-card,dai-link@0 { + format = "left_j"; + frame-master = <0xec>; + bitclock-master = <0xec>; + + cpu { + sound-dai = <0xed>; + phandle = <0xec>; + }; + + codec { + playback-only; + sound-dai = <0xee>; + }; + }; + }; + + r-irc-rx0@c0887000 { + compatible = "spacemit-k1,irc"; + reg = <0x00 0xc0887000 0x00 0x100>; + interrupts = <0x112 0x04>; + interrupt-parent = <0x82>; + clocks = <0xd0 0x0a>; + resets = <0xd0 0x05>; + status = "disabled"; + }; + + r-irc-rx1@c088e000 { + compatible = "spacemit-k1,irc"; + reg = <0x00 0xc088e000 0x00 0x100>; + interrupts = <0x113 0x04>; + interrupt-parent = <0x82>; + clocks = <0xd0 0x0b>; + resets = <0xd0 0x06>; + status = "disabled"; + }; + + rspi0@c0885000 { + compatible = "spacemit,k3-spi"; + reg = <0x00 0xc0885000 0x00 0x30>; + interrupt-parent = <0x82>; + interrupts = <0x10d 0x04>; + clocks = <0xef 0x00 0xef 0x03>; + clock-names = "func\0bus"; + resets = <0xef 0x00>; + spi-max-frequency = <0x30d4000>; + #address-cells = <0x01>; + #size-cells = <0x00>; + status = "disabled"; + }; + + rspi1@c0885100 { + compatible = "spacemit,k3-spi"; + reg = <0x00 0xc0885100 0x00 0x30>; + interrupt-parent = <0x82>; + interrupts = <0x10e 0x04>; + clocks = <0xef 0x01 0xef 0x04>; + clock-names = "func\0bus"; + resets = <0xef 0x01>; + spi-max-frequency = <0x30d4000>; + #address-cells = <0x01>; + #size-cells = <0x00>; + status = "disabled"; + }; + + rspi2@c0885200 { + compatible = "spacemit,k3-spi"; + reg = <0x00 0xc0885200 0x00 0x30>; + interrupt-parent = <0x82>; + interrupts = <0x10f 0x04>; + clocks = <0xef 0x02 0xef 0x05>; + clock-names = "func\0bus"; + resets = <0xef 0x02>; + spi-max-frequency = <0x30d4000>; + #address-cells = <0x01>; + #size-cells = <0x00>; + status = "disabled"; + }; + + display-subsystem-dsi { + compatible = "spacemit,saturn-hee"; + reg = <0x00 0xc0340000 0x00 0x54000>; + hw_ver = <0x02>; + ports = <0xf0 0xf1>; + }; + + dpu_crtc0 { + compatible = "spacemit,dpu-saturn"; + reg = <0x00 0xd421a800 0x00 0x200 0x00 0xd421aa00 0x00 0x200>; + interrupt-parent = <0x82>; + interrupts = <0x5a 0x04>; + interrupt-names = "ONLINE_IRQ"; + clocks = <0x05 0x17 0x05 0x18 0x05 0x15 0x05 0x14 0x05 0x36 0x05 0x16>; + clock-names = "pxclk\0mclk\0hclk\0escclk\0aclk\0dscclk"; + resets = <0x05 0x07 0x05 0x05 0x05 0x04 0x05 0x3a 0x05 0x08>; + reset-names = "mclk_reset\0lcd_reset\0esc_reset\0aclk_reset\0dsc_reset"; + power-domains = <0x88 0x03>; + pipeline-id = <0x01>; + is_edp = <0x00>; + dpu-id = <0x00>; + ip = "spacemit-saturn"; + spacemit-dpu-min-mclk = <0x2710000>; + spacemit-dpu-dsipll; + status = "okay"; + memory-region = <0xf2>; + spacemit-dpu-bitclk = <0x29b92700>; + phandle = <0xf0>; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + #address-cells = <0x01>; + #size-cells = <0x00>; + + endpoint@0 { + reg = <0x00>; + remote-endpoint = <0xf3>; + phandle = <0xf9>; + }; + + endpoint@1 { + reg = <0x01>; + remote-endpoint = <0xf4>; + phandle = <0xfa>; + }; + }; + }; + }; + + dpu_crtc1 { + compatible = "spacemit,dpu-saturn"; + reg = <0x00 0xd421a800 0x00 0x200 0x00 0xd421aa00 0x00 0x200>; + interrupt-parent = <0x82>; + interrupts = <0x59 0x04>; + interrupt-names = "OFFLINE_IRQ"; + clocks = <0x05 0x17 0x05 0x18 0x05 0x15 0x05 0x14 0x05 0x36 0x05 0x16>; + clock-names = "pxclk\0mclk\0hclk\0escclk\0aclk\0dscclk"; + resets = <0x05 0x07 0x05 0x05 0x05 0x04 0x05 0x3a 0x05 0x08>; + reset-names = "mclk_reset\0lcd_reset\0esc_reset\0aclk_reset\0dsc_reset"; + power-domains = <0x88 0x03>; + pipeline-id = <0x02>; + is_edp = <0x01>; + ip = "spacemit-saturn"; + spacemit-dpu-min-mclk = <0x2710000>; + status = "disabled"; + memory-region = <0xf5>; + phandle = <0xf1>; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint@0 { + remote-endpoint = <0xf6>; + phandle = <0xfb>; + }; + }; + }; + }; + + dsi0@d421a800 { + compatible = "spacemit,dsi-host"; + #address-cells = <0x01>; + #size-cells = <0x00>; + reg = <0x00 0xd421a800 0x00 0x200>; + interrupt-parent = <0x82>; + interrupts = <0x4f 0x04>; + ip = "synopsys-dhost"; + dev-id = <0x02>; + status = "okay"; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + #address-cells = <0x01>; + #size-cells = <0x00>; + + endpoint { + remote-endpoint = <0xf7>; + phandle = <0xfc>; + }; + + endpoint@1 { + reg = <0x01>; + remote-endpoint = <0xf8>; + phandle = <0x91>; + }; + }; + + port@1 { + reg = <0x01>; + + endpoint { + remote-endpoint = <0xf9>; + phandle = <0xf3>; + }; + }; + }; + + panel0@0 { + status = "ok"; + compatible = "raspberrypi,dpi-panel"; + force-attached = "lcd_tc358762xbg_dpi_800x480"; + }; + }; + + wb0 { + compatible = "spacemit,wb0"; + dev-id = <0x00>; + status = "ok"; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint { + remote-endpoint = <0xfa>; + phandle = <0xf4>; + }; + }; + + port@1 { + reg = <0x01>; + + endpoint { + remote-endpoint = <0xfb>; + phandle = <0xf6>; + }; + }; + }; + }; + + dphy0@d421a800 { + compatible = "spacemit,dsi-phy"; + #address-cells = <0x01>; + #size-cells = <0x00>; + reg = <0x00 0xd421a800 0x00 0x200>; + ip = "spacemit-dphy"; + dev-id = <0x02>; + status = "ok"; + + port@0 { + reg = <0x00>; + + endpoint { + remote-endpoint = <0xfc>; + phandle = <0xf7>; + }; + }; + }; + + display-subsystem-dp1 { + compatible = "spacemit,saturn-edp"; + reg = <0x00 0xc0440000 0x00 0x54000>; + hw_ver = <0x02>; + ports = <0xfd>; + }; + + dpu1_crtc0 { + compatible = "spacemit,dpu-saturn"; + interrupt-parent = <0x82>; + interrupts = <0x8b 0x04 0x8a 0x04>; + interrupt-names = "ONLINE_IRQ\0OFFLINE_IRQ"; + clocks = <0x05 0x33 0x05 0x34 0x05 0x35 0x05 0x31 0x05 0x32>; + clock-names = "pxclk\0mclk\0aclk\0escclk\0dscclk"; + resets = <0x05 0x37 0x05 0x35 0x05 0x36 0x05 0x39 0x05 0x38>; + reset-names = "mclk_reset\0esc_reset\0lcd_reset\0aclk_reset\0dsc_reset"; + power-domains = <0x88 0x04>; + pipeline-id = <0x01>; + is_edp = <0x01>; + dpu-id = <0x01>; + ip = "spacemit-saturn"; + spacemit-dpu-min-mclk = <0x2710000>; + status = "okay"; + memory-region = <0xf5>; + phandle = <0xfd>; + + ports { + #address-cells = <0x01>; + #size-cells = <0x00>; + + port@0 { + reg = <0x00>; + + endpoint@0 { + remote-endpoint = <0xfe>; + phandle = <0x100>; + }; + }; + }; + }; + + dp1@cac88000 { + compatible = "spacemit,inno-dp1"; + reg = <0x00 0xcac88000 0x00 0x4000>; + spacemit,apmu = <0x05>; + interrupt-parent = <0x82>; + interrupts = <0x8c 0x04>; + clocks = <0x05 0x39>; + clock-names = "pxclk"; + resets = <0x05 0x3d>; + reset-names = "reset"; + dp-id = <0x01>; + #sound-dai-cells = <0x00>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <0xff>; + phandle = <0xee>; + + port { + #address-cells = <0x01>; + #size-cells = <0x00>; + + endpoint@0 { + reg = <0x00>; + remote-endpoint = <0x100>; + phandle = <0xfe>; + }; + }; + }; + + csiphy@d420a000 { + compatible = "spacemit,csi-dphy"; + cell-index = <0x00>; + spacemit,apmu = <0x05>; + spacemit,ctrl-offset = <0x37c>; + spacemit,bifmode-enable = <0x00>; + reg = <0x00 0xd420a000 0x00 0x13f>; + reg-names = "csiphy-regs"; + clocks = <0x05 0x1a>; + clock-names = "csi_dphy"; + resets = <0x05 0x0b>; + reset-names = "csi_dphy_reset"; + status = "okay"; + phandle = <0xdf>; + }; + + csiphy@d420a800 { + compatible = "spacemit,csi-dphy"; + cell-index = <0x01>; + spacemit,apmu = <0x05>; + spacemit,ctrl-offset = <0x37c>; + spacemit,bifmode-enable = <0x00>; + reg = <0x00 0xd420a800 0x00 0x13f>; + reg-names = "csiphy-regs"; + clocks = <0x05 0x08>; + clock-names = "csi_dphy"; + resets = <0x05 0x01>; + reset-names = "csi_dphy_reset"; + status = "okay"; + phandle = <0xe0>; + }; + + csiphy@d4206000 { + compatible = "spacemit,csi-dphy"; + cell-index = <0x02>; + spacemit,apmu = <0x05>; + spacemit,ctrl-offset = <0x37c>; + spacemit,bifmode-enable = <0x00>; + reg = <0x00 0xd4206000 0x00 0x13f>; + reg-names = "csiphy-regs"; + clocks = <0x05 0x09>; + clock-names = "csi_dphy"; + resets = <0x05 0x02>; + reset-names = "csi_dphy_reset"; + status = "okay"; + phandle = <0xe1>; + }; + }; + + aliases { + serial0 = "/soc/serial@d4017000"; + serial1 = "/soc/serial@f0612000"; + serial2 = "/soc/serial@d4017100"; + serial3 = "/soc/serial@d4017200"; + serial4 = "/soc/serial@d4017300"; + serial5 = "/soc/serial@d4017400"; + serial6 = "/soc/serial@d4017500"; + serial7 = "/soc/serial@d4017600"; + serial8 = "/soc/serial@d4017700"; + serial9 = "/soc/serial@d4017800"; + serial10 = "/soc/serial@d401f000"; + serial11 = "/soc/serial@c0881000"; + serial12 = "/soc/serial@c0881100"; + serial13 = "/soc/serial@c0881200"; + serial14 = "/soc/serial@c0881300"; + serial15 = "/soc/serial@c0881400"; + serial16 = "/soc/serial@c0881500"; + mmc0 = "/soc/mmc@d4280000"; + mmc1 = "/soc/mmc@d4280800"; + mmc2 = "/soc/mmc@d4281000"; + ethernet0 = "/soc/ethernet@cac80000"; + ethernet1 = "/soc/ethernet@cac82000"; + ethernet2 = "/soc/ethernet@cac8e000"; + ethernet3 = "/soc/ethernet@a0000000"; + i2c0 = "/soc/i2c@d4010800"; + i2c1 = "/soc/i2c@d4011000"; + i2c2 = "/soc/i2c@d4012000"; + i2c3 = "/soc/i2c@f0614000"; + i2c4 = "/soc/i2c@d4012800"; + i2c5 = "/soc/i2c@d4013800"; + i2c6 = "/soc/i2c@d4018800"; + i2c8 = "/soc/i2c@d401d800"; + spi0 = "/soc/spi@d4040000"; + spi1 = "/soc/spi@d4040800"; + spi2 = "/soc/spi@f0613000"; + spi3 = "/soc/spi@d401c000"; + }; + + clocks { + + clock-1m { + compatible = "fixed-clock"; + clock-frequency = <0xf4240>; + clock-output-names = "vctcxo_1m"; + #clock-cells = <0x00>; + phandle = <0x7b>; + }; + + clock-24m { + compatible = "fixed-clock"; + clock-frequency = <0x16e3600>; + clock-output-names = "vctcxo_24m"; + #clock-cells = <0x00>; + phandle = <0x7d>; + }; + + clock-3m { + compatible = "fixed-clock"; + clock-frequency = <0x2dc6c0>; + clock-output-names = "vctcxo_3m"; + #clock-cells = <0x00>; + phandle = <0x7c>; + }; + + clock-32k { + compatible = "fixed-clock"; + clock-frequency = <0x8000>; + clock-output-names = "osc_32k"; + #clock-cells = <0x00>; + phandle = <0x7a>; + }; + + clock-reserved { + compatible = "fixed-clock"; + clock-frequency = <0x00>; + clock-output-names = "reserved_clk"; + #clock-cells = <0x00>; + phandle = <0x7e>; + }; + + clock-external { + compatible = "fixed-clock"; + clock-frequency = <0x00>; + clock-output-names = "external_clk"; + #clock-cells = <0x00>; + phandle = <0x7f>; + }; + }; + + memory@102000000 { + device_type = "memory"; + reg = <0x01 0x2000000 0x01 0xfe000000>; + }; + + apb-pclk { + compatible = "fixed-clock"; + #clock-cells = <0x00>; + clock-output-names = "clk14mhz"; + clock-frequency = <0xd59f80>; + phandle = <0x60>; + }; + + reserved-memory { + #address-cells = <0x02>; + #size-cells = <0x02>; + ranges; + + rcpu0_pwr@100200000 { + reg = <0x01 0x200000 0x00 0x300000>; + no-map; + phandle = <0x9a>; + }; + + rcpu0_heap@100500000 { + reg = <0x01 0x500000 0x00 0x200000>; + no-map; + phandle = <0x9b>; + }; + + vdev0vring0@c0876000 { + reg = <0x00 0xc0876000 0x00 0x3000>; + no-map; + phandle = <0x9c>; + }; + + vdev0vring1@c0879000 { + reg = <0x00 0xc0879000 0x00 0x3000>; + no-map; + phandle = <0x9e>; + }; + + vdev0vring2@c087c000 { + reg = <0x00 0xc087c000 0x00 0x1000>; + no-map; + }; + + vdev0buffer@100700000 { + compatible = "shared-dma-pool"; + reg = <0x01 0x700000 0x00 0xfc000>; + no-map; + phandle = <0x9d>; + }; + + rcpu0_rsc_table@1007fc000 { + reg = <0x01 0x7fc000 0x00 0x4000>; + no-map; + phandle = <0x9f>; + }; + + rpmi0@100800000 { + reg = <0x01 0x800000 0x00 0x4000>; + no-map; + }; + + rcpu1_runtime@100804000 { + reg = <0x01 0x804000 0x00 0x300000>; + no-map; + phandle = <0xa2>; + }; + + rcpu1_heap@100B04000 { + reg = <0x01 0xb04000 0x00 0x200000>; + no-map; + phandle = <0xa3>; + }; + + vdev0vring0@c086c000 { + reg = <0x00 0xc086c000 0x00 0x3000>; + no-map; + phandle = <0xa4>; + }; + + vdev0vring1@c086f000 { + reg = <0x00 0xc086f000 0x00 0x3000>; + no-map; + phandle = <0xa6>; + }; + + vdev0buffer@100d04000 { + compatible = "shared-dma-pool"; + reg = <0x01 0xd04000 0x00 0xfc000>; + no-map; + phandle = <0xa5>; + }; + + rcpu1_rsc_table@100e00000 { + reg = <0x01 0xe00000 0x00 0x4000>; + no-map; + phandle = <0xa7>; + }; + + rcpu_dtb_table@100e04000 { + reg = <0x01 0xe04000 0x00 0x300000>; + no-map; + }; + + dpu_reserved@101b00000 { + compatible = "shared-dma-pool"; + reg = <0x01 0x1b00000 0x00 0x280000>; + no-map; + phandle = <0xf2>; + }; + + dpu_reserved1@101d80000 { + compatible = "shared-dma-pool"; + reg = <0x01 0x1d80000 0x00 0x280000>; + no-map; + phandle = <0xf5>; + }; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x00 0x20000000>; + alloc-ranges = <0x01 0x40000000 0x00 0x20000000>; + linux,cma-default; + }; + }; + + lcds { + status = "okay"; + + lcd_tc358762xbg_dpi_800x480 { + dsi-work-mode = <0x01>; + dsi-lane-number = <0x01>; + dsi-color-format = "rgb888"; + width-mm = <0x5f>; + height-mm = <0x35>; + use-dcs-write; + height = <0x1e0>; + width = <0x320>; + hfp = <0x01>; + hbp = <0x2e>; + hsync = <0x02>; + vfp = <0x07>; + vbp = <0x15>; + vsync = <0x02>; + fps = <0x37>; + work-mode = <0x00>; + rgb-mode = <0x03>; + lane-number = <0x01>; + phy-freq = <0xaae60>; + phy-escape-clock = <0xcb20>; + phy-bit-clock = <0x29b92700>; + split-enable = <0x00>; + eotp-enable = <0x00>; + burst-mode = <0x02>; + esd-check-enable = <0x00>; + initial-command = [39 01 f0 01 11 39 01 28 01 29]; + sleep-in-command = [39 01 78 01 28 39 01 78 01 10]; + sleep-out-command = [39 01 96 01 11 39 01 32 01 29]; + + display-timings { + + timing0 { + clock-frequency = <0x17d7840>; + hactive = <0x320>; + hfront-porch = <0x01>; + hback-porch = <0x2e>; + hsync-len = <0x02>; + vactive = <0x1e0>; + vfront-porch = <0x07>; + vback-porch = <0x15>; + vsync-len = <0x02>; + vsync-active = <0x01>; + hsync-active = <0x01>; + }; + }; + }; + }; + + chosen { + bootargs = "earlycon=sbi console=ttyS0,115200 loglevel=8 random.trust_bootloader=1 unaligned_scalar_speed=fast unaligned_vector_speed=fast"; + rng-seed = <0x25d69b2 0xff555073 0xd23238ea 0x57aa5455 0x792478ed 0xa744f28e 0x6ba4fc54 0xa2bf20fc>; + stdout-path = "serial0:115200"; + }; + + rfkill-pcie-wlan { + compatible = "rfkill-gpio"; + label = "rfkill-pcie-wlan"; + pinctrl-names = "default"; + pinctrl-0 = <0x101>; + radio-type = "wlan"; + shutdown-gpios = <0x8b 0x02 0x09 0x01>; + }; + + rfkill-m2-bt { + compatible = "rfkill-gpio"; + label = "rfkill-m2-bt"; + pinctrl-names = "default"; + pinctrl-0 = <0x102>; + radio-type = "bluetooth"; + shutdown-gpios = <0x8b 0x01 0x19 0x01>; + }; + + hub-reset { + compatible = "regulator-fixed"; + regulator-name = "hub-reset"; + regulator-min-microvolt = <0x325aa0>; + regulator-max-microvolt = <0x325aa0>; + enable-active-high; + regulator-boot-on; + gpio = <0x8b 0x01 0x15 0x00>; + phandle = <0xc3>; + }; +}; diff --git a/platform/riscv64/k3-com260/image/dts/zone0.dts b/platform/riscv64/k3-com260/image/dts/zone0.dts new file mode 100644 index 000000000..d24709138 --- /dev/null +++ b/platform/riscv64/k3-com260/image/dts/zone0.dts @@ -0,0 +1,4005 @@ +/dts-v1/; + +/ { + #address-cells = <0x02>; + #size-cells = <0x02>; + model = "SpacemiT K3 Com260 IFX"; + compatible = "spacemit,k3-com260-ifx"; + + cpus { + #address-cells = <0x01>; + #size-cells = <0x00>; + timebase-frequency = <0x16e3600>; + + cpu@0 { + device_type = "cpu"; + reg = <0x00>; + model = "Spacemit(R) X100"; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdcv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i\0m\0a\0f\0d\0c\0v\0smaia\0smstateen\0ssaia\0sscofpmf\0sstc\0svpbmt\0svinval\0svnapot\0zawrs\0zba\0zbb\0zbc\0zbs\0zcb\0zca\0zcmop\0zfa\0zfh\0zfhmin\0zkt\0zicbom\0zicbop\0zicboz\0zicntr\0zicond\0zicsr\0zifencei\0zihintpause\0zihintntl\0zihpm\0zimop\0zvbb\0zvbc\0zvfh\0zvfhmin\0zvkb\0zvkg\0zvkn\0zvknc\0zvkned\0zvkng\0zvknha\0zvknhb\0zvks\0zvksc\0zvksed\0zvksh\0zvksg\0zvkt\0zcd"; + riscv,cbom-block-size = <0x40>; + riscv,cboz-block-size = <0x40>; + riscv,cbop-block-size = <0x40>; + i-cache-block-size = <0x40>; + i-cache-size = <0x10000>; + i-cache-sets = <0x100>; + d-cache-block-size = <0x40>; + d-cache-size = <0x10000>; + d-cache-sets = <0x100>; + next-level-cache = <0x01>; + // cpu-idle-states = <0x02 0x03>; + mmu-type = "riscv,sv39"; + #cooling-cells = <0x02>; + clst-supply = <0x04>; + clocks = <0x05 0x04 0x05 0x05>; + clock-names = "cls0\0cls1"; + // operating-points-v2 = <0x06>; + phandle = <0x0b>; + + interrupt-controller { + #interrupt-cells = <0x01>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + phandle = <0x69>; + }; + }; + + cpu@1 { + device_type = "cpu"; + reg = <0x01>; + model = "Spacemit(R) X100"; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdcv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i\0m\0a\0f\0d\0c\0v\0smaia\0smstateen\0ssaia\0sscofpmf\0sstc\0svpbmt\0svinval\0svnapot\0zawrs\0zba\0zbb\0zbc\0zbs\0zcb\0zca\0zcmop\0zfa\0zfh\0zfhmin\0zkt\0zicbom\0zicbop\0zicboz\0zicntr\0zicond\0zicsr\0zifencei\0zihintpause\0zihintntl\0zihpm\0zimop\0zvbb\0zvbc\0zvfh\0zvfhmin\0zvkb\0zvkg\0zvkn\0zvknc\0zvkned\0zvkng\0zvknha\0zvknhb\0zvks\0zvksc\0zvksed\0zvksh\0zvksg\0zvkt\0zcd"; + riscv,cbom-block-size = <0x40>; + riscv,cboz-block-size = <0x40>; + riscv,cbop-block-size = <0x40>; + i-cache-block-size = <0x40>; + i-cache-size = <0x10000>; + i-cache-sets = <0x100>; + d-cache-block-size = <0x40>; + d-cache-size = <0x10000>; + d-cache-sets = <0x100>; + next-level-cache = <0x01>; + // cpu-idle-states = <0x02 0x03>; + mmu-type = "riscv,sv39"; + #cooling-cells = <0x02>; + clst-supply = <0x04>; + clocks = <0x05 0x04 0x05 0x05>; + clock-names = "cls0\0cls1"; + // operating-points-v2 = <0x06>; + phandle = <0x0c>; + + interrupt-controller { + #interrupt-cells = <0x01>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + phandle = <0x6a>; + }; + }; + + cpu@2 { + device_type = "cpu"; + reg = <0x02>; + model = "Spacemit(R) X100"; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdcv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i\0m\0a\0f\0d\0c\0v\0smaia\0smstateen\0ssaia\0sscofpmf\0sstc\0svpbmt\0svinval\0svnapot\0zawrs\0zba\0zbb\0zbc\0zbs\0zcb\0zca\0zcmop\0zfa\0zfh\0zfhmin\0zkt\0zicbom\0zicbop\0zicboz\0zicntr\0zicond\0zicsr\0zifencei\0zihintpause\0zihintntl\0zihpm\0zimop\0zvbb\0zvbc\0zvfh\0zvfhmin\0zvkb\0zvkg\0zvkn\0zvknc\0zvkned\0zvkng\0zvknha\0zvknhb\0zvks\0zvksc\0zvksed\0zvksh\0zvksg\0zvkt\0zcd"; + riscv,cbom-block-size = <0x40>; + riscv,cboz-block-size = <0x40>; + riscv,cbop-block-size = <0x40>; + i-cache-block-size = <0x40>; + i-cache-size = <0x10000>; + i-cache-sets = <0x100>; + d-cache-block-size = <0x40>; + d-cache-size = <0x10000>; + d-cache-sets = <0x100>; + next-level-cache = <0x01>; + // cpu-idle-states = <0x02 0x03>; + mmu-type = "riscv,sv39"; + #cooling-cells = <0x02>; + clst-supply = <0x04>; + clocks = <0x05 0x04 0x05 0x05>; + clock-names = "cls0\0cls1"; + // operating-points-v2 = <0x06>; + phandle = <0x0d>; + + interrupt-controller { + #interrupt-cells = <0x01>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + phandle = <0x6b>; + }; + }; + + cpu@3 { + device_type = "cpu"; + reg = <0x03>; + model = "Spacemit(R) X100"; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdcv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i\0m\0a\0f\0d\0c\0v\0smaia\0smstateen\0ssaia\0sscofpmf\0sstc\0svpbmt\0svinval\0svnapot\0zawrs\0zba\0zbb\0zbc\0zbs\0zcb\0zca\0zcmop\0zfa\0zfh\0zfhmin\0zkt\0zicbom\0zicbop\0zicboz\0zicntr\0zicond\0zicsr\0zifencei\0zihintpause\0zihintntl\0zihpm\0zimop\0zvbb\0zvbc\0zvfh\0zvfhmin\0zvkb\0zvkg\0zvkn\0zvknc\0zvkned\0zvkng\0zvknha\0zvknhb\0zvks\0zvksc\0zvksed\0zvksh\0zvksg\0zvkt\0zcd"; + riscv,cbom-block-size = <0x40>; + riscv,cboz-block-size = <0x40>; + riscv,cbop-block-size = <0x40>; + i-cache-block-size = <0x40>; + i-cache-size = <0x10000>; + i-cache-sets = <0x100>; + d-cache-block-size = <0x40>; + d-cache-size = <0x10000>; + d-cache-sets = <0x100>; + next-level-cache = <0x01>; + // cpu-idle-states = <0x02 0x03>; + mmu-type = "riscv,sv39"; + #cooling-cells = <0x02>; + clst-supply = <0x04>; + clocks = <0x05 0x04 0x05 0x05>; + clock-names = "cls0\0cls1"; + // operating-points-v2 = <0x06>; + phandle = <0x0e>; + + interrupt-controller { + #interrupt-cells = <0x01>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + phandle = <0x6c>; + }; + }; + + cpu@4 { + device_type = "cpu"; + reg = <0x04>; + model = "Spacemit(R) X100"; + status = "disabled"; + compatible = "riscv"; + riscv,isa = "rv64imafdcv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i\0m\0a\0f\0d\0c\0v\0smaia\0smstateen\0ssaia\0sscofpmf\0sstc\0svpbmt\0svinval\0svnapot\0zawrs\0zba\0zbb\0zbc\0zbs\0zcb\0zca\0zcmop\0zfa\0zfh\0zfhmin\0zkt\0zicbom\0zicbop\0zicboz\0zicntr\0zicond\0zicsr\0zifencei\0zihintpause\0zihintntl\0zihpm\0zimop\0zvbb\0zvbc\0zvfh\0zvfhmin\0zvkb\0zvkg\0zvkn\0zvknc\0zvkned\0zvkng\0zvknha\0zvknhb\0zvks\0zvksc\0zvksed\0zvksh\0zvksg\0zvkt\0zcd"; + riscv,cbom-block-size = <0x40>; + riscv,cboz-block-size = <0x40>; + riscv,cbop-block-size = <0x40>; + i-cache-block-size = <0x40>; + i-cache-size = <0x10000>; + i-cache-sets = <0x100>; + d-cache-block-size = <0x40>; + d-cache-size = <0x10000>; + d-cache-sets = <0x100>; + next-level-cache = <0x07>; + // cpu-idle-states = <0x02 0x03>; + mmu-type = "riscv,sv39"; + #cooling-cells = <0x02>; + clst-supply = <0x04>; + clocks = <0x05 0x04 0x05 0x05>; + clock-names = "cls0\0cls1"; + // operating-points-v2 = <0x06>; + phandle = <0x0f>; + + interrupt-controller { + #interrupt-cells = <0x01>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + phandle = <0x6d>; + }; + }; + + cpu@5 { + device_type = "cpu"; + reg = <0x05>; + model = "Spacemit(R) X100"; + status = "disabled"; + compatible = "riscv"; + riscv,isa = "rv64imafdcv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i\0m\0a\0f\0d\0c\0v\0smaia\0smstateen\0ssaia\0sscofpmf\0sstc\0svpbmt\0svinval\0svnapot\0zawrs\0zba\0zbb\0zbc\0zbs\0zcb\0zca\0zcmop\0zfa\0zfh\0zfhmin\0zkt\0zicbom\0zicbop\0zicboz\0zicntr\0zicond\0zicsr\0zifencei\0zihintpause\0zihintntl\0zihpm\0zimop\0zvbb\0zvbc\0zvfh\0zvfhmin\0zvkb\0zvkg\0zvkn\0zvknc\0zvkned\0zvkng\0zvknha\0zvknhb\0zvks\0zvksc\0zvksed\0zvksh\0zvksg\0zvkt\0zcd"; + riscv,cbom-block-size = <0x40>; + riscv,cboz-block-size = <0x40>; + riscv,cbop-block-size = <0x40>; + i-cache-block-size = <0x40>; + i-cache-size = <0x10000>; + i-cache-sets = <0x100>; + d-cache-block-size = <0x40>; + d-cache-size = <0x10000>; + d-cache-sets = <0x100>; + next-level-cache = <0x07>; + // cpu-idle-states = <0x02 0x03>; + mmu-type = "riscv,sv39"; + #cooling-cells = <0x02>; + clst-supply = <0x04>; + clocks = <0x05 0x04 0x05 0x05>; + clock-names = "cls0\0cls1"; + // operating-points-v2 = <0x06>; + phandle = <0x10>; + + interrupt-controller { + #interrupt-cells = <0x01>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + phandle = <0x6e>; + }; + }; + + cpu@6 { + device_type = "cpu"; + reg = <0x06>; + model = "Spacemit(R) X100"; + status = "disabled"; + compatible = "riscv"; + riscv,isa = "rv64imafdcv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i\0m\0a\0f\0d\0c\0v\0smaia\0smstateen\0ssaia\0sscofpmf\0sstc\0svpbmt\0svinval\0svnapot\0zawrs\0zba\0zbb\0zbc\0zbs\0zcb\0zca\0zcmop\0zfa\0zfh\0zfhmin\0zkt\0zicbom\0zicbop\0zicboz\0zicntr\0zicond\0zicsr\0zifencei\0zihintpause\0zihintntl\0zihpm\0zimop\0zvbb\0zvbc\0zvfh\0zvfhmin\0zvkb\0zvkg\0zvkn\0zvknc\0zvkned\0zvkng\0zvknha\0zvknhb\0zvks\0zvksc\0zvksed\0zvksh\0zvksg\0zvkt\0zcd"; + riscv,cbom-block-size = <0x40>; + riscv,cboz-block-size = <0x40>; + riscv,cbop-block-size = <0x40>; + i-cache-block-size = <0x40>; + i-cache-size = <0x10000>; + i-cache-sets = <0x100>; + d-cache-block-size = <0x40>; + d-cache-size = <0x10000>; + d-cache-sets = <0x100>; + next-level-cache = <0x07>; + // cpu-idle-states = <0x02 0x03>; + mmu-type = "riscv,sv39"; + #cooling-cells = <0x02>; + clst-supply = <0x04>; + clocks = <0x05 0x04 0x05 0x05>; + clock-names = "cls0\0cls1"; + // operating-points-v2 = <0x06>; + phandle = <0x11>; + + interrupt-controller { + #interrupt-cells = <0x01>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + phandle = <0x6f>; + }; + }; + + cpu@7 { + device_type = "cpu"; + reg = <0x07>; + model = "Spacemit(R) X100"; + status = "disabled"; + compatible = "riscv"; + riscv,isa = "rv64imafdcv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i\0m\0a\0f\0d\0c\0v\0smaia\0smstateen\0ssaia\0sscofpmf\0sstc\0svpbmt\0svinval\0svnapot\0zawrs\0zba\0zbb\0zbc\0zbs\0zcb\0zca\0zcmop\0zfa\0zfh\0zfhmin\0zkt\0zicbom\0zicbop\0zicboz\0zicntr\0zicond\0zicsr\0zifencei\0zihintpause\0zihintntl\0zihpm\0zimop\0zvbb\0zvbc\0zvfh\0zvfhmin\0zvkb\0zvkg\0zvkn\0zvknc\0zvkned\0zvkng\0zvknha\0zvknhb\0zvks\0zvksc\0zvksed\0zvksh\0zvksg\0zvkt\0zcd"; + riscv,cbom-block-size = <0x40>; + riscv,cboz-block-size = <0x40>; + riscv,cbop-block-size = <0x40>; + i-cache-block-size = <0x40>; + i-cache-size = <0x10000>; + i-cache-sets = <0x100>; + d-cache-block-size = <0x40>; + d-cache-size = <0x10000>; + d-cache-sets = <0x100>; + next-level-cache = <0x07>; + // cpu-idle-states = <0x02 0x03>; + mmu-type = "riscv,sv39"; + #cooling-cells = <0x02>; + clst-supply = <0x04>; + clocks = <0x05 0x04 0x05 0x05>; + clock-names = "cls0\0cls1"; + // operating-points-v2 = <0x06>; + phandle = <0x12>; + + interrupt-controller { + #interrupt-cells = <0x01>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + phandle = <0x70>; + }; + }; + + l2-cache1 { + compatible = "cache"; + cache-block-size = <0x40>; + cache-level = <0x02>; + cache-size = <0x400000>; + cache-sets = <0x1000>; + cache-unified; + phandle = <0x01>; + }; + + l2-cache2 { + compatible = "cache"; + cache-block-size = <0x40>; + cache-level = <0x02>; + cache-size = <0x400000>; + cache-sets = <0x1000>; + cache-unified; + phandle = <0x07>; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <0x0b>; + }; + + core1 { + cpu = <0x0c>; + }; + + core2 { + cpu = <0x0d>; + }; + + core3 { + cpu = <0x0e>; + }; + }; + + cluster1 { + + core0 { + cpu = <0x0f>; + }; + + core1 { + cpu = <0x10>; + }; + + core2 { + cpu = <0x11>; + }; + + core3 { + cpu = <0x12>; + }; + }; + }; + }; + + riscv-timer { + compatible = "riscv,timer"; + riscv,timer-cannot-wake-cpu; + }; + + soc { + #address-cells = <0x02>; + #size-cells = <0x02>; + compatible = "simple-bus"; + dma-noncoherent; + ranges; + + interrupt-controller@e0400000 { + compatible = "riscv,imsics"; + interrupts-extended = <0x69 0x09 0x6a 0x09 0x6b 0x09 0x6c 0x09>; + reg = <0x00 0xe0400000 0x00 0x4000>; + interrupt-controller; + #interrupt-cells = <0x00>; + #msi-cells = <0x00>; + msi-controller; + riscv,num-ids = <0x1ff>; + riscv,num-guest-ids = <0x1ff>; + riscv,hart-index-bits = <0x03>; + riscv,guest-index-bits = <0>; + status = "okay"; + phandle = <0x79>; + }; + + interrupt-controller@e0804000 { + compatible = "riscv,aplic"; + reg = <0x00 0xe0804000 0x00 0x4000>; + msi-parent = <0x79>; + #interrupt-cells = <0x02>; + interrupt-controller; + riscv,num-sources = <0x200>; + status = "okay"; + phandle = <0x82>; + }; + + system-controller@d4050000 { + compatible = "spacemit,k3-syscon-mpmu"; + reg = <0x00 0xd4050000 0x00 0x10000>; + clocks = <0x7a 0x7b 0x7c 0x7d 0x7e 0x7f>; + clock-names = "osc_32k\0vctcxo_1m\0vctcxo_3m\0vctcxo_24m\0reserved_clk\0external_clk"; + #clock-cells = <0x01>; + #reset-cells = <0x01>; + phandle = <0x80>; + }; + + clock-controller@d4090000 { + compatible = "spacemit,k3-pll"; + reg = <0x00 0xd4090000 0x00 0x10000>; + clocks = <0x7d>; + spacemit,mpmu = <0x80>; + #clock-cells = <0x01>; + phandle = <0x1b>; + }; + + system-controller@d4282800 { + compatible = "spacemit,k3-syscon-apmu"; + reg = <0x00 0xd4282800 0x00 0x400>; + clocks = <0x7a 0x7b 0x7c 0x7d 0x7e 0x7f>; + clock-names = "osc_32k\0vctcxo_1m\0vctcxo_3m\0vctcxo_24m\0reserved_clk\0external_clk"; + #clock-cells = <0x01>; + #power-domain-cells = <0x01>; + #reset-cells = <0x01>; + phandle = <0x05>; + }; + + system-controller@d4015000 { + compatible = "spacemit,k3-syscon-apbc"; + reg = <0x00 0xd4015000 0x00 0x1000>; + clocks = <0x7a 0x7b 0x7c 0x7d 0x7e 0x7f>; + clock-names = "osc_32k\0vctcxo_1m\0vctcxo_3m\0vctcxo_24m\0reserved_clk\0external_clk"; + #clock-cells = <0x01>; + #reset-cells = <0x01>; + phandle = <0x81>; + }; + + syscon-gpio { + compatible = "syscon"; + reg = <0x00 0xd4019000 0x00 0x800>; + phandle = <0x83>; + }; + + syscon-gpio-edge { + compatible = "syscon"; + reg = <0x00 0xd4019800 0x00 0x10>; + phandle = <0x84>; + }; + + gpio@d4019000 { + compatible = "spacemit,k3-gpio"; + reg = <0x00 0xd4019000 0x00 0x100>; + clocks = <0x81 0x14 0x81 0x15>; + clock-names = "core\0bus"; + gpio-controller; + #gpio-cells = <0x03>; + interrupts = <0x3a 0x04>; + interrupt-parent = <0x82>; + interrupt-controller; + #interrupt-cells = <0x03>; + syscon-gpio-regs = <0x83>; + syscon-gpio-edge = <0x84>; + gpio-ranges = <0x85 0x00 0x00 0x00 0x20 0x85 0x01 0x00 0x20 0x20 0x85 0x02 0x00 0x40 0x20 0x85 0x03 0x00 0x60 0x20>; + phandle = <0x8b>; + }; + + pinctrl@d401e000 { + compatible = "spacemit,k3-pinctrl"; + reg = <0x00 0xd401e000 0x00 0x400 0x00 0xd401e800 0x00 0x34>; + clocks = <0x81 0x67 0x81 0x68>; + clock-names = "func\0bus"; + interrupt-controller; + #interrupt-cells = <0x02>; + interrupts = <0x3c 0x04>; + interrupt-parent = <0x82>; + spacemit,gpio-edge = <0x84>; + spacemit,apbc = <0x81 0x50>; + spacemit,apmu = <0x05>; + phandle = <0x85>; + + uart0-0-cfg { + phandle = <0x86>; + + uart0-0-pins { + pinmux = <0x950002 0x960002>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + uart0-1-cfg { + + uart0-0-pins { + pinmux = <0x840002 0x850002>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + uart0-2-cfg { + + uart0-0-pins { + pinmux = <0x910005 0x920005>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + uart0-3-cfg { + + uart0-0-pins { + pinmux = <0x2a0002 0x2b0002>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + uart0-4-cfg { + + uart0-0-pins { + pinmux = <0x5d0003 0x5e0003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + uart1-0-cfg { + + uart1-0-pins { + pinmux = <0x5f0002 0x600002 0x610002 0x620002>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + uart1-1-cfg { + + uart1-0-pins { + pinmux = <0x760001 0x770001 0x780001 0x790001>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + uart2-0-cfg { + + uart2-0-pins { + pinmux = <0x860002 0x870002 0x880002 0x890002>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + uart2-1-cfg { + + uart2-0-pins { + pinmux = <0x610001 0x620001>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + uart3-0-cfg { + + uart3-0-pins { + pinmux = <0x1a0002 0x1b0002 0x1c0002 0x1d0002>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + uart3-1-cfg { + + uart3-0-pins { + pinmux = <0x350002 0x360002 0x370002 0x380002>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + uart4-0-cfg { + + uart4-0-pins { + pinmux = <0x560003 0x570003 0x5a0003 0x5b0003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + uart4-1-cfg { + + uart4-0-pins { + pinmux = <0x630003 0x640003 0x650003 0x660003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + uart5-0-cfg { + + uart5-0-pins { + pinmux = <0x910004 0x920004>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + uart5-1-cfg { + + uart5-0-pins { + pinmux = <0x150002 0x160002 0x170002 0x180002>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + uart5-2-cfg { + + uart5-0-pins { + pinmux = <0x520004 0x530004>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + uart6-0-cfg { + + uart6-0-pins { + pinmux = <0x300002 0x310002 0x320002 0x330002>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + uart6-1-cfg { + + uart6-0-pins { + pinmux = <0x7a0003 0x7b0003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + uart7-0-cfg { + + uart7-0-pins { + pinmux = <0xb0002 0xc0002 0xd0002 0xe0002>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + uart7-1-cfg { + + uart7-0-pins { + pinmux = <0x170005 0x180005 0x190005 0x1a0005>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + uart8-0-cfg { + + uart8-0-pins { + pinmux = <0xb0005 0xc0005>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + uart8-1-cfg { + + uart8-0-pins { + pinmux = <0x4c0003 0x4d0003 0x4e0003 0x4f0003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + uart9-0-cfg { + + uart9-0-pins { + pinmux = <0x930004 0x940004>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + uart9-1-cfg { + + uart9-0-pins { + pinmux = <0x520003 0x530003 0x540003 0x550003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + uart10-0-cfg { + + uart10-0-pins { + pinmux = <0x1f0002 0x200002 0x210002 0x220002>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + uart10-1-cfg { + + uart10-0-pins { + pinmux = <0x2c0002 0x2d0002 0x2e0002 0x2f0002>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + ruart0-0-cfg { + + ruart0-0-pins { + pinmux = <0x840004 0x850004>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + ruart0-1-cfg { + + ruart0-0-pins { + pinmux = <0x910006 0x920006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + ruart0-2-cfg { + + ruart0-0-pins { + pinmux = <0x6d0003 0x6e0003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + ruart0-3-cfg { + + ruart0-0-pins { + pinmux = <0x7a0004 0x7b0004>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + ruart1_0-cfg { + + ruart1-0-pins { + pinmux = <0x8a0002 0x8b0002 0x8c0002 0x8d0002>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + ruart1-1-cfg { + + ruart1-0-pins { + pinmux = <0x110005 0x120005 0x130005 0x140005>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + ruart2-0-cfg { + + ruart2-0-pins { + pinmux = <0x390002 0x3a0002>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + ruart3-0-cfg { + + ruart3-0-pins { + pinmux = <0x370004 0x380004>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + ruart3-1-cfg { + + ruart3-0-pins { + pinmux = <0x580003 0x590003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + ruart4-0-cfg { + + ruart4-0-pins { + pinmux = <0x150005 0x160005>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + ruart4-1-cfg { + + ruart4-0-pins { + pinmux = <0x500003 0x510003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + ruart5-0-cfg { + + ruart5-0-pins { + pinmux = <0x3b0002 0x3c0002>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + i2c0-0-cfg { + phandle = <0x89>; + + i2c0-0-pins { + pinmux = <0x06 0x10006>; + bias-pull-up; + drive-strength = <0x19>; + power-source = <0xce4>; + }; + }; + + i2c0-1-cfg { + + i2c0-0-pins { + pinmux = <0x2a0005 0x2b0005>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + i2c0-2-cfg { + + i2c0-0-pins { + pinmux = <0x300005 0x310005>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + i2c0-3-cfg { + + i2c0-0-pins { + pinmux = <0x4c0006 0x4d0006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + i2c0-4-cfg { + + i2c0-0-pins { + pinmux = <0x730004 0x740004>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + i2c1-0-cfg { + + i2c1-0-pins { + pinmux = <0x20006 0x30006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + i2c1-1-cfg { + phandle = <0x8e>; + + i2c1-0-pins { + pinmux = <0x360005 0x370005>; + bias-pull-up; + drive-strength = <0x19>; + power-source = <0x708>; + }; + }; + + i2c1-2-cfg { + + i2c1-0-pins { + pinmux = <0x4e0006 0x4f0006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + i2c1-3-cfg { + + i2c1-0-pins { + pinmux = <0x660006 0x670006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + i2c2-0-cfg { + + i2c2-0-pins { + pinmux = <0x50006 0x60006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + i2c2-1-cfg { + phandle = <0x8f>; + + i2c2-0-pins { + pinmux = <0x2e0005 0x2f0005>; + bias-pull-up; + drive-strength = <0x19>; + power-source = <0x708>; + }; + }; + + i2c2-2-cfg { + + i2c2-0-pins { + pinmux = <0x500006 0x510006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + i2c2-3-cfg { + + i2c2-0-pins { + pinmux = <0x780002 0x790002>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + i2c3-0-cfg { + + i2c3-0-pins { + pinmux = <0x8e0005 0x8f0005>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + i2c3-1-cfg { + + i2c3-0-pins { + pinmux = <0x240004 0x250004>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + i2c3-2-cfg { + phandle = <0x90>; + + i2c3-0-pins { + pinmux = <0x520006 0x530006>; + bias-pull-up; + drive-strength = <0x19>; + power-source = <0xce4>; + }; + }; + + i2c3-3-cfg { + + i2c3-0-pins { + pinmux = <0x690004 0x6a0004>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + i2c4-0-cfg { + + i2c4-0-pins { + pinmux = <0x880006 0x890006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + i2c4-1-cfg { + + i2c4-0-pins { + pinmux = <0xb0006 0xc0006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + i2c4-2-cfg { + + i2c4-0-pins { + pinmux = <0x320005 0x330005>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + i2c4-3-cfg { + + i2c4-0-pins { + pinmux = <0x6f0004 0x700004>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + touchpad-int-cfg { + + touchpad-int-pins { + pinmux = <0x1a0000>; + bias-pull-up; + power-source = <0xce4>; + }; + }; + + i2c5-0-cfg { + + i2c5-0-pins { + pinmux = <0x190006 0x1a0006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + i2c5-1-cfg { + + i2c5-0-pins { + pinmux = <0x3f0005 0x400005>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + i2c5-2-cfg { + phandle = <0x92>; + + i2c5-0-pins { + pinmux = <0x5d0005 0x5e0005>; + bias-pull-up; + drive-strength = <0x19>; + power-source = <0x708>; + }; + }; + + i2c5-3-cfg { + + i2c5-0-pins { + pinmux = <0x7e0004 0x7f0004>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + i2c6-0-cfg { + + i2c6-0-pins { + pinmux = <0x970002 0x980002>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + i2c6-1-cfg { + phandle = <0x96>; + + i2c6-0-pins { + pinmux = <0x70006 0x80006>; + bias-pull-up; + drive-strength = <0x12>; + power-source = <0xce4>; + }; + }; + + i2c6-2-cfg { + + i2c6-0-pins { + pinmux = <0xe0006 0xf0006>; + bias-pull-up; + drive-strength = <0x12>; + }; + }; + + i2c6-3-cfg { + + i2c6-0-pins { + pinmux = <0x3d0005 0x3e0005>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + i2c8-cfg { + + i2c8-pins { + pinmux = <0x800000 0x810000>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + i2c8-cfg-rcpu { + phandle = <0xa9>; + + i2c8-pins-rcpu { + pinmux = <0x800001 0x810001>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + ri2c0-0-cfg { + + ri2c0-0-pins { + pinmux = <0x1b0006 0x1c0006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + ri2c0-1-cfg { + + ri2c0-0-pins { + pinmux = <0x390005 0x3a0005>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + ri2c0-2-cfg { + + ri2c0-0-pins { + pinmux = <0x4a0006 0x4b0006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + ri2c0-3-cfg { + + ri2c0-0-pins { + pinmux = <0x730006 0x740006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + ri2c1-0-cfg { + + ri2c1-0-pins { + pinmux = <0x210006 0x220006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + ri2c1-1-cfg { + + ri2c1-0-pins { + pinmux = <0x270004 0x280004>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + ri2c1-2-cfg { + + ri2c1-0-pins { + pinmux = <0x3b0005 0x3c0005>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + ri2c1-3-cfg { + + ri2c1-0-pins { + pinmux = <0x690003 0x6a0003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm0-0-cfg { + + pwm0-0-pins { + pinmux = <0x2b0006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm0-1-cfg { + + pwm0-0-pins { + pinmux = <0x2a0006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm1-0-cfg { + + pwm1-0-pins { + pinmux = <0x10003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm1-2-cfg { + + pwm1-0-pins { + pinmux = <0x5f0006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm2-0-cfg { + + pwm2-0-pins { + pinmux = <0x20003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm2-1-cfg { + + pwm2-0-pins { + pinmux = <0x2c0006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm2-2-cfg { + + pwm2-0-pins { + pinmux = <0x600006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm2-3-cfg { + + pwm2-0-pins { + pinmux = <0x860004>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm3-0-cfg { + + pwm3-0-pins { + pinmux = <0x30003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm3-1-cfg { + + pwm3-0-pins { + pinmux = <0x2d0006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm3-2-cfg { + + pwm3-0-pins { + pinmux = <0x610006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm3-3-cfg { + + pwm3-0-pins { + pinmux = <0x870004>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm4-0-cfg { + + pwm4-0-pins { + pinmux = <0x40003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm4-1-cfg { + + pwm4-0-pins { + pinmux = <0x2e0006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm4-2-cfg { + + pwm4-0-pins { + pinmux = <0x880004>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm5-0-cfg { + + pwm5-0-pins { + pinmux = <0x50003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm5-1-cfg { + + pwm5-0-pins { + pinmux = <0x2f0006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm5-2-cfg { + + pwm5-0-pins { + pinmux = <0x890004>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm6-0-cfg { + + pwm6-0-pins { + pinmux = <0x60003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm6-1-cfg { + + pwm6-0-pins { + pinmux = <0x910003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm6-2-cfg { + + pwm6-0-pins { + pinmux = <0x300006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm7-0-cfg { + + pwm7-0-pins { + pinmux = <0x70003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm7-1-cfg { + + pwm7-0-pins { + pinmux = <0x920003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm7-2-cfg { + + pwm7-0-pins { + pinmux = <0x310006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm8-0-cfg { + + pwm8-0-pins { + pinmux = <0x80003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm8-1-cfg { + + pwm8-0-pins { + pinmux = <0x930003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm8-2-cfg { + + pwm8-0-pins { + pinmux = <0x320006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm9-0-cfg { + + pwm9-0-pins { + pinmux = <0x90003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm9-1-cfg { + + pwm9-0-pins { + pinmux = <0x940003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm9-2-cfg { + + pwm9-0-pins { + pinmux = <0x330006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm10-0-cfg { + + pwm10-0-pins { + pinmux = <0xa0003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm10-1-cfg { + + pwm10-0-pins { + pinmux = <0x340006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm10-2-cfg { + + pwm10-0-pins { + pinmux = <0x8d0004>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm11-0-cfg { + + pwm11-0-pins { + pinmux = <0x350006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm11-1-cfg { + + pwm11-0-pins { + pinmux = <0x8c0004>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm12-0-cfg { + + pwm12-0-pins { + pinmux = <0x360006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm12-1-cfg { + + pwm12-0-pins { + pinmux = <0x8b0004>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm13-0-cfg { + + pwm13-0-pins { + pinmux = <0x370006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm13-1-cfg { + + pwm13-0-pins { + pinmux = <0x8a0004>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm13-2-cfg { + + pwm13-0-pins { + pinmux = <0xd0003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm14-0-cfg { + + pwm14-0-pins { + pinmux = <0x380006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm14-1-cfg { + + pwm14-0-pins { + pinmux = <0x900004>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm14-2-cfg { + + pwm14-0-pins { + pinmux = <0xe0003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm15-0-cfg { + + pwm15-0-pins { + pinmux = <0x390006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm15-1-cfg { + + pwm15-0-pins { + pinmux = <0x8e0004>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm15-2-cfg { + + pwm15-0-pins { + pinmux = <0x150003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm16-0-cfg { + + pwm16-0-pins { + pinmux = <0x3a0006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm16-1-cfg { + + pwm16-0-pins { + pinmux = <0x8f0004>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm16-2-cfg { + + pwm16-0-pins { + pinmux = <0x160003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm17-0-cfg { + + pwm17-0-pins { + pinmux = <0x170003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm17-1-cfg { + + pwm17-0-pins { + pinmux = <0x3b0006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm17-2-cfg { + + pwm17-0-pins { + pinmux = <0x690006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm18-0-cfg { + + pwm18-0-pins { + pinmux = <0x180003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm18-1-cfg { + + pwm18-0-pins { + pinmux = <0x3c0006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm18-2-cfg { + + pwm18-0-pins { + pinmux = <0x6a0006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm19-0-cfg { + + pwm19-0-pins { + pinmux = <0x190003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm19-1-cfg { + + pwm19-0-pins { + pinmux = <0x3d0006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwm19-2-cfg { + + pwm19-0-pins { + pinmux = <0x6b0006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rpwm0-0-cfg { + + rpwm0-0-pins { + pinmux = <0xf0003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rpwm0-1-cfg { + + rpwm0-0-pins { + pinmux = <0x1b0003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rpwm0-2-cfg { + + rpwm0-0-pins { + pinmux = <0x400006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rpwm1-0-cfg { + + rpwm1-0-pins { + pinmux = <0x100003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rpwm1-1-cfg { + + rpwm1-0-pins { + pinmux = <0x1c0003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rpwm1-2-cfg { + + rpwm1-0-pins { + pinmux = <0x410006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rpwm2-0-cfg { + + rpwm2-0-pins { + pinmux = <0x110003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rpwm2-1-cfg { + + rpwm2-0-pins { + pinmux = <0x1d0003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rpwm2-2-cfg { + + rpwm2-0-pins { + pinmux = <0x420006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rpwm3-0-cfg { + + rpwm3-0-pins { + pinmux = <0x120003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rpwm3-1-cfg { + + rpwm3-0-pins { + pinmux = <0x1e0003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rpwm3-2-cfg { + + rpwm3-0-pins { + pinmux = <0x430006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rpwm4-0-cfg { + + rpwm4-0-pins { + pinmux = <0x130003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rpwm4-1-cfg { + + rpwm4-0-pins { + pinmux = <0x1f0003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rpwm4-2-cfg { + + rpwm4-0-pins { + pinmux = <0x5d0006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rpwm5-0-cfg { + + rpwm5-0-pins { + pinmux = <0x140003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rpwm5-1-cfg { + + rpwm5-0-pins { + pinmux = <0x200003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rpwm5-2-cfg { + + rpwm5-0-pins { + pinmux = <0x5c0005>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rpwm6-0-cfg { + + rpwm6-0-pins { + pinmux = <0x210003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rpwm6-1-cfg { + + rpwm6-0-pins { + pinmux = <0x5e0006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rpwm6-2-cfg { + + rpwm6-0-pins { + pinmux = <0x6d0006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rpwm7-0-cfg { + + rpwm7-0-pins { + pinmux = <0x220003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rpwm7-1-cfg { + + rpwm7-0-pins { + pinmux = <0x6e0006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rpwm8-0-cfg { + + rpwm8-0-pins { + pinmux = <0x230003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rpwm8-1-cfg { + + rpwm8-0-pins { + pinmux = <0x6f0006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rpwm9-0-cfg { + + rpwm9-0-pins { + pinmux = <0x240003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rpwm9-1-cfg { + + rpwm9-0-pins { + pinmux = <0x700006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + ir0-0-cfg { + + ir0-0-pins { + pinmux = <0x290005>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + ir0-1-cfg { + + ir0-0-pins { + pinmux = <0x6c0004>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + ir1-0-cfg { + + ir1-0-pins { + pinmux = <0x04>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + ir1-1-cfg { + + ir1-0-pins { + pinmux = <0x460004>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rir0-0-cfg { + + rir0-0-pins { + pinmux = <0x280005>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rir0-1-cfg { + + rir0-0-pins { + pinmux = <0x470004>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rir1-0-cfg { + + rir1-0-pins { + pinmux = <0x10004>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rir1-1-cfg { + + rir1-0-pins { + pinmux = <0x490004>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + can0-0-cfg { + + can0-0-pins { + pinmux = <0xb0003 0xc0003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + can0-1-cfg { + + can0-0-pins { + pinmux = <0x2c0003 0x2d0003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + can0-2-cfg { + + can0-0-pins { + pinmux = <0x4c0004 0x4d0004>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + can1-0-cfg { + + can1-0-pins { + pinmux = <0x300003 0x310003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + can1-1-cfg { + + can1-0-pins { + pinmux = <0x580006 0x590006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + can1-2-cfg { + + can1-0-pins { + pinmux = <0x6d0004 0x6e0004>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + can2-0-cfg { + + can2-0-pins { + pinmux = <0x320003 0x330003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + can2-1-cfg { + phandle = <0xa0>; + + can2-0-pins { + pinmux = <0x560004 0x570004>; + bias-pull-up; + drive-strength = <0x19>; + power-source = <0xce4>; + }; + }; + + can3-0-cfg { + + can3-0-pins { + pinmux = <0x500004 0x510004>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + can3-1-cfg { + + can3-0-pins { + pinmux = <0x670004 0x680004>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + can4-0-cfg { + + can4-0-pins { + pinmux = <0x280006 0x290006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + can4-1-cfg { + + can4-0-pins { + pinmux = <0x650004 0x660004>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + can4-2-cfg { + + can4-0-pins { + pinmux = <0x780004 0x790004>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rcan0-0-cfg { + + rcan0-0-pins { + pinmux = <0x390003 0x3a0003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rcan0-1-cfg { + + rcan0-0-pins { + pinmux = <0x5a0006 0x5b0006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rcan1-0-cfg { + + rcan1-0-pins { + pinmux = <0x8e0002 0x900002>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rcan2-0-cfg { + + rcan2-0-pins { + pinmux = <0x630004 0x640004>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rcan3-0-cfg { + + rcan3-0-pins { + pinmux = <0x780003 0x790003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rcan4-0-cfg { + + rcan4-0-pins { + pinmux = <0x6b0003 0x6c0003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + sspa0-0-cfg { + + sspa0-0-pins { + pinmux = <0x510002 0x520002 0x530002 0x540002 0x550002>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + sspa0-1-cfg { + + sspa0-0-pins { + pinmux = <0x6f0002 0x700002 0x710002 0x720002 0x730002>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + sspa1-0-cfg { + + sspa1-0-pins { + pinmux = <0xf0002 0x100002 0x110002 0x120002 0x130002>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + sspa1-1-cfg { + + sspa1-0-pins { + pinmux = <0x7a0002 0x7b0002 0x7c0002 0x7d0002 0x7e0002>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + sspa2-0-cfg { + + sspa2-0-pins { + pinmux = <0x4c0002 0x4d0002 0x4e0002 0x4f0002 0x500002>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + sspa3-0-cfg { + + sspa3-0-pins { + pinmux = <0x630002 0x640002 0x650002 0x660002 0x670002>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + sspa4-0-cfg { + + sspa4-0-pins { + pinmux = <0x450002 0x460002 0x470002 0x480002 0x490002>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + sspa5-0-cfg { + + sspa5-0-pins { + pinmux = <0x02 0x10002 0x20002 0x30002 0x40002>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rsspa0-0-cfg { + + rsspa0-0-pins { + pinmux = <0x60002 0x70002 0x80002 0x90002 0xa0002>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rsspa0-1-cfg { + + rsspa0-0-pins { + pinmux = <0x4c0001 0x4d0001 0x4e0001 0x4f0001 0x500001>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rsspa1-0-cfg { + + rsspa1-0-pins { + pinmux = <0x240002 0x250002 0x260002 0x270002 0x280002>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pcie0-0-cfg { + + pcie0-0-pins { + pinmux = <0x2a0004 0x2b0004 0x2c0004>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + pcie0-1-cfg { + phandle = <0xd8>; + + pcie0-0-pins { + pinmux = <0x4f0005 0x510005>; + bias-disable; + drive-strength = <0x26>; + power-source = <0xce4>; + bias-pull-up; + }; + }; + + pcie0-2-cfg { + + pcie0-0-pins { + pinmux = <0x6c0005 0x6d0005 0x6e0005>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + pcie1-0-cfg { + + pcie1-0-pins { + pinmux = <0x150004 0x160004 0x170004>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + pcie1-1-cfg { + + pcie1-0-pins { + pinmux = <0x580004 0x590004 0x5a0004>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + pcie1-2-cfg { + + pcie1-0-pins { + pinmux = <0x710005 0x720005 0x730005>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + pcie2-0-cfg { + + pcie2-0-pins { + pinmux = <0xc0004 0xd0004 0xe0004>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + pcie2-1-cfg { + + pcie2-0-pins { + pinmux = <0x190004 0x1a0004 0x1b0004>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + pcie2-2-cfg { + + pcie2-0-pins { + pinmux = <0x3a0004 0x3b0004 0x3c0004>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + pcie3-0-cfg { + phandle = <0xdb>; + + pcie3-0-pins { + pinmux = <0x30004 0x50004>; + bias-disable; + drive-strength = <0x26>; + bias-pull-up; + power-source = <0xce4>; + }; + }; + + pcie3-1-cfg { + + pcie3-0-pins { + pinmux = <0x690005 0x6a0005 0x6b0005>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + pcie3-2-cfg { + + pcie3-0-pins { + pinmux = <0x7c0003 0x7d0003 0x7e0003>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + pcie4-0-cfg { + + pcie4-0-pins { + pinmux = <0x1f0004 0x200004 0x210004>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + pcie4-1-cfg { + phandle = <0xdd>; + + pcie4-0-pins { + pinmux = <0x4c0005 0x500005 0x4e0005>; + bias-disable; + drive-strength = <0x26>; + bias-pull-up; + power-source = <0xce4>; + }; + }; + + gmac0-cfg { + + gmac0-0-pins { + pinmux = <0x01 0x10001 0x20001 0x30001 0x60001 0x70001 0xb0001 0xc0001 0xd0001>; + bias-disable; + drive-strength = <0x19>; + }; + + gmac0-1-pins { + pinmux = <0x40001 0x50001 0x80001 0x90001 0xa0001>; + bias-disable; + drive-strength = <0x19>; + }; + + gmac0-2-pins { + pinmux = <0xf0001 0x100001 0x110001 0x120001>; + bias-disable; + drive-strength = <0x19>; + }; + + gmac0-3-pins { + pinmux = <0xe0001>; + bias-disable; + drive-strength = <0x19>; + }; + + gmac0-4-pins { + pinmux = <0x130001>; + bias-disable; + drive-strength = <0x19>; + }; + + gmac0-5-pins { + pinmux = <0x140001>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + gmac1-cfg { + phandle = <0xce>; + + gmac1-0-pins { + pinmux = <0x150001 0x160001 0x170001 0x180001 0x1b0001 0x1c0001 0x200001 0x210001 0x220001>; + bias-disable; + drive-strength = <0x19>; + power-source = <0x708>; + }; + + gmac1-1-pins { + pinmux = <0x190001 0x1a0001 0x1d0001 0x1e0001 0x1f0001>; + bias-disable; + drive-strength = <0x19>; + power-source = <0x708>; + }; + + gmac1-3-pins { + pinmux = <0x230001>; + bias-disable; + drive-strength = <0x19>; + power-source = <0x708>; + }; + + gmac1-6-pins { + pinmux = <0x250000>; + bias-disable; + drive-strength = <0x19>; + power-source = <0x708>; + }; + }; + + gmac2-cfg { + + gmac2-0-pins { + pinmux = <0x2a0001 0x2b0001 0x2c0001 0x2d0001 0x300001 0x310001 0x350001 0x360001 0x370001>; + bias-disable; + drive-strength = <0x19>; + }; + + gmac2-1-pins { + pinmux = <0x2e0001 0x2f0001 0x320001 0x330001 0x340001>; + bias-disable; + drive-strength = <0x19>; + }; + + gmac2-2-pins { + pinmux = <0x380001>; + bias-disable; + drive-strength = <0x19>; + }; + + gmac2-3-pins { + pinmux = <0x3a0001>; + bias-disable; + drive-strength = <0x19>; + }; + + gmac2-4-pins { + pinmux = <0x390001>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + gmac3-cfg { + + gmac3-0-pins { + pinmux = <0x3b0001 0x3c0001 0x3d0001 0x3e0001 0x410001 0x420001 0x460001 0x470001 0x480001>; + bias-disable; + drive-strength = <0x19>; + }; + + gmac3-1-pins { + pinmux = <0x3f0001 0x400001 0x430001 0x440001 0x450001>; + bias-disable; + drive-strength = <0x19>; + }; + + gmac3-2-pins { + pinmux = <0x490001>; + bias-disable; + drive-strength = <0x19>; + }; + + gmac3-3-pins { + pinmux = <0x4b0001>; + bias-disable; + drive-strength = <0x19>; + }; + + gmac3-4-pins { + pinmux = <0x4a0001>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + ssp0-0-cfg { + + ssp0-0-pins { + pinmux = <0x350003 0x360003 0x370003>; + bias-disable; + drive-strength = <0x19>; + }; + + ssp0-1-pins { + pinmux = <0x380003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + ssp0-1-cfg { + + ssp0-0-pins { + pinmux = <0x510001 0x520001 0x530001>; + bias-disable; + drive-strength = <0x19>; + }; + + ssp0-1-pins { + pinmux = <0x540001>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + ssp0-2-cfg { + + ssp0-0-pins { + pinmux = <0x680001 0x690001 0x6a0001>; + bias-disable; + drive-strength = <0x19>; + }; + + ssp0-1-pins { + pinmux = <0x6b0001>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + ssp1-0-cfg { + + ssp1-0-pins { + pinmux = <0x200005 0x210005 0x220005>; + bias-disable; + drive-strength = <0x19>; + }; + + ssp1-1-pins { + pinmux = <0x230005>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + ssp1-1-cfg { + + ssp1-0-pins { + pinmux = <0x6f0001 0x700001 0x710001>; + bias-disable; + drive-strength = <0x19>; + }; + + ssp1-1-pins { + pinmux = <0x720001>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + ssp2-0-cfg { + + ssp2-0-pins { + pinmux = <0x1c0005 0x1d0005 0x1e0005>; + bias-disable; + drive-strength = <0x19>; + }; + + ssp2-1-pins { + pinmux = <0x1f0005>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + ssp2-1-cfg { + + ssp2-0-pins { + pinmux = <0x680002 0x690002 0x6a0002>; + bias-disable; + drive-strength = <0x19>; + }; + + ssp2-1-pins { + pinmux = <0x6b0002>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + ssp3-0-cfg { + + ssp3-0-pins { + pinmux = <0x440006 0x450006 0x460006>; + bias-disable; + drive-strength = <0x19>; + }; + + ssp3-1-pins { + pinmux = <0x470006>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + ssp3-1-cfg { + + ssp3-0-pins { + pinmux = <0x630001 0x640001 0x650001>; + bias-disable; + drive-strength = <0x19>; + }; + + ssp3-1-pins { + pinmux = <0x660001>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rssp0-0-cfg { + + rssp0-0-pins { + pinmux = <0x3c0003 0x3d0003 0x3e0003>; + bias-disable; + drive-strength = <0x19>; + }; + + rssp0-1-pins { + pinmux = <0x3f0003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rssp0-1-cfg { + + rssp0-0-pins { + pinmux = <0x560001 0x570001 0x580001>; + bias-disable; + drive-strength = <0x19>; + }; + + rssp0-1-pins { + pinmux = <0x590001>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rssp1-0-cfg { + + rssp1-0-pins { + pinmux = <0x400003 0x410003 0x420003>; + bias-disable; + drive-strength = <0x19>; + }; + + rssp1-1-pins { + pinmux = <0x430003>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + rssp1-1-cfg { + + rssp1-0-pins { + pinmux = <0x6c0001 0x6d0001 0x740001>; + bias-disable; + drive-strength = <0x19>; + }; + + rssp1-1-pins { + pinmux = <0x750001>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + pwr_ssp-cfg { + + pwr_ssp-0-pins { + pinmux = <0x970000 0x980000 0x950000>; + bias-disable; + drive-strength = <0x19>; + }; + + pwr_ssp-1-pins { + pinmux = <0x960000>; + bias-pull-up; + drive-strength = <0x19>; + }; + }; + + qspi-cfg { + phandle = <0x98>; + + qspi-0-pins { + pinmux = <0x8a0000 0x8b0000 0x8c0000 0x8d0000 0x900000>; + bias-disable; + drive-strength = <0x19>; + power-source = <0x708>; + }; + }; + + espi0-0-cfg { + + espi0-0-pins { + pinmux = <0x05 0x10005 0x20005 0x30005 0x40005 0x60005 0x70005>; + bias-pull-up; + drive-strength = <0x19>; + }; + + espi0-1-pins { + pinmux = <0x50005>; + bias-pull-down; + drive-strength = <0x19>; + }; + }; + + espi0-1-cfg { + + espi0-0-pins { + pinmux = <0x440003 0x450003 0x460003 0x470003 0x480003 0x4a0003 0x4b0003>; + bias-pull-up; + drive-strength = <0x19>; + }; + + espi0-1-pins { + pinmux = <0x490003>; + bias-pull-down; + drive-strength = <0x19>; + }; + }; + + espi0-2-cfg { + + espi0-0-pins { + pinmux = <0x5b0004 0x5c0004 0x5d0004 0x5e0004 0x5f0004 0x610004 0x620004>; + bias-pull-up; + drive-strength = <0x19>; + power-source = <0x708>; + }; + + espi0-1-pins { + pinmux = <0x600004>; + bias-pull-down; + drive-strength = <0x19>; + power-source = <0x708>; + }; + }; + + respi0-cfg { + + respi0-0-pins { + pinmux = <0x560002 0x570002 0x580002 0x590002 0x5a0002 0x5c0002 0x5d0002>; + bias-pull-up; + drive-strength = <0x19>; + }; + + respi0-1-pins { + pinmux = <0x5b0002>; + bias-pull-down; + drive-strength = <0x19>; + }; + }; + + mmc1-cfg { + phandle = <0xd1>; + + mmc1-0-pins { + pinmux = <0x840000 0x850000 0x860000 0x870000 0x880000>; + bias-pull-up; + drive-strength = <0x08>; + power-source = <0xce4>; + }; + + mmc1-1-pins { + pinmux = <0x890000>; + bias-pull-down; + drive-strength = <0x08>; + power-source = <0xce4>; + }; + }; + + mmc1-uhs-cfg { + phandle = <0xd3>; + + mmc1-0-pins { + pinmux = <0x840000 0x850000 0x860000 0x870000 0x880000>; + bias-pull-up; + drive-strength = <0x07>; + power-source = <0x708>; + }; + + mmc1-1-pins { + pinmux = <0x890000>; + bias-pull-down; + drive-strength = <0x06>; + power-source = <0x708>; + }; + }; + + mmc1-debug-cfg { + + mmc1-0-pins { + pinmux = <0x840002 0x850002 0x860000 0x870000 0x880000>; + bias-pull-up; + drive-strength = <0x08>; + power-source = <0xce4>; + }; + + mmc1-1-pins { + pinmux = <0x890000>; + bias-pull-down; + drive-strength = <0x08>; + power-source = <0xce4>; + }; + }; + + mmc2-cfg { + + mmc2-0-pins { + pinmux = <0x7a0001 0x7b0001 0x7c0001 0x7d0001 0x7e0001>; + bias-pull-up; + drive-strength = <0x19>; + }; + + mmc2-1-pins { + pinmux = <0x7f0001>; + bias-pull-down; + drive-strength = <0x19>; + }; + }; + + cam0-0-cfg { + + cam0-0-pins { + pinmux = <0xd0005>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + cam0-1-cfg { + + cam0-0-pins { + pinmux = <0x2e0003>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + cam0-2-cfg { + phandle = <0x95>; + + cam1-0-pins { + pinmux = <0x4b0002>; + bias-disable; + drive-strength = <0x19>; + power-source = <0x708>; + }; + }; + + cam1-0-cfg { + + cam1-0-pins { + pinmux = <0x220004>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + cam1-1-cfg { + + cam1-0-pins { + pinmux = <0x2f0003>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + cam1-2-cfg { + + cam0-0-pins { + pinmux = <0x4a0002>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + cam2-0-cfg { + + cam2-0-pins { + pinmux = <0x230004>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + cam2-1-cfg { + + cam2-0-pins { + pinmux = <0x340005>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + cam2-2-cfg { + + cam2-0-pins { + pinmux = <0x550001>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + cam3-0-cfg { + + cam3-0-pins { + pinmux = <0x2b0003>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + cam3-1-cfg { + + cam3-0-pins { + pinmux = <0x430004>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + cam3-2-cfg { + + cam3-0-pins { + pinmux = <0x630006>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + dsi-0-cfg { + + dsi-0-pins { + pinmux = <0xd0006>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + dsi-1-cfg { + + dsi-0-pins { + pinmux = <0x260006>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + dsi-2-cfg { + + dsi-0-pins { + pinmux = <0x450005>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + dsi-3-cfg { + + dsi-0-pins { + pinmux = <0x480005>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + dsi-4-cfg { + + dsi-0-pins { + pinmux = <0x540006>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + dsi-5-cfg { + + dsi-0-pins { + pinmux = <0x5a0001>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + dsi-6-cfg { + + dsi-0-pins { + pinmux = <0x5c0006>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + edp0-0-cfg { + + edp0-0-pins { + pinmux = <0x1e0006>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + edp0-1-cfg { + + edp0-0-pins { + pinmux = <0x390004>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + edp1-0-cfg { + + edp1-0-pins { + pinmux = <0x1f0006>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + dp0-0-cfg { + + dp0-0-pins { + pinmux = <0x90006>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + dp0-1-cfg { + + dp0-0-pins { + pinmux = <0x170006>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + dp0-2-cfg { + + dp0-0-pins { + pinmux = <0x610005>; + bias-disable; + drive-strength = <0x19>; + power-source = <0xce4>; + }; + }; + + dp0-3-cfg { + + dp0-0-pins { + pinmux = <0x7c0004>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + dp1-0-cfg { + + dp1-0-pins { + pinmux = <0xa0006>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + dp1-1-cfg { + + dp1-0-pins { + pinmux = <0x180006>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + dp1-2-cfg { + + dp1-0-pins { + pinmux = <0x450004>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + dp1-3-cfg { + phandle = <0xff>; + + dp1-0-pins { + pinmux = <0x480004>; + bias-disable; + drive-strength = <0x19>; + power-source = <0xce4>; + }; + }; + + dp1-4-cfg { + + dp1-0-pins { + pinmux = <0x620005>; + bias-disable; + drive-strength = <0x19>; + power-source = <0xce4>; + }; + }; + + dp1-5-cfg { + + dp1-0-pins { + pinmux = <0x7d0004>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + usb20_host_drv-0-cfg { + + usb20_host_drv-pins { + pinmux = <0x100006>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + usb20_host_drv-1-cfg { + + usb20_host_drv-pins { + pinmux = <0x270005>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + usb20_host_drv-2-cfg { + + usb20_host_drv-pins { + pinmux = <0x490005>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + usb20_host_drv-3-cfg { + + usb20_host_drv-pins { + pinmux = <0x670003>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + usb20_host_drv-4-cfg { + + usb20_host_drv-pins { + pinmux = <0x6c0002>; + bias-disable; + drive-strength = <0x19>; + }; + }; + + usb30_drd-0-cfg { + + usb30_drd-pins { + pinmux = <0x110006 0x120006 0x130006>; + bias-pull-down; + drive-strength = <0x19>; + }; + }; + + usb30_drd-1-cfg { + + usb30_drd-pins { + pinmux = <0x5f0003 0x600003 0x610003>; + bias-pull-down; + drive-strength = <0x19>; + }; + }; + + usb30_drd-2-cfg { + + usb30_drd-pins { + pinmux = <0x740002 0x750002 0x760002>; + bias-pull-down; + drive-strength = <0x19>; + }; + }; + + usb30_drd_int-0-cfg { + + usb30_drd_int-pins { + pinmux = <0x6f0005>; + bias-pull-down; + drive-strength = <0x19>; + }; + }; + + usb30_drd_int-1-cfg { + + usb30_drd_int-pins { + pinmux = <0x770002>; + bias-pull-down; + drive-strength = <0x19>; + }; + }; + + usb30_b_drv-0-cfg { + + usb30_c_drv-pins { + pinmux = <0x540004>; + bias-pull-down; + drive-strength = <0x19>; + }; + }; + + usb30_c_drv-0-cfg { + + usb30_c_drv-pins { + pinmux = <0x550004>; + bias-pull-down; + drive-strength = <0x19>; + }; + }; + + usb30_c_drv-1-cfg { + + usb30_c_drv-pins { + pinmux = <0x7f0006>; + bias-pull-down; + drive-strength = <0x19>; + }; + }; + + usb30_d_drv-0-cfg { + + usb30_d_drv-pins { + pinmux = <0x140006>; + bias-pull-down; + drive-strength = <0x19>; + }; + }; + + usb30_d_drv-1-cfg { + + usb30_d_drv-pins { + pinmux = <0x1b0005>; + bias-pull-down; + drive-strength = <0x19>; + }; + }; + + usb30_d_drv-2-cfg { + + usb30_d_drv-pins { + pinmux = <0x700005>; + bias-pull-down; + drive-strength = <0x19>; + }; + }; + + usb30h1_drv-0-cfg { + + usb30h1_drv-pins { + pinmux = <0x4a0005>; + bias-pull-down; + drive-strength = <0x19>; + }; + }; + + usb30h1_drv-1-cfg { + + usb30h1_drv-pins { + pinmux = <0x680003>; + bias-pull-down; + drive-strength = <0x19>; + }; + }; + + usb30h2_drv-0-cfg { + + usb30h2_drv-pins { + pinmux = <0x4b0005>; + bias-pull-down; + drive-strength = <0x19>; + }; + }; + + usb30_drd_dir-0-cfg { + + usb30_drd_dir-pins { + pinmux = <0x560006>; + bias-pull-down; + drive-strength = <0x19>; + }; + }; + + usb30_drd_dir-1-cfg { + + usb30_drd_dir-pins { + pinmux = <0x6b0004>; + bias-pull-down; + drive-strength = <0x19>; + }; + }; + + fusb301-cfg { + phandle = <0x8a>; + + fusb301-0-pins { + pinmux = <0x3a0000>; + bias-pull-up; + drive-strength = <0x19>; + power-source = <0x708>; + }; + }; + + m2-wdis1-cfg { + phandle = <0x101>; + + m2-wdis1-pins { + pinmux = <0x490000>; + bias-pull-up; + drive-strength = <0x26>; + power-source = <0xce4>; + }; + }; + + m2-wdis2-cfg { + phandle = <0x102>; + + m2-wdis2-pins { + pinmux = <0x390000>; + bias-pull-up; + drive-strength = <0x26>; + power-source = <0xce4>; + }; + }; + + cam-mux-cfg { + phandle = <0x94>; + + cam-mux-pins { + pinmux = <0x670000>; + bias-pull-up; + drive-strength = <0x19>; + power-source = <0x708>; + }; + }; + + mmc1-cd-cfg { + phandle = <0xd2>; + + mmc1-cd-pins { + pinmux = <0x40000>; + bias-pull-up = <0x01>; + drive-strength = <0x08>; + power-source = <0xce4>; + }; + }; + }; + + serial@d4017000 { + compatible = "spacemit,k1-uart\0intel,xscale-uart"; + reg = <0x00 0xd4017000 0x00 0x100>; + clocks = <0x81 0x00 0x81 0x0a 0x80 0x19>; + clock-names = "core\0bus\0gate"; + resets = <0x81 0x00>; + reg-shift = <0x02>; + reg-io-width = <0x04>; + fifo-size = <0x100>; + tx-threshold = <0x20>; + interrupt-parent = <0x82>; + interrupts = <0x2a 0x04>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <0x86>; + }; + + ufshc@0xc0e00000 { + #address-cells = <0x02>; + #size-cells = <0x02>; + compatible = "spacemit,k3-ufshcd"; + reg = <0x00 0xc0e00000 0x00 0x40000>; + interrupt-parent = <0x82>; + interrupts = <0x87 0x04>; + clocks = <0x05 0x37>; + clock-names = "ufs-aclk"; + resets = <0x05 0x3b>; + reset-names = "ufs-aclk-rst"; + clock-freq = <0x1d4c0000>; + freq-table-hz = <0x1d4c0000 0x1d4c0000>; + lanes-per-direction = <0x02>; + ref-clk-freq = <0x124f800>; + }; + + stmmac-axi-config { + snps,wr_osr_lmt = <0x0f>; + snps,rd_osr_lmt = <0x0f>; + snps,blen = <0x100 0x80 0x40 0x20 0x10 0x00 0x00>; + phandle = <0xcb>; + }; + + ethernet@cac82000 { + compatible = "spacemit,k3-gmac\0snps,dwmac-5.10a"; + reg = <0x00 0xcac82000 0x00 0x2000>; + spacemit,apmu = <0x05>; + spacemit,ctrl-offset = <0x3ec>; + spacemit,dline-offset = <0x3f0>; + clocks = <0x05 0x4e 0x05 0x50>; + clock-names = "stmmaceth\0ptp_ref"; + resets = <0x05 0x4e>; + reset-names = "stmmaceth"; + interrupt-parent = <0x82>; + interrupts = <0x85 0x04 0x115 0x04>; + interrupt-names = "macirq\0eth_wake_irq"; + mac-address = [00 00 00 00 00 00]; + tx-fifo-depth = <0x2000>; + rx-fifo-depth = <0x2000>; + snps,tso; + snps,force_sf_dma_mode; + snps,axi-config = <0xcb>; + snps,mtl-rx-config = <0xcc>; + snps,mtl-tx-config = <0xcd>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <0xce>; + max-speed = <0x3e8>; + phy-mode = "rgmii"; + phy-handle = <0xcf>; + snps,reset-gpios = <0x8b 0x01 0x05 0x01>; + snps,reset-delays-us = <0x00 0x4e20 0x186a0>; + spacemit,wake-irq-enable; + spacemit,clk-tuning-enable; + spacemit,clk-tuning-by-delayline; + spacemit,tx-phase = <0x2f>; + spacemit,rx-phase = <0x35>; + phandle = <0xca>; + + mdio { + #address-cells = <0x01>; + #size-cells = <0x00>; + compatible = "snps,dwmac-mdio"; + + ethernet-phy@1 { + compatible = "ethernet-phy-id001c.c916\0ethernet-phy-ieee802.3-c22"; + reg = <0x01>; + phandle = <0xcf>; + + leds { + #address-cells = <0x01>; + #size-cells = <0x00>; + + led@1 { + reg = <0x01>; + function = "lan"; + color = <0x02>; + default-state = "keep"; + }; + + led@2 { + reg = <0x02>; + function = "lan"; + color = <0x06>; + default-state = "keep"; + }; + }; + }; + }; + }; + + mpxy_mbox@0 { + compatible = "riscv,sbi-mpxy-mbox"; + #mbox-cells = <0x02>; + status = "okay"; + phandle = <0xa8>; + }; + + rpmi_regulator@0 { + compatible = "riscv,rpmi-regulator"; + mboxes = <0xa8 0x07 0x00>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <0xa9>; + + pvin { + regulator-min-microvolt = <0x4c4b40>; + regulator-max-microvolt = <0x4c4b40>; + regulator-always-on; + regulator-boot-on; + }; + + edcdc2 { + regulator-min-microvolt = <0x825f0>; + regulator-max-microvolt = <0xf55c8>; + regulator-always-on; + regulator-boot-on; + }; + + edcdc1 { + regulator-min-microvolt = <0x825f0>; + regulator-max-microvolt = <0xf55c8>; + regulator-always-on; + regulator-boot-on; + phandle = <0x04>; + }; + + p3v3 { + regulator-min-microvolt = <0x325aa0>; + regulator-max-microvolt = <0x325aa0>; + regulator-always-on; + regulator-boot-on; + phandle = <0xd4>; + }; + + p1v8 { + regulator-min-microvolt = <0x1b7740>; + regulator-max-microvolt = <0x1b7740>; + regulator-always-on; + regulator-boot-on; + }; + + dcdc1 { + regulator-min-microvolt = <0x100590>; + regulator-max-microvolt = <0x100590>; + regulator-always-on; + regulator-boot-on; + }; + + dcdc3 { + regulator-min-microvolt = "\0\f5"; + regulator-max-microvolt = "\0\f5"; + regulator-always-on; + regulator-boot-on; + }; + + dcdc4 { + regulator-min-microvolt = <0x200b20>; + regulator-max-microvolt = <0x200b20>; + regulator-always-on; + regulator-boot-on; + }; + + dcdc5 { + regulator-min-microvolt = <0x1b7740>; + regulator-max-microvolt = <0x1b7740>; + regulator-always-on; + regulator-boot-on; + }; + + dcdc6 { + regulator-min-microvolt = <0x7a120>; + regulator-max-microvolt = <0x927c0>; + regulator-always-on; + regulator-boot-on; + }; + + aldo1 { + regulator-min-microvolt = <0x1b7740>; + regulator-max-microvolt = <0x325aa0>; + regulator-always-on; + regulator-boot-on; + phandle = <0xd5>; + }; + + aldo2 { + regulator-min-microvolt = <0x1b7740>; + regulator-max-microvolt = <0x1b7740>; + regulator-always-on; + regulator-boot-on; + }; + + aldo3 { + regulator-min-microvolt = <0x7a120>; + regulator-max-microvolt = <0x33e140>; + phandle = <0x93>; + }; + + aldo4 { + regulator-min-microvolt = <0x325aa0>; + regulator-max-microvolt = <0x325aa0>; + regulator-always-on; + regulator-boot-on; + }; + + dldo1 { + regulator-min-microvolt = <0x124f80>; + regulator-max-microvolt = <0x124f80>; + regulator-always-on; + regulator-boot-on; + }; + + dldo2 { + regulator-min-microvolt = <0xdbba0>; + regulator-max-microvolt = <0xdbba0>; + regulator-always-on; + regulator-boot-on; + }; + + dldo3 { + regulator-min-microvolt = "\0\f5"; + regulator-max-microvolt = "\0\f5"; + regulator-always-on; + regulator-boot-on; + }; + + dldo4 { + regulator-min-microvolt = <0x1b7740>; + regulator-max-microvolt = <0x1b7740>; + regulator-always-on; + regulator-boot-on; + }; + + dldo5 { + regulator-min-microvolt = <0x1b7740>; + regulator-max-microvolt = <0x1b7740>; + regulator-always-on; + regulator-boot-on; + }; + + dldo6 { + regulator-min-microvolt = <0x1b7740>; + regulator-max-microvolt = <0x1b7740>; + regulator-always-on; + regulator-boot-on; + }; + + dldo7 { + regulator-min-microvolt = <0x1b7740>; + regulator-max-microvolt = <0x1b7740>; + regulator-always-on; + regulator-boot-on; + }; + + pwr_x100 { + regulator-min-microvolt = <0x325aa0>; + regulator-max-microvolt = <0x325aa0>; + regulator-always-on; + regulator-boot-on; + }; + + pwr_a100 { + regulator-min-microvolt = <0x325aa0>; + regulator-max-microvolt = <0x325aa0>; + regulator-always-on; + regulator-boot-on; + }; + + pwr_ext { + regulator-min-microvolt = <0x325aa0>; + regulator-max-microvolt = <0x325aa0>; + regulator-always-on; + regulator-boot-on; + }; + }; + + mmc@d4280000 { + compatible = "spacemit,k3-sdhci"; + reg = <0x00 0xd4280000 0x00 0x200>; + clocks = <0x05 0x1c 0x05 0x1d>; + clock-names = "core\0io"; + interrupt-parent = <0x82>; + interrupts = <0x63 0x04>; + resets = <0x05 0x0c 0x05 0x0d>; + reset-names = "sdh_axi\0sdh0"; + status = "okay"; + pinctrl-names = "default\0uhs"; + pinctrl-0 = <0xd1 0xd2>; + pinctrl-1 = <0xd3 0xd2>; + bus-width = <0x04>; + wp-inverted; + cd-gpios = <0x8b 0x00 0x04 0x00>; + vmmc-supply = <0xd4>; + vqmmc-supply = <0xd5>; + no-mmc; + no-sdio; + clock-frequency = "\f5\0"; + spacemit,tx_delaycode = <0x1f>; + }; + }; + + aliases { + serial0 = "/soc/serial@d4017000"; + }; + + clocks { + clock-1m { + compatible = "fixed-clock"; + clock-frequency = <0xf4240>; + clock-output-names = "vctcxo_1m"; + #clock-cells = <0x00>; + phandle = <0x7b>; + }; + + clock-24m { + compatible = "fixed-clock"; + clock-frequency = <0x16e3600>; + clock-output-names = "vctcxo_24m"; + #clock-cells = <0x00>; + phandle = <0x7d>; + }; + + clock-3m { + compatible = "fixed-clock"; + clock-frequency = <0x2dc6c0>; + clock-output-names = "vctcxo_3m"; + #clock-cells = <0x00>; + phandle = <0x7c>; + }; + + clock-32k { + compatible = "fixed-clock"; + clock-frequency = <0x8000>; + clock-output-names = "osc_32k"; + #clock-cells = <0x00>; + phandle = <0x7a>; + }; + + clock-reserved { + compatible = "fixed-clock"; + clock-frequency = <0x00>; + clock-output-names = "reserved_clk"; + #clock-cells = <0x00>; + phandle = <0x7e>; + }; + + clock-external { + compatible = "fixed-clock"; + clock-frequency = <0x00>; + clock-output-names = "external_clk"; + #clock-cells = <0x00>; + phandle = <0x7f>; + }; + }; + + memory@107000000 { + device_type = "memory"; + reg = <0x01 0x07000000 0x0 0xF9000000>; + }; + + apb-pclk { + compatible = "fixed-clock"; + #clock-cells = <0x00>; + clock-output-names = "clk14mhz"; + clock-frequency = <0xd59f80>; + phandle = <0x60>; + }; + + reserved-memory { + #address-cells = <0x02>; + #size-cells = <0x02>; + ranges; + + nonroot@180000000 { + no-map; + reg = <0x01 0x80000000 0x00 0x80000000>; + }; + + dtbfile@10f000000 { + no-map; + reg = <0x01 0x0f000000 0x00 0x01000000>; + }; + + rcpu0_pwr@100200000 { + reg = <0x01 0x200000 0x00 0x300000>; + no-map; + phandle = <0x9a>; + }; + + rcpu0_heap@100500000 { + reg = <0x01 0x500000 0x00 0x200000>; + no-map; + phandle = <0x9b>; + }; + + vdev0vring0@c0876000 { + reg = <0x00 0xc0876000 0x00 0x3000>; + no-map; + phandle = <0x9c>; + }; + + vdev0vring1@c0879000 { + reg = <0x00 0xc0879000 0x00 0x3000>; + no-map; + phandle = <0x9e>; + }; + + vdev0vring2@c087c000 { + reg = <0x00 0xc087c000 0x00 0x1000>; + no-map; + }; + + vdev0buffer@100700000 { + compatible = "shared-dma-pool"; + reg = <0x01 0x700000 0x00 0xfc000>; + no-map; + phandle = <0x9d>; + }; + + rcpu0_rsc_table@1007fc000 { + reg = <0x01 0x7fc000 0x00 0x4000>; + no-map; + phandle = <0x9f>; + }; + + rpmi0@100800000 { + reg = <0x01 0x800000 0x00 0x4000>; + no-map; + }; + + rcpu1_runtime@100804000 { + reg = <0x01 0x804000 0x00 0x300000>; + no-map; + phandle = <0xa2>; + }; + + rcpu1_heap@100B04000 { + reg = <0x01 0xb04000 0x00 0x200000>; + no-map; + phandle = <0xa3>; + }; + + vdev0vring0@c086c000 { + reg = <0x00 0xc086c000 0x00 0x3000>; + no-map; + phandle = <0xa4>; + }; + + vdev0vring1@c086f000 { + reg = <0x00 0xc086f000 0x00 0x3000>; + no-map; + phandle = <0xa6>; + }; + + vdev0buffer@100d04000 { + compatible = "shared-dma-pool"; + reg = <0x01 0xd04000 0x00 0xfc000>; + no-map; + phandle = <0xa5>; + }; + + rcpu1_rsc_table@100e00000 { + reg = <0x01 0xe00000 0x00 0x4000>; + no-map; + phandle = <0xa7>; + }; + + rcpu_dtb_table@100e04000 { + reg = <0x01 0xe04000 0x00 0x300000>; + no-map; + }; + + dpu_reserved@101b00000 { + compatible = "shared-dma-pool"; + reg = <0x01 0x1b00000 0x00 0x280000>; + no-map; + phandle = <0xf2>; + }; + + dpu_reserved1@101d80000 { + compatible = "shared-dma-pool"; + reg = <0x01 0x1d80000 0x00 0x280000>; + no-map; + phandle = <0xf5>; + }; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x00 0x20000000>; + alloc-ranges = <0x01 0x40000000 0x00 0x20000000>; + linux,cma-default; + }; + }; + + hvisor_virtio_device { + compatible = "hvisor"; + interrupt-parent = <0x82>; + interrupts = <0x20 0x04>; + }; + + chosen { + bootargs = "earlycon=sbi console=ttyS0,115200 loglevel=8 root=/dev/sda3 rootwait rw random.trust_bootloader=1 unaligned_scalar_speed=fast unaligned_vector_speed=fast"; + stdout-path = "serial0:115200"; + }; + + hub-reset { + compatible = "regulator-fixed"; + regulator-name = "hub-reset"; + regulator-min-microvolt = <0x325aa0>; + regulator-max-microvolt = <0x325aa0>; + enable-active-high; + regulator-boot-on; + gpio = <0x8b 0x01 0x15 0x00>; + phandle = <0xc3>; + }; +}; diff --git a/platform/riscv64/k3-com260/image/dts/zone1-linux.dts b/platform/riscv64/k3-com260/image/dts/zone1-linux.dts new file mode 100644 index 000000000..c496abdcb --- /dev/null +++ b/platform/riscv64/k3-com260/image/dts/zone1-linux.dts @@ -0,0 +1,286 @@ +/dts-v1/; + +/ { + #address-cells = <0x02>; + #size-cells = <0x02>; + model = "SpacemiT K3 Com260 IFX"; + compatible = "spacemit,k3-com260-ifx"; + + cpus { + #address-cells = <0x01>; + #size-cells = <0x00>; + timebase-frequency = <0x16e3600>; + + cpu@4 { + device_type = "cpu"; + reg = <0x04>; + model = "Spacemit(R) X100"; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdcv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i\0m\0a\0f\0d\0c\0v\0smaia\0smstateen\0ssaia\0sscofpmf\0sstc\0svpbmt\0svinval\0svnapot\0zawrs\0zba\0zbb\0zbc\0zbs\0zcb\0zca\0zcmop\0zfa\0zfh\0zfhmin\0zkt\0zicbom\0zicbop\0zicboz\0zicntr\0zicond\0zicsr\0zifencei\0zihintpause\0zihintntl\0zimop\0zvbb\0zvbc\0zvfh\0zvfhmin\0zvkb\0zvkg\0zvkn\0zvknc\0zvkned\0zvkng\0zvknha\0zvknhb\0zvks\0zvksc\0zvksed\0zvksh\0zvksg\0zvkt\0zcd"; + riscv,cbom-block-size = <0x40>; + riscv,cboz-block-size = <0x40>; + riscv,cbop-block-size = <0x40>; + i-cache-block-size = <0x40>; + i-cache-size = <0x10000>; + i-cache-sets = <0x100>; + d-cache-block-size = <0x40>; + d-cache-size = <0x10000>; + d-cache-sets = <0x100>; + next-level-cache = <0x07>; + // cpu-idle-states = <0x02 0x03>; + mmu-type = "riscv,sv39"; + #cooling-cells = <0x02>; + clst-supply = <0x04>; + clocks = <0x05 0x04 0x05 0x05>; + clock-names = "cls0\0cls1"; + // operating-points-v2 = <0x06>; + phandle = <0x0f>; + + interrupt-controller { + #interrupt-cells = <0x01>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + phandle = <0x6d>; + }; + }; + + cpu@5 { + device_type = "cpu"; + reg = <0x05>; + model = "Spacemit(R) X100"; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdcv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i\0m\0a\0f\0d\0c\0v\0smaia\0smstateen\0ssaia\0sscofpmf\0sstc\0svpbmt\0svinval\0svnapot\0zawrs\0zba\0zbb\0zbc\0zbs\0zcb\0zca\0zcmop\0zfa\0zfh\0zfhmin\0zkt\0zicbom\0zicbop\0zicboz\0zicntr\0zicond\0zicsr\0zifencei\0zihintpause\0zihintntl\0zimop\0zvbb\0zvbc\0zvfh\0zvfhmin\0zvkb\0zvkg\0zvkn\0zvknc\0zvkned\0zvkng\0zvknha\0zvknhb\0zvks\0zvksc\0zvksed\0zvksh\0zvksg\0zvkt\0zcd"; + riscv,cbom-block-size = <0x40>; + riscv,cboz-block-size = <0x40>; + riscv,cbop-block-size = <0x40>; + i-cache-block-size = <0x40>; + i-cache-size = <0x10000>; + i-cache-sets = <0x100>; + d-cache-block-size = <0x40>; + d-cache-size = <0x10000>; + d-cache-sets = <0x100>; + next-level-cache = <0x07>; + // cpu-idle-states = <0x02 0x03>; + mmu-type = "riscv,sv39"; + #cooling-cells = <0x02>; + clst-supply = <0x04>; + clocks = <0x05 0x04 0x05 0x05>; + clock-names = "cls0\0cls1"; + // operating-points-v2 = <0x06>; + phandle = <0x10>; + + interrupt-controller { + #interrupt-cells = <0x01>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + phandle = <0x6e>; + }; + }; + + cpu@6 { + device_type = "cpu"; + reg = <0x06>; + model = "Spacemit(R) X100"; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdcv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i\0m\0a\0f\0d\0c\0v\0smaia\0smstateen\0ssaia\0sscofpmf\0sstc\0svpbmt\0svinval\0svnapot\0zawrs\0zba\0zbb\0zbc\0zbs\0zcb\0zca\0zcmop\0zfa\0zfh\0zfhmin\0zkt\0zicbom\0zicbop\0zicboz\0zicntr\0zicond\0zicsr\0zifencei\0zihintpause\0zihintntl\0zimop\0zvbb\0zvbc\0zvfh\0zvfhmin\0zvkb\0zvkg\0zvkn\0zvknc\0zvkned\0zvkng\0zvknha\0zvknhb\0zvks\0zvksc\0zvksed\0zvksh\0zvksg\0zvkt\0zcd"; + riscv,cbom-block-size = <0x40>; + riscv,cboz-block-size = <0x40>; + riscv,cbop-block-size = <0x40>; + i-cache-block-size = <0x40>; + i-cache-size = <0x10000>; + i-cache-sets = <0x100>; + d-cache-block-size = <0x40>; + d-cache-size = <0x10000>; + d-cache-sets = <0x100>; + next-level-cache = <0x07>; + // cpu-idle-states = <0x02 0x03>; + mmu-type = "riscv,sv39"; + #cooling-cells = <0x02>; + clst-supply = <0x04>; + clocks = <0x05 0x04 0x05 0x05>; + clock-names = "cls0\0cls1"; + // operating-points-v2 = <0x06>; + phandle = <0x11>; + + interrupt-controller { + #interrupt-cells = <0x01>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + phandle = <0x6f>; + }; + }; + + cpu@7 { + device_type = "cpu"; + reg = <0x07>; + model = "Spacemit(R) X100"; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdcv"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i\0m\0a\0f\0d\0c\0v\0smaia\0smstateen\0ssaia\0sscofpmf\0sstc\0svpbmt\0svinval\0svnapot\0zawrs\0zba\0zbb\0zbc\0zbs\0zcb\0zca\0zcmop\0zfa\0zfh\0zfhmin\0zkt\0zicbom\0zicbop\0zicboz\0zicntr\0zicond\0zicsr\0zifencei\0zihintpause\0zihintntl\0zimop\0zvbb\0zvbc\0zvfh\0zvfhmin\0zvkb\0zvkg\0zvkn\0zvknc\0zvkned\0zvkng\0zvknha\0zvknhb\0zvks\0zvksc\0zvksed\0zvksh\0zvksg\0zvkt\0zcd"; + riscv,cbom-block-size = <0x40>; + riscv,cboz-block-size = <0x40>; + riscv,cbop-block-size = <0x40>; + i-cache-block-size = <0x40>; + i-cache-size = <0x10000>; + i-cache-sets = <0x100>; + d-cache-block-size = <0x40>; + d-cache-size = <0x10000>; + d-cache-sets = <0x100>; + next-level-cache = <0x07>; + // cpu-idle-states = <0x02 0x03>; + mmu-type = "riscv,sv39"; + #cooling-cells = <0x02>; + clst-supply = <0x04>; + clocks = <0x05 0x04 0x05 0x05>; + clock-names = "cls0\0cls1"; + // operating-points-v2 = <0x06>; + phandle = <0x12>; + + interrupt-controller { + #interrupt-cells = <0x01>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + phandle = <0x70>; + }; + }; + + l2-cache1 { + compatible = "cache"; + cache-block-size = <0x40>; + cache-level = <0x02>; + cache-size = <0x400000>; + cache-sets = <0x1000>; + cache-unified; + phandle = <0x01>; + }; + + l2-cache2 { + compatible = "cache"; + cache-block-size = <0x40>; + cache-level = <0x02>; + cache-size = <0x400000>; + cache-sets = <0x1000>; + cache-unified; + phandle = <0x07>; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <0x0b>; + }; + + core1 { + cpu = <0x0c>; + }; + + core2 { + cpu = <0x0d>; + }; + + core3 { + cpu = <0x0e>; + }; + }; + + cluster1 { + + core0 { + cpu = <0x0f>; + }; + + core1 { + cpu = <0x10>; + }; + + core2 { + cpu = <0x11>; + }; + + core3 { + cpu = <0x12>; + }; + }; + }; + }; + + soc { + #address-cells = <0x02>; + #size-cells = <0x02>; + compatible = "simple-bus"; + dma-noncoherent; + ranges; + + //system-controller@d4282800 { + // compatible = "spacemit,k3-syscon-apmu"; + // reg = <0x00 0xd4282800 0x00 0x400>; + // clocks = <0x7a 0x7b 0x7c 0x7d 0x7e 0x7f>; + // clock-names = "osc_32k\0vctcxo_1m\0vctcxo_3m\0vctcxo_24m\0reserved_clk\0external_clk"; + // #clock-cells = <0x01>; + // #power-domain-cells = <0x01>; + // #reset-cells = <0x01>; + // phandle = <0x05>; + //}; + + interrupt-controller@e0400000 { + compatible = "riscv,imsics"; + interrupts-extended = <0x6d 0x09 0x6e 0x09 0x6f 0x09 0x70 0x09>; + reg = <0x00 0xe0400000 0x00 0x4000>; + interrupt-controller; + #interrupt-cells = <0x00>; + #msi-cells = <0x00>; + msi-controller; + riscv,num-ids = <0x1ff>; + riscv,num-guest-ids = <0x1ff>; + riscv,hart-index-bits = <2>; + riscv,guest-index-bits = <0>; + status = "okay"; + phandle = <0x79>; + }; + + interrupt-controller@e0804000 { + compatible = "riscv,aplic"; + reg = <0x00 0xe0804000 0x00 0x4000>; + msi-parent = <0x79>; + #interrupt-cells = <0x02>; + interrupt-controller; + riscv,num-sources = <0x200>; + status = "okay"; + phandle = <0x82>; + }; + + virtio_mmio@10006000 { + interrupts = <0x06 0x04>; + interrupt-parent = <0x82>; + reg = <0x00 0x10006000 0x00 0x1000>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@10007000 { + interrupts = <0x07 0x04>; + interrupt-parent = <0x82>; + reg = <0x00 0x10007000 0x00 0x1000>; + compatible = "virtio,mmio"; + }; + }; + + memory@180000000 { + device_type = "memory"; + reg = <0x01 0x80000000 0x0 0x80000000>; + }; + + chosen { + bootargs = "earlycon=sbi console=hvc0 loglevel=8 root=/dev/vda rootwait rw"; + }; +}; diff --git a/platform/riscv64/k3-com260/kconfig/defconfig b/platform/riscv64/k3-com260/kconfig/defconfig new file mode 100644 index 000000000..9e080ea02 --- /dev/null +++ b/platform/riscv64/k3-com260/kconfig/defconfig @@ -0,0 +1,4 @@ +CONFIG_AIA=y +CONFIG_ARCH_RISCV64=y +CONFIG_SSTC=y +CONFIG_RVA23=y \ No newline at end of file diff --git a/platform/riscv64/k3-com260/linker.ld b/platform/riscv64/k3-com260/linker.ld new file mode 100644 index 000000000..6f4636bf8 --- /dev/null +++ b/platform/riscv64/k3-com260/linker.ld @@ -0,0 +1,64 @@ +ENTRY(arch_entry) +BASE_ADDRESS = 0x102200000; +CPU_NUM = 8; + + +SECTIONS +{ + . = BASE_ADDRESS; + skernel = .; + + stext = .; + .text : { + *(.text.entry) + *(.text .text.*) + } + + . = ALIGN(4K); + etext = .; + srodata = .; + .rodata : { + *(.rodata .rodata.*) + *(.srodata .srodata.*) + } + + . = ALIGN(4K); + erodata = .; + sdata = .; + .data : { + *(.data .data.*) + *(.sdata .sdata.*) + } + + . = ALIGN(4K); + edata = .; + .bss : { + *(.bss.stack) + sbss = .; + *(.bss .bss.*) + *(.sbss .sbss.*) + } + + . = ALIGN(4K); + _percpu_start = .; + _percpu_end = _percpu_start + SIZEOF(.percpu); + .percpu 0x0 (NOLOAD) : AT(_percpu_start) { + _percpu_load_start = .; + *(.percpu .percpu.*) + _percpu_load_end = .; + . = _percpu_load_start + ALIGN(64) * CPU_NUM; + } + . = _percpu_end; + + . = ALIGN(4K); + ebss = .; + ekernel = .; + + /DISCARD/ : { + *(.eh_frame) + } + . = ALIGN(4K); + __core_end = .; +} + +__hv_end = __core_end + HV_EXTENDED_SIZE; diff --git a/platform/riscv64/k3-com260/platform.mk b/platform/riscv64/k3-com260/platform.mk new file mode 100644 index 000000000..586207c95 --- /dev/null +++ b/platform/riscv64/k3-com260/platform.mk @@ -0,0 +1,13 @@ + +BOOT_PATH := $(image_dir)/../ +HVISOR_RAW_BIN_ABS := $(abspath $(hvisor_bin).tmp) + +$(hvisor_bin): elf + @if ! command -v mkimage > /dev/null; then \ + sudo apt-get install -y u-boot-tools; \ + fi + $(OBJCOPY) $(hvisor_elf) --strip-all -O binary $(hvisor_bin).tmp + cp $(BOOT_PATH)hvisor.its $(BOOT_PATH)hvisor.its.tmp + sed -i 's|hvisor.bin.tmp|$(HVISOR_RAW_BIN_ABS)|g' $(BOOT_PATH)hvisor.its.tmp + mkimage -f $(BOOT_PATH)hvisor.its.tmp $(hvisor_bin) + rm -f $(hvisor_bin).tmp $(BOOT_PATH)hvisor.its.tmp diff --git a/platform/riscv64/k3-com260/scripts/boot_zone1.sh b/platform/riscv64/k3-com260/scripts/boot_zone1.sh new file mode 100644 index 000000000..71b07a3f0 --- /dev/null +++ b/platform/riscv64/k3-com260/scripts/boot_zone1.sh @@ -0,0 +1,10 @@ +su root # passwd: bianbu + +insmod hvisor.ko + +nohup ./hvisor virtio start virtio-backend.json & +./hvisor zone start zone1-linux-virtio.json + +./hvisor zone list + +screen /dev/pts/0 \ No newline at end of file diff --git a/platform/riscv64/megrez/cargo/features b/platform/riscv64/megrez/cargo/features deleted file mode 100644 index d1314d861..000000000 --- a/platform/riscv64/megrez/cargo/features +++ /dev/null @@ -1,2 +0,0 @@ -eic770x_soc -plic diff --git a/platform/riscv64/megrez/configs/zone1-linux.json b/platform/riscv64/megrez/configs/zone1-linux.json index bf957af8d..323495d11 100644 --- a/platform/riscv64/megrez/configs/zone1-linux.json +++ b/platform/riscv64/megrez/configs/zone1-linux.json @@ -71,5 +71,6 @@ "plic_size": "0x4000000", "aplic_base": "0xd000000", "aplic_size": "0x8000" - } -} \ No newline at end of file + }, + "pci_config": [] +} diff --git a/platform/riscv64/megrez/kconfig/defconfig b/platform/riscv64/megrez/kconfig/defconfig new file mode 100644 index 000000000..54604c280 --- /dev/null +++ b/platform/riscv64/megrez/kconfig/defconfig @@ -0,0 +1,3 @@ +CONFIG_ARCH_RISCV64=y +CONFIG_HYPERVISOR_V0_6=y +CONFIG_PLIC=y diff --git a/platform/riscv64/qemu-aia/board.rs b/platform/riscv64/qemu-aia/board.rs index bcfa1d780..7880cd9f7 100644 --- a/platform/riscv64/qemu-aia/board.rs +++ b/platform/riscv64/qemu-aia/board.rs @@ -93,8 +93,8 @@ pub const ROOT_PCI_CONFIG: [HvPciConfig; 1] = [HvPciConfig { pub const ROOT_ZONE_IVC_CONFIG: &[HvIvcConfig] = &[]; pub const ROOT_PCI_DEVS: &[HvPciDevConfig] = &[ - pci_dev!(0x0, 0x0, 0x0, 0x0, VpciDevType::Physical), - pci_dev!(0x0, 0x0, 0x1, 0x0, VpciDevType::Physical), - // pci_dev!(0x0, 0x0, 0x3, 0x0, VpciDevType::Physical), - // pci_dev!(0x0, 0x0, 0x5, 0x0, VpciDevType::StandardVdev), + pci_dev!(0x0, 0x0, 0x0, 0x0 => 0x0, 0x0, 0x0, VpciDevType::Physical), + pci_dev!(0x0, 0x0, 0x1, 0x0 => 0x0, 0x1, 0x0, VpciDevType::Physical), + // pci_dev!(0x0, 0x0, 0x3, 0x0 => 0x0, 0x3, 0x0, VpciDevType::Physical), + // pci_dev!(0x0, 0x0, 0x5, 0x0 => 0x0, 0x5, 0x0, VpciDevType::StandardVdev), ]; diff --git a/platform/riscv64/qemu-aia/cargo/features b/platform/riscv64/qemu-aia/cargo/features deleted file mode 100644 index 2600021b4..000000000 --- a/platform/riscv64/qemu-aia/cargo/features +++ /dev/null @@ -1,6 +0,0 @@ -aia -sstc -pci -ecam_pcie -riscv_iommu -share_s2pt diff --git a/platform/riscv64/qemu-aia/configs/zone1-linux-passthrough.json b/platform/riscv64/qemu-aia/configs/zone1-linux-passthrough.json index 814697550..016661183 100644 --- a/platform/riscv64/qemu-aia/configs/zone1-linux-passthrough.json +++ b/platform/riscv64/qemu-aia/configs/zone1-linux-passthrough.json @@ -60,6 +60,9 @@ "bus": "0x0", "device": "0x0", "function": "0x0", + "v_bus": "0x0", + "v_device": "0x0", + "v_function": "0x0", "dev_type": "0" }, { @@ -67,7 +70,10 @@ "bus": "0x0", "device": "0x2", "function": "0x0", + "v_bus": "0x0", + "v_device": "0x2", + "v_function": "0x0", "dev_type": "0" } ] -} \ No newline at end of file +} diff --git a/platform/riscv64/qemu-aia/configs/zone1-linux-virtio.json b/platform/riscv64/qemu-aia/configs/zone1-linux-virtio.json index 218629ba7..80f1c7740 100644 --- a/platform/riscv64/qemu-aia/configs/zone1-linux-virtio.json +++ b/platform/riscv64/qemu-aia/configs/zone1-linux-virtio.json @@ -59,6 +59,9 @@ "bus": "0x0", "device": "0x0", "function": "0x0", + "v_bus": "0x0", + "v_device": "0x0", + "v_function": "0x0", "dev_type": "0" }, { @@ -66,7 +69,10 @@ "bus": "0x0", "device": "0x2", "function": "0x0", + "v_bus": "0x0", + "v_device": "0x2", + "v_function": "0x0", "dev_type": "0" } ] -} \ No newline at end of file +} diff --git a/platform/riscv64/qemu-aia/image/dts/virt.dts b/platform/riscv64/qemu-aia/image/dts/virt.dts index 5e5f7ff36..6ddaa5e96 100644 --- a/platform/riscv64/qemu-aia/image/dts/virt.dts +++ b/platform/riscv64/qemu-aia/image/dts/virt.dts @@ -47,10 +47,10 @@ riscv,cbop-block-size = <0x40>; riscv,cboz-block-size = <0x40>; riscv,cbom-block-size = <0x40>; - riscv,isa-extensions = "i\0m\0a\0f\0d\0c\0h\0zic64b\0zicbom\0zicbop\0zicboz\0ziccamoa\0ziccif\0zicclsm\0ziccrse\0zicntr\0zicsr\0zifencei\0zihintntl\0zihintpause\0zihpm\0zmmul\0za64rs\0zaamo\0zalrsc\0zawrs\0zfa\0zca\0zcd\0zba\0zbb\0zbc\0zbs\0sdtrig\0shcounterenw\0shgatpa\0shtvala\0shvsatpa\0shvstvala\0shvstvecd\0smaia\0ssaia\0ssccptr\0sscounterenw\0ssstrict\0sstc\0sstvala\0sstvecd\0ssu64xl\0svadu\0svvptc"; + riscv,isa-extensions = "i\0m\0a\0f\0d\0c\0b\0v\0h\0zic64b\0zicbom\0zicbop\0zicboz\0ziccamoa\0ziccif\0zicclsm\0ziccrse\0zicond\0zicntr\0zicsr\0zifencei\0zihintntl\0zihintpause\0zihpm\0zimop\0zmmul\0za64rs\0zaamo\0zalrsc\0zawrs\0zfa\0zfhmin\0zca\0zcb\0zcd\0zcmop\0zba\0zbb\0zbs\0zkt\0zvbb\0zve32f\0zve32x\0zve64f\0zve64d\0zve64x\0zvfhmin\0zvkb\0zvkt\0sdtrig\0shcounterenw\0sha\0shgatpa\0shtvala\0shvsatpa\0shvstvala\0shvstvecd\0smaia\0smnpm\0smstateen\0ssaia\0ssccptr\0sscofpmf\0sscounterenw\0ssnpm\0ssstateen\0ssstrict\0sstc\0sstvala\0sstvecd\0ssu64xl\0supm\0svade\0svinval\0svnapot\0svpbmt"; riscv,isa-base = "rv64i"; - riscv,isa = "rv64imafdch_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_zicsr_zifencei_zihintntl_zihintpause_zihpm_zmmul_za64rs_zaamo_zalrsc_zawrs_zfa_zca_zcd_zba_zbb_zbc_zbs_sdtrig_shcounterenw_shgatpa_shtvala_shvsatpa_shvstvala_shvstvecd_smaia_ssaia_ssccptr_sscounterenw_ssstrict_sstc_sstvala_sstvecd_ssu64xl_svadu_svvptc"; - mmu-type = "riscv,sv57"; + riscv,isa = "rv64imafdcbvh_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_zicond_zicntr_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_zmmul_za64rs_zaamo_zalrsc_zawrs_zfa_zfhmin_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkt_zvbb_zve32f_zve32x_zve64f_zve64d_zve64x_zvfhmin_zvkb_zvkt_sdtrig_shcounterenw_sha_shgatpa_shtvala_shvsatpa_shvstvala_shvstvecd_smaia_smnpm_smstateen_ssaia_ssccptr_sscofpmf_sscounterenw_ssnpm_ssstateen_ssstrict_sstc_sstvala_sstvecd_ssu64xl_supm_svade_svinval_svnapot_svpbmt"; + mmu-type = "riscv,sv39"; interrupt-controller { #interrupt-cells = <0x01>; @@ -69,10 +69,10 @@ riscv,cbop-block-size = <0x40>; riscv,cboz-block-size = <0x40>; riscv,cbom-block-size = <0x40>; - riscv,isa-extensions = "i\0m\0a\0f\0d\0c\0h\0zic64b\0zicbom\0zicbop\0zicboz\0ziccamoa\0ziccif\0zicclsm\0ziccrse\0zicntr\0zicsr\0zifencei\0zihintntl\0zihintpause\0zihpm\0zmmul\0za64rs\0zaamo\0zalrsc\0zawrs\0zfa\0zca\0zcd\0zba\0zbb\0zbc\0zbs\0sdtrig\0shcounterenw\0shgatpa\0shtvala\0shvsatpa\0shvstvala\0shvstvecd\0smaia\0ssaia\0ssccptr\0sscounterenw\0ssstrict\0sstc\0sstvala\0sstvecd\0ssu64xl\0svadu\0svvptc"; + riscv,isa-extensions = "i\0m\0a\0f\0d\0c\0b\0v\0h\0zic64b\0zicbom\0zicbop\0zicboz\0ziccamoa\0ziccif\0zicclsm\0ziccrse\0zicond\0zicntr\0zicsr\0zifencei\0zihintntl\0zihintpause\0zihpm\0zimop\0zmmul\0za64rs\0zaamo\0zalrsc\0zawrs\0zfa\0zfhmin\0zca\0zcb\0zcd\0zcmop\0zba\0zbb\0zbs\0zkt\0zvbb\0zve32f\0zve32x\0zve64f\0zve64d\0zve64x\0zvfhmin\0zvkb\0zvkt\0sdtrig\0shcounterenw\0sha\0shgatpa\0shtvala\0shvsatpa\0shvstvala\0shvstvecd\0smaia\0smnpm\0smstateen\0ssaia\0ssccptr\0sscofpmf\0sscounterenw\0ssnpm\0ssstateen\0ssstrict\0sstc\0sstvala\0sstvecd\0ssu64xl\0supm\0svade\0svinval\0svnapot\0svpbmt"; riscv,isa-base = "rv64i"; - riscv,isa = "rv64imafdch_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_zicsr_zifencei_zihintntl_zihintpause_zihpm_zmmul_za64rs_zaamo_zalrsc_zawrs_zfa_zca_zcd_zba_zbb_zbc_zbs_sdtrig_shcounterenw_shgatpa_shtvala_shvsatpa_shvstvala_shvstvecd_smaia_ssaia_ssccptr_sscounterenw_ssstrict_sstc_sstvala_sstvecd_ssu64xl_svadu_svvptc"; - mmu-type = "riscv,sv57"; + riscv,isa = "rv64imafdcbvh_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_zicond_zicntr_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_zmmul_za64rs_zaamo_zalrsc_zawrs_zfa_zfhmin_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkt_zvbb_zve32f_zve32x_zve64f_zve64d_zve64x_zvfhmin_zvkb_zvkt_sdtrig_shcounterenw_sha_shgatpa_shtvala_shvsatpa_shvstvala_shvstvecd_smaia_smnpm_smstateen_ssaia_ssccptr_sscofpmf_sscounterenw_ssnpm_ssstateen_ssstrict_sstc_sstvala_sstvecd_ssu64xl_supm_svade_svinval_svnapot_svpbmt"; + mmu-type = "riscv,sv39"; interrupt-controller { #interrupt-cells = <0x01>; @@ -91,10 +91,10 @@ riscv,cbop-block-size = <0x40>; riscv,cboz-block-size = <0x40>; riscv,cbom-block-size = <0x40>; - riscv,isa-extensions = "i\0m\0a\0f\0d\0c\0h\0zic64b\0zicbom\0zicbop\0zicboz\0ziccamoa\0ziccif\0zicclsm\0ziccrse\0zicntr\0zicsr\0zifencei\0zihintntl\0zihintpause\0zihpm\0zmmul\0za64rs\0zaamo\0zalrsc\0zawrs\0zfa\0zca\0zcd\0zba\0zbb\0zbc\0zbs\0sdtrig\0shcounterenw\0shgatpa\0shtvala\0shvsatpa\0shvstvala\0shvstvecd\0smaia\0ssaia\0ssccptr\0sscounterenw\0ssstrict\0sstc\0sstvala\0sstvecd\0ssu64xl\0svadu\0svvptc"; + riscv,isa-extensions = "i\0m\0a\0f\0d\0c\0b\0v\0h\0zic64b\0zicbom\0zicbop\0zicboz\0ziccamoa\0ziccif\0zicclsm\0ziccrse\0zicond\0zicntr\0zicsr\0zifencei\0zihintntl\0zihintpause\0zihpm\0zimop\0zmmul\0za64rs\0zaamo\0zalrsc\0zawrs\0zfa\0zfhmin\0zca\0zcb\0zcd\0zcmop\0zba\0zbb\0zbs\0zkt\0zvbb\0zve32f\0zve32x\0zve64f\0zve64d\0zve64x\0zvfhmin\0zvkb\0zvkt\0sdtrig\0shcounterenw\0sha\0shgatpa\0shtvala\0shvsatpa\0shvstvala\0shvstvecd\0smaia\0smnpm\0smstateen\0ssaia\0ssccptr\0sscofpmf\0sscounterenw\0ssnpm\0ssstateen\0ssstrict\0sstc\0sstvala\0sstvecd\0ssu64xl\0supm\0svade\0svinval\0svnapot\0svpbmt"; riscv,isa-base = "rv64i"; - riscv,isa = "rv64imafdch_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_zicsr_zifencei_zihintntl_zihintpause_zihpm_zmmul_za64rs_zaamo_zalrsc_zawrs_zfa_zca_zcd_zba_zbb_zbc_zbs_sdtrig_shcounterenw_shgatpa_shtvala_shvsatpa_shvstvala_shvstvecd_smaia_ssaia_ssccptr_sscounterenw_ssstrict_sstc_sstvala_sstvecd_ssu64xl_svadu_svvptc"; - mmu-type = "riscv,sv57"; + riscv,isa = "rv64imafdcbvh_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_zicond_zicntr_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_zmmul_za64rs_zaamo_zalrsc_zawrs_zfa_zfhmin_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkt_zvbb_zve32f_zve32x_zve64f_zve64d_zve64x_zvfhmin_zvkb_zvkt_sdtrig_shcounterenw_sha_shgatpa_shtvala_shvsatpa_shvstvala_shvstvecd_smaia_smnpm_smstateen_ssaia_ssccptr_sscofpmf_sscounterenw_ssnpm_ssstateen_ssstrict_sstc_sstvala_sstvecd_ssu64xl_supm_svade_svinval_svnapot_svpbmt"; + mmu-type = "riscv,sv39"; interrupt-controller { #interrupt-cells = <0x01>; @@ -113,10 +113,10 @@ riscv,cbop-block-size = <0x40>; riscv,cboz-block-size = <0x40>; riscv,cbom-block-size = <0x40>; - riscv,isa-extensions = "i\0m\0a\0f\0d\0c\0h\0zic64b\0zicbom\0zicbop\0zicboz\0ziccamoa\0ziccif\0zicclsm\0ziccrse\0zicntr\0zicsr\0zifencei\0zihintntl\0zihintpause\0zihpm\0zmmul\0za64rs\0zaamo\0zalrsc\0zawrs\0zfa\0zca\0zcd\0zba\0zbb\0zbc\0zbs\0sdtrig\0shcounterenw\0shgatpa\0shtvala\0shvsatpa\0shvstvala\0shvstvecd\0smaia\0ssaia\0ssccptr\0sscounterenw\0ssstrict\0sstc\0sstvala\0sstvecd\0ssu64xl\0svadu\0svvptc"; + riscv,isa-extensions = "i\0m\0a\0f\0d\0c\0b\0v\0h\0zic64b\0zicbom\0zicbop\0zicboz\0ziccamoa\0ziccif\0zicclsm\0ziccrse\0zicond\0zicntr\0zicsr\0zifencei\0zihintntl\0zihintpause\0zihpm\0zimop\0zmmul\0za64rs\0zaamo\0zalrsc\0zawrs\0zfa\0zfhmin\0zca\0zcb\0zcd\0zcmop\0zba\0zbb\0zbs\0zkt\0zvbb\0zve32f\0zve32x\0zve64f\0zve64d\0zve64x\0zvfhmin\0zvkb\0zvkt\0sdtrig\0shcounterenw\0sha\0shgatpa\0shtvala\0shvsatpa\0shvstvala\0shvstvecd\0smaia\0smnpm\0smstateen\0ssaia\0ssccptr\0sscofpmf\0sscounterenw\0ssnpm\0ssstateen\0ssstrict\0sstc\0sstvala\0sstvecd\0ssu64xl\0supm\0svade\0svinval\0svnapot\0svpbmt"; riscv,isa-base = "rv64i"; - riscv,isa = "rv64imafdch_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_zicsr_zifencei_zihintntl_zihintpause_zihpm_zmmul_za64rs_zaamo_zalrsc_zawrs_zfa_zca_zcd_zba_zbb_zbc_zbs_sdtrig_shcounterenw_shgatpa_shtvala_shvsatpa_shvstvala_shvstvecd_smaia_ssaia_ssccptr_sscounterenw_ssstrict_sstc_sstvala_sstvecd_ssu64xl_svadu_svvptc"; - mmu-type = "riscv,sv57"; + riscv,isa = "rv64imafdcbvh_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_zicond_zicntr_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_zmmul_za64rs_zaamo_zalrsc_zawrs_zfa_zfhmin_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkt_zvbb_zve32f_zve32x_zve64f_zve64d_zve64x_zvfhmin_zvkb_zvkt_sdtrig_shcounterenw_sha_shgatpa_shtvala_shvsatpa_shvstvala_shvstvecd_smaia_smnpm_smstateen_ssaia_ssccptr_sscofpmf_sscounterenw_ssnpm_ssstateen_ssstrict_sstc_sstvala_sstvecd_ssu64xl_supm_svade_svinval_svnapot_svpbmt"; + mmu-type = "riscv,sv39"; interrupt-controller { #interrupt-cells = <0x01>; @@ -172,7 +172,7 @@ chosen { stdout-path = "/soc/serial@10000000"; - rng-seed = <0xa7312a61 0xb4333ebb 0x2b9e3913 0x2ffef846 0x3fdd1be9 0x53a17643 0x37180ee 0x9010f234>; + rng-seed = <0xd84b7de8 0x55c728a4 0xadbe81a1 0x824d757b 0x2208e43d 0x1b7ba0d5 0x9ef0cf9d 0x28cf7f82>; }; soc { @@ -202,6 +202,16 @@ compatible = "sifive,test1\0sifive,test0\0syscon"; }; + iommu@3010000 { + msi-parent = <0x0a>; + interrupts = <0x24 0x01 0x25 0x01 0x26 0x01 0x27 0x01>; + interrupt-parent = <0x0c>; + reg = <0x00 0x3010000 0x00 0x1000>; + phandle = <0x8000>; + #iommu-cells = <0x01>; + compatible = "riscv,iommu"; + }; + virtio_mmio@10008000 { interrupts = <0x08 0x04>; interrupt-parent = <0x0c>; @@ -315,6 +325,7 @@ pci@30000000 { interrupt-map-mask = <0x1800 0x00 0x00 0x07>; interrupt-map = <0x00 0x00 0x00 0x01 0x0c 0x20 0x04 0x00 0x00 0x00 0x02 0x0c 0x21 0x04 0x00 0x00 0x00 0x03 0x0c 0x22 0x04 0x00 0x00 0x00 0x04 0x0c 0x23 0x04 0x800 0x00 0x00 0x01 0x0c 0x21 0x04 0x800 0x00 0x00 0x02 0x0c 0x22 0x04 0x800 0x00 0x00 0x03 0x0c 0x23 0x04 0x800 0x00 0x00 0x04 0x0c 0x20 0x04 0x1000 0x00 0x00 0x01 0x0c 0x22 0x04 0x1000 0x00 0x00 0x02 0x0c 0x23 0x04 0x1000 0x00 0x00 0x03 0x0c 0x20 0x04 0x1000 0x00 0x00 0x04 0x0c 0x21 0x04 0x1800 0x00 0x00 0x01 0x0c 0x23 0x04 0x1800 0x00 0x00 0x02 0x0c 0x20 0x04 0x1800 0x00 0x00 0x03 0x0c 0x21 0x04 0x1800 0x00 0x00 0x04 0x0c 0x22 0x04>; + iommu-map = <0x00 0x8000 0x00 0x00 0x00 0x8000 0x00 0xffff>; ranges = <0x1000000 0x00 0x00 0x00 0x3000000 0x00 0x10000 0x2000000 0x00 0x40000000 0x00 0x40000000 0x00 0x40000000 0x3000000 0x04 0x00 0x04 0x00 0x04 0x00>; reg = <0x00 0x30000000 0x00 0x10000000>; msi-parent = <0x0a>; diff --git a/platform/riscv64/qemu-aia/image/dts/zone0.dts b/platform/riscv64/qemu-aia/image/dts/zone0.dts index 3b0589b6f..be2ad5ffe 100644 --- a/platform/riscv64/qemu-aia/image/dts/zone0.dts +++ b/platform/riscv64/qemu-aia/image/dts/zone0.dts @@ -47,9 +47,9 @@ riscv,cbop-block-size = <0x40>; riscv,cboz-block-size = <0x40>; riscv,cbom-block-size = <0x40>; - riscv,isa-extensions = "i\0m\0a\0f\0d\0c\0ssaia\0sstc"; + riscv,isa-extensions = "i\0m\0a\0f\0d\0c\0v\0ssstateen\0ssaia\0sstc\0svpbmt\0zicbom\0zicbop\0zicboz"; riscv,isa-base = "rv64i"; - riscv,isa = "rv64imafdc_ssaia_sstc"; + riscv,isa = "rv64imafdcv_ssstateen_ssaia_sstc_svpbmt_zicbom_zicbop_zicboz"; mmu-type = "riscv,sv57"; interrupt-controller { @@ -69,9 +69,9 @@ riscv,cbop-block-size = <0x40>; riscv,cboz-block-size = <0x40>; riscv,cbom-block-size = <0x40>; - riscv,isa-extensions = "i\0m\0a\0f\0d\0c\0ssaia\0sstc"; + riscv,isa-extensions = "i\0m\0a\0f\0d\0c\0v\0ssstateen\0ssaia\0sstc\0svpbmt\0zicbom\0zicbop\0zicboz"; riscv,isa-base = "rv64i"; - riscv,isa = "rv64imafdc_ssaia_sstc"; + riscv,isa = "rv64imafdcv_ssstateen_ssaia_sstc_svpbmt_zicbom_zicbop_zicboz"; mmu-type = "riscv,sv57"; interrupt-controller { @@ -91,9 +91,9 @@ riscv,cbop-block-size = <0x40>; riscv,cboz-block-size = <0x40>; riscv,cbom-block-size = <0x40>; - riscv,isa-extensions = "i\0m\0a\0f\0d\0c\0ssaia\0sstc"; + riscv,isa-extensions = "i\0m\0a\0f\0d\0c\0v\0ssstateen\0ssaia\0sstc\0svpbmt\0zicbom\0zicbop\0zicboz"; riscv,isa-base = "rv64i"; - riscv,isa = "rv64imafdc_ssaia_sstc"; + riscv,isa = "rv64imafdcv_ssstateen_ssaia_sstc_svpbmt_zicbom_zicbop_zicboz"; mmu-type = "riscv,sv57"; interrupt-controller { @@ -103,24 +103,6 @@ phandle = <0x04>; }; }; - - cpu-map { - - cluster0 { - - core0 { - cpu = <0x07>; - }; - - core1 { - cpu = <0x05>; - }; - - core2 { - cpu = <0x03>; - }; - }; - }; }; soc { @@ -159,9 +141,20 @@ compatible = "qemu,imsics\0riscv,imsics"; }; + iommu@3010000 { + msi-parent = <0x0a>; + interrupts = <0x24 0x01 0x25 0x01 0x26 0x01 0x27 0x01>; + interrupt-parent = <0x0c>; + reg = <0x00 0x3010000 0x00 0x1000>; + phandle = <0x8000>; + #iommu-cells = <0x01>; + compatible = "riscv,iommu"; + }; + pci@30000000 { interrupt-map-mask = <0x1800 0x00 0x00 0x07>; interrupt-map = <0x00 0x00 0x00 0x01 0x0c 0x20 0x04 0x00 0x00 0x00 0x02 0x0c 0x21 0x04 0x00 0x00 0x00 0x03 0x0c 0x22 0x04 0x00 0x00 0x00 0x04 0x0c 0x23 0x04 0x800 0x00 0x00 0x01 0x0c 0x21 0x04 0x800 0x00 0x00 0x02 0x0c 0x22 0x04 0x800 0x00 0x00 0x03 0x0c 0x23 0x04 0x800 0x00 0x00 0x04 0x0c 0x20 0x04 0x1000 0x00 0x00 0x01 0x0c 0x22 0x04 0x1000 0x00 0x00 0x02 0x0c 0x23 0x04 0x1000 0x00 0x00 0x03 0x0c 0x20 0x04 0x1000 0x00 0x00 0x04 0x0c 0x21 0x04 0x1800 0x00 0x00 0x01 0x0c 0x23 0x04 0x1800 0x00 0x00 0x02 0x0c 0x20 0x04 0x1800 0x00 0x00 0x03 0x0c 0x21 0x04 0x1800 0x00 0x00 0x04 0x0c 0x22 0x04>; + iommu-map = <0x00 0x8000 0x00 0x00 0x00 0x8000 0x00 0xffff>; ranges = <0x1000000 0x00 0x00 0x00 0x3000000 0x00 0x10000 0x2000000 0x00 0x40000000 0x00 0x40000000 0x00 0x40000000 0x3000000 0x04 0x00 0x04 0x00 0x04 0x00>; reg = <0x00 0x30000000 0x00 0x10000000>; msi-parent = <0x0a>; @@ -186,4 +179,4 @@ bootargs = "root=/dev/vda rw earlycon console=ttyS0"; }; -}; \ No newline at end of file +}; diff --git a/platform/riscv64/qemu-aia/image/dts/zone1-linux.dts b/platform/riscv64/qemu-aia/image/dts/zone1-linux.dts index 8d5101679..c517219fa 100644 --- a/platform/riscv64/qemu-aia/image/dts/zone1-linux.dts +++ b/platform/riscv64/qemu-aia/image/dts/zone1-linux.dts @@ -18,9 +18,9 @@ riscv,cbop-block-size = <0x40>; riscv,cboz-block-size = <0x40>; riscv,cbom-block-size = <0x40>; - riscv,isa-extensions = "i\0m\0a\0f\0d\0c\0ssaia\0sstc"; + riscv,isa-extensions = "i\0m\0a\0f\0d\0c\0v\0ssstateen\0ssaia\0sstc\0svpbmt\0zicbom\0zicbop\0zicboz"; riscv,isa-base = "rv64i"; - riscv,isa = "rv64imafdc_ssaia_sstc"; + riscv,isa = "rv64imafdcv_ssstateen_ssaia_sstc_svpbmt_zicbom_zicbop_zicboz"; mmu-type = "riscv,sv57"; interrupt-controller { @@ -72,9 +72,20 @@ compatible = "virtio,mmio"; }; + iommu@3010000 { + msi-parent = <0x0a>; + interrupts = <0x24 0x01 0x25 0x01 0x26 0x01 0x27 0x01>; + interrupt-parent = <0x0c>; + reg = <0x00 0x3010000 0x00 0x1000>; + phandle = <0x8000>; + #iommu-cells = <0x01>; + compatible = "riscv,iommu"; + }; + pci@30000000 { interrupt-map-mask = <0x1800 0x00 0x00 0x07>; interrupt-map = <0x00 0x00 0x00 0x01 0x0c 0x20 0x04 0x00 0x00 0x00 0x02 0x0c 0x21 0x04 0x00 0x00 0x00 0x03 0x0c 0x22 0x04 0x00 0x00 0x00 0x04 0x0c 0x23 0x04 0x800 0x00 0x00 0x01 0x0c 0x21 0x04 0x800 0x00 0x00 0x02 0x0c 0x22 0x04 0x800 0x00 0x00 0x03 0x0c 0x23 0x04 0x800 0x00 0x00 0x04 0x0c 0x20 0x04 0x1000 0x00 0x00 0x01 0x0c 0x22 0x04 0x1000 0x00 0x00 0x02 0x0c 0x23 0x04 0x1000 0x00 0x00 0x03 0x0c 0x20 0x04 0x1000 0x00 0x00 0x04 0x0c 0x21 0x04 0x1800 0x00 0x00 0x01 0x0c 0x23 0x04 0x1800 0x00 0x00 0x02 0x0c 0x20 0x04 0x1800 0x00 0x00 0x03 0x0c 0x21 0x04 0x1800 0x00 0x00 0x04 0x0c 0x22 0x04>; + iommu-map = <0x00 0x8000 0x00 0x00 0x00 0x8000 0x00 0xffff>; ranges = <0x1000000 0x00 0x00 0x00 0x3000000 0x00 0x10000 0x2000000 0x00 0x40000000 0x00 0x40000000 0x00 0x40000000 0x3000000 0x04 0x00 0x04 0x00 0x04 0x00>; reg = <0x00 0x30000000 0x00 0x10000000>; msi-parent = <0x0a>; diff --git a/platform/riscv64/qemu-aia/kconfig/defconfig b/platform/riscv64/qemu-aia/kconfig/defconfig new file mode 100644 index 000000000..3d7ff1683 --- /dev/null +++ b/platform/riscv64/qemu-aia/kconfig/defconfig @@ -0,0 +1,9 @@ +CONFIG_AIA=y +CONFIG_ARCH_RISCV64=y +CONFIG_IOMMU=y +CONFIG_PCI=y +CONFIG_PCIE_ECAM=y +CONFIG_RISCV_IOMMU=y +CONFIG_RVA23=y +CONFIG_SHARE_S2PT=y +CONFIG_VIOMMU=y diff --git a/platform/riscv64/qemu-aia/platform.mk b/platform/riscv64/qemu-aia/platform.mk index c53c431a8..414f75bdc 100644 --- a/platform/riscv64/qemu-aia/platform.mk +++ b/platform/riscv64/qemu-aia/platform.mk @@ -12,7 +12,7 @@ zone0_dtb := $(image_dir)/dts/zone0.dtb QEMU_ARGS := -machine virt,aia=aplic-imsic,aia-guests=1,iommu-sys=on QEMU_ARGS += -bios default -QEMU_ARGS += -cpu rv64 +QEMU_ARGS += -cpu rva23s64 QEMU_ARGS += -smp 4 QEMU_ARGS += -m 2G QEMU_ARGS += -nographic -S @@ -25,11 +25,12 @@ QEMU_ARGS += -device loader,file="$(zone0_dtb)",addr=0x8f000000,force-raw=on QEMU_ARGS += -drive if=none,file=$(FSIMG1),id=hd0,format=raw # QEMU_ARGS += -device virtio-blk-device,drive=hd0,bus=virtio-mmio-bus.7 -QEMU_ARGS += -device virtio-blk-pci,drive=hd0,disable-legacy=on,disable-modern=off,addr=01.0 +QEMU_ARGS += -device virtio-blk-pci,drive=hd0,disable-legacy=on,disable-modern=off,addr=01.0,iommu_platform=on QEMU_ARGS += -device virtio-serial-device,bus=virtio-mmio-bus.6 -chardev pty,id=X10007000 -device virtconsole,chardev=X10007000 -S QEMU_ARGS += -drive if=none,file=$(FSIMG2),id=hd1,format=qcow2 # QEMU_ARGS += -device virtio-blk-device,drive=hd1,bus=virtio-mmio-bus.5 -QEMU_ARGS += -device virtio-blk-pci,drive=hd1,disable-legacy=on,disable-modern=off,addr=02.0 +QEMU_ARGS += -device virtio-blk-pci,drive=hd1,disable-legacy=on,disable-modern=off,addr=02.0,iommu_platform=on +# QEMU_ARGS += -d trace:riscv_iommu_* # ------------------------------------------------------------------- # QEMU_ARGS := -machine virt @@ -51,4 +52,4 @@ QEMU_ARGS += -device virtio-blk-pci,drive=hd1,disable-legacy=on,disable-modern=o # QEMU_ARGS += -device virtio-serial-device -chardev pty,id=serial3 -device virtconsole,chardev=serial3 $(hvisor_bin): elf - $(OBJCOPY) $(hvisor_elf) --strip-all -O binary $@ \ No newline at end of file + $(OBJCOPY) $(hvisor_elf) --strip-all -O binary $@ diff --git a/platform/riscv64/qemu-aia/test/runner.sh b/platform/riscv64/qemu-aia/test/runner.sh index c51268536..ce3fb0350 100755 --- a/platform/riscv64/qemu-aia/test/runner.sh +++ b/platform/riscv64/qemu-aia/test/runner.sh @@ -6,10 +6,7 @@ PWD=$(pwd) THIS=$(basename $0) CARGO_BUILD_INPUT_ARG0=$1 -# capture env: FEATURES, ARCH - ARCH=${ARCH} -FEATURES=${FEATURES} BOARD=${BOARD} HVISOR_ELF=$CARGO_BUILD_INPUT_ARG0 @@ -25,7 +22,7 @@ info() { echo "[INFO | $THIS] $1" } -info "Running cargo test with env: ARCH=$ARCH, FEATURES=$FEATURES, BOARD=$BOARD" +info "Running cargo test with env: ARCH=$ARCH, BOARD=$BOARD" info "Building hvisor with $CARGO_BUILD_INPUT_ARG0" info "PWD=$PWD, running cargo test" @@ -33,7 +30,7 @@ $OBJCOPY $HVISOR_ELF --strip-all -O binary $HVISOR_BIN qemu-system-riscv64 \ -machine virt,aia=aplic-imsic,aia-guests=1,iommu-sys=on \ - -bios default -cpu rv64 -smp 4 -m 4G -nographic \ + -bios default -cpu rva23s64 -smp 4 -m 4G -nographic \ -kernel $HVISOR_BIN -exit 0 \ No newline at end of file +exit 0 diff --git a/platform/riscv64/qemu-plic/README.md b/platform/riscv64/qemu-plic/README.md index b6884c55d..898babb38 100644 --- a/platform/riscv64/qemu-plic/README.md +++ b/platform/riscv64/qemu-plic/README.md @@ -73,5 +73,5 @@ Both the root zone and zone1 are assigned one virtio-pci-blk device(using wired- Please confirm qemu-system-riscv64 version >= 10.0.0, add iommu-sys=on for machine param and iommu_platform=on for devices linked behind iommu. (refer to platform.mk) -Add `iommu` and `share_s2pt` features for hvisor. +Enable IOMMU in **`kconfig/defconfig`** (`CONFIG_IOMMU`, `CONFIG_RISCV_IOMMU`, `CONFIG_SHARE_S2PT`, etc.) for hvisor. diff --git a/platform/riscv64/qemu-plic/board.rs b/platform/riscv64/qemu-plic/board.rs index 80c278c2d..84c7dbccb 100644 --- a/platform/riscv64/qemu-plic/board.rs +++ b/platform/riscv64/qemu-plic/board.rs @@ -47,9 +47,9 @@ pub const ROOT_ZONE_NAME: &str = "root-linux"; pub const ROOT_ZONE_MEMORY_REGIONS: &[HvConfigMemoryRegion] = &[ HvConfigMemoryRegion { mem_type: MEM_TYPE_RAM, - physical_start: 0x83000000, - virtual_start: 0x83000000, - size: 0x7D000000, + physical_start: 0x84600000, + virtual_start: 0x84600000, + size: 0x7BA00000, }, // ram HvConfigMemoryRegion { mem_type: MEM_TYPE_IO, @@ -104,8 +104,8 @@ pub const ROOT_PCI_CONFIG: [HvPciConfig; 1] = [HvPciConfig { pub const ROOT_ZONE_IVC_CONFIG: &[HvIvcConfig] = &[]; pub const ROOT_PCI_DEVS: &[HvPciDevConfig] = &[ - pci_dev!(0x0, 0x0, 0x0, 0x0, VpciDevType::Physical), - pci_dev!(0x0, 0x0, 0x1, 0x0, VpciDevType::Physical), - // pci_dev!(0x0, 0x0, 0x3, 0x0, VpciDevType::Physical), - // pci_dev!(0x0, 0x0, 0x5, 0x0, VpciDevType::StandardVdev), + pci_dev!(0x0, 0x0, 0x0, 0x0 => 0x0, 0x0, 0x0, VpciDevType::Physical), + pci_dev!(0x0, 0x0, 0x1, 0x0 => 0x0, 0x1, 0x0, VpciDevType::Physical), + // pci_dev!(0x0, 0x0, 0x3, 0x0 => 0x0, 0x3, 0x0, VpciDevType::Physical), + // pci_dev!(0x0, 0x0, 0x5, 0x0 => 0x0, 0x5, 0x0, VpciDevType::StandardVdev), ]; diff --git a/platform/riscv64/qemu-plic/cargo/features b/platform/riscv64/qemu-plic/cargo/features deleted file mode 100644 index 6be000e7e..000000000 --- a/platform/riscv64/qemu-plic/cargo/features +++ /dev/null @@ -1,5 +0,0 @@ -aclint -plic -sstc -pci -ecam_pcie diff --git a/platform/riscv64/qemu-plic/configs/virtio-backend.json b/platform/riscv64/qemu-plic/configs/virtio-backend.json index 7ab478162..5ce9f9bea 100644 --- a/platform/riscv64/qemu-plic/configs/virtio-backend.json +++ b/platform/riscv64/qemu-plic/configs/virtio-backend.json @@ -10,14 +10,22 @@ } ], "devices": [ - { - "type": "console", - "addr": "0x10007000", - "len": "0x1000", - "irq": 7, - "status": "enable" - } - ] + { + "type": "blk", + "addr": "0x10006000", + "len": "0x1000", + "irq": 6, + "img": "rootfs2.ext4", + "status": "enable" + }, + { + "type": "console", + "addr": "0x10007000", + "len": "0x1000", + "irq": 7, + "status": "enable" + } + ] } ] -} \ No newline at end of file +} diff --git a/platform/riscv64/qemu-plic/configs/zone1-linux-passthrough.json b/platform/riscv64/qemu-plic/configs/zone1-linux-passthrough.json index 11930624d..c7272daec 100644 --- a/platform/riscv64/qemu-plic/configs/zone1-linux-passthrough.json +++ b/platform/riscv64/qemu-plic/configs/zone1-linux-passthrough.json @@ -54,11 +54,14 @@ }], "num_pci_devs": 2, "alloc_pci_devs": [ - { + { "domain": "0x0", "bus": "0x0", "device": "0x0", "function": "0x0", + "v_bus": "0x0", + "v_device": "0x0", + "v_function": "0x0", "dev_type": "0" }, { @@ -66,7 +69,10 @@ "bus": "0x0", "device": "0x2", "function": "0x0", + "v_bus": "0x0", + "v_device": "0x2", + "v_function": "0x0", "dev_type": "0" } ] -} \ No newline at end of file +} diff --git a/platform/riscv64/qemu-plic/configs/zone1-linux-virtio.json b/platform/riscv64/qemu-plic/configs/zone1-linux-virtio.json index 08bad2a15..434c719db 100644 --- a/platform/riscv64/qemu-plic/configs/zone1-linux-virtio.json +++ b/platform/riscv64/qemu-plic/configs/zone1-linux-virtio.json @@ -53,6 +53,9 @@ "bus": "0x0", "device": "0x0", "function": "0x0", + "v_bus": "0x0", + "v_device": "0x0", + "v_function": "0x0", "dev_type": "0" }, { @@ -60,7 +63,10 @@ "bus": "0x0", "device": "0x2", "function": "0x0", + "v_bus": "0x0", + "v_device": "0x1", + "v_function": "0x0", "dev_type": "0" } ] -} \ No newline at end of file +} diff --git a/platform/riscv64/qemu-plic/configs/zone1-linux.json b/platform/riscv64/qemu-plic/configs/zone1-linux.json new file mode 100644 index 000000000..a745e5338 --- /dev/null +++ b/platform/riscv64/qemu-plic/configs/zone1-linux.json @@ -0,0 +1,68 @@ +{ + "arch": "riscv", + "name": "linux2", + "zone_id": 1, + "cpus": [2, 3], + "memory_regions": [ + { + "type": "ram", + "physical_start": "0x85000000", + "virtual_start": "0x85000000", + "size": "0x0a000000" + }, + { + "type": "virtio", + "physical_start": "0x10006000", + "virtual_start": "0x10006000", + "size": "0x1000" + }, + { + "type": "virtio", + "physical_start": "0x10007000", + "virtual_start": "0x10007000", + "size": "0x1000" + } + ], + "interrupts": [6, 7], + "ivc_configs": [], + "kernel_filepath": "./Image", + "dtb_filepath": "./zone1-linux.dtb", + "kernel_load_paddr": "0x86000000", + "dtb_load_paddr": "0x85000000", + "entry_point": "0x86000000", + "arch_config": { + "plic_base": "0xc000000", + "plic_size": "0x4000000", + "aplic_base": "0xd000000", + "aplic_size": "0x8000" + }, + "pci_config": [{ + "ecam_base": "0x30000000", + "ecam_size": "0x10000000", + "io_base": "0x3000000", + "io_size": "0x10000", + "pci_io_base": "0x0", + "mem32_base": "0x40000000", + "mem32_size": "0x40000000", + "pci_mem32_base": "0x40000000", + "mem64_base": "0x400000000", + "mem64_size": "0x400000000", + "pci_mem64_base": "0x400000000", + "bus_range_begin": "0x0", + "bus_range_end": "0x1f", + "domain": "0x0" + }], + "num_pci_devs": 1, + "alloc_pci_devs": [ + { + "domain": "0x0", + "bus": "0x0", + "device": "0x0", + "function": "0x0", + "v_bus": "0x0", + "v_device": "0x0", + "v_function": "0x0", + "dev_type": "0" + } + ] +} diff --git a/platform/riscv64/qemu-plic/image/dts/zone0.dts b/platform/riscv64/qemu-plic/image/dts/zone0.dts index a1e6cdb4c..fa9460632 100644 --- a/platform/riscv64/qemu-plic/image/dts/zone0.dts +++ b/platform/riscv64/qemu-plic/image/dts/zone0.dts @@ -16,7 +16,8 @@ reg = <0x0>; status = "okay"; compatible = "riscv"; - riscv,isa = "rv64imafdcsu_sstc"; + // Advertise the Vector extension to the root-zone kernel. + riscv,isa = "rv64imafdcvsu_sstc_svpbmt"; mmu-type = "riscv,sv39"; cpu0_intc: interrupt-controller { @@ -31,7 +32,8 @@ reg = <0x1>; status = "okay"; compatible = "riscv"; - riscv,isa = "rv64imafdcsu_sstc"; + // Advertise the Vector extension to the root-zone kernel. + riscv,isa = "rv64imafdcvsu_sstc_svpbmt"; mmu-type = "riscv,sv39"; cpu1_intc: interrupt-controller { diff --git a/platform/riscv64/qemu-plic/image/dts/zone1-linux.dts b/platform/riscv64/qemu-plic/image/dts/zone1-linux.dts index 9583df748..370806640 100644 --- a/platform/riscv64/qemu-plic/image/dts/zone1-linux.dts +++ b/platform/riscv64/qemu-plic/image/dts/zone1-linux.dts @@ -16,7 +16,8 @@ reg = <0x02>; status = "okay"; compatible = "riscv"; - riscv,isa = "rv64imafdcsu_sstc"; + // Advertise the Vector extension to the guest kernel. + riscv,isa = "rv64imafdcvsu_sstc_svpbmt"; mmu-type = "riscv,sv39"; interrupt-controller { @@ -32,7 +33,8 @@ reg = <0x03>; status = "okay"; compatible = "riscv"; - riscv,isa = "rv64imafdcsu_sstc"; + // Advertise the Vector extension to the guest kernel. + riscv,isa = "rv64imafdcvsu_sstc_svpbmt"; mmu-type = "riscv,sv39"; interrupt-controller { @@ -97,6 +99,13 @@ #address-cells = <0x03>; }; + virtio_mmio@10006000 { + interrupts = <0x06>; + interrupt-parent = <0x02>; + reg = <0x00 0x10006000 0x00 0x1000>; + compatible = "virtio,mmio"; + }; + virtio_mmio@10007000 { interrupts = <0x07>; interrupt-parent = <0x02>; @@ -108,4 +117,4 @@ chosen { bootargs = "root=/dev/vda rw earlycon console=hvc0"; }; -}; \ No newline at end of file +}; diff --git a/platform/riscv64/qemu-plic/kconfig/defconfig b/platform/riscv64/qemu-plic/kconfig/defconfig new file mode 100644 index 000000000..9ccd56376 --- /dev/null +++ b/platform/riscv64/qemu-plic/kconfig/defconfig @@ -0,0 +1,6 @@ +CONFIG_ACLINT=y +CONFIG_ARCH_RISCV64=y +CONFIG_PCI=y +CONFIG_PCIE_ECAM=y +CONFIG_PLIC=y +CONFIG_RVA23=y diff --git a/platform/riscv64/qemu-plic/platform.mk b/platform/riscv64/qemu-plic/platform.mk index a3574dc57..703513728 100644 --- a/platform/riscv64/qemu-plic/platform.mk +++ b/platform/riscv64/qemu-plic/platform.mk @@ -12,7 +12,7 @@ zone0_dtb := $(image_dir)/dts/zone0.dtb QEMU_ARGS := -machine virt,aclint=on # ,iommu-sys=on # -d trace:*iommu* QEMU_ARGS += -bios default -QEMU_ARGS += -cpu rv64 +QEMU_ARGS += -cpu rva23s64 QEMU_ARGS += -smp 4 QEMU_ARGS += -m 4G QEMU_ARGS += -nographic @@ -51,4 +51,4 @@ QEMU_ARGS += -device virtio-blk-pci,drive=hd1,disable-legacy=on,disable-modern=o # QEMU_ARGS += -device virtio-serial-device -chardev pty,id=serial3 -device virtconsole,chardev=serial3 $(hvisor_bin): elf - $(OBJCOPY) $(hvisor_elf) --strip-all -O binary $@ \ No newline at end of file + $(OBJCOPY) $(hvisor_elf) --strip-all -O binary $@ diff --git a/platform/riscv64/qemu-plic/scripts/boot_zone1.sh b/platform/riscv64/qemu-plic/scripts/boot_zone1.sh index 889f5fa49..d3ffe3505 100644 --- a/platform/riscv64/qemu-plic/scripts/boot_zone1.sh +++ b/platform/riscv64/qemu-plic/scripts/boot_zone1.sh @@ -3,9 +3,7 @@ insmod hvisor.ko mount -t proc proc /proc mount -t sysfs sysfs /sys -rm nohup.out mkdir -p /dev/pts mount -t devpts devpts /dev/pts -nohup ./hvisor virtio start virtio-backend.json & -./hvisor zone start zone1-linux-virtio.json && \ -cat nohup.out | grep "char device" \ No newline at end of file +./hvisor virtio start virtio-backend.json & +./hvisor zone start zone1-linux.json diff --git a/platform/riscv64/qemu-plic/test/runner.sh b/platform/riscv64/qemu-plic/test/runner.sh index cbf1e5703..51752d0ea 100755 --- a/platform/riscv64/qemu-plic/test/runner.sh +++ b/platform/riscv64/qemu-plic/test/runner.sh @@ -6,10 +6,7 @@ PWD=$(pwd) THIS=$(basename $0) CARGO_BUILD_INPUT_ARG0=$1 -# capture env: FEATURES, ARCH - ARCH=${ARCH} -FEATURES=${FEATURES} BOARD=${BOARD} HVISOR_ELF=$CARGO_BUILD_INPUT_ARG0 @@ -25,7 +22,7 @@ info() { echo "[INFO | $THIS] $1" } -info "Running cargo test with env: ARCH=$ARCH, FEATURES=$FEATURES, BOARD=$BOARD" +info "Running cargo test with env: ARCH=$ARCH, BOARD=$BOARD" info "Building hvisor with $CARGO_BUILD_INPUT_ARG0" info "PWD=$PWD, running cargo test" @@ -33,7 +30,7 @@ $OBJCOPY $HVISOR_ELF --strip-all -O binary $HVISOR_BIN qemu-system-riscv64 \ -machine virt,aclint=on \ - -bios default -cpu rv64 -smp 4 -m 4G -nographic \ + -bios default -cpu rva23s64 -smp 4 -m 4G -nographic \ -kernel $HVISOR_BIN exit 0 diff --git a/platform/riscv64/ur-dp1000/cargo/features b/platform/riscv64/ur-dp1000/cargo/features deleted file mode 100644 index cac3e049a..000000000 --- a/platform/riscv64/ur-dp1000/cargo/features +++ /dev/null @@ -1,2 +0,0 @@ -plic -dp1000_plic diff --git a/platform/riscv64/ur-dp1000/kconfig/defconfig b/platform/riscv64/ur-dp1000/kconfig/defconfig new file mode 100644 index 000000000..58f138b2b --- /dev/null +++ b/platform/riscv64/ur-dp1000/kconfig/defconfig @@ -0,0 +1,3 @@ +CONFIG_ARCH_RISCV64=y +CONFIG_DP1000_PLIC=y +CONFIG_PLIC=y diff --git a/platform/x86_64/ecx-2300f-peg/board.rs b/platform/x86_64/ecx-2300f-peg/board.rs index 1b295342d..97e630435 100644 --- a/platform/x86_64/ecx-2300f-peg/board.rs +++ b/platform/x86_64/ecx-2300f-peg/board.rs @@ -156,30 +156,30 @@ pub const ROOT_PCI_CONFIG: [HvPciConfig; 1] = [HvPciConfig { pub const ROOT_PCI_MAX_BUS: usize = 3; pub const ROOT_PCI_DEVS: [HvPciDevConfig; 19] = [ - pci_dev!(0x0, 0x0, 0x0, 0x0, VpciDevType::Physical), // host bridge - pci_dev!(0x0, 0x0, 0x1, 0x0, VpciDevType::Physical), // PCI bridge - pci_dev!(0x0, 0x0, 0x1, 0x1, VpciDevType::Physical), // PCI bridge - // pci_dev!(0x0, 0x0, 0x2, 0x0, VpciDevType::Physical), // display controller - pci_dev!(0x0, 0x0, 0x8, 0x0, VpciDevType::Physical), // system peripheral - pci_dev!(0x0, 0x0, 0x12, 0x0, VpciDevType::Physical), // signal processing controller - pci_dev!(0x0, 0x0, 0x14, 0x0, VpciDevType::Physical), // USB controller - pci_dev!(0x0, 0x0, 0x14, 0x2, VpciDevType::Physical), // RAM memory - pci_dev!(0x0, 0x0, 0x14, 0x5, VpciDevType::Physical), // SD host controller - pci_dev!(0x0, 0x0, 0x15, 0x0, VpciDevType::Physical), // serial bus controller - pci_dev!(0x0, 0x0, 0x16, 0x0, VpciDevType::Physical), // communication controller - pci_dev!(0x0, 0x0, 0x16, 0x3, VpciDevType::Physical), // serial controller - pci_dev!(0x0, 0x0, 0x17, 0x0, VpciDevType::Physical), // SATA controller - pci_dev!(0x0, 0x0, 0x1d, 0x0, VpciDevType::Physical), // PCI bridge - // pci_dev!(0x0, 0x0, 0x1f, 0x0, VpciDevType::Physical), // ISA bridge - pci_dev!(0x0, 0x0, 0x1f, 0x3, VpciDevType::Physical), // audio device - pci_dev!(0x0, 0x0, 0x1f, 0x4, VpciDevType::Physical), // SMBus - pci_dev!(0x0, 0x0, 0x1f, 0x5, VpciDevType::Physical), // serial bus controller - // pci_dev!(0x0, 0x0, 0x1f, 0x6, VpciDevType::Physical), // ethernet controller - pci_dev!(0x0, 0x2, 0x0, 0x0, VpciDevType::Physical), // VGA controller - pci_dev!(0x0, 0x2, 0x0, 0x1, VpciDevType::Physical), // audio device - pci_dev!(0x0, 0x3, 0x0, 0x0, VpciDevType::Physical), // ethernet controller + pci_dev!(0x0, 0x0, 0x0, 0x0 => 0x0, 0x0, 0x0, VpciDevType::Physical), // host bridge + pci_dev!(0x0, 0x0, 0x1, 0x0 => 0x0, 0x1, 0x0, VpciDevType::Physical), // PCI bridge + pci_dev!(0x0, 0x0, 0x1, 0x1 => 0x0, 0x1, 0x1, VpciDevType::Physical), // PCI bridge + // pci_dev!(0x0, 0x0, 0x2, 0x0 => 0x0, 0x2, 0x0, VpciDevType::Physical), // display controller + pci_dev!(0x0, 0x0, 0x8, 0x0 => 0x0, 0x8, 0x0, VpciDevType::Physical), // system peripheral + pci_dev!(0x0, 0x0, 0x12, 0x0 => 0x0, 0x12, 0x0, VpciDevType::Physical), // signal processing controller + pci_dev!(0x0, 0x0, 0x14, 0x0 => 0x0, 0x14, 0x0, VpciDevType::Physical), // USB controller + pci_dev!(0x0, 0x0, 0x14, 0x2 => 0x0, 0x14, 0x2, VpciDevType::Physical), // RAM memory + pci_dev!(0x0, 0x0, 0x14, 0x5 => 0x0, 0x14, 0x5, VpciDevType::Physical), // SD host controller + pci_dev!(0x0, 0x0, 0x15, 0x0 => 0x0, 0x15, 0x0, VpciDevType::Physical), // serial bus controller + pci_dev!(0x0, 0x0, 0x16, 0x0 => 0x0, 0x16, 0x0, VpciDevType::Physical), // communication controller + pci_dev!(0x0, 0x0, 0x16, 0x3 => 0x0, 0x16, 0x3, VpciDevType::Physical), // serial controller + pci_dev!(0x0, 0x0, 0x17, 0x0 => 0x0, 0x17, 0x0, VpciDevType::Physical), // SATA controller + pci_dev!(0x0, 0x0, 0x1d, 0x0 => 0x0, 0x1d, 0x0, VpciDevType::Physical), // PCI bridge + // pci_dev!(0x0, 0x0, 0x1f, 0x0 => 0x0, 0x1f, 0x0, VpciDevType::Physical), // ISA bridge + pci_dev!(0x0, 0x0, 0x1f, 0x3 => 0x0, 0x1f, 0x3, VpciDevType::Physical), // audio device + pci_dev!(0x0, 0x0, 0x1f, 0x4 => 0x0, 0x1f, 0x4, VpciDevType::Physical), // SMBus + pci_dev!(0x0, 0x0, 0x1f, 0x5 => 0x0, 0x1f, 0x5, VpciDevType::Physical), // serial bus controller + // pci_dev!(0x0, 0x0, 0x1f, 0x6 => 0x0, 0x1f, 0x6, VpciDevType::Physical), // ethernet controller + pci_dev!(0x0, 0x2, 0x0, 0x0 => 0x2, 0x0, 0x0, VpciDevType::Physical), // VGA controller + pci_dev!(0x0, 0x2, 0x0, 0x1 => 0x2, 0x0, 0x1, VpciDevType::Physical), // audio device + pci_dev!(0x0, 0x3, 0x0, 0x0 => 0x3, 0x0, 0x0, VpciDevType::Physical), // ethernet controller ]; -#[cfg(all(feature = "graphics"))] +#[cfg(all(graphics))] pub const GRAPHICS_FONT: &[u8] = include_bytes!("../../platform/x86_64/qemu/image/font/spleen-6x12.psf"); diff --git a/platform/x86_64/ecx-2300f-peg/cargo/features b/platform/x86_64/ecx-2300f-peg/cargo/features deleted file mode 100644 index e4ad1c134..000000000 --- a/platform/x86_64/ecx-2300f-peg/cargo/features +++ /dev/null @@ -1,2 +0,0 @@ -pci -uart16550a diff --git a/platform/x86_64/ecx-2300f-peg/kconfig/defconfig b/platform/x86_64/ecx-2300f-peg/kconfig/defconfig new file mode 100644 index 000000000..770397dbb --- /dev/null +++ b/platform/x86_64/ecx-2300f-peg/kconfig/defconfig @@ -0,0 +1,4 @@ +CONFIG_ARCH_X86_64=y +CONFIG_PCI=y +CONFIG_PCIE_ECAM=y +CONFIG_UART16550A=y diff --git a/platform/x86_64/nuc14mnk/board.rs b/platform/x86_64/nuc14mnk/board.rs index bceb2bfe8..1768ecea9 100644 --- a/platform/x86_64/nuc14mnk/board.rs +++ b/platform/x86_64/nuc14mnk/board.rs @@ -53,7 +53,7 @@ const ROOT_ZONE_UEFI_REGION: HvConfigMemoryRegion = HvConfigMemoryRegion { const ROOT_ZONE_UEFI_REGION_ID: usize = 0x3; pub const ROOT_ZONE_NAME: &str = "root-linux"; -pub const ROOT_ZONE_CMDLINE: &str = "video=vesafb console=tty0 nointremap no_timer_check efi=noruntime pci=pcie_scan_all root=/dev/nvme0n1p5 rw init=/init rootwait\0"; +pub const ROOT_ZONE_CMDLINE: &str = "video=vesafb console=tty0 earlycon=efifb nointremap no_timer_check efi=noruntime pci=pcie_scan_all root=/dev/nvme0n1p5 rw init=/init rootwait\0"; // pub const ROOT_ZONE_CMDLINE: &str = "video=vesafb console=ttyS0 earlyprintk=serial nointremap no_timer_check pci=pcie_scan_all root=/dev/vda rw init=/init\0"; //"console=ttyS0 earlyprintk=serial rdinit=/init nokaslr nointremap\0"; // noapic // video=vesafb @@ -113,9 +113,9 @@ pub const ROOT_ZONE_MEMORY_REGIONS: [HvConfigMemoryRegion; 15] = [ }, // pnp 00:05 HvConfigMemoryRegion { mem_type: MEM_TYPE_RESERVED, - physical_start: 0xfe01_1000, - virtual_start: 0xfe01_1000, - size: 0x40_0000, + physical_start: 0xfe00_0000, + virtual_start: 0xfe00_0000, + size: 0xd0_0000, }, // reserved HvConfigMemoryRegion { mem_type: MEM_TYPE_RESERVED, @@ -179,27 +179,27 @@ pub const ROOT_PCI_CONFIG: [HvPciConfig; 1] = [HvPciConfig { pub const ROOT_PCI_MAX_BUS: usize = 2; pub const ROOT_PCI_DEVS: [HvPciDevConfig; 18] = [ - pci_dev!(0x0, 0x0, 0x0, 0x0, VpciDevType::Physical), // host bridge - pci_dev!(0x0, 0x0, 0x2, 0x0, VpciDevType::Physical), // VGA controller - pci_dev!(0x0, 0x0, 0x4, 0x0, VpciDevType::Physical), - pci_dev!(0x0, 0x0, 0x8, 0x0, VpciDevType::Physical), - pci_dev!(0x0, 0x0, 0xa, 0x0, VpciDevType::Physical), + pci_dev!(0x0, 0x0, 0x0, 0x0 => 0x0, 0x0, 0x0, VpciDevType::Physical), // host bridge + pci_dev!(0x0, 0x0, 0x2, 0x0 => 0x0, 0x2, 0x0, VpciDevType::Physical), // VGA controller + pci_dev!(0x0, 0x0, 0x4, 0x0 => 0x0, 0x4, 0x0, VpciDevType::Physical), + pci_dev!(0x0, 0x0, 0x8, 0x0 => 0x0, 0x8, 0x0, VpciDevType::Physical), + pci_dev!(0x0, 0x0, 0xa, 0x0 => 0x0, 0xa, 0x0, VpciDevType::Physical), // pci_dev!(0x0, 0x0, 0xd, 0x0), // USB controller - pci_dev!(0x0, 0x0, 0x12, 0x0, VpciDevType::Physical), // serial controller - pci_dev!(0x0, 0x0, 0x14, 0x0, VpciDevType::Physical), // USB controller - pci_dev!(0x0, 0x0, 0x14, 0x2, VpciDevType::Physical), // RAM memory - pci_dev!(0x0, 0x0, 0x14, 0x3, VpciDevType::Physical), // network controller - pci_dev!(0x0, 0x0, 0x16, 0x0, VpciDevType::Physical), // communication controller - pci_dev!(0x0, 0x0, 0x1c, 0x0, VpciDevType::Physical), // PCI bridge - pci_dev!(0x0, 0x0, 0x1d, 0x0, VpciDevType::Physical), // PCI bridge - pci_dev!(0x0, 0x0, 0x1f, 0x0, VpciDevType::Physical), // ISA bridge - pci_dev!(0x0, 0x0, 0x1f, 0x3, VpciDevType::Physical), // audio controller - pci_dev!(0x0, 0x0, 0x1f, 0x4, VpciDevType::Physical), // SMBus - pci_dev!(0x0, 0x0, 0x1f, 0x5, VpciDevType::Physical), // serial bus controller - pci_dev!(0x0, 0x1, 0x0, 0x0, VpciDevType::Physical), // ethernet controller - pci_dev!(0x0, 0x2, 0x0, 0x0, VpciDevType::Physical), // memory controller + pci_dev!(0x0, 0x0, 0x12, 0x0 => 0x0, 0x12, 0x0, VpciDevType::Physical), // serial controller + pci_dev!(0x0, 0x0, 0x14, 0x0 => 0x0, 0x14, 0x0, VpciDevType::Physical), // USB controller + pci_dev!(0x0, 0x0, 0x14, 0x2 => 0x0, 0x14, 0x2, VpciDevType::Physical), // RAM memory + pci_dev!(0x0, 0x0, 0x14, 0x3 => 0x0, 0x14, 0x3, VpciDevType::Physical), // network controller + pci_dev!(0x0, 0x0, 0x16, 0x0 => 0x0, 0x16, 0x0, VpciDevType::Physical), // communication controller + pci_dev!(0x0, 0x0, 0x1c, 0x0 => 0x0, 0x1c, 0x0, VpciDevType::Physical), // PCI bridge + pci_dev!(0x0, 0x0, 0x1d, 0x0 => 0x0, 0x1d, 0x0, VpciDevType::Physical), // PCI bridge + pci_dev!(0x0, 0x0, 0x1f, 0x0 => 0x0, 0x1f, 0x0, VpciDevType::Physical), // ISA bridge + pci_dev!(0x0, 0x0, 0x1f, 0x3 => 0x0, 0x1f, 0x3, VpciDevType::Physical), // audio controller + pci_dev!(0x0, 0x0, 0x1f, 0x4 => 0x0, 0x1f, 0x4, VpciDevType::Physical), // SMBus + pci_dev!(0x0, 0x0, 0x1f, 0x5 => 0x0, 0x1f, 0x5, VpciDevType::Physical), // serial bus controller + pci_dev!(0x0, 0x1, 0x0, 0x0 => 0x1, 0x0, 0x0, VpciDevType::Physical), // ethernet controller + pci_dev!(0x0, 0x2, 0x0, 0x0 => 0x2, 0x0, 0x0, VpciDevType::Physical), // memory controller ]; -#[cfg(all(feature = "graphics"))] +#[cfg(all(graphics))] pub const GRAPHICS_FONT: &[u8] = include_bytes!("../../platform/x86_64/qemu/image/font/spleen-6x12.psf"); diff --git a/platform/x86_64/nuc14mnk/cargo/features b/platform/x86_64/nuc14mnk/cargo/features deleted file mode 100644 index 69fb95c99..000000000 --- a/platform/x86_64/nuc14mnk/cargo/features +++ /dev/null @@ -1,6 +0,0 @@ -pci -ecam_pcie -no_pcie_bar_realloc -uart16550a -graphics -split_screen \ No newline at end of file diff --git a/platform/x86_64/nuc14mnk/kconfig/defconfig b/platform/x86_64/nuc14mnk/kconfig/defconfig new file mode 100644 index 000000000..fb35c8fcb --- /dev/null +++ b/platform/x86_64/nuc14mnk/kconfig/defconfig @@ -0,0 +1,7 @@ +CONFIG_ARCH_X86_64=y +CONFIG_GRAPHICS=y +CONFIG_NO_PCIE_BAR_REALLOC=y +CONFIG_PCI=y +CONFIG_PCIE_ECAM=y +CONFIG_SPLIT_SCREEN=y +CONFIG_UART16550A=y diff --git a/platform/x86_64/qemu/board.rs b/platform/x86_64/qemu/board.rs index a0a420b58..b29fe4d8a 100644 --- a/platform/x86_64/qemu/board.rs +++ b/platform/x86_64/qemu/board.rs @@ -54,7 +54,9 @@ const ROOT_ZONE_UEFI_REGION_ID: usize = 0x3; pub const ROOT_ZONE_NAME: &str = "root-linux"; pub const ROOT_ZONE_CMDLINE: &str = - "console=tty0 console=ttyS0 earlycon=efifb earlyprintk=serial nointremap no_timer_check efi=noruntime pci=pcie_scan_all,lastbus=1 root=/dev/vda rw init=/init\0"; +// "BOOT_IMAGE=/boot/aster-kernel-osdk-bin SHELL=/bin/sh LOGNAME=root HOME=/ USER=root PATH=/bin:/benchmark ostd.log_level=info console=ttyS0 console=tty0 -- sh -l"; +// TODO: Asterinas +"console=ttyS0 earlyprintk=serial nointremap no_timer_check efi=noruntime pci=pcie_scan_all,lastbus=1 root=/dev/vda rw init=/init\0"; //"console=ttyS0 earlyprintk=serial rdinit=/init nokaslr nointremap\0"; // noapic // video=vesafb // /lib/systemd/systemd @@ -109,6 +111,8 @@ pub const ROOT_ZONE_MEMORY_REGIONS: [HvConfigMemoryRegion; 10] = [ ]; const ROOT_ZONE_CMDLINE_ADDR: GuestPhysAddr = 0x9000; +// TODO: Asterinas +// const ROOT_ZONE_SETUP_ADDR: GuestPhysAddr = 0xf_f000; const ROOT_ZONE_SETUP_ADDR: GuestPhysAddr = 0xa000; const ROOT_ZONE_VMLINUX_ENTRY_ADDR: GuestPhysAddr = 0x10_0000; const ROOT_ZONE_SCREEN_BASE_ADDR: GuestPhysAddr = 0x7000_0000; @@ -122,8 +126,9 @@ pub const ROOT_ARCH_ZONE_CONFIG: HvArchZoneConfig = HvArchZoneConfig { kernel_entry_gpa: ROOT_ZONE_VMLINUX_ENTRY_ADDR, cmdline_load_gpa: ROOT_ZONE_CMDLINE_ADDR, setup_load_gpa: ROOT_ZONE_SETUP_ADDR, - initrd_load_gpa: 0, // 0x1500_0000, - initrd_size: 0, //0x26_b000, + // TODO: Asterinas + initrd_load_gpa: 0, // 0x1530_0000, + initrd_size: 0, // 0x210_0000, //0x26_b000, rsdp_memory_region_id: ROOT_ZONE_RSDP_REGION_ID, acpi_memory_region_id: ROOT_ZONE_ACPI_REGION_ID, uefi_memory_region_id: ROOT_ZONE_UEFI_REGION_ID, @@ -149,17 +154,19 @@ pub const ROOT_PCI_CONFIG: [HvPciConfig; 1] = [HvPciConfig { }]; pub const ROOT_PCI_MAX_BUS: usize = 1; -pub const ROOT_PCI_DEVS: [HvPciDevConfig; 7] = [ - pci_dev!(0x0, 0x0, 0x0, 0x0, VpciDevType::Physical), // host bridge - pci_dev!(0x0, 0x0, 0x1, 0x0, VpciDevType::Physical), // VGA controller - pci_dev!(0x0, 0x0, 0x2, 0x0, VpciDevType::Physical), // Ethernet controller - pci_dev!(0x0, 0x0, 0x3, 0x0, VpciDevType::Physical), // PCI bridge - pci_dev!(0x0, 0x0, 0x1f, 0x0, VpciDevType::Physical), // ISA bridge - pci_dev!(0x0, 0x0, 0x1f, 0x2, VpciDevType::Physical), // SATA controller - // pci_dev!(0x0, 0x0, 0x1f, 0x3, VpciDevType::Physical), // SMBus - pci_dev!(0x0, 0x1, 0x0, 0x0, VpciDevType::Physical), // SCSI controller +pub const ROOT_PCI_DEVS: [HvPciDevConfig; 8] = [ + pci_dev!(0x0, 0x0, 0x0, 0x0 => 0x0, 0x0, 0x0, VpciDevType::Physical), // host bridge + pci_dev!(0x0, 0x0, 0x1, 0x0 => 0x0, 0x1, 0x0, VpciDevType::Physical), // VGA controller + pci_dev!(0x0, 0x0, 0x2, 0x0 => 0x0, 0x2, 0x0, VpciDevType::Physical), // Ethernet controller + pci_dev!(0x0, 0x0, 0x3, 0x0 => 0x0, 0x3, 0x0, VpciDevType::Physical), // PCI bridge + // Asterinas + pci_dev!(0x0, 0x0, 0x4, 0x0 => 0x0, 0x4, 0x0, VpciDevType::Physical), // PCI bridge + pci_dev!(0x0, 0x0, 0x1f, 0x0 => 0x0, 0x1f, 0x0, VpciDevType::Physical), // ISA bridge + pci_dev!(0x0, 0x0, 0x1f, 0x2 => 0x0, 0x1f, 0x2, VpciDevType::Physical), // SATA controller + // pci_dev!(0x0, 0x0, 0x1f, 0x3 => 0x0, 0x1f, 0x3, VpciDevType::Physical), // SMBus + pci_dev!(0x0, 0x1, 0x0, 0x0 => 0x1, 0x0, 0x0, VpciDevType::Physical), // SCSI controller ]; -#[cfg(all(feature = "graphics"))] +#[cfg(all(graphics))] pub const GRAPHICS_FONT: &[u8] = include_bytes!("../../platform/x86_64/qemu/image/font/spleen-6x12.psf"); diff --git a/platform/x86_64/qemu/cargo/features b/platform/x86_64/qemu/cargo/features deleted file mode 100644 index fc6ef1e68..000000000 --- a/platform/x86_64/qemu/cargo/features +++ /dev/null @@ -1,5 +0,0 @@ -pci -ecam_pcie -no_pcie_bar_realloc -uart16550a -intel_vtd \ No newline at end of file diff --git a/platform/x86_64/qemu/configs/virtio_cfg_asterinas.json b/platform/x86_64/qemu/configs/virtio_cfg_asterinas.json new file mode 100644 index 000000000..34d7ff2ea --- /dev/null +++ b/platform/x86_64/qemu/configs/virtio_cfg_asterinas.json @@ -0,0 +1,45 @@ +{ + "zones": [ + { + "id": 1, + "memory_region": [ + { + "zone0_ipa": "0x40300000", + "zonex_ipa": "0x0", + "size": "0x20000000" + }, + { + "zone0_ipa": "0x100000000", + "zonex_ipa": "0x20000000", + "size": "0x40000000" + } + ], + "devices": [ + { + "type": "console", + "status": "enable", + "addr": "0xFEB00000", + "len": "0x200", + "irq": "16" + }, + { + "type": "net", + "status": "enable", + "addr": "0xFEB00200", + "len": "0x200", + "irq": "17", + "tap": "tap0", + "mac": ["0x00", "0x16", "0x3e", "0x10", "0x10", "0x10"] + }, + { + "type": "blk", + "status": "enable", + "addr": "0xFEB00400", + "len": "0x200", + "irq": "18", + "img": "/zone1_disk.img" + } + ] + } + ] +} diff --git a/platform/x86_64/qemu/configs/zone1-asterinas.json b/platform/x86_64/qemu/configs/zone1-asterinas.json new file mode 100644 index 000000000..4ded57c8c --- /dev/null +++ b/platform/x86_64/qemu/configs/zone1-asterinas.json @@ -0,0 +1,90 @@ +{ + "name": "asterinas", + "zone_id": 1, + "cpus": [2], + "memory_regions": [ + { + "type": "ram", + "physical_start": "0x40300000", + "virtual_start": "0x0", + "size": "0xe0000" + }, + { + "type": "ram", + "physical_start": "0x403e0000", + "virtual_start": "0xe0000", + "size": "0x20000" + }, + { + "type": "ram", + "physical_start": "0x40400000", + "virtual_start": "0x100000", + "size": "0x1fe00000" + }, + { + "type": "ram", + "physical_start": "0x60200000", + "virtual_start": "0x1ff00000", + "size": "0x100000" + }, + { + "type": "ram", + "physical_start": "0x100000000", + "virtual_start": "0x20000000", + "size": "0x40000000" + }, + { + "type": "virtio", + "physical_start": "0xFEB00000", + "virtual_start": "0xFEB00000", + "size": "0x2000" + } + ], + "interrupts": [16, 17, 18], + "ivc_configs": [], + "kernel_filepath": "./aster-kernel-osdk-bin", + "dtb_filepath": "null", + "kernel_load_paddr": "0x8000000", + "dtb_load_paddr": "0x00000000", + "entry_point": "0x8000", + "multiboot_enabled": true, + "multiboot_info_paddr": "0x9000000", + "kernel_cmdline": "console=hvc0 ostd.log_level=error SHELL=/bin/sh LOGNAME=root HOME=/ USER=root PATH=/bin:/benchmark init=/init -- sh -l", + "initramfs_filepath": "./initramfs.cpio.gz", + "initramfs_load_gpa": "0x10000000", + "arch_config": { + "ioapic_base": "0xfec00000", + "ioapic_size": "0x1000", + "boot_filepath": "mb2_boot.bin", + "boot_load_paddr": "0x8000", + "kernel_entry_gpa": "0x8001238", + "cmdline_load_gpa": "0x9020000", + "setup_load_gpa": "0x80000", + "initrd_load_gpa": "0x0", + "initrd_size": "0x0", + "rsdp_memory_region_id": 1, + "acpi_memory_region_id": 3, + "uefi_memory_region_id": 0, + "screen_base": "0x0" + }, + "pci_config": [ + { + "ecam_base": "0xe0000000", + "ecam_size": "0x200000", + "io_base": "0x0", + "io_size": "0x0", + "pci_io_base": "0x0", + "mem32_base": "0x0", + "mem32_size": "0x0", + "pci_mem32_base": "0x0", + "mem64_base": "0x0", + "mem64_size": "0x0", + "pci_mem64_base": "0x0", + "bus_range_begin": "0x0", + "bus_range_end": "0x1f", + "domain": "0x0" + } + ], + "num_pci_devs": 0, + "alloc_pci_devs": [] +} diff --git a/platform/x86_64/qemu/configs/zone1_linux.json b/platform/x86_64/qemu/configs/zone1_linux.json index b5ffd2d82..de122b12c 100644 --- a/platform/x86_64/qemu/configs/zone1_linux.json +++ b/platform/x86_64/qemu/configs/zone1_linux.json @@ -94,7 +94,7 @@ }, "pci_config": [ { - "ecam_base": "0xb0000000", + "ecam_base": "0xe0000000", "ecam_size": "0x200000", "io_base": "0x0", "io_size": "0x0", @@ -117,6 +117,9 @@ "bus": "0x0", "device": "0x0", "function": "0x0", + "v_bus": "0x0", + "v_device": "0x0", + "v_function": "0x0", "dev_type": "0x0" } ] diff --git a/platform/x86_64/qemu/image/iso/boot/grub/grub.cfg b/platform/x86_64/qemu/image/iso/boot/grub/grub.cfg index c2a54ae3b..93796f90c 100644 --- a/platform/x86_64/qemu/image/iso/boot/grub/grub.cfg +++ b/platform/x86_64/qemu/image/iso/boot/grub/grub.cfg @@ -3,13 +3,22 @@ set default=0 # default menu entry index insmod all_video + menuentry "Hvisor" { multiboot2 /boot/hvisor # use multiboot spec to boot module2 /boot/kernel/boot.bin 0 module2 /boot/kernel/boot.bin 5008000 module2 /boot/kernel/setup.bin 500a000 module2 /boot/kernel/vmlinux.bin 5100000 - module2 /boot/kernel/initramfs.cpio.gz 1a000000 + boot +} + +menuentry "Asterinas" { + multiboot2 /boot/hvisor # use multiboot spec to boot + module2 /boot/kernel/boot.bin 0 + module2 /boot/kernel/boot.bin 5008000 + module2 /boot/kernel/aster-kernel-osdk-bin 50ff000 + module2 /boot/kernel/initramfs.cpio.gz 1a300000 boot } diff --git a/platform/x86_64/qemu/image/mb2_bootloader/mb2_boot.S b/platform/x86_64/qemu/image/mb2_bootloader/mb2_boot.S new file mode 100644 index 000000000..eb0cfa2b7 --- /dev/null +++ b/platform/x86_64/qemu/image/mb2_bootloader/mb2_boot.S @@ -0,0 +1,68 @@ +# Multiboot2 bootloader for Asterinas zone1 +# Transitions from 16-bit real mode to 32-bit protected mode, +# sets up GDT with TSS, then jumps to the kernel entry point. +# +# Entry state (from VMCS guest_regs via unrestricted guest): +# EAX = Multiboot2 magic (0x36D76289) +# EBX = Multiboot2 info pointer (GPA) +# ESI = Kernel entry point (GPA) + +.section .text +.code16 +.global mb2_entry16 +mb2_entry16: + cli + cld + + mov ebp, eax # save multiboot magic + mov edi, ebx # save multiboot info pointer + mov ecx, esi # save kernel entry point + + xor ax, ax + mov ds, ax + mov es, ax + mov ss, ax + + lgdt [mb2_gdt_desc] + mov eax, cr0 + or eax, 0x1 + mov cr0, eax + + ljmp 0x08, mb2_entry32 + +.code32 +.global mb2_entry32 +mb2_entry32: + mov ax, 0x10 + mov ds, ax + mov es, ax + mov ss, ax + mov fs, ax + mov gs, ax + + # Load TSS (entry 4 at selector 0x20) + mov ax, 0x20 + ltr ax + + # Restore Multiboot2 parameters + mov eax, ebp + mov ebx, edi + + # Set up stack + mov esp, MB2_STACK + + # Jump to kernel entry + jmp ecx + +.align 16 +mb2_gdt: + .quad 0x0000000000000000 # 0x00: null + .quad 0x00cf9b000000ffff # 0x08: 32-bit code + .quad 0x00cf93000000ffff # 0x10: 32-bit data + .quad 0x0000000000000000 # 0x18: unused + .quad MB2_TSS_DESCRIPTOR # 0x20: 32-bit available TSS +mb2_gdt_end: + +mb2_gdt_desc: + .short mb2_gdt_end - mb2_gdt - 1 + .long mb2_gdt diff --git a/platform/x86_64/qemu/image/mb2_bootloader/mb2_boot.ld b/platform/x86_64/qemu/image/mb2_bootloader/mb2_boot.ld new file mode 100644 index 000000000..dc5e86666 --- /dev/null +++ b/platform/x86_64/qemu/image/mb2_bootloader/mb2_boot.ld @@ -0,0 +1,15 @@ +OUTPUT_ARCH(i386) +BASE_ADDRESS = 0x8000; + +ENTRY(mb2_entry16) +SECTIONS +{ + . = BASE_ADDRESS; + .text : { + *(.text .text.*) + } + + /DISCARD/ : { + *(.eh_frame) *(.eh_frame_hdr) + } +} diff --git a/platform/x86_64/qemu/image/mb2_bootloader/mb2_boot.mk b/platform/x86_64/qemu/image/mb2_bootloader/mb2_boot.mk new file mode 100644 index 000000000..9917a74eb --- /dev/null +++ b/platform/x86_64/qemu/image/mb2_bootloader/mb2_boot.mk @@ -0,0 +1,40 @@ +mb2_boot_dir := $(image_dir)/mb2_bootloader +mb2_boot_out_dir := $(image_dir)/mb2_bootloader/out + +mb2_boot_src := $(mb2_boot_dir)/mb2_boot.S +mb2_boot_lds := $(mb2_boot_dir)/mb2_boot.ld + +mb2_boot_o := $(mb2_boot_out_dir)/mb2_boot.o +mb2_boot_elf := $(mb2_boot_out_dir)/mb2_boot.elf +mb2_boot_bin := $(mb2_boot_out_dir)/mb2_boot.bin + +AS ?= as +LD ?= ld +OBJCOPY ?= objcopy + +# TSS descriptor: base=0x1fffc000, limit=103, type=0x89 (32-bit available TSS) +# Encoded bytes: 67 00 00 c0 ff 89 00 1f +# Stack/TSS live near the top of zone1 low RAM, outside the kernel LOAD range. +# The stack at 0x1fffe000 must not grow more than 8KB into the TSS below. +MB2_TSS_DESC := 0x1F0089FFC0000067 +MB2_STACK := 0x1fffe000 + +mb2_boot_flags := --32 -msyntax=intel -mnaked-reg +mb2_boot_flags += --defsym MB2_STACK=$(MB2_STACK) +mb2_boot_flags += --defsym MB2_TSS_DESCRIPTOR=$(MB2_TSS_DESC) + +mb2_boot: | $(mb2_boot_out_dir) $(mb2_boot_bin) + +$(mb2_boot_out_dir): + mkdir -p $@ + +$(mb2_boot_o): $(mb2_boot_src) + $(AS) $(mb2_boot_flags) $< -o $@ + +$(mb2_boot_elf): $(mb2_boot_o) $(mb2_boot_lds) + $(LD) -T$(mb2_boot_lds) $< -o $@ + +$(mb2_boot_bin): $(mb2_boot_elf) + $(OBJCOPY) $< --strip-all -O binary $@ + +.PHONY: mb2_boot diff --git a/platform/x86_64/qemu/kconfig/defconfig b/platform/x86_64/qemu/kconfig/defconfig new file mode 100644 index 000000000..007ce3484 --- /dev/null +++ b/platform/x86_64/qemu/kconfig/defconfig @@ -0,0 +1,7 @@ +CONFIG_ARCH_X86_64=y +CONFIG_INTEL_VTD=y +CONFIG_IOMMU=y +CONFIG_NO_PCIE_BAR_REALLOC=y +CONFIG_PCI=y +CONFIG_PCIE_ECAM=y +CONFIG_UART16550A=y diff --git a/platform/x86_64/qemu/platform.mk b/platform/x86_64/qemu/platform.mk index fd119bce8..eb9692595 100644 --- a/platform/x86_64/qemu/platform.mk +++ b/platform/x86_64/qemu/platform.mk @@ -1,8 +1,10 @@ QEMU := qemu-system-x86_64 zone0_boot := $(image_dir)/bootloader/out/boot.bin +zone1_mb2_boot := $(image_dir)/mb2_bootloader/out/mb2_boot.bin zone0_setup := $(image_dir)/kernel/setup.bin zone0_vmlinux := $(image_dir)/kernel/vmlinux.bin +zone0_asterinas := $(image_dir)/kernel/aster-kernel-osdk-bin zone0_initrd := $(image_dir)/virtdisk/initramfs.cpio.gz zone0_rootfs := $(image_dir)/virtdisk/rootfs1.img zone1_rootfs := $(image_dir)/virtdisk/rootfs2.img @@ -10,20 +12,29 @@ zone1_rootfs := $(image_dir)/virtdisk/rootfs2.img QEMU_ARGS := -machine q35,kernel-irqchip=split QEMU_ARGS += -cpu host,+x2apic,+invtsc,+vmx -accel kvm QEMU_ARGS += -smp 4 +# TODO: Asterinas QEMU_ARGS += -serial mon:stdio QEMU_ARGS += -m 4G QEMU_ARGS += -bios /usr/share/ovmf/OVMF.fd QEMU_ARGS += -vga std -# QEMU_ARGS += -nographic +QEMU_ARGS += -nographic QEMU_ARGS += -nodefaults QEMU_ARGS += -net nic -net user QEMU_ARGS += -device intel-iommu,intremap=on,eim=on,caching-mode=on,device-iotlb=on,aw-bits=48 QEMU_ARGS += -device ioh3420,id=pcie.1,chassis=1 + +# TODO: Asterinas QEMU_ARGS += -drive if=none,file="$(zone0_rootfs)",id=X10008000,format=raw QEMU_ARGS += -device virtio-blk-pci,bus=pcie.1,drive=X10008000,disable-legacy=on,disable-modern=off,iommu_platform=on,ats=on +# TODO: Asterinas +# QEMU_ARGS += -device virtio-serial +# QEMU_ARGS += -device virtconsole,chardev=mux +# QEMU_ARGS += -serial chardev:mux +# QEMU_ARGS += -chardev stdio,id=mux,mux=on,signal=off + # QEMU_ARGS += -drive if=none,file="$(zone0_rootfs)",id=X10009000,format=raw # QEMU_ARGS += -device nvme,serial=deadbeef,drive=X10009000 # QEMU_ARGS += -drive if=none,file="$(zone1_rootfs)",id=X10009000,format=raw @@ -36,6 +47,8 @@ QEMU_ARGS += -device virtio-blk-pci,bus=pcie.1,drive=X10008000,disable-legacy=on # QEMU_ARGS += -kernel $(hvisor_elf) QEMU_ARGS += -drive file=$(image_dir)/virtdisk/hvisor.iso,format=raw,index=0,media=disk +QEMU_ARGS += -nographic + # QEMU_ARGS += -device loader,file="$(zone0_boot)",addr=0x5008000,force-raw=on # QEMU_ARGS += -device loader,file="$(zone0_setup)",addr=0x500a000,force-raw=on @@ -43,7 +56,7 @@ QEMU_ARGS += -drive file=$(image_dir)/virtdisk/hvisor.iso,format=raw,index=0,med # QEMU_ARGS += -device loader,file="$(zone0_initrd)",addr=0x1a000000,force-raw=on # QEMU_ARGS += -append "initrd_size=$(shell stat -c%s $(zone0_initrd))" -$(hvisor_bin): elf boot +$(hvisor_bin): elf boot mb2_boot $(OBJCOPY) $(hvisor_elf) --strip-all -O binary $@ cp $(hvisor_elf) $(image_dir)/iso/boot mkdir -p $(image_dir)/iso/boot/kernel @@ -66,12 +79,28 @@ $(hvisor_bin): elf boot echo "Warning: $(zone0_vmlinux) not found, skipping"; \ fi + if [ -f $(zone0_asterinas) ]; then \ + cp $(zone0_asterinas) $(image_dir)/iso/boot/kernel; \ + else \ + echo "Warning: $(zone0_asterinas) not found, skipping"; \ + fi + mkdir -p $(image_dir)/virtdisk + if [ -f $(zone0_initrd) ]; then \ + cp $(zone0_initrd) $(image_dir)/iso/boot/kernel; \ + else \ + echo "Warning: $(zone0_initrd) not found, skipping"; \ + fi + if [ -f $(zone1_mb2_boot) ]; then \ + cp $(zone1_mb2_boot) $(image_dir)/iso/boot/kernel; \ + fi + if command -v xorriso >/dev/null 2>&1; then \ grub-mkrescue /usr/lib/grub/x86_64-efi -o $(image_dir)/virtdisk/hvisor.iso $(image_dir)/iso; \ else \ echo "Warning: xorriso not installed, skipping ISO creation"; \ fi -include $(image_dir)/bootloader/boot.mk \ No newline at end of file +include $(image_dir)/bootloader/boot.mk +include $(image_dir)/mb2_bootloader/mb2_boot.mk diff --git a/platform/x86_64/qemu/scripts/boot_zone1.sh b/platform/x86_64/qemu/scripts/boot_zone1.sh new file mode 100644 index 000000000..4e25c216f --- /dev/null +++ b/platform/x86_64/qemu/scripts/boot_zone1.sh @@ -0,0 +1,5 @@ +#!/bin/bash + +insmod hvisor.ko +nohup ./hvisor virtio start virtio_cfg.json & +./hvisor zone start ./zone1_linux.json \ No newline at end of file diff --git a/platform/x86_64/qemu/scripts/boot_zone1_asterinas.sh b/platform/x86_64/qemu/scripts/boot_zone1_asterinas.sh new file mode 100644 index 000000000..21a219f96 --- /dev/null +++ b/platform/x86_64/qemu/scripts/boot_zone1_asterinas.sh @@ -0,0 +1,6 @@ +#!/bin/bash + +insmod hvisor.ko +nohup ./hvisor virtio start virtio_cfg_asterinas.json & +sleep 3 +./hvisor zone start ./zone1-asterinas.json diff --git a/platform/x86_64/qemu/scripts/insmod.sh b/platform/x86_64/qemu/scripts/insmod.sh new file mode 100644 index 000000000..268bb6aa0 --- /dev/null +++ b/platform/x86_64/qemu/scripts/insmod.sh @@ -0,0 +1,3 @@ +#!/bin/bash + +insmod hvisor.ko \ No newline at end of file diff --git a/platform/x86_64/qemu/scripts/setup.sh b/platform/x86_64/qemu/scripts/setup.sh new file mode 100644 index 000000000..05a7907cf --- /dev/null +++ b/platform/x86_64/qemu/scripts/setup.sh @@ -0,0 +1,2 @@ +#!/bin/bash + diff --git a/platform/x86_64/qemu/scripts/start_zone1.sh b/platform/x86_64/qemu/scripts/start_zone1.sh new file mode 100644 index 000000000..88afc8e9b --- /dev/null +++ b/platform/x86_64/qemu/scripts/start_zone1.sh @@ -0,0 +1,3 @@ +#!/bin/bash + +./hvisor zone start ./zone1_linux.json \ No newline at end of file diff --git a/platform/x86_64/qemu/scripts/stop_zone1.sh b/platform/x86_64/qemu/scripts/stop_zone1.sh new file mode 100644 index 000000000..8d4a6d14c --- /dev/null +++ b/platform/x86_64/qemu/scripts/stop_zone1.sh @@ -0,0 +1,3 @@ +#!/bin/bash + +./hvisor zone shutdown -id 1 \ No newline at end of file diff --git a/platform/x86_64/qemu/scripts/virtio_start.sh b/platform/x86_64/qemu/scripts/virtio_start.sh new file mode 100644 index 000000000..302288868 --- /dev/null +++ b/platform/x86_64/qemu/scripts/virtio_start.sh @@ -0,0 +1,3 @@ +#!/bin/bash + +nohup ./hvisor virtio start virtio_cfg.json & \ No newline at end of file diff --git a/src/arch/aarch64/cache.rs b/src/arch/aarch64/cache.rs index 9ec2897c0..0b2e1f459 100644 --- a/src/arch/aarch64/cache.rs +++ b/src/arch/aarch64/cache.rs @@ -15,11 +15,16 @@ // Jingyu Liu // -pub unsafe fn invalidate_dcache_range(start: usize, size: usize, line_size: usize) { +pub unsafe fn invalidate_dcache_range(start: usize, size: usize) { + // Get cache line size from CTR_EL0[16:19] (min line size, in words of 4 bytes) + let ctr_el0: u64; + core::arch::asm!("mrs {0}, ctr_el0", out(reg) ctr_el0, options(nostack, preserves_flags)); + let line_size = (1 << ((ctr_el0 >> 16 & 0xF) as usize)) * 4; + let mut addr = start & !(line_size - 1); let end = start + size; while addr < end { - core::arch::asm!("dc ivac, {0}", in(reg) addr, options(nostack, preserves_flags)); + core::arch::asm!("dc civac, {0}", in(reg) addr, options(nostack, preserves_flags)); addr += line_size; } core::arch::asm!("dsb sy", options(nostack, preserves_flags)); diff --git a/src/arch/aarch64/cpu.rs b/src/arch/aarch64/cpu.rs index 13cbb0deb..8c3a1c81f 100644 --- a/src/arch/aarch64/cpu.rs +++ b/src/arch/aarch64/cpu.rs @@ -16,7 +16,7 @@ use crate::{ arch::{mm::new_s2_memory_set, sysreg::write_sysreg}, consts::{MAX_CPU_NUM, PAGE_SIZE, PER_CPU_ARRAY_PTR, PER_CPU_SIZE}, - cpu_data::this_cpu_data, + cpu_data::{this_cpu_data, VcpuState}, memory::{ addr::PHYS_VIRT_OFFSET, mm::PARKING_MEMORY_SET, GuestPhysAddr, HostPhysAddr, MemFlags, MemoryRegion, VirtAddr, PARKING_INST_PAGE, @@ -70,7 +70,6 @@ impl GeneralRegisters { pub struct ArchCpu { pub cpuid: usize, pub is_aarch32: bool, - pub power_on: bool, } impl ArchCpu { @@ -78,7 +77,6 @@ impl ArchCpu { Self { cpuid, is_aarch32: false, - power_on: false, } } @@ -125,7 +123,9 @@ impl ArchCpu { + HCR_EL2::TSC::EnableTrapEl1SmcToEl2 + HCR_EL2::VM::SET + HCR_EL2::IMO::SET - + HCR_EL2::FMO::SET, + + HCR_EL2::FMO::SET + + HCR_EL2::API::SET + + HCR_EL2::APK::SET, ); } @@ -133,6 +133,7 @@ impl ArchCpu { PER_CPU_ARRAY_PTR as VirtAddr + (self.cpuid + 1) as usize * PER_CPU_SIZE } + #[allow(clippy::mut_from_ref)] fn guest_reg(&self) -> &mut GeneralRegisters { unsafe { &mut *((self.stack_top() - 32 * 8) as *mut GeneralRegisters) } } @@ -198,7 +199,7 @@ impl ArchCpu { // Return to AArch32 Supervisor (SVC) mode, disable IRQ, FIQ, ABT SPSR_EL2.set(0x1D3); } - self.power_on = true; + this_cpu_data().vcpu_state.store(VcpuState::Running); info!( "cpu {} started at {:#x?}", self.cpuid, @@ -214,7 +215,7 @@ impl ArchCpu { assert!(this_cpu_id() == self.cpuid); let cpu_data = this_cpu_data(); let _lock = cpu_data.ctrl_lock.lock(); - self.power_on = false; + cpu_data.vcpu_state.store(VcpuState::Stopped); drop(_lock); // reset current cpu -> pc = 0x0 (wfi) diff --git a/src/arch/aarch64/entry.rs b/src/arch/aarch64/entry.rs index 8b8678f02..12b41b9fe 100644 --- a/src/arch/aarch64/entry.rs +++ b/src/arch/aarch64/entry.rs @@ -14,7 +14,7 @@ // Authors: // use crate::consts::PER_CPU_SIZE; -use crate::platform::BOARD_MPIDR_MAPPINGS; +use crate::platform::{BOARD_EARLY_CACHE_INVALIDATE_MASKS, BOARD_MPIDR_MAPPINGS}; const INVALID_CPUID: usize = (-1) as _; @@ -25,8 +25,9 @@ pub unsafe extern "C" fn arch_entry() -> ! { unsafe { core::arch::asm!( " - // x0 = dtbaddr - mov x18, x0 + // `arch_entry` receives dtbaddr in `x0`. Keep it in `x20` until `rust_main`. + // Note: Only callee-saved registers (x19-x28) are guaranteed to be preserved across function calls. + mov x20, x0 /* Insert nop instruction to ensure byte at offset 10 in hvisor binary is non-zero. * Rockchip U-Boot (arch_preboot_os@arch/arm/mach-rockchip/board.c:670) performs @@ -36,7 +37,8 @@ pub unsafe extern "C" fn arch_entry() -> ! { nop nop - bl {boot_cpuid_get} // x17 = cpuid + // boot_cpuid_get returns the logical cpuid in `x19`. + bl {boot_cpuid_get} adrp x2, __core_end // x2 = &__core_end mov x3, {per_cpu_size} // x3 = per_cpu_size @@ -47,36 +49,65 @@ pub unsafe extern "C" fn arch_entry() -> ! { // disable cache and MMU mrs x1, sctlr_el2 bic x1, x1, #0xf - msr sctlr_el2, x1 + msr sctlr_el2, x1 // SCTLR_EL2 &= ~0xf; + isb + + // clear i-cache and sync + dsb sy + ic iallu + isb + + // flush tlb + tlbi alle2is + + // per-cpu mask bits: bit0->L1(D), bit1->L2, bit2->L3. + adrp x9, {cache_inv_masks} // Get Symbol Table Page Address + add x9, x9, :lo12:{cache_inv_masks} // Get Symbol Table Page Offset + lsl x10, x19, #3 + add x9, x9, x10 + ldr x9, [x9] // cache_invalidate(0): clear dl1$ + tbz x9, #0, 20f mov x0, #0 bl {cache_invalidate} + 20: + // cache_invalidate(2): clear l2$ + tbz x9, #1, 21f + mov x0, #2 + bl {cache_invalidate} + + 21: + // cache_invalidate(4): clear l3$ + tbz x9, #2, 22f + mov x0, #4 + bl {cache_invalidate} + + 22: + // clear i-cache and sync + dsb sy ic iallu + isb + // if cpuid == 0, clear bss and init boot page table. cmp x19, 0 b.ne 1f - // if (cpu_id == 0) cache_invalidate(2): clear l2$ - mov x0, #2 - bl {cache_invalidate} - - // ic iallu - bl {clear_bss} bl {boot_pt_init} 1: bl {mmu_enable} - mov x1, x18 + mov x1, x20 mov x0, x19 - mov x18, #0 + mov x20, #0 mov x19, #0 bl {rust_main} // x0 = cpuid, x1 = dtbaddr ", options(noreturn), boot_cpuid_get = sym boot_cpuid_get, + cache_inv_masks = sym BOARD_EARLY_CACHE_INVALIDATE_MASKS, cache_invalidate = sym cache_invalidate, per_cpu_size = const PER_CPU_SIZE, rust_main = sym crate::rust_main, @@ -94,6 +125,7 @@ pub unsafe extern "C" fn boot_cpuid_get() { core::arch::asm!( " + // Return convention for `arch_entry`: leave the logical cpuid in x19. mrs x19, mpidr_el1 ldr x2, ={mpidr_mask} and x19, x19, x2 @@ -177,6 +209,7 @@ unsafe extern "C" fn cache_invalidate(cache_level: usize) { core::arch::asm!( r#" msr csselr_el1, {0} + isb mrs x4, ccsidr_el1 // read cache size id. and x1, x4, #0x7 add x1, x1, #0x4 // x1 = cache line size. @@ -202,6 +235,7 @@ unsafe extern "C" fn cache_invalidate(cache_level: usize) { add x5, x5, #1 // else, next way. cmp x5, x3 // last way reached yet? ble 1b // if not, iterate way_loop + dsb sy "#, in(reg) cache_level, options(nostack) diff --git a/src/arch/aarch64/hypercall.rs b/src/arch/aarch64/hypercall.rs index d06be7a9e..2b641ab36 100644 --- a/src/arch/aarch64/hypercall.rs +++ b/src/arch/aarch64/hypercall.rs @@ -14,7 +14,6 @@ // Authors: // ForeverYolo <2572131118@qq.com> -use crate::arch::cpu::this_cpu_id; use crate::arch::ivc::{IvcInfo, IVC_INFOS}; use crate::config::CONFIG_MAGIC_VERSION; use crate::cpu_data::this_zone; @@ -24,6 +23,10 @@ use crate::hypercall::HyperCallResult; use crate::zone::this_zone_id; impl<'a> HyperCall<'a> { + pub fn hv_get_ecam_base(&mut self, _ecam_base: *mut u64) -> HyperCallResult { + HyperCallResult::Ok(0) + } + pub fn hv_ivc_info(&mut self, ivc_info_ipa: u64) -> HyperCallResult { let zone_id = this_zone_id(); let zone = this_zone(); @@ -72,11 +75,6 @@ impl<'a> HyperCall<'a> { return list_addr; } - pub fn check_cpu_id(&self) { - let cpuid = this_cpu_id(); - trace!("CPU ID: {} Start Zone", cpuid); - } - pub fn hv_virtio_get_irq(&self, _virtio_irq: *mut u32) -> HyperCallResult { trace!("hv_virtio_get_irq is not need for AArch64"); HyperCallResult::Ok(0) diff --git a/src/arch/aarch64/ipi.rs b/src/arch/aarch64/ipi.rs index 974a30136..1904e61a5 100644 --- a/src/arch/aarch64/ipi.rs +++ b/src/arch/aarch64/ipi.rs @@ -15,10 +15,15 @@ // use crate::device::irqchip::gic_send_event; + pub fn arch_send_event(cpu_id: u64, sgi_num: u64) { gic_send_event(cpu_id, sgi_num); } +pub fn arch_notify_event(cpu_id: u64, sgi_num: u64, _event_id: usize, _queue_was_empty: bool) { + arch_send_event(cpu_id, sgi_num); +} + pub fn arch_check_events(event: Option) { match event { _ => { @@ -29,7 +34,3 @@ pub fn arch_check_events(event: Option) { } } } - -pub fn arch_prepare_send_event(_cpu_id: usize, _ipi_int_id: usize, _event_id: usize) { - debug!("aarch64 arch_prepare_send_event: do nothing now.") -} diff --git a/src/arch/aarch64/mod.rs b/src/arch/aarch64/mod.rs index 78a8b85e2..f3ab85ad0 100644 --- a/src/arch/aarch64/mod.rs +++ b/src/arch/aarch64/mod.rs @@ -28,6 +28,12 @@ pub mod sysreg; pub mod time; pub mod trap; pub mod zone; - pub use s2pt::stage2_mode_detect; pub use s2pt::Stage2PageTable; +#[cfg(aarch64_uefi_support)] +pub mod uefi; + +pub fn arch_config_by_args(_cpuid: usize, _host_dtb: usize) { + #[cfg(aarch64_uefi_support)] + uefi::memory_map_init(_host_dtb); +} diff --git a/src/arch/aarch64/trap.rs b/src/arch/aarch64/trap.rs index 066f28b7f..26eab6d97 100644 --- a/src/arch/aarch64/trap.rs +++ b/src/arch/aarch64/trap.rs @@ -14,6 +14,7 @@ // Authors: // use aarch64_cpu::{asm::wfi, registers::*}; +use bit_field::BitField; use core::arch::global_asm; use super::cpu::GeneralRegisters; @@ -24,7 +25,7 @@ use crate::{ cpu::mpidr_to_cpuid, sysreg::{read_sysreg, write_sysreg}, }, - cpu_data::{get_cpu_data, this_cpu_data, this_zone}, + cpu_data::{get_cpu_data, this_cpu_data, this_zone, VcpuState}, device::irqchip::gic_handle_irq, event::{send_event, IPI_EVENT_SHUTDOWN, IPI_EVENT_WAKEUP}, hypercall::{HyperCall, SGI_IPI_ID}, @@ -212,6 +213,42 @@ fn handle_iabt(_regs: &mut GeneralRegisters) { // arch_skip_instruction(frame); } +/// Returns the start and end of hvisor's physical memory range [hv_start, hv_end). +fn hvisor_mem_range() -> (usize, usize) { + extern "C" { + fn skernel(); + fn __hv_end(); + } + (skernel as usize, __hv_end as usize) +} + +/// Check if `addr` falls within hvisor's own physical memory range. +/// If true, print diagnostic suggesting the guest DTB/config is wrong. +fn check_fault_in_hvisor_mem(fault_addr: usize) -> bool { + let (hv_start, hv_end) = hvisor_mem_range(); + if (hv_start..hv_end).contains(&fault_addr) { + error!( + "FAULT ADDRESS {:#x} is within hvisor's physical memory range [{:#x}, {:#x})", + fault_addr, hv_start, hv_end, + ); + error!( + "LIKELY CAUSE: the guest device tree (DTB) or memory config \ + includes hvisor's physical address range." + ); + error!( + "FIX: ensure the guest's DTB and zone memory_regions exclude \ + the hvisor range [{:#x}, {:#x}).", + hv_start, hv_end, + ); + if is_this_root_zone() { + error!(" For root zone: also check ROOT_ZONE_MEMORY_REGIONS in board.rs."); + } + true + } else { + false + } +} + fn handle_dabt(regs: &mut GeneralRegisters) { let iss = ESR_EL2.read(ESR_EL2::ISS); let is_write = (iss >> 6 & 0x1) != 0; @@ -248,6 +285,7 @@ fn handle_dabt(regs: &mut GeneralRegisters) { } } Err(e) => { + check_fault_in_hvisor_mem(address as usize); error!("mmio_handle_access: {:#x?}", e); zone_error(); } @@ -256,22 +294,64 @@ fn handle_dabt(regs: &mut GeneralRegisters) { arch_skip_instruction(regs); } +#[derive(Debug)] +struct SysRegEncoding { + is_read: bool, // true = MRS, false = MSR + op0: u8, + op1: u8, + crn: u8, + crm: u8, + op2: u8, + rt: u8, +} + +fn decode_sysreg(esr: u64) -> SysRegEncoding { + let iss = esr.get_bits(0..=24); + + SysRegEncoding { + is_read: iss.get_bit(0), + op0: iss.get_bits(20..=21) as u8, + op1: iss.get_bits(14..=16) as u8, + crn: iss.get_bits(10..=13) as u8, + crm: iss.get_bits(1..=4) as u8, + op2: iss.get_bits(17..=19) as u8, + rt: iss.get_bits(5..=9) as u8, + } +} + +fn is_icc_sgi1r_el1(sys: &SysRegEncoding) -> bool { + !sys.is_read && // Must be MSR + sys.op0 == 3 && + sys.op1 == 0 && + sys.crn == 12 && + sys.crm == 11 && + sys.op2 == 5 +} + fn handle_sysreg(regs: &mut GeneralRegisters) { - //TODO check sysreg type //send sgi trace!("esr_el2: iss {:#x?}", ESR_EL2.read(ESR_EL2::ISS)); - let rt = (ESR_EL2.get() >> 5) & 0x1f; - let val = regs.usr[rt as usize]; - trace!("esr_el2 rt{}: {:#x?}", rt, val); - let sgi_id: u64 = (val & (0xf << 24)) >> 24; - if !this_cpu_data().arch_cpu.power_on { - warn!("skip send sgi {:#x?}", sgi_id); + + let esr = ESR_EL2.get(); + let sys = decode_sysreg(esr); + + if is_icc_sgi1r_el1(&sys) { + trace!("handle sgi el1"); + let rt = sys.rt as usize; + let val = if rt == 31 { 0 } else { regs.usr[rt] }; + trace!("esr_el2 rt{}: {:#x?}", rt, val); + let sgi_id: u64 = (val & (0xf << 24)) >> 24; + if !this_cpu_data().vcpu_state.is_running() { + trace!("skip send sgi {:#x?}", sgi_id); + } else { + trace!("send sgi {:#x?}", sgi_id); + write_sysreg!(icc_sgi1r_el1, val); + } + arch_skip_instruction(regs); //skip sgi write } else { - trace!("send sgi {:#x?}", sgi_id); - write_sysreg!(icc_sgi1r_el1, val); + error!("unhandled msr or mrs sys: {:#x?}", sys); + loop {} } - - arch_skip_instruction(regs); //skip sgi write } fn handle_hvc(regs: &mut GeneralRegisters) { @@ -352,9 +432,9 @@ fn psci_emulate_cpu_on(regs: &mut GeneralRegisters) -> u64 { let target_data = get_cpu_data(cpu as _); let _lock = target_data.ctrl_lock.lock(); - if !target_data.arch_cpu.power_on { + if target_data.vcpu_state.is_stopped() { target_data.cpu_on_entry = regs.usr[2] as _; - target_data.arch_cpu.power_on = true; + target_data.vcpu_state.store(VcpuState::Ready); send_event(cpu as _, SGI_IPI_ID as _, IPI_EVENT_WAKEUP); } else { error!("psci: cpu {} already on", cpu); @@ -383,7 +463,7 @@ fn handle_psci_smc( todo!(); } PsciFnId::PSCI_AFFINITY_INFO_32 | PsciFnId::PSCI_AFFINITY_INFO_64 => { - !get_cpu_data(arg0 as _).arch_cpu.power_on as _ + !get_cpu_data(arg0 as _).vcpu_state.is_online() as _ } PsciFnId::PSCI_MIG_INFO_TYPE => PSCI_TOS_NOT_PRESENT_MP, PsciFnId::PSCI_FEATURES => psci_emulate_features_info(regs.usr[1]), diff --git a/src/arch/aarch64/uefi.rs b/src/arch/aarch64/uefi.rs new file mode 100644 index 000000000..1cd9f3a54 --- /dev/null +++ b/src/arch/aarch64/uefi.rs @@ -0,0 +1,320 @@ +// Copyright (c) 2025 Syswonder +// hvisor is licensed under Mulan PSL v2. +// You can use this software according to the terms and conditions of the Mulan PSL v2. +// You may obtain a copy of Mulan PSL v2 at: +// http://license.coscl.org.cn/MulanPSL2 +// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR +// FIT FOR A PARTICULAR PURPOSE. +// See the Mulan PSL v2 for more details. +// +// Syswonder Website: +// https://www.syswonder.org +// +// Authors: +// ForeverYolo <2572131118@qq.com> +#![allow(unused_variables)] +#![allow(dead_code)] +use super::cache::invalidate_dcache_range; +use crate::arch::zone::{Uefi, UefiConfig}; +use crate::config::MEM_TYPE_RAM; +use crate::config::{root_zone_config, HvZoneConfig}; +use alloc::vec::Vec; +use core::cmp::min; +use core::mem::size_of; +use spin::Once; + +const PTR_SIZE: usize = size_of::(); + +const EFI_RESERVED_TYPE: u32 = 0; +const EFI_LOADER_CODE: u32 = 1; +const EFI_LOADER_DATA: u32 = 2; +const EFI_BOOT_SERVICES_CODE: u32 = 3; +const EFI_BOOT_SERVICES_DATA: u32 = 4; +const EFI_RUNTIME_SERVICES_CODE: u32 = 5; +pub const EFI_RUNTIME_SERVICES_DATA: u32 = 6; +const EFI_CONVENTIONAL_MEMORY: u32 = 7; +const EFI_UNUSABLE_MEMORY: u32 = 8; +const EFI_ACPI_RECLAIM_MEMORY: u32 = 9; +const EFI_ACPI_MEMORY_NVS: u32 = 10; +const EFI_MEMORY_MAPPED_IO: u32 = 11; +const EFI_MEMORY_MAPPED_IO_PORT_SPACE: u32 = 12; +const EFI_PAL_CODE: u32 = 13; +const EFI_PERSISTENT_MEMORY: u32 = 14; +const EFI_MAX_MEMORY_TYPE: u32 = 15; +const EFI_PAGE_SIZE: u64 = 4096; + +bitflags::bitflags! { + #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)] + pub struct EfiMemoryAttributes: u64 { + const UC = 0x0000_0000_0000_0001; // Uncached + const WC = 0x0000_0000_0000_0002; // Write-coalescing + const WT = 0x0000_0000_0000_0004; // Write-through + const WB = 0x0000_0000_0000_0008; // Write-back + const UCE = 0x0000_0000_0000_0010; // Uncached, exported + const WP = 0x0000_0000_0000_1000; // Write-protect + const RP = 0x0000_0000_0000_2000; // Read-protect + const XP = 0x0000_0000_0000_4000; // Execute-protect + const NV = 0x0000_0000_0000_8000; // Non-volatile + const MORE_RELIABLE = 0x0000_0000_0001_0000; // Higher reliability + const RO = 0x0000_0000_0002_0000; // Read-only + const RUNTIME = 0x8000_0000_0000_0000; // Range requires runtime mapping + } +} + +const EFI_MEMORY_DESCRIPTOR_VERSION: usize = 1; + +#[repr(C)] +#[derive(Debug, Clone)] +pub struct EfiMemoryDescriptor { + pub memory_type: u32, + pub pad: u32, + pub physical_start: u64, + pub virtual_start: u64, + pub number_of_pages: u64, + pub attribute: u64, +} + +#[repr(C)] +#[derive(Debug, Clone)] +pub struct EfiBootMemMap { + pub map_size: u64, + pub desc_size: u64, + pub desc_ver: u32, + pub key: u64, +} + +pub static UEFI_BOOT_CONFIG: Once = Once::new(); +pub static MEM_MAP: Once> = Once::new(); + +pub fn memory_map_init(config_addr: usize) { + let zone_config = root_zone_config(); + match zone_config.arch_config.uefi_config { + UefiConfig::NoUefi => { + panic!("UEFI support is enabled, but no UEFI parameters are passed") + } + UefiConfig::Uefi(ref uefi_config) => { + info!("memory_map_init: config_addr = {:#x}", config_addr); + UEFI_BOOT_CONFIG.call_once(|| EfiBootMemMap { + map_size: unsafe { **((config_addr + PTR_SIZE) as *const *const u64) }, + desc_size: unsafe { **((config_addr + 2 * PTR_SIZE) as *const *const u64) }, + desc_ver: unsafe { **((config_addr + 3 * PTR_SIZE) as *const *const u32) }, + key: unsafe { **((config_addr + 4 * PTR_SIZE) as *const *const u64) }, + }); + info!("UEFI_BOOT_CONFIG: {:#x?}", UEFI_BOOT_CONFIG.get().unwrap()); + let mut vs = vec![]; + let mut desc_base = unsafe { **(config_addr as *const *const usize) }; + let bound = desc_base + UEFI_BOOT_CONFIG.get().unwrap().map_size as usize; + while desc_base < bound { + let desc = unsafe { &*(desc_base as *const EfiMemoryDescriptor) }; + trace!("desc: {:#x?}", desc); + vs.push(EfiMemoryDescriptor { + memory_type: desc.memory_type, + pad: desc.pad, + physical_start: desc.physical_start, + virtual_start: desc.virtual_start, + number_of_pages: desc.number_of_pages, + attribute: desc.attribute, + }); + desc_base += UEFI_BOOT_CONFIG.get().unwrap().desc_size as usize; + trace!("desc_base : {:#x}", desc_base); + } + // if ROOT_ZONE_UEFI_SYS_TABLE_ADDR != 0 { + // vs.push(EfiMemoryDescriptor{ + // memory_type: EFI_RUNTIME_SERVICES_DATA, + // pad: 0, + // physical_start: ROOT_ZONE_UEFI_SYS_TABLE_ADDR, + // virtual_start: 0, + // number_of_pages: 1, + // attribute: (EfiMemoryAttributes::UC | + // EfiMemoryAttributes::WC | + // EfiMemoryAttributes::WT | + // EfiMemoryAttributes::WB | + // EfiMemoryAttributes::RUNTIME).bits() + // }); + // } + vs.sort_by_key(|t| t.physical_start); + MEM_MAP.call_once(|| vs); + trace!("MEM_MAP: {:#x?}", MEM_MAP.get().unwrap()); + create_fake_memory_map(zone_config, uefi_config); + } + } +} + +pub fn create_fake_memory_map(hv_zone_config: &HvZoneConfig, uefi_config: &Uefi) { + // First, place the entries other than EFI_CONVENTIONAL_MEMORY. + let mut fake_map_base = uefi_config.memory_map_addr as usize; + let mut real_size = 0; + let memory_attrs = (EfiMemoryAttributes::UC + | EfiMemoryAttributes::WC + | EfiMemoryAttributes::WT + | EfiMemoryAttributes::WB) + .bits(); + for desc in MEM_MAP.get().unwrap().iter() { + if desc.attribute & EfiMemoryAttributes::RUNTIME.bits() != 0 { + unsafe { + let p = fake_map_base as *mut EfiMemoryDescriptor; + *p = desc.clone(); + info!("fake desc: {:#x?}", *p); + } + fake_map_base += UEFI_BOOT_CONFIG.get().unwrap().desc_size as usize; + real_size += UEFI_BOOT_CONFIG.get().unwrap().desc_size as usize; + trace!("fake_map_base : {:#x}", fake_map_base); + } + } + trace!("real_size : {:#x}", real_size); + // Then, fill the gaps with EFI_CONVENTIONAL_MEMORY. + for region in hv_zone_config.memory_regions().iter() { + if region.mem_type == MEM_TYPE_RAM { + let mut base_addr = region.physical_start; + let bound_addr = region.physical_start + region.size; + let (mut index, overlap_type) = get_first_overlap_desc(base_addr as usize); + trace!( + "region: {:#x?}, index: {}, overlap_type: {}", + region, + index, + overlap_type + ); + if overlap_type == NO_OVERLAP { + fake_map_base = add_new_desc( + fake_map_base, + EFI_CONVENTIONAL_MEMORY, + region.physical_start, + 0, + region.size, + memory_attrs, + ); + real_size += UEFI_BOOT_CONFIG.get().unwrap().desc_size as usize; + trace!("fake_map_base : {:#x}", fake_map_base); + } else { + if overlap_type == LEFT_OVERLAP { + base_addr = MEM_MAP.get().unwrap()[index].physical_start + + (MEM_MAP.get().unwrap()[index].number_of_pages * EFI_PAGE_SIZE); + index += 1; + } + let map_size = MEM_MAP.get().unwrap().len(); + while index < map_size { + if MEM_MAP.get().unwrap()[index].attribute & EfiMemoryAttributes::RUNTIME.bits() + == 0 + { + index += 1; + continue; + } + let desc_start = MEM_MAP.get().unwrap()[index].physical_start as usize; + let desc_end = desc_start + + (MEM_MAP.get().unwrap()[index].number_of_pages * EFI_PAGE_SIZE) as usize; + info!( + "desc_start: {:#x}, bound_addr: {:#x}, base_addr: {:#x}", + desc_start, bound_addr, base_addr + ); + let new_memory_size = min(desc_start, bound_addr as usize) - base_addr as usize; + if new_memory_size % EFI_PAGE_SIZE as usize != 0 { + panic!("memory is not aligned to EFI_PAGE_SIZE"); + } + if new_memory_size != 0 { + fake_map_base = add_new_desc( + fake_map_base, + EFI_CONVENTIONAL_MEMORY, + base_addr, + 0, + new_memory_size as u64, + memory_attrs, + ); + real_size += UEFI_BOOT_CONFIG.get().unwrap().desc_size as usize; + trace!("fake_map_base : {:#x}", fake_map_base); + } + index += 1; + base_addr = desc_end as u64; + if base_addr >= bound_addr { + trace!( + "break at index: {}, base_addr: {:#x}, bound_addr: {:#x}", + index, + base_addr, + bound_addr + ); + break; + } + } + } + if base_addr < bound_addr { + let new_memory_size = bound_addr as usize - base_addr as usize; + if new_memory_size % EFI_PAGE_SIZE as usize != 0 { + panic!("memory is not aligned to EFI_PAGE_SIZE"); + } + fake_map_base = add_new_desc( + fake_map_base, + EFI_CONVENTIONAL_MEMORY, + base_addr, + 0, + new_memory_size as u64, + memory_attrs, + ); + real_size += UEFI_BOOT_CONFIG.get().unwrap().desc_size as usize; + trace!("fake_map_base : {:#x}", fake_map_base); + } + } + } + info!("final real_size : {:#x}", real_size); + let memory_map_size = uefi_config.memory_map_size as usize; + if real_size < memory_map_size { + // fill zero + unsafe { + let p = fake_map_base as *mut u8; + core::ptr::write_bytes(p, 0, memory_map_size - real_size); + } + } + // We need to write this table to memory, in order to let linux see. + unsafe { + invalidate_dcache_range(uefi_config.memory_map_addr as usize, real_size); + } + info!("Fake memory map write back done"); +} + +// case 1: +// |___________| +// what we need to find -> |________| LEFT_OVERLAP + +// case 2: +// |____________| +// what we need to find -> |________| RIGHT_OVERLAP +const LEFT_OVERLAP: usize = 0; +const RIGHT_OVERLAP: usize = 1; +const NO_OVERLAP: usize = 2; +pub fn get_first_overlap_desc(start_addr: usize) -> (usize, usize) { + for (i, desc) in MEM_MAP.get().unwrap().iter().enumerate() { + if desc.attribute & EfiMemoryAttributes::RUNTIME.bits() != 0 { + let desc_start = desc.physical_start as usize; + let desc_end = desc_start + (desc.number_of_pages * EFI_PAGE_SIZE) as usize; + if desc_start > start_addr { + return (i, RIGHT_OVERLAP); + } else if desc_end > start_addr { + return (i, LEFT_OVERLAP); + } + } + } + (usize::MAX, NO_OVERLAP) +} + +pub fn add_new_desc( + addr: usize, + memory_type: u32, + physical_start: u64, + virtual_start: u64, + size: u64, + attribute: u64, +) -> usize { + let desc = EfiMemoryDescriptor { + memory_type, + pad: 0, + physical_start, + virtual_start, + number_of_pages: size / EFI_PAGE_SIZE, + attribute, + }; + unsafe { + let p = addr as *mut EfiMemoryDescriptor; + *p = desc; + info!("new desc: {:#x?}", *p); + }; + addr + UEFI_BOOT_CONFIG.get().unwrap().desc_size as usize +} diff --git a/src/arch/aarch64/zone.rs b/src/arch/aarch64/zone.rs index 15883ba84..e1ef2bf16 100644 --- a/src/arch/aarch64/zone.rs +++ b/src/arch/aarch64/zone.rs @@ -142,10 +142,6 @@ impl Zone { // the cores within the inner-shareable domain will // be affected by the broadcast invalidation. unsafe { - // Get cache line size from CTR_EL0[16:19] (min line size, in words of 4 bytes) - let ctr_el0: u64; - core::arch::asm!("mrs {0}, ctr_el0", out(reg) ctr_el0, options(nostack, preserves_flags)); - let dcache_line_size = (1 << ((ctr_el0 >> 16 & 0xF) as usize)) * 4; let inner = self.read(); inner.gpm().for_each_region(|region| { // Invalidate all RAM regions of the guest @@ -156,7 +152,7 @@ impl Zone { let hva_start = phys_to_virt(phys_start); info!("Invalidate Guest related cache, region.start: {:#x}, region.size: {:#x}, phys_start: {:#x}, hva_start: {:#x}", region.start, region.size, phys_start, hva_start); // D-cache invalid operation will broadcast to all cores, just do it once. There is no need to do it on each core. - invalidate_dcache_range(hva_start, region.size, dcache_line_size); + invalidate_dcache_range(hva_start, region.size); } }); } @@ -169,6 +165,24 @@ impl Zone { pub struct HvArchZoneConfig { pub is_aarch32: u8, pub gic_config: GicConfig, + pub uefi_config: UefiConfig, +} + +#[repr(C, usize)] +#[derive(Debug, Clone)] +#[allow(unused)] +pub enum UefiConfig { + Uefi(Uefi), + NoUefi, +} + +#[repr(C)] +#[derive(Clone, Debug)] +#[allow(unused)] +pub struct Uefi { + pub memory_map_addr: u64, + pub memory_map_size: u64, + pub sys_map_addr: u64, } #[repr(C, usize)] diff --git a/src/arch/loongarch64/cpu.rs b/src/arch/loongarch64/cpu.rs index 9c035d7fe..7281572ac 100644 --- a/src/arch/loongarch64/cpu.rs +++ b/src/arch/loongarch64/cpu.rs @@ -17,18 +17,16 @@ use super::ipi::*; use super::zone::ZoneContext; use crate::arch::zone::disable_hwi_through; -use crate::cpu_data::this_cpu_data; -use crate::device::common::MMIODerefWrapper; +use crate::cpu_data::{this_cpu_data, VcpuState}; use crate::zone::find_zone; use core::arch::asm; use core::fmt::{self, Debug, Formatter}; use loongArch64::register::crmd::Crmd; use loongArch64::register::pgdl; use loongArch64::register::{cpuid, crmd}; -use tock_registers::interfaces::Writeable; use crate::{ - consts::{PER_CPU_ARRAY_PTR, PER_CPU_SIZE}, + consts::{MAX_CPU_NUM, PER_CPU_ARRAY_PTR, PER_CPU_SIZE}, memory::VirtAddr, }; @@ -38,7 +36,6 @@ pub struct ArchCpu { pub ctx: ZoneContext, pub stack_top: usize, pub cpuid: usize, - pub power_on: bool, pub init: bool, } @@ -48,7 +45,6 @@ impl ArchCpu { ctx: super::trap::dump_reset_gcsrs(), stack_top: 0, cpuid, - power_on: false, init: false, }; return ret; @@ -66,7 +62,7 @@ impl ArchCpu { pub fn run(&mut self) -> ! { assert!(this_cpu_id() == self.get_cpuid()); this_cpu_data().activate_gpm(); - self.power_on = true; + this_cpu_data().vcpu_state.store(VcpuState::Running); if !self.init { self.init(this_cpu_data().cpu_on_entry, this_cpu_data().id, 0); self.init = true; @@ -75,15 +71,18 @@ impl ArchCpu { for i in 0..32 { self.ctx.x[i] = 0; } - // set all zone's GCSR.CPUID to 0 beacuse linux running on it will believe it's CPU0 - // - wheatfox 2025.5.20 - self.ctx.gcsr_cpuid = 0; + let physical_cpu = this_cpu_data().id; + self.ctx.gcsr_cpuid = this_cpu_data() + .zone + .as_ref() + .and_then(|zone| zone.read().phys_to_guest_cpu(physical_cpu)) + .unwrap_or(0); info!( "[[CPU virtualization]] CPU{} run@{:#x}", self.get_cpuid(), self.ctx.sepc ); - info!("loongarch64: @{:#x?}", self); + debug!("loongarch64: @{:#x?}", self); // step 1: enable guest mode // step 2: set guest entry to era // step 3: run ertn and enter guest mode @@ -118,8 +117,6 @@ impl ArchCpu { } super::trap::_vcpu_return(ctx_addr as usize); - - panic!("loongarch64: ArchCpu::run: unreachable"); } pub fn idle(&mut self) -> ! { let ctx_addr = &mut self.ctx as *mut ZoneContext; @@ -134,8 +131,12 @@ impl ArchCpu { ); } info!("loongarch64: ArchCpu::idle: cpuid={}", self.get_cpuid()); + this_cpu_data().vcpu_state.store(VcpuState::Stopped); // enable ipi on ecfg ecfg_ipi_enable(); + // The trap vector is installed with interrupts disabled. Enable them only + // after this CPU has valid trap context and stack pointers in SAVE3/SAVE4. + super::trap::enable_global_interrupt(); loop {} } } @@ -145,19 +146,15 @@ pub fn this_cpu_id() -> usize { } pub fn cpu_start(cpuid: usize, start_addr: usize, opaque: usize) { + if cpuid >= MAX_CPU_NUM { + error!("loongarch64: cpu_start: invalid cpuid={}", cpuid); + return; + } + + let _ = opaque; let start_addr = start_addr & 0x0000_ffff_ffff_ffff; - let ipi: &MMIODerefWrapper = match cpuid { - 1 => &CORE1_IPI, - 2 => &CORE2_IPI, - 3 => &CORE3_IPI, - _ => { - panic!("loongarch64: cpu_start: invalid cpuid={}", cpuid); - } - }; - ipi.ipi_enable.write(IpiEnable::IPIENABLE.val(0xffffffff)); - let entry_addr = start_addr; - mail_send(entry_addr, cpuid, 0); - ipi_write_action(cpuid, SMP_BOOT_CPU); + mail_send_percore(start_addr, cpuid, 0); + ipi_write_action_percore(cpuid, SMP_BOOT_CPU); } pub fn store_cpu_pointer_to_reg(pointer: usize) { diff --git a/src/arch/loongarch64/hypercall.rs b/src/arch/loongarch64/hypercall.rs index 6b56282f4..ad3ae2530 100644 --- a/src/arch/loongarch64/hypercall.rs +++ b/src/arch/loongarch64/hypercall.rs @@ -14,23 +14,18 @@ // Authors: // ForeverYolo <2572131118@qq.com> -use crate::arch::cpu::this_cpu_id; use crate::config::HvZoneConfig; use crate::config::CONFIG_MAGIC_VERSION; -use crate::device::virtio_trampoline::MAX_DEVS; use crate::hypercall::HyperCall; use crate::hypercall::HyperCallResult; impl<'a> HyperCall<'a> { - pub fn hv_ivc_info(&mut self, ivc_info_ipa: u64) -> HyperCallResult { - warn!("hv_ivc_info is not implemented for LoongArch64"); + pub fn hv_get_ecam_base(&mut self, _ecam_base: *mut u64) -> HyperCallResult { HyperCallResult::Ok(0) } - pub fn wait_for_interrupt(&mut self, irq_list: &mut [u64; MAX_DEVS + 1]) { - use crate::device::irqchip::ls7a2000::*; - let status = GLOBAL_IRQ_INJECT_STATUS.lock(); - drop(status); - irq_list[0] = 0; // CAUTION: this is a workaround for loongarch64 + pub fn hv_ivc_info(&mut self, ivc_info_ipa: u64) -> HyperCallResult { + warn!("hv_ivc_info is not implemented for LoongArch64"); + HyperCallResult::Ok(0) } pub fn hv_zone_config_check(&self, magic_version: *mut u64) -> HyperCallResult { @@ -58,11 +53,6 @@ impl<'a> HyperCall<'a> { return list_addr; } - pub fn check_cpu_id(&self) { - let cpuid = this_cpu_id(); - assert_eq!(cpuid, 0); - } - pub fn hv_virtio_get_irq(&self, virtio_irq: *mut u32) -> HyperCallResult { trace!("hv_virtio_get_irq is not need for LoongArch64"); HyperCallResult::Ok(0) diff --git a/src/arch/loongarch64/ipi.rs b/src/arch/loongarch64/ipi.rs index 1e1f0cfdb..54dab3653 100644 --- a/src/arch/loongarch64/ipi.rs +++ b/src/arch/loongarch64/ipi.rs @@ -15,81 +15,61 @@ // Yulong Han // use crate::arch::cpu::this_cpu_id; -use crate::consts::IPI_EVENT_CLEAR_INJECT_IRQ; -use crate::device::common::MMIODerefWrapper; +use crate::consts::{IPI_EVENT_CLEAR_INJECT_IRQ, IPI_EVENT_SEND_IPI}; use core::arch::asm; use core::ptr::write_volatile; -use loongArch64::cpu; use loongArch64::register::ecfg::LineBasedInterrupt; use loongArch64::register::*; -use loongArch64::time; -use tock_registers::fields::FieldValue; -use tock_registers::interfaces::{ReadWriteable, Readable, Writeable}; -use tock_registers::register_bitfields; -use tock_registers::register_structs; -use tock_registers::registers::{ReadOnly, ReadWrite, WriteOnly}; pub fn arch_send_event(cpu_id: u64, sgi_num: u64) { debug!( "loongarch64: arch_send_event: sending event to cpu: {}, sgi_num: {}", cpu_id, sgi_num ); - // just call ipi_write_action - ipi_write_action(cpu_id as usize, sgi_num as usize); + // Route hvisor event doorbells through the IOCSR sender, whose payload + // carries the target CPU ID instead of indexing the fixed legacy table. + ipi_write_action_percore(cpu_id as usize, sgi_num as usize); } -register_bitfields! [ - u32, - pub IpiStatus [ IPISTATUS OFFSET(0) NUMBITS(32) ], - pub IpiEnable [ IPIENABLE OFFSET(0) NUMBITS(32) ], - pub IpiSet [ IPISET OFFSET(0) NUMBITS(32) ], - pub IpiClear [ IPICLEAR OFFSET(0) NUMBITS(32) ], -]; - -register_bitfields! [ - u64, - pub Mailbox0 [ MAILBOX0 OFFSET(0) NUMBITS(64) ], - pub Mailbox1 [ MAILBOX1 OFFSET(0) NUMBITS(64) ], - pub Mailbox2 [ MAILBOX2 OFFSET(0) NUMBITS(64) ], - pub Mailbox3 [ MAILBOX3 OFFSET(0) NUMBITS(64) ], -]; - -register_structs! { - #[allow(non_snake_case)] - pub IpiRegisters { - (0x00 => pub ipi_status: ReadOnly), - (0x04 => pub ipi_enable: ReadWrite), - (0x08 => pub ipi_set: WriteOnly), - (0x0c => pub ipi_clear: WriteOnly), - (0x10 => _reserved0: [u8; 0x10]), - (0x20 => pub mailbox0: ReadWrite), - (0x28 => pub mailbox1: ReadWrite), - (0x30 => pub mailbox2: ReadWrite), - (0x38 => pub mailbox3: ReadWrite), - (0x40 => @END), - } +pub fn arch_notify_event(cpu_id: u64, sgi_num: u64, event_id: usize, queue_was_empty: bool) { + debug!( + "loongarch64: notify event: cpu={}, ipi={}, event={}, queue_was_empty={}", + cpu_id, sgi_num, event_id, queue_was_empty + ); + if queue_was_empty { + arch_send_event(cpu_id, sgi_num); + } } const MMIO_BASE: usize = 0x8000_0000_1fe0_0000; -const IPI_MMIO_BASE: usize = MMIO_BASE; -const IPI_ANY_SEND_BASE: usize = MMIO_BASE + 0x1158; +const IOCSR_IPI_STATUS: usize = 0x1000; +const IOCSR_IPI_ENABLE: usize = 0x1004; +const IOCSR_IPI_CLEAR: usize = 0x100c; -// IPI registers, use this if you don't want to use the percore-IPI feature -pub static CORE0_IPI: MMIODerefWrapper = - unsafe { MMIODerefWrapper::new(IPI_MMIO_BASE + 0x1000) }; -pub static CORE1_IPI: MMIODerefWrapper = - unsafe { MMIODerefWrapper::new(IPI_MMIO_BASE + 0x1100) }; -pub static CORE2_IPI: MMIODerefWrapper = - unsafe { MMIODerefWrapper::new(IPI_MMIO_BASE + 0x1200) }; -pub static CORE3_IPI: MMIODerefWrapper = - unsafe { MMIODerefWrapper::new(IPI_MMIO_BASE + 0x1300) }; +#[inline] +fn iocsr_read32(reg: usize) -> u32 { + let value: usize; + unsafe { + asm!("iocsrrd.w {}, {}", out(reg) value, in(reg) reg); + } + value as u32 +} + +#[inline] +fn iocsr_write32(value: u32, reg: usize) { + unsafe { + asm!("iocsrwr.w {}, {}", in(reg) value as usize, in(reg) reg); + } +} // ipi actions pub const SMP_BOOT_CPU: usize = 0x1; pub const SMP_RESCHEDULE: usize = 0x2; pub const SMP_CALL_FUNCTION: usize = 0x4; // customized actions :), since there is no docs on this yet -pub const HVISOR_START_VCPU: usize = 0x8; +/// Dedicated physical IPI bit used only as the hvisor event-queue doorbell. +/// Linux SMP actions use bits 0..=2, so sharing those bits can drop guest IPI work. +pub const HVISOR_EVENT_DOORBELL: usize = 0x8; fn iocsr_mbuf_send_box_lo(a: usize) -> usize { a << 1 @@ -182,115 +162,32 @@ pub fn ipi_write_action_percore(cpu_id: usize, _action: usize) { ); } -pub fn ipi_write_action(cpu_id: usize, _action: usize) { - // just write _action directly to the target cpu legacy IPI registers - // which is the IPI_SET register - debug!( - "ipi_write_action_legacy: sending action: {:#x} to cpu: {}", - _action, cpu_id - ); - let ipi: &MMIODerefWrapper = match cpu_id { - 0 => &CORE0_IPI, - 1 => &CORE1_IPI, - 2 => &CORE2_IPI, - 3 => &CORE3_IPI, - _ => { - error!("ipi_write_action_legacy: invalid cpu_id: {}", cpu_id); - return; - } - }; - ipi.ipi_set.write(IpiSet::IPISET.val(_action as u32)); - debug!( - "ipi_write_action_legacy: finished sending action: {:#x} to cpu: {}", - _action, cpu_id - ); +pub fn enable_ipi() { + iocsr_write32(u32::MAX, IOCSR_IPI_ENABLE); + debug!("enable_ipi: IPI enabled for cpu {}", this_cpu_id()); } -pub fn mail_send(data: usize, cpu_id: usize, mailbox_id: usize) { - // just write data to the target cpu mailbox registers - // which is the mailbox0 register +pub fn clear_all_ipi() { + iocsr_write32(u32::MAX, IOCSR_IPI_CLEAR); debug!( - "mail_send: sending data: {:#x} to cpu: {}, mailbox_id: {}", - data, cpu_id, mailbox_id - ); - let ipi: &MMIODerefWrapper = match cpu_id { - 0 => &CORE0_IPI, - 1 => &CORE1_IPI, - 2 => &CORE2_IPI, - 3 => &CORE3_IPI, - _ => { - error!("mail_send: invalid cpu_id: {}", cpu_id); - return; - } - }; - match mailbox_id { - 0 => ipi.mailbox0.write(Mailbox0::MAILBOX0.val(data as u64)), - 1 => ipi.mailbox1.write(Mailbox1::MAILBOX1.val(data as u64)), - 2 => ipi.mailbox2.write(Mailbox2::MAILBOX2.val(data as u64)), - 3 => ipi.mailbox3.write(Mailbox3::MAILBOX3.val(data as u64)), - _ => { - error!("mail_send: invalid mailbox_id: {}", mailbox_id); - return; - } - } - debug!( - "mail_send: finished sending data: {:#x} to cpu: {}, mailbox_id: {}", - data, cpu_id, mailbox_id + "clear_all_ipi: IPI status for cpu {}: {:#x}", + this_cpu_id(), + iocsr_read32(IOCSR_IPI_STATUS) ); } -pub fn enable_ipi(cpu_id: usize) { - let ipi: &MMIODerefWrapper = match cpu_id { - 0 => &CORE0_IPI, - 1 => &CORE1_IPI, - 2 => &CORE2_IPI, - 3 => &CORE3_IPI, - _ => { - error!("enable_ipi: invalid cpu_id: {}", cpu_id); - return; - } - }; - ipi.ipi_enable.write(IpiEnable::IPIENABLE.val(0xffffffff)); - debug!("enable_ipi: IPI enabled for cpu {}", cpu_id); +pub fn clear_ipi_bits(mask: u32) { + iocsr_write32(mask, IOCSR_IPI_CLEAR); } -pub fn clear_all_ipi(cpu_id: usize) { - let ipi: &MMIODerefWrapper = match cpu_id { - 0 => &CORE0_IPI, - 1 => &CORE1_IPI, - 2 => &CORE2_IPI, - 3 => &CORE3_IPI, - _ => { - error!("clear_all_ipi: invalid cpu_id: {}", cpu_id); - return; - } - }; - ipi.ipi_clear.write(IpiClear::IPICLEAR.val(0xffffffff)); - debug!( - "clear_all_ipi: IPI status for cpu {}: {:#x}", - cpu_id, - ipi.ipi_status.read(IpiStatus::IPISTATUS) - ); -} - -pub fn reset_ipi(cpu_id: usize) { +pub fn reset_ipi() { // clear all IPIs and enable all IPIs - clear_all_ipi(cpu_id); - enable_ipi(cpu_id); + clear_all_ipi(); + enable_ipi(); } -pub fn get_ipi_status(cpu_id: usize) -> u32 { - let ipi: &MMIODerefWrapper = match cpu_id { - 0 => &CORE0_IPI, - 1 => &CORE1_IPI, - 2 => &CORE2_IPI, - 3 => &CORE3_IPI, - _ => { - error!("get_ipi_status: invalid cpu_id: {}", cpu_id); - return 0; - } - }; - ipi.ipi_status.read(IpiStatus::IPISTATUS) +pub fn get_ipi_status() -> u32 { + iocsr_read32(IOCSR_IPI_STATUS) } pub fn ecfg_ipi_enable() { @@ -315,53 +212,16 @@ pub fn ecfg_ipi_disable() { ); } -pub fn dump_ipi_registers() { - info!( - "dump_ipi_registers: dumping IPI registers for this cpu {}", - this_cpu_id() - ); - let ipi: &MMIODerefWrapper = match this_cpu_id() { - 0 => &CORE0_IPI, - 1 => &CORE1_IPI, - 2 => &CORE2_IPI, - 3 => &CORE3_IPI, - _ => { - error!("dump_ipi_registers: invalid cpu_id: {}", this_cpu_id()); - return; - } - }; - println!( - "ipi_status: {:#x}, ipi_enable: {:#x}", - ipi.ipi_status.read(IpiStatus::IPISTATUS), - ipi.ipi_enable.read(IpiEnable::IPIENABLE), - ); - println!( - "mailbox0: {:#x}, mailbox1: {:#x}, mailbox2: {:#x}, mailbox3: {:#x}", - ipi.mailbox0.read(Mailbox0::MAILBOX0), - ipi.mailbox1.read(Mailbox1::MAILBOX1), - ipi.mailbox2.read(Mailbox2::MAILBOX2), - ipi.mailbox3.read(Mailbox3::MAILBOX3) - ); -} - pub fn arch_check_events(event: Option) { match event { Some(IPI_EVENT_CLEAR_INJECT_IRQ) => { - // clear the injected IPI interrupt - use crate::device::irqchip::ls7a2000::clear_hwi_injected_irq; - clear_hwi_injected_irq(); + warn!("legacy CLEAR_INJECT_IRQ event ignored; use the per-IRQ line API"); + } + Some(IPI_EVENT_SEND_IPI) => { + crate::arch::zone::sync_virtual_ipi_line(); } _ => { panic!("arch_check_events: unhandled event: {:?}", event); } } } - -pub fn arch_prepare_send_event(cpu_id: usize, ipi_int_id: usize, event_id: usize) { - use crate::event::fetch_event; - while !fetch_event(cpu_id).is_none() {} - debug!( - "loongarch64:: send_event: cpu_id: {}, ipi_int_id: {}, event_id: {}", - cpu_id, ipi_int_id, event_id - ); -} diff --git a/src/arch/loongarch64/mod.rs b/src/arch/loongarch64/mod.rs index d592cd94c..26f045ade 100644 --- a/src/arch/loongarch64/mod.rs +++ b/src/arch/loongarch64/mod.rs @@ -34,3 +34,7 @@ pub mod zone; pub use s1pt::Stage1PageTable; pub use s2pt::stage2_mode_detect; pub use s2pt::Stage2PageTable; + +pub fn arch_config_by_args(_cpuid: usize, _host_dtb: usize) { + // Do nothing now. +} diff --git a/src/arch/loongarch64/register/gintc.rs b/src/arch/loongarch64/register/gintc.rs index 26e3ece2c..3cf968d49 100644 --- a/src/arch/loongarch64/register/gintc.rs +++ b/src/arch/loongarch64/register/gintc.rs @@ -20,25 +20,49 @@ impl_define_csr!(Gintc, "GINTC"); impl_read_csr!(0x52, Gintc); impl Gintc { - pub fn hwis(&self) -> usize { + pub fn vip(&self) -> usize { self.bits.get_bits(0..=7) } - pub fn hwip(&self) -> usize { + pub fn pip(&self) -> usize { self.bits.get_bits(8..=15) } - pub fn hwic(&self) -> usize { + pub fn hc(&self) -> usize { self.bits.get_bits(16..=23) } + + pub fn hwis(&self) -> usize { + self.vip() + } + + pub fn hwip(&self) -> usize { + self.pip() + } + + pub fn hwic(&self) -> usize { + self.hc() + } +} + +pub fn write_vip(vip: usize) { + set_csr_loong_bits!(0x52, 0..=7, vip); +} + +pub fn write_pip(pip: usize) { + set_csr_loong_bits!(0x52, 8..=15, pip); +} + +pub fn write_hc(hc: usize) { + set_csr_loong_bits!(0x52, 16..=23, hc); } pub fn set_hwis(hwis: usize) { - set_csr_loong_bits!(0x52, 0..=7, hwis); + write_vip(hwis); } pub fn set_hwip(hwip: usize) { - set_csr_loong_bits!(0x52, 8..=15, hwip); + write_pip(hwip); } pub fn set_hwic(hwic: usize) { - set_csr_loong_bits!(0x52, 16..=23, hwic); + write_hc(hwic); } diff --git a/src/arch/loongarch64/trap.rs b/src/arch/loongarch64/trap.rs index e6f8b25b8..5087c8faf 100644 --- a/src/arch/loongarch64/trap.rs +++ b/src/arch/loongarch64/trap.rs @@ -19,11 +19,11 @@ use super::register::*; use super::zone::ZoneContext; use crate::arch::cpu::this_cpu_id; use crate::arch::ipi::*; -use crate::consts::{IPI_EVENT_CLEAR_INJECT_IRQ, MAX_CPU_NUM}; +use crate::consts::MAX_CPU_NUM; use crate::cpu_data::this_cpu_data; use crate::device::irqchip::inject_irq; use crate::device::irqchip::ls7a2000::chip::*; -use crate::event::{check_events, dump_cpu_events, dump_events}; +use crate::event::{dump_events, handle_next_event}; use crate::hypercall::{SGI_IPI_ID, *}; use crate::memory::{addr, mmio_handle_access, MMIOAccess}; use crate::zone::Zone; @@ -100,8 +100,6 @@ pub fn install_trap_vector() { euen::set_fpe(true); // basic floating point euen::set_sxe(true); // 128-bit SIMD euen::set_asxe(true); // 256-bit SIMD - - enable_global_interrupt() } /// enable CRMD.IE @@ -599,7 +597,7 @@ fn signed_ext(value: usize, size: usize) -> usize { } #[no_mangle] -pub fn _vcpu_return(ctx: usize) { +pub fn _vcpu_return(ctx: usize) -> ! { let z = this_cpu_data().zone.as_ref(); let vm_id; if z.is_none() { @@ -916,7 +914,8 @@ extern "C" fn _hyp_trap_vector() { } #[no_mangle] -pub unsafe extern "C" fn _hyp_trap_return(ctx: usize) { +#[inline(never)] +pub unsafe extern "C" fn _hyp_trap_return(ctx: usize) -> ! { unsafe { asm!( // a0 -> sp @@ -1045,6 +1044,7 @@ pub unsafe extern "C" fn _hyp_trap_return(ctx: usize) { "gcsrwr $r12, {LOONGARCH_GCSR_DMW2}", "ld.d $r12, $r3, 256+8*60", "gcsrwr $r12, {LOONGARCH_GCSR_DMW3}", + in("$r4") ctx, LOONGARCH_CSR_ERA = const 0x6, LOONGARCH_GCSR_CRMD = const 0x0, LOONGARCH_GCSR_PRMD = const 0x1, @@ -1130,6 +1130,9 @@ pub unsafe extern "C" fn _hyp_trap_return(ctx: usize) { // LOONGARCH_CSR_PGDH = const 0x1a, // ); asm!( + // Re-establish the context base instead of relying on $r3 to remain + // unchanged across two independent asm blocks. + "move $r3, $r4", // restore sp "ld.d $r12, $r3, 24", "csrwr $r12, {LOONGARCH_CSR_DESAVE}", @@ -1168,7 +1171,9 @@ pub unsafe extern "C" fn _hyp_trap_return(ctx: usize) { "ld.d $r31, $r3, 248", "csrwr $r3, {LOONGARCH_CSR_DESAVE}", "ertn", - LOONGARCH_CSR_DESAVE = const 0x502 + in("$r4") ctx, + LOONGARCH_CSR_DESAVE = const 0x502, + options(noreturn) ); } } @@ -1269,34 +1274,37 @@ fn handle_interrupt(is: usize) { // Handle IPI interrupts if is & IPI_BIT != 0 { let cpu_id = this_cpu_id(); - let ipi_status = get_ipi_status(cpu_id); + let ipi_status = get_ipi_status(); debug!( "CPU {} received IPI interrupt, status = {:#x}", cpu_id, ipi_status ); - match ipi_status { - status if status == SGI_IPI_ID as _ => { - let events = dump_cpu_events(cpu_id); - debug!("CPU {} events: {:?}", cpu_id, events); - while check_events() {} - } - status if status == 0x8 => { - debug!("CPU {} received unhandled IPI status {:#x}", cpu_id, status); - } - status => { - warn!("CPU {} received unknown IPI status {:#x}", cpu_id, status); + let hvisor_mask = SGI_IPI_ID as u32; + if ipi_status & hvisor_mask != 0 { + // Clear before each fetch. If the fetch observes an empty queue while a + // producer enqueues concurrently, its doorbell remains pending and + // re-fires. Clearing after the fetch could lose that coalesced wakeup. + clear_ipi_bits(hvisor_mask); + while handle_next_event() { + clear_ipi_bits(hvisor_mask); } } - reset_ipi(cpu_id); + + let unhandled = ipi_status & !hvisor_mask; + if unhandled != 0 { + error!( + "CPU {} has unhandled physical IPI status {:#x}; preserving those bits", + cpu_id, unhandled + ); + } return; } // Handle timer interrupts if is & TIMER_BIT != 0 { - warn!("Timer interrupt received"); + debug!("Timer interrupt received"); loongArch64::register::ticlr::clear_timer_interrupt(); - crate::device::irqchip::ls7a2000::clear_hwi_injected_irq(); return; } @@ -1352,7 +1360,7 @@ fn emulate_cpucfg(ins: usize, ctx: &mut ZoneContext) { const MAX_CPUCFG_REGS: usize = 21; - info!( + debug!( "cpucfg emulation, target cpucfg index is {:#x}", cpucfg_target_idx ); @@ -1389,19 +1397,19 @@ fn emulate_csrx(ins: usize, ctx: &mut ZoneContext) { match ty { 0 => { // csrrd - info!("csrrd emulation for CSR {:#x}", csr); + debug!("csrrd emulation for CSR {:#x}", csr); ctx.x[rd] = 0; // just set it to 0 } 1 => { // csrwr - info!("csrwr emulation for CSR {:#x}", csr); + debug!("csrwr emulation for CSR {:#x}", csr); ctx.x[rd] = 0; // do nothing to GCSR, but we also need to set rd to 0 } _ => { // csrxchg - info!("csrxchg emulation for CSR {:#x}", csr); + debug!("csrxchg emulation for CSR {:#x}", csr); ctx.x[rd] = 0; // do nothing to GCSR, but we also need to set rd to 0 } diff --git a/src/arch/loongarch64/zone.rs b/src/arch/loongarch64/zone.rs index baa50d137..5db3981d6 100644 --- a/src/arch/loongarch64/zone.rs +++ b/src/arch/loongarch64/zone.rs @@ -16,24 +16,30 @@ // use crate::device::irqchip::ls7a2000::chip::get_extioi_sr; use crate::{ - arch::{cpu::this_cpu_id, trap::GLOBAL_TRAP_CONTEXT_HELPER_PER_CPU, Stage2PageTable}, + arch::{ + cpu::this_cpu_id, ipi::SMP_BOOT_CPU, trap::GLOBAL_TRAP_CONTEXT_HELPER_PER_CPU, + Stage2PageTable, + }, config::*, - consts::PAGE_SIZE, + consts::{IPI_EVENT_SEND_IPI, MAX_CPU_NUM, PAGE_SIZE}, + cpu_data::{get_cpu_data, this_cpu_data, VcpuState}, device::virtio_trampoline::mmio_virtio_handler, error::{HvError, HvResult}, + event::{send_event, IPI_EVENT_WAKEUP}, + hypercall::SGI_IPI_ID, memory::{ addr::{align_down, align_up}, mmio_generic_handler, mmio_perform_access, GuestPhysAddr, HostPhysAddr, MMIOAccess, MemFlags, MemoryRegion, MemorySet, }, - zone::Zone, + zone::{is_this_root_zone, Zone}, PHY_TO_DMW_UNCACHED, }; use alloc::boxed::Box; use alloc::collections::BTreeMap; use alloc::string::String; use alloc::vec::Vec; -use core::sync::atomic::{fence, AtomicU64, Ordering}; +use core::sync::atomic::{fence, AtomicU32, AtomicU64, Ordering}; use core::{arch::asm, ptr::write_volatile}; use spin::lazy::Lazy; use spin::Mutex; @@ -457,6 +463,12 @@ const LOG_INTERVAL: u64 = 100000; const BASE_ADDR: usize = PHY_TO_DMW_UNCACHED!(0x1fe0_0000); const UART0_BASE: usize = PHY_TO_DMW_UNCACHED!(0x1fe0_01e0); const UART0_SIZE: usize = 0x8; +const IPI_REG_BASE: usize = PHY_TO_DMW_UNCACHED!(0x1fe0_1000); +const IPI_REG_SIZE: usize = 0x400; +const IPI_SEND_BASE: usize = PHY_TO_DMW_UNCACHED!(0x1fe0_1040); +const IPI_SEND_SIZE: usize = 0x4; +const IPI_MAIL_SEND_BASE: usize = PHY_TO_DMW_UNCACHED!(0x1fe0_1048); +const IPI_MAIL_SEND_SIZE: usize = 0x8; const LIOINTC_MAP_BASE: usize = PHY_TO_DMW_UNCACHED!(0x1fe0_1400); // 1400-141f const LIOINTC_MAP_SIZE: usize = 0x20; const ANYSEND_BASE: usize = PHY_TO_DMW_UNCACHED!(0x1fe0_1158); @@ -484,6 +496,39 @@ macro_rules! is_in_mmio_range { }; } +const IPI_STATUS: usize = 0x00; +const IPI_ENABLE: usize = 0x04; +const IPI_SET: usize = 0x08; +const IPI_CLEAR: usize = 0x0c; +const IPI_MAILBOX_BASE: usize = 0x20; +const IPI_MAILBOX_SIZE: usize = 0x20; + +static VIRTUAL_IPI_STATUS: [AtomicU32; MAX_CPU_NUM] = { + const C: AtomicU32 = AtomicU32::new(0); + [C; MAX_CPU_NUM] +}; +static VIRTUAL_IPI_ENABLE: [AtomicU32; MAX_CPU_NUM] = { + const C: AtomicU32 = AtomicU32::new(0xffff_ffff); + [C; MAX_CPU_NUM] +}; +static VIRTUAL_IPI_MAILBOX: [AtomicU64; MAX_CPU_NUM * 4] = { + const C: AtomicU64 = AtomicU64::new(0); + [C; MAX_CPU_NUM * 4] +}; +const IOCSR_IPI_SEND_BLOCKING: u32 = 1 << 31; + +pub fn reset_virtual_ipi_state(cpu: usize) { + if cpu >= MAX_CPU_NUM { + return; + } + + VIRTUAL_IPI_STATUS[cpu].store(0, Ordering::Release); + VIRTUAL_IPI_ENABLE[cpu].store(0xffff_ffff, Ordering::Release); + for mailbox in 0..4 { + VIRTUAL_IPI_MAILBOX[cpu * 4 + mailbox].store(0, Ordering::Release); + } +} + fn handle_uart_mmio(mmio: &mut MMIOAccess, base_addr: usize) -> HvResult { mmio_perform_access(base_addr, mmio); Ok(()) @@ -513,9 +558,9 @@ fn handle_extioi_mapping_mmio(mmio: &mut MMIOAccess, base_addr: usize, size: usi return Ok(()); } - // if this is nonroot, we ignore the mmio - if this_cpu_id() != 0 { - info!("nonroot's write to extioi mapping regs, ignored"); + // Non-root zones see a virtual CPU0 even when running on another physical CPU. + if !is_this_root_zone() { + debug!("nonroot's write to extioi mapping regs, ignored"); return Ok(()); } @@ -587,6 +632,249 @@ fn handle_generic_mmio(mmio: &mut MMIOAccess, base_addr: usize) -> HvResult { Ok(()) } +fn this_guest_cpu_id() -> usize { + this_cpu_data() + .zone + .as_ref() + .and_then(|zone| zone.read().phys_to_guest_cpu(this_cpu_id())) + .unwrap_or(0) +} + +fn guest_cpu_to_physical_cpu(guest_cpu: usize) -> Option { + this_cpu_data() + .zone + .as_ref() + .and_then(|zone| zone.read().guest_to_phys_cpu(guest_cpu)) +} + +pub fn sync_virtual_ipi_line() { + let cpu = this_cpu_id(); + let status = VIRTUAL_IPI_STATUS[cpu].load(Ordering::Acquire); + + if status != 0 { + crate::device::irqchip::ls7a2000::inject_irq(12, false); + } else { + crate::device::irqchip::ls7a2000::clear_injected_irq(12); + } +} + +fn sync_or_notify_virtual_ipi_line(cpu: usize) { + if cpu == this_cpu_id() { + sync_virtual_ipi_line(); + } else { + send_event(cpu, SGI_IPI_ID as usize, IPI_EVENT_SEND_IPI); + } +} + +fn virtual_ipi_send(target_guest_cpu: usize, ipi_bits: u32, blocking: bool) -> HvResult { + let Some(target_cpu) = guest_cpu_to_physical_cpu(target_guest_cpu) else { + warn!( + "loongarch64: guest IPI target vCPU {} out of range", + target_guest_cpu + ); + return Ok(()); + }; + + if ipi_bits & SMP_BOOT_CPU as u32 != 0 { + let entry = VIRTUAL_IPI_MAILBOX[target_cpu * 4].load(Ordering::Acquire) as usize; + let target_data = get_cpu_data(target_cpu); + let _lock = target_data.ctrl_lock.lock(); + if target_data.vcpu_state.is_stopped() { + debug!( + "loongarch64: guest boots vCPU{}(pCPU{}) through IPI, entry={:#x}", + target_guest_cpu, target_cpu, entry + ); + target_data.cpu_on_entry = entry; + target_data.vcpu_state.store(VcpuState::Ready); + send_event(target_cpu, SGI_IPI_ID as usize, IPI_EVENT_WAKEUP); + } else { + warn!( + "loongarch64: guest tried to boot running vCPU{}(pCPU{})", + target_guest_cpu, target_cpu + ); + } + } + + let pending = ipi_bits & !(SMP_BOOT_CPU as u32); + if pending == 0 { + if blocking { + fence(Ordering::SeqCst); + } + return Ok(()); + } + + // Match the in-kernel LoongArch IPI model: commit the status update before + // returning from the send write, merge repeated actions, and only notify on + // the zero-to-nonzero transition. Bit 31 does not wait for guest IPI_CLEAR. + let old = VIRTUAL_IPI_STATUS[target_cpu].fetch_or(pending, Ordering::AcqRel); + let new = old | pending; + if old == 0 && new != 0 { + sync_or_notify_virtual_ipi_line(target_cpu); + } + + if blocking { + // The emulated send is synchronous: the target status and event queue + // are globally visible before the trapped IOCSR write completes. + fence(Ordering::SeqCst); + } + + Ok(()) +} + +fn handle_ipi_any_send_mmio(mmio: &mut MMIOAccess) -> HvResult { + if !mmio.is_write { + mmio.value = 0; + return Ok(()); + } + if mmio.size != 4 { + warn!("loongarch64: unsupported guest IPI send size {}", mmio.size); + return Ok(()); + } + + let value = mmio.value as u32; + let ipi_id = value & 0x1f; + let target_guest_cpu = ((value >> 16) & 0x3ff) as usize; + let blocking = value & IOCSR_IPI_SEND_BLOCKING != 0; + virtual_ipi_send(target_guest_cpu, 1u32 << ipi_id, blocking) +} + +fn handle_ipi_mail_send_mmio(mmio: &mut MMIOAccess) -> HvResult { + if !mmio.is_write { + mmio.value = 0; + return Ok(()); + } + if mmio.size != 8 { + warn!( + "loongarch64: unsupported guest mailbox send size {}", + mmio.size + ); + return Ok(()); + } + + let value = mmio.value as u64; + let target_guest_cpu = ((value >> 16) & 0x3ff) as usize; + let box_half = ((value >> 2) & 0x7) as usize; + let mailbox = box_half / 2; + let is_high = (box_half & 1) != 0; + let data = (value >> 32) as u32; + + let Some(target_cpu) = guest_cpu_to_physical_cpu(target_guest_cpu) else { + warn!( + "loongarch64: invalid guest mailbox send target_vcpu={}, mailbox={}", + target_guest_cpu, mailbox + ); + return Ok(()); + }; + + if mailbox >= 4 { + warn!( + "loongarch64: invalid guest mailbox send target_vcpu={}, mailbox={}", + target_guest_cpu, mailbox + ); + return Ok(()); + } + + let slot = &VIRTUAL_IPI_MAILBOX[target_cpu * 4 + mailbox]; + if is_high { + let old = slot.load(Ordering::Acquire); + let new = (old & 0x0000_0000_ffff_ffff) | ((data as u64) << 32); + slot.store(new, Ordering::Release); + } else { + let old = slot.load(Ordering::Acquire); + let new = (old & 0xffff_ffff_0000_0000) | data as u64; + slot.store(new, Ordering::Release); + } + + Ok(()) +} + +fn handle_ipi_mmio(mmio: &mut MMIOAccess) -> HvResult { + let cpu_block = (mmio.address - offset(IPI_REG_BASE)) / 0x100; + let reg = (mmio.address - offset(IPI_REG_BASE)) % 0x100; + let guest_cpu = if cpu_block == 0 { + this_guest_cpu_id() + } else { + cpu_block + }; + let Some(cpu) = guest_cpu_to_physical_cpu(guest_cpu) else { + warn!( + "loongarch64: guest IPI register access for invalid vCPU {}", + guest_cpu + ); + if !mmio.is_write { + mmio.value = 0; + } + return Ok(()); + }; + + match reg { + IPI_STATUS => { + if !mmio.is_write { + mmio.value = VIRTUAL_IPI_STATUS[cpu].load(Ordering::Acquire) as usize; + if mmio.value != 0 { + debug!( + "loongarch64: guest cpu{} reads IPI_STATUS cpu{} = {:#x}", + this_guest_cpu_id(), + guest_cpu, + mmio.value + ); + } + } + } + IPI_ENABLE => { + if mmio.is_write { + VIRTUAL_IPI_ENABLE[cpu].store(mmio.value as u32, Ordering::Release); + } else { + mmio.value = VIRTUAL_IPI_ENABLE[cpu].load(Ordering::Acquire) as usize; + } + } + IPI_SET => { + if mmio.is_write { + virtual_ipi_send(guest_cpu, mmio.value as u32, false)?; + } else { + mmio.value = 0; + } + } + IPI_CLEAR => { + if mmio.is_write { + let mask = mmio.value as u32; + let old = VIRTUAL_IPI_STATUS[cpu].fetch_and(!mask, Ordering::AcqRel); + let new = old & !mask; + if old != 0 && new == 0 { + sync_or_notify_virtual_ipi_line(cpu); + } + if old != 0 || mmio.value != 0 { + debug!( + "loongarch64: guest cpu{} clears IPI_STATUS cpu{}, mask={:#x}, old={:#x}", + this_guest_cpu_id(), + guest_cpu, + mmio.value, + old + ); + } + } else { + mmio.value = 0; + } + } + IPI_MAILBOX_BASE..=0x3f if reg < IPI_MAILBOX_BASE + IPI_MAILBOX_SIZE => { + let mailbox = (reg - IPI_MAILBOX_BASE) / 8; + if mmio.is_write { + VIRTUAL_IPI_MAILBOX[cpu * 4 + mailbox].store(mmio.value as u64, Ordering::Release); + } else { + mmio.value = + VIRTUAL_IPI_MAILBOX[cpu * 4 + mailbox].load(Ordering::Acquire) as usize; + } + } + _ => { + if !mmio.is_write { + mmio.value = 0; + } + } + } + + Ok(()) +} + fn handle_mmio_stats(mmio: &mut MMIOAccess) { let key = MMIOAccessKey { offset: mmio.address, @@ -644,27 +932,33 @@ pub fn loongarch_generic_mmio_handler(mmio: &mut MMIOAccess, arg: usize) -> HvRe let ret; - if is_in_mmio_range!(mmio.address, EXTIOI_MAP_CORE_BASE, EXTIOI_MAP_CORE_SIZE) { + if is_in_mmio_range!(mmio.address, IPI_SEND_BASE, IPI_SEND_SIZE) { + ret = handle_ipi_any_send_mmio(mmio); + } else if is_in_mmio_range!(mmio.address, IPI_MAIL_SEND_BASE, IPI_MAIL_SEND_SIZE) { + ret = handle_ipi_mail_send_mmio(mmio); + } else if is_in_mmio_range!(mmio.address, IPI_REG_BASE, IPI_REG_SIZE) { + ret = handle_ipi_mmio(mmio); + } else if is_in_mmio_range!(mmio.address, EXTIOI_MAP_CORE_BASE, EXTIOI_MAP_CORE_SIZE) { ret = handle_extioi_mapping_mmio(mmio, EXTIOI_MAP_CORE_BASE, EXTIOI_MAP_CORE_SIZE); } else if is_in_mmio_range!(mmio.address, EXTIOI_SR_CORE_BASE, EXTIOI_SR_CORE_SIZE) { ret = handle_extioi_status_mmio(mmio, EXTIOI_SR_CORE_BASE, EXTIOI_SR_CORE_SIZE); } else if is_in_mmio_range!(mmio.address, EXTIOI_ENABLE_BASE, EXTIOI_ENABLE_SIZE) { - if this_cpu_id() != 0 && mmio.is_write { - info!("nonroot's write to extioi enable regs, ignored"); + if !is_this_root_zone() && mmio.is_write { + debug!("nonroot's write to extioi enable regs, ignored"); return Ok(()); } else { ret = handle_generic_mmio(mmio, BASE_ADDR); } } else if is_in_mmio_range!(mmio.address, EXTIOI_BOUNCE_BASE, EXTIOI_BOUNCE_SIZE) { - if this_cpu_id() != 0 && mmio.is_write { - info!("nonroot's write to extioi bounce regs, ignored"); + if !is_this_root_zone() && mmio.is_write { + debug!("nonroot's write to extioi bounce regs, ignored"); return Ok(()); } else { ret = handle_generic_mmio(mmio, BASE_ADDR); } } else if is_in_mmio_range!(mmio.address, EXTIOI_NODE_SEL_BASE, EXTIOI_NODE_SEL_SIZE) { - if this_cpu_id() != 0 && mmio.is_write { - info!("nonroot's write to extioi node sel regs, ignored"); + if !is_this_root_zone() && mmio.is_write { + debug!("nonroot's write to extioi node sel regs, ignored"); return Ok(()); } else { ret = handle_generic_mmio(mmio, BASE_ADDR); @@ -700,7 +994,10 @@ impl Zone { Ok(()) } - pub fn arch_zone_reset(&mut self, _config: &HvZoneConfig) -> HvResult { + pub fn arch_zone_reset(&mut self, config: &HvZoneConfig) -> HvResult { + for cpu in config.cpus().iter() { + reset_virtual_ipi_state(*cpu as usize); + } Ok(()) } } diff --git a/src/arch/riscv64/cpu.rs b/src/arch/riscv64/cpu.rs index 0dea57d17..9e595e5f2 100644 --- a/src/arch/riscv64/cpu.rs +++ b/src/arch/riscv64/cpu.rs @@ -14,7 +14,7 @@ // Authors: // use super::csr::*; -use crate::cpu_data::this_cpu_data; +use crate::cpu_data::{this_cpu_data, VcpuState}; use crate::platform::{BOARD_HARTID_MAP, BOARD_NCPUS}; use crate::{ arch::mm::new_s2_memory_set, @@ -37,8 +37,11 @@ pub struct ArchCpu { pub stack_top: usize, pub cpuid: usize, // pub first_cpu: usize, - pub power_on: bool, - pub init: bool, + /// Whether Sstc is exposed to this VS-mode guest. + /// + /// This is distinct from `cfg(isa_sstc)`, which describes host-platform + /// support. They currently have the same value, but may differ when Sstc + /// exposure becomes configurable per guest. pub sstc: bool, } @@ -54,9 +57,8 @@ impl ArchCpu { stack_top: 0, cpuid, // first_cpu: 0, - power_on: false, - init: false, - sstc: cfg!(feature = "sstc"), + // Initially expose Sstc whenever the host platform supports it. + sstc: cfg!(isa_sstc), }; ret } @@ -72,11 +74,31 @@ impl ArchCpu { write_csr!(CSR_SSCRATCH, self as *const _ as usize); //arch cpu pointer self.sepc = entry; self.hstatus = 1 << 7 | 2 << 32; // HSTATUS_SPV | HSTATUS_VSXL_64 - #[cfg(feature = "aia")] + #[cfg(aia)] { self.hstatus |= 1 << 12; // HSTATUS_VGEIN } - self.sstatus = 1 << 8 | 1 << 63 | 3 << 13 | 3 << 15; //SPP + #[cfg(all(aia, rva23))] + { + // Permit the AIA guest state advertised by qemu-aia. Without these + // enables, accesses from VS-mode to the corresponding state raise a + // virtual-instruction exception. + set_csr!( + CSR_HSTATEEN0, + HSTATEEN0_IMSIC + | HSTATEEN0_AIA + | HSTATEEN0_CSRIND + | HSTATEEN0_SENVCFG + | HSTATEEN0_SSTATEEN + ); + } + self.sstatus = SSTATUS_SPP | SSTATUS_FS_DIRTY; + #[cfg(isa_vector)] + { + // With V=1, vector instructions require both the HS-level + // sstatus.VS and the guest's vsstatus.VS to be enabled. + self.sstatus |= SSTATUS_VS_DIRTY; + } self.stack_top = self.stack_top() as usize; for i in 0..32 { self.x[i] = 0; @@ -84,20 +106,58 @@ impl ArchCpu { self.x[10] = cpu_id; // cpu id self.x[11] = dtb; // dtb addr - if self.sstc { - // hvisor doesn't handle timer interrupt. + // Hypervisor v0.6 does not define henvcfg, so never access this CSR + // when building for that version. + #[cfg(not(hypervisor_v0_6))] + { + #[cfg(any(isa_sstc, isa_svpbmt, isa_cmo))] + let mut henvcfg = 0; + #[cfg(not(any(isa_sstc, isa_svpbmt, isa_cmo)))] + let henvcfg = 0; + #[cfg(isa_sstc)] + { + // STCE controls whether this guest may access vstimecmp. + if self.sstc { + henvcfg |= HENVCFG_STCE; + } else { + // Sstc is not exposed to this guest; keep STCE clear. + } + } + #[cfg(isa_svpbmt)] + { + henvcfg |= HENVCFG_PBMTE; + } + #[cfg(isa_cmo)] + { + // Zicbom uses CBIE for CBO.INVAL and CBCFE for + // CBO.CLEAN/CBO.FLUSH. Zicboz uses CBZE for CBO.ZERO. + // Zicbop prefetch hints require no HENVCFG enable bit. + henvcfg |= HENVCFG_CBIE | HENVCFG_CBCFE | HENVCFG_CBZE; + } + // Write the complete value once so a vCPU reset cannot retain stale bits. + write_csr!(CSR_HENVCFG, henvcfg); + } + + #[cfg(isa_sstc)] + { + // The host-platform Sstc timer is not used by hvisor. set_csr!(CSR_STIMECMP, usize::MAX); - set_csr!(CSR_HENVCFG, 1 << 63); + // HS-mode can program vstimecmp whenever the platform supports + // Sstc, regardless of whether direct access is exposed to VS-mode. set_csr!(CSR_VSTIMECMP, usize::MAX); - } else { - // In megrez board, this instruction is not supported. (illegal instruction) - #[cfg(not(feature = "eic770x_soc"))] - set_csr!(CSR_HENVCFG, 0); } set_csr!(CSR_HCOUNTEREN, 1 << 1); // HCOUNTEREN_TM // In VU-mode, a counter is not readable unless the applicable bits are set in both hcounteren and scounteren. write_csr!(CSR_HTIMEDELTA, 0); write_csr!(CSR_HIE, 0); + // Initialize the guest's virtual supervisor floating-point state on + // every platform. SD and XS are read-only summary fields. + write_csr!(CSR_VSSTATUS, SSTATUS_FS_DIRTY); + #[cfg(isa_vector)] + { + // Expose Vector state to the guest when the V extension is enabled. + set_csr!(CSR_VSSTATUS, SSTATUS_VS_DIRTY); + } write_csr!(CSR_VSTVEC, 0); write_csr!(CSR_VSSCRATCH, 0); write_csr!(CSR_VSEPC, 0); @@ -109,10 +169,21 @@ impl ArchCpu { pub fn init_interrupt(&self) { // Used before enter into VM. - set_csr!(CSR_HIDELEG, 1 << 2 | 1 << 6 | 1 << 10); // HIDELEG_VSSI | HIDELEG_VSTI | HIDELEG_VSEI - // Note: Breakpoint exception is temporarily needed. - // TODO: This is need to be checked in the future. - set_csr!(CSR_HEDELEG, 1 << 3 | 1 << 8 | 1 << 12 | 1 << 13 | 1 << 15); // HEDELEG_ECU | HEDELEG_IPF | HEDELEG_LPF | HEDELEG_SPF + // HIDELEG_VSSI | HIDELEG_VSTI | HIDELEG_VSEI + set_csr!(CSR_HIDELEG, 1 << 2 | 1 << 6 | 1 << 10); + // Linux uses an illegal-instruction trap on the first Vector use of an allowed user thread while vsstatus.VS is Off, + // then allocates and enables the thread's Vector context. Delegate the exception so the guest handles this first-use path. + // Delegated synchronous exceptions in HEDELEG: + // bit 2 - Illegal instruction + // bit 3 - Breakpoint + // bit 8 - Environment call from U-mode or VU-mode + // bit 12 - Instruction page fault + // bit 13 - Load page fault + // bit 15 - Store/AMO page fault + set_csr!( + CSR_HEDELEG, + 1 << 2 | 1 << 3 | 1 << 8 | 1 << 12 | 1 << 13 | 1 << 15 + ); set_csr!(CSR_SIE, 1 << 9 | 1 << 5 | 1 << 1); // Enable all interrupts (SEIE STIE SSIE). } @@ -129,12 +200,7 @@ impl ArchCpu { } assert!(this_cpu_id() == self.cpuid); - // change power_on - self.power_on = true; - - if !self.init { - self.init = true; - } + this_cpu_data().vcpu_state.store(VcpuState::Running); self.init_interrupt(); // reset all registers related @@ -157,7 +223,7 @@ impl ArchCpu { fn vcpu_arch_entry() -> !; } assert!(this_cpu_id() == self.cpuid); - self.power_on = false; + this_cpu_data().vcpu_state.store(VcpuState::Stopped); PARKING_MEMORY_SET.call_once(|| { let parking_code: [u8; 8] = [0x73, 0x00, 0x50, 0x10, 0x6F, 0xF0, 0xDF, 0xFF]; // 1: wfi; b 1b @@ -202,7 +268,6 @@ impl ArchCpu { // debug!("sip: {:#x}", read_csr!(CSR_SIP)); // // clear_csr!(CSR_SIP, 1 << 1); // debug!("sip*: {:#x}", read_csr!(CSR_SIP)); - // self.init = true; // unsafe { // vcpu_arch_entry(); diff --git a/src/arch/riscv64/csr.rs b/src/arch/riscv64/csr.rs index 2c1917e40..5d5e5038d 100644 --- a/src/arch/riscv64/csr.rs +++ b/src/arch/riscv64/csr.rs @@ -52,6 +52,7 @@ pub const CSR_HGEIP: u64 = 0xE07; /* Hypervisor Configuration */ pub const CSR_HENVCFG: u64 = 0x60A; pub const CSR_HENVCFGH: u64 = 0x61A; +pub const CSR_HSTATEEN0: u64 = 0x60C; /* Sstc Extension */ pub const CSR_STIMECMP: u64 = 0x14D; @@ -59,6 +60,38 @@ pub const CSR_STIMECMPH: u64 = 0x15D; pub const HSTATUS_SPV: u64 = 1 << 7; +// sstatus/vsstatus state fields. +pub const SSTATUS_SPP: usize = 1 << 8; +pub const SSTATUS_FS_DIRTY: usize = 0b11 << 13; +// vsstatus.VS: vector state is dirty and available to VS/VU-mode. +pub const SSTATUS_VS_SHIFT: usize = 9; +pub const SSTATUS_VS_DIRTY: usize = 0b11 << SSTATUS_VS_SHIFT; + +// HENVCFG.STCE: enable vstimecmp access from VS-mode (Sstc). +pub const HENVCFG_STCE: usize = 1 << 63; +// HENVCFG.PBMTE: enable page-based memory types from Svpbmt in VS-mode. +pub const HENVCFG_PBMTE: usize = 1 << 62; +// HENVCFG controls for cache-block operations advertised to VS-mode. +// Zicbom uses CBIE[5:4]=01 for CBO.INVAL (performed as a flush) and CBCFE for +// CBO.CLEAN/CBO.FLUSH. Zicboz uses CBZE for CBO.ZERO. Zicbop prefetch hints +// do not require an HENVCFG enable bit. +pub const HENVCFG_CBIE: usize = 1 << 4; +pub const HENVCFG_CBCFE: usize = 1 << 6; +pub const HENVCFG_CBZE: usize = 1 << 7; + +// HSTATEEN0 controls access to extension state from VS/VU-mode. +// These fields are defined by Smstateen/Ssstateen and AIA: +// bit 58: IMSIC guest interrupt-file state, including vstopei. +// bit 59: AIA state not covered by CSRIND or IMSIC. +// bit 60: indirect CSR state (siselect/sireg, exposed as vsiselect/vsireg). +// bit 62: senvcfg state. +// bit 63: sstateen* CSRs, i.e. the supervisor state-enable view for VS-mode. +pub const HSTATEEN0_IMSIC: usize = 1 << 58; +pub const HSTATEEN0_AIA: usize = 1 << 59; +pub const HSTATEEN0_CSRIND: usize = 1 << 60; +pub const HSTATEEN0_SENVCFG: usize = 1 << 62; +pub const HSTATEEN0_SSTATEEN: usize = 1 << 63; + macro_rules! read_csr { ($csr_number:expr) => { { diff --git a/src/arch/riscv64/hypercall.rs b/src/arch/riscv64/hypercall.rs index ab8f4a198..4228211c3 100644 --- a/src/arch/riscv64/hypercall.rs +++ b/src/arch/riscv64/hypercall.rs @@ -14,13 +14,16 @@ // Authors: // ForeverYolo <2572131118@qq.com> -use crate::arch::cpu::this_cpu_id; use crate::config::CONFIG_MAGIC_VERSION; use crate::device::virtio_trampoline::MAX_DEVS; use crate::hypercall::HyperCall; use crate::hypercall::HyperCallResult; impl<'a> HyperCall<'a> { + pub fn hv_get_ecam_base(&mut self, _ecam_base: *mut u64) -> HyperCallResult { + HyperCallResult::Ok(0) + } + pub fn hv_ivc_info(&mut self, _ivc_info_ipa: u64) -> HyperCallResult { warn!("hv_ivc_info is not implemented for Risc-V"); HyperCallResult::Ok(0) @@ -52,11 +55,6 @@ impl<'a> HyperCall<'a> { return list_addr; } - pub fn check_cpu_id(&self) { - let cpuid = this_cpu_id(); - trace!("CPU ID: {} Start Zone", cpuid); - } - pub fn hv_virtio_get_irq(&self, _virtio_irq: *mut u32) -> HyperCallResult { trace!("hv_virtio_get_irq is not need for RISC-V"); HyperCallResult::Ok(0) diff --git a/src/arch/riscv64/ipi.rs b/src/arch/riscv64/ipi.rs index d4ad55d27..fca1e2491 100644 --- a/src/arch/riscv64/ipi.rs +++ b/src/arch/riscv64/ipi.rs @@ -15,17 +15,16 @@ // Jingyu Liu // use crate::consts::IPI_EVENT_SEND_IPI; -#[cfg(feature = "plic")] +#[cfg(plic)] use crate::consts::IPI_EVENT_UPDATE_HART_LINE; use crate::platform::BOARD_HARTID_MAP; -// arch_send_event pub fn arch_send_event(cpu_id: u64, _sgi_num: u64) { let hart_id = BOARD_HARTID_MAP[cpu_id as usize]; debug!("arch_send_event: cpu_id: {}", hart_id); - #[cfg(feature = "aclint")] + #[cfg(aclint)] crate::device::irqchip::aclint::aclint_send_ipi(hart_id as usize); - #[cfg(not(feature = "aclint"))] + #[cfg(not(aclint))] { let sbi_ret: sbi_rt::SbiRet = sbi_rt::send_ipi(sbi_rt::HartMask::from_mask_base(1 << hart_id, 0)); @@ -35,6 +34,10 @@ pub fn arch_send_event(cpu_id: u64, _sgi_num: u64) { } } +pub fn arch_notify_event(cpu_id: u64, sgi_num: u64, _event_id: usize, _queue_was_empty: bool) { + arch_send_event(cpu_id, sgi_num); +} + /// Handle send_ipi event. pub fn arch_ipi_handler() { unsafe { @@ -44,7 +47,7 @@ pub fn arch_ipi_handler() { pub fn arch_check_events(event: Option) { match event { - #[cfg(feature = "plic")] + #[cfg(plic)] Some(IPI_EVENT_UPDATE_HART_LINE) => { use crate::device::irqchip::plic::update_hart_line; update_hart_line(); @@ -58,7 +61,3 @@ pub fn arch_check_events(event: Option) { } } } - -pub fn arch_prepare_send_event(_cpu_id: usize, _ipi_int_id: usize, _event_id: usize) { - debug!("risc-v arch_prepare_send_event: do nothing now.") -} diff --git a/src/arch/riscv64/mod.rs b/src/arch/riscv64/mod.rs index 9a1b2e6b0..6288400b2 100644 --- a/src/arch/riscv64/mod.rs +++ b/src/arch/riscv64/mod.rs @@ -36,3 +36,7 @@ pub mod zone; // pub use s1pt::Stage1PageTable; pub use s2pt::stage2_mode_detect; pub use s2pt::Stage2PageTable; + +pub fn arch_config_by_args(_cpuid: usize, _host_dtb: usize) { + // Do nothing now. +} diff --git a/src/arch/riscv64/paging.rs b/src/arch/riscv64/paging.rs index d9167d840..b23036ada 100644 --- a/src/arch/riscv64/paging.rs +++ b/src/arch/riscv64/paging.rs @@ -162,7 +162,8 @@ where assert!(pt_level >= 3 && pt_level <= 5, "pt_level must be 3, 4 or 5"); // Note: riscv spec requires G-stage's root page table addr to be 16KB aligned. Self { - root: Frame::new_16().expect("failed to allocate root frame for host page table"), + root: Frame::new_contiguous_with_base(4, 2) + .expect("failed to allocate root frame for host page table"), pt_level: pt_level, _phantom: PhantomData, } diff --git a/src/arch/riscv64/sbi.rs b/src/arch/riscv64/sbi.rs index d922f1032..479887f07 100644 --- a/src/arch/riscv64/sbi.rs +++ b/src/arch/riscv64/sbi.rs @@ -17,13 +17,15 @@ use super::cpu::ArchCpu; use crate::arch::cpu::hartid_to_cpuid; -use crate::arch::csr::*; +#[cfg(isa_sstc)] +use crate::arch::csr::{write_csr, CSR_VSTIMECMP}; use crate::consts::IPI_EVENT_SEND_IPI; -use crate::cpu_data::{get_cpu_data, this_cpu_data}; +use crate::cpu_data::{get_cpu_data, this_cpu_data, VcpuState}; use crate::event::{send_event, IPI_EVENT_WAKEUP}; use crate::hypercall::HyperCall; -use core::sync::atomic; +#[cfg(not(isa_sstc))] use riscv::register::sie; +#[cfg(not(isa_sstc))] use riscv_h::register::hvip; use sbi_rt::{HartMask, SbiRet}; use sbi_spec::binary::{ @@ -194,11 +196,24 @@ pub fn sbi_time_handler(fid: usize, current_cpu: &mut ArchCpu) -> SbiRet { }; } let stime_value = current_cpu.x[10]; - if current_cpu.sstc { - // Set the vstimecmp, and don't need to inject timer interrupt. + // `cfg(isa_sstc)` describes whether the host platform supports Sstc + // and can safely access vstimecmp. + #[cfg(isa_sstc)] + { + // HS-mode can program the guest timer whenever the platform supports + // Sstc. `ArchCpu.sstc` only controls whether VS-mode may access + // vstimecmp directly through HENVCFG.STCE. write_csr!(CSR_VSTIMECMP, stime_value); - } else { - // Hvisor should receive timer interrupt and inject it to guest. + SbiRet { + error: RET_SUCCESS, + value: 0, + } + } + + #[cfg(not(isa_sstc))] + { + // The host platform lacks Sstc. Let hvisor receive the timer interrupt + // and inject a virtual timer interrupt into the guest. sbi_rt::set_timer(stime_value as _); unsafe { // clear guest timer interrupt pending @@ -206,24 +221,11 @@ pub fn sbi_time_handler(fid: usize, current_cpu: &mut ArchCpu) -> SbiRet { // enable timer interrupt sie::set_stimer(); } + SbiRet { + error: RET_SUCCESS, + value: 0, + } } - SbiRet { - error: RET_SUCCESS, - value: 0, - } -} - -#[allow(unused)] -#[allow(non_camel_case_types)] -#[derive(Debug, PartialEq)] -pub enum HSM_STATUS { - STARTED, - STOPPED, - START_PENDING, - STOP_PENDING, - SUSPENDED, - SUSPEND_PENDING, - RESUMING_PENDING, } /// SBI Hart State Management handler. @@ -278,15 +280,12 @@ pub fn sbi_hsm_start_handler(current_cpu: &mut ArchCpu) -> SbiRet { ); let target_cpu = get_cpu_data(cpuid); let _lock = target_cpu.ctrl_lock.lock(); - // Todo: use hsm status, not just hvisor defined power_on. - if target_cpu.arch_cpu.power_on { + if !target_cpu.vcpu_state.is_stopped() { sbi_ret.error = RET_ERR_FAILED; } else { - // Set the target cpu to start-pending. target_cpu.cpu_on_entry = start_addr; target_cpu.dtb_ipa = opaque; - // Insert memory fence. - atomic::fence(atomic::Ordering::SeqCst); + target_cpu.vcpu_state.store(VcpuState::Ready); send_event(cpuid, 0, IPI_EVENT_WAKEUP); } drop(_lock); diff --git a/src/arch/riscv64/trap.rs b/src/arch/riscv64/trap.rs index 99277f72e..4c8de184f 100644 --- a/src/arch/riscv64/trap.rs +++ b/src/arch/riscv64/trap.rs @@ -15,7 +15,7 @@ // use super::cpu::ArchCpu; use crate::arch::sbi::sbi_vs_handler; -#[cfg(feature = "plic")] +#[cfg(plic)] use crate::device::irqchip::plic::{inject_irq, plic_get_hwirq}; use crate::event::check_events; use crate::memory::GuestPhysAddr; @@ -417,7 +417,7 @@ pub fn handle_software_interrupt(_current_cpu: &mut ArchCpu) { /// Handle supervisor external interrupt. pub fn handle_external_interrupt(_current_cpu: &mut ArchCpu) { - #[cfg(feature = "plic")] + #[cfg(plic)] { // Note: in hvisor, all external interrupts are assigned to VS. // 1. claim hw irq. @@ -431,7 +431,7 @@ pub fn handle_external_interrupt(_current_cpu: &mut ArchCpu) { // 2. inject hw irq to zone. inject_irq(irq_id as usize, true); } - #[cfg(feature = "aia")] + #[cfg(aia)] { // Note: no irq belongs to hvisor, so hvisor won't handle external interrupt. panic!("HS extensional interrupt") diff --git a/src/arch/x86_64/acpi.rs b/src/arch/x86_64/acpi.rs index 701b5dffb..123b26971 100644 --- a/src/arch/x86_64/acpi.rs +++ b/src/arch/x86_64/acpi.rs @@ -697,6 +697,13 @@ pub fn root_get_config_space_info() -> Option<(usize, usize)> { Some((acpi.config_space_base, acpi.config_space_size)) } +pub fn try_get_cpu_id(apic_id: usize) -> Option { + ROOT_ACPI + .get() + .and_then(|acpi| acpi.apic_id_to_cpu_id.get(&apic_id)) + .copied() +} + fn contains_apic_id(apic_id: usize) -> bool { ROOT_ACPI .get() diff --git a/src/arch/x86_64/boot.rs b/src/arch/x86_64/boot.rs index b3191ef19..e4ef27242 100644 --- a/src/arch/x86_64/boot.rs +++ b/src/arch/x86_64/boot.rs @@ -22,7 +22,10 @@ use crate::{ memory::{GuestPhysAddr, HostPhysAddr, MemFlags, MemoryRegion, MemorySet, PAGE_SIZE}, platform::MEM_TYPE_RESERVED, }; -use alloc::string::{String, ToString}; +use alloc::{ + string::{String, ToString}, + vec::Vec, +}; use bit_field::BitField; use core::{ arch::{self, global_asm}, @@ -185,7 +188,7 @@ impl BootParams { } as HostPhysAddr; let boot_params = unsafe { &mut *(boot_params_hpa as *mut BootParams) }; - // info!("boot_proto_version: {:x?}", boot_params.boot_proto_version); + info!("boot_proto_version: {:x?}", boot_params.boot_proto_version); if boot_params.boot_proto_version < 0x0204 { panic!("kernel boot protocol version older than 2.04 not supported!"); } @@ -394,9 +397,9 @@ impl BootParams { let bytes_per_pixel = (fb_info.bpp as usize) / 8; let width = fb_info.width as usize; - #[cfg(not(feature = "split_screen"))] + #[cfg(not(split_screen))] let height = fb_info.height as usize; - #[cfg(all(feature = "split_screen"))] + #[cfg(all(split_screen))] let height = (fb_info.height / 2) as usize; self.screen_info.lfb_base = config.arch_config.screen_base as _; @@ -415,7 +418,7 @@ impl BootParams { self.screen_info.red_pos = 16; self.screen_info.alpha_size = 8; self.screen_info.alpha_pos = 24; - self.screen_info.orig_video_is_vga = VIDEO_TYPE_EFI; + self.screen_info.orig_video_is_vga = VIDEO_TYPE_VLFB; self.screen_info.capabilities = 0; self.vid_mode = 0xffff; @@ -534,50 +537,336 @@ pub fn print_memory_map() { } } +/// Construct Multiboot2 info structure in guest memory at `multiboot_info_paddr`. +pub fn multiboot2_info_fill( + config: &HvZoneConfig, + gpm: &mut MemorySet, + multiboot_info_paddr: GuestPhysAddr, +) -> HvResult { + let info_gpa = multiboot_info_paddr; + let (info_hpa, _, _) = unsafe { + gpm.page_table_query(info_gpa) + .expect("multiboot2 info GPA unmapped") + }; + + // Read raw cmdline from guest memory FIRST, before writing tags + // (cmdline is at the same GPA as multiboot info, so writing tags + // would overwrite it) + let mut cmdline_buf = [0u8; 256]; + let cmdline_len = { + let cmdline_gpa = config.arch_config.cmdline_load_gpa as GuestPhysAddr; + if cmdline_gpa != 0 { + if let Ok((cmdline_hpa, _, _)) = unsafe { gpm.page_table_query(cmdline_gpa) } { + let src = cmdline_hpa as *const u8; + let mut len = 0usize; + while len < 255 && unsafe { *src.add(len) } != 0 { + cmdline_buf[len] = unsafe { *src.add(len) }; + len += 1; + } + len + } else { + 0 + } + } else { + 0 + } + }; + + let info_ptr = info_hpa as *mut u8; + + const TAG_END: u32 = 0; + const TAG_CMDLINE: u32 = 1; + const TAG_BASIC_MEMINFO: u32 = 4; + const TAG_MMAP: u32 = 6; + const MB_MEM_AVAILABLE: u32 = 1; + const LOW_MEM_TOP: u64 = 0xC0000000; + const LOW_MMIO_TOP: u64 = 0x100000000; + + let mut offset = 8usize; + + // Tag 1: Basic memory info + let total_ram: u64 = config + .memory_regions() + .iter() + .filter(|r| r.mem_type == MEM_TYPE_RAM) + .map(|r| r.size) + .sum(); + let mem_upper_kb = if total_ram > 0x100000 { + ((total_ram - 0x100000) / 1024) as u32 + } else { + 0 + }; + unsafe { + let t = info_ptr.add(offset); + *(t as *mut u32) = TAG_BASIC_MEMINFO; + *(t.add(4) as *mut u32) = 16; + *(t.add(8) as *mut u32) = 640; + *(t.add(12) as *mut u32) = mem_upper_kb; + } + offset += 16; + + // Tag 2: Memory map. Available RAM is carved around reserved regions so + // Asterinas cannot reclaim the bootloader, kernel, cmdline, info buffer, + // or initramfs pages. + const BOOTLOADER_RESERVED_END: u64 = 0x10000; + + let entry_size = 24usize; + let mmap_hdr = offset; + offset += 16; + let mut entry_count = 0u32; + + let mut reserved: Vec<(u64, u64)> = Vec::new(); + if config.kernel_size > 0 { + let kernel_start = config.kernel_load_paddr; + reserved.push((kernel_start, kernel_start + config.kernel_size)); + } + reserved.push((info_gpa as u64, info_gpa as u64 + PAGE_SIZE as u64)); + if config.arch_config.cmdline_load_gpa != 0 + && config.arch_config.cmdline_load_gpa as u64 != info_gpa as u64 + { + let cmdline_gpa = config.arch_config.cmdline_load_gpa as u64; + reserved.push((cmdline_gpa, cmdline_gpa + PAGE_SIZE as u64)); + } + let initrd_gpa = config.arch_config.initrd_load_gpa as u64; + let initrd_size = config.arch_config.initrd_size as u64; + if initrd_size > 0 { + reserved.push((initrd_gpa, initrd_gpa + initrd_size)); + } + reserved.push((0x8000, BOOTLOADER_RESERVED_END)); + reserved.sort_unstable(); + + let mut available: Vec<(u64, u64)> = Vec::new(); + for r in config + .memory_regions() + .iter() + .filter(|r| r.mem_type == MEM_TYPE_RAM) + { + let start = r.virtual_start; + let end = start + r.size; + let mut cursor = start; + for &(reserved_start, reserved_end) in &reserved { + if reserved_end <= cursor || reserved_start >= end { + continue; + } + let s = reserved_start.max(cursor); + if s > cursor { + available.push((cursor, s.min(end))); + } + cursor = reserved_end.max(cursor); + if cursor >= end { + break; + } + } + if cursor < end { + available.push((cursor, end)); + } + } + + for (start, end) in available { + if start < LOW_MEM_TOP { + let s = start; + let e = end.min(LOW_MEM_TOP); + if e > s { + unsafe { + let p = info_ptr.add(offset); + *(p as *mut u64) = s; + *(p.add(8) as *mut u64) = e - s; + *(p.add(16) as *mut u32) = MB_MEM_AVAILABLE; + *(p.add(20) as *mut u32) = 0; + } + offset += entry_size; + entry_count += 1; + } + } + if end > LOW_MMIO_TOP { + let s = start.max(LOW_MMIO_TOP); + if end > s { + unsafe { + let p = info_ptr.add(offset); + *(p as *mut u64) = s; + *(p.add(8) as *mut u64) = end - s; + *(p.add(16) as *mut u32) = MB_MEM_AVAILABLE; + *(p.add(20) as *mut u32) = 0; + } + offset += entry_size; + entry_count += 1; + } + } + } + + let mmap_tag_size = (16 + entry_count as usize * entry_size) as u32; + unsafe { + *(info_ptr.add(mmap_hdr) as *mut u32) = TAG_MMAP; + *(info_ptr.add(mmap_hdr + 4) as *mut u32) = mmap_tag_size; + *(info_ptr.add(mmap_hdr + 8) as *mut u32) = entry_size as u32; + *(info_ptr.add(mmap_hdr + 12) as *mut u32) = 0; + } + offset = (offset + 7) & !7; + + // Tag 3: Command line (from pre-read buffer) + if cmdline_len > 0 { + let tag_size = ((8 + cmdline_len + 1 + 7) & !7) as u32; + unsafe { + *(info_ptr.add(offset) as *mut u32) = TAG_CMDLINE; + *(info_ptr.add(offset + 4) as *mut u32) = tag_size; + for i in 0..cmdline_len { + *info_ptr.add(offset + 8 + i) = cmdline_buf[i]; + } + *info_ptr.add(offset + 8 + cmdline_len) = 0; + } + offset += tag_size as usize; + } + + // Tag 4: Module (initramfs) + let initrd_gpa = config.arch_config.initrd_load_gpa as u64; + let initrd_size = config.arch_config.initrd_size as u64; + if initrd_size > 0 { + const TAG_MODULE: u32 = 3; + let mod_cmd = b"./initramfs.cpio.gz\0"; + let mod_cmd_len = mod_cmd.len(); + let tag_size = ((8 + 8 + mod_cmd_len + 7) & !7) as u32; + unsafe { + *(info_ptr.add(offset) as *mut u32) = TAG_MODULE; + *(info_ptr.add(offset + 4) as *mut u32) = tag_size; + *(info_ptr.add(offset + 8) as *mut u32) = initrd_gpa as u32; + *(info_ptr.add(offset + 12) as *mut u32) = (initrd_gpa + initrd_size) as u32; + for i in 0..mod_cmd_len { + *info_ptr.add(offset + 16 + i) = mod_cmd[i]; + } + } + offset += tag_size as usize; + } + + // End tag + unsafe { + *(info_ptr.add(offset) as *mut u32) = TAG_END; + *(info_ptr.add(offset + 4) as *mut u32) = 8; + } + offset += 8; + + // Header + unsafe { + *(info_ptr as *mut u32) = offset as u32; + *(info_ptr.add(4) as *mut u32) = 0; + } + + info!( + "Multiboot2 info: {} bytes, {} mmap entries, RAM {:#x}", + offset, entry_count, total_ram + ); + Ok(()) +} + /// copy kernel modules to the right place pub fn module_init(info_addr: usize) { println!("module_init"); + + const MAX_MODULES: usize = 16; + + #[derive(Clone, Copy)] + struct ModuleInfo { + start: usize, + end: usize, + dst: usize, + string_ptr: usize, + } + + let mut modules = [ModuleInfo { + start: 0, + end: 0, + dst: 0, + string_ptr: 0, + }; MAX_MODULES]; + let mut module_count = 0; + let mut cur = info_addr; let total_size = unsafe { *(cur as *const u32) } as usize; - - let mut cnt = 0; cur += 8; - while cur < info_addr + total_size { + while cur < info_addr + total_size && module_count < MAX_MODULES { let tag_type = unsafe { *(cur as *const u32) }; - let ptr = cur as *const multiboot_tag::Modules; - cur += ((unsafe { *((cur + 4) as *const u32) } as usize + 7) & (!7)); - if tag_type == multiboot_tag::END { break; } - if tag_type != multiboot_tag::MODULES { - continue; + if tag_type == multiboot_tag::MODULES { + let ptr = cur as *const multiboot_tag::Modules; + let module = unsafe { *ptr }; + let string_ptr = (ptr as usize) + size_of::(); + modules[module_count] = ModuleInfo { + start: module.mod_start as usize, + end: module.mod_end as usize, + dst: 0, // parse later + string_ptr, + }; + module_count += 1; } + cur += ((unsafe { *((cur + 4) as *const u32) } as usize + 7) & (!7)); + } - let module = unsafe { *ptr }; - let dst = unsafe { - usize::from_str_radix( - CStr::from_ptr(((ptr as usize) + size_of::()) as *const c_char) - .to_str() - .unwrap(), - 16, - ) - .unwrap() - }; - println!("module: {:#x?}, addr: {:#x?}", module, dst); - cnt += 1; + // parse dst + for i in 0..module_count { + let cstr = unsafe { CStr::from_ptr(modules[i].string_ptr as *const c_char) }; + modules[i].dst = usize::from_str_radix(cstr.to_str().unwrap(), 16).unwrap(); + println!( + "module: start={:#x}, end={:#x}, dst={:#x}", + modules[i].start, modules[i].end, modules[i].dst + ); + } - if dst == 0x0 { - continue; + // now move in order + let mut moved = [false; MAX_MODULES]; + let mut moved_count = 0; + while moved_count < module_count { + let mut found = false; + for i in 0..module_count { + if moved[i] { + continue; + } + let dst = modules[i].dst; + let dst_end = dst + (modules[i].end - modules[i].start); + let mut can_move = true; + for j in 0..module_count { + if moved[j] || i == j { + continue; + } + let start = modules[j].start; + let end = modules[j].end; + if dst < end && dst_end > start { + can_move = false; + break; + } + } + if can_move { + if modules[i].dst != 0 { + let size = modules[i].end - modules[i].start + 1; + let dst_end = modules[i].dst + size; + let overlaps_self = + modules[i].dst < modules[i].end && dst_end > modules[i].start; + unsafe { + if overlaps_self { + core::ptr::copy( + modules[i].start as *const u8, + modules[i].dst as *mut u8, + size, + ); + } else { + core::ptr::copy_nonoverlapping( + modules[i].start as *const u8, + modules[i].dst as *mut u8, + size, + ); + } + } + } + moved[i] = true; + moved_count += 1; + found = true; + break; + } + } + if !found { + panic!("Cannot move modules due to overlapping addresses"); } - - unsafe { - core::ptr::copy( - module.mod_start as *mut u8, - dst as *mut u8, - (module.mod_end - module.mod_start + 1) as usize, - ) - }; } - println!("module cnt: {:x}", cnt); + + println!("module cnt: {:x}", module_count); } diff --git a/src/arch/x86_64/cpu.rs b/src/arch/x86_64/cpu.rs index 808515b0e..5741dce7e 100644 --- a/src/arch/x86_64/cpu.rs +++ b/src/arch/x86_64/cpu.rs @@ -30,7 +30,7 @@ use crate::{ vmx::*, }, consts::{self, core_end, PER_CPU_SIZE}, - cpu_data::{this_cpu_data, this_zone}, + cpu_data::{this_cpu_data, this_zone, VcpuState}, device::iommu, device::irqchip::pic::{check_pending_vectors, clear_vectors, ioapic, lapic::VirtLocalApic}, error::{HvError, HvResult}, @@ -178,7 +178,6 @@ pub struct ArchCpu { guest_regs: GeneralRegisters, host_stack_top: u64, pub cpuid: usize, - pub power_on: bool, pub virt_lapic: VirtLocalApic, vmx_on: bool, vmcs_revision_id: u32, @@ -194,7 +193,6 @@ impl ArchCpu { guest_regs: GeneralRegisters::default(), host_stack_top: 0, cpuid, - power_on: false, virt_lapic: VirtLocalApic::new(), vmx_on: false, vmcs_revision_id: 0, @@ -228,7 +226,7 @@ impl ArchCpu { assert!(this_cpu_id() == self.cpuid); - self.power_on = false; + this_cpu_data().vcpu_state.store(VcpuState::Stopped); self.activate_vmx().unwrap(); // info!("idle! cpuid: {:x}", self.cpuid); @@ -270,7 +268,7 @@ impl ArchCpu { } pub fn run(&mut self) { - if self.power_on { + if this_cpu_data().vcpu_state.is_running() { // x86 wake up cpu will send ipi twice, but we only want once return; } @@ -282,7 +280,7 @@ impl ArchCpu { // info!("run! cpuid: {:x}", self.cpuid); - self.power_on = true; + per_cpu.vcpu_state.store(VcpuState::Running); self.activate_vmx().unwrap(); if !per_cpu.boot_cpu { @@ -298,7 +296,7 @@ impl ArchCpu { if per_cpu.boot_cpu { // must be called after activate_gpm() - #[cfg(feature = "intel_vtd")] + #[cfg(intel_vtd)] iommu::activate(); self.guest_regs = self.vm_launch_guest_regs.clone(); } @@ -321,6 +319,13 @@ impl ArchCpu { self.vm_launch_guest_regs.rsi = rsi; } + pub fn set_multiboot_boot_regs(&mut self, multiboot_info_addr: u64, kernel_entry: u64) { + const MULTIBOOT2_MAGIC: u64 = 0x36D76289; + self.vm_launch_guest_regs.rax = MULTIBOOT2_MAGIC; + self.vm_launch_guest_regs.rbx = multiboot_info_addr; + self.vm_launch_guest_regs.rsi = kernel_entry; + } + fn activate_vmx(&mut self) -> HvResult { if self.vmx_on { return Ok(()); @@ -385,9 +390,11 @@ impl ArchCpu { Vmcs::clear(start_paddr)?; Vmcs::load(start_paddr)?; + // Setup VMCS control fields first (includes secondary controls like UNRESTRICTED_GUEST) + // This must be done before setup_vmcs_guest so that guest state is properly initialized + self.setup_vmcs_control()?; self.setup_vmcs_host(&self.host_stack_top as *const _ as usize)?; self.setup_vmcs_guest(entry, ROOT_ZONE_BOOT_STACK)?; - self.setup_vmcs_control()?; Ok(()) } @@ -468,7 +475,7 @@ impl ArchCpu { // pass-through exceptions, set I/O bitmap and MSR bitmaps VmcsControl32::EXCEPTION_BITMAP.write(0)?; - if self.power_on { + if this_cpu_data().vcpu_state.is_running() { let pio_bitmap = get_pio_bitmap(this_zone_id()); VmcsControl64::IO_BITMAP_A_ADDR.write(pio_bitmap.a.start_paddr() as _)?; VmcsControl64::IO_BITMAP_B_ADDR.write(pio_bitmap.b.start_paddr() as _)?; @@ -535,7 +542,7 @@ impl ArchCpu { VmcsGuest64::IA32_EFER.write(0)?; // for AP start up, set CS_BASE to entry address, and RIP to 0. - if self.power_on && !this_cpu_data().boot_cpu { + if this_cpu_data().vcpu_state.is_running() && !this_cpu_data().boot_cpu { VmcsGuestNW::RIP.write(0)?; VmcsGuestNW::CS_BASE.write(entry)?; } @@ -582,7 +589,7 @@ impl ArchCpu { fn vmexit_handler(&mut self) { crate::arch::trap::handle_vmexit(self).unwrap(); - if (self.power_on) { + if this_cpu_data().vcpu_state.is_running() { check_pending_vectors(self.cpuid); } } diff --git a/src/arch/x86_64/cpuid.rs b/src/arch/x86_64/cpuid.rs index 989666d55..b76922752 100644 --- a/src/arch/x86_64/cpuid.rs +++ b/src/arch/x86_64/cpuid.rs @@ -21,6 +21,7 @@ pub enum CpuIdEax { VendorInfo = 0x0, FeatureInfo = 0x1, StructuredExtendedFeatureInfo = 0x7, + TscInfo = 0x15, ProcessorFrequencyInfo = 0x16, HypervisorInfo = 0x4000_0000, HypervisorFeatures = 0x4000_0001, diff --git a/src/arch/x86_64/entry.rs b/src/arch/x86_64/entry.rs index 2a6db8bd6..9b7a883b9 100644 --- a/src/arch/x86_64/entry.rs +++ b/src/arch/x86_64/entry.rs @@ -80,7 +80,7 @@ extern "C" fn rust_entry(magic: u32, info_addr: usize) { crate::clear_bss(); unsafe { PHYS_VIRT_OFFSET = X86_PHYS_VIRT_OFFSET }; boot::multiboot_init(info_addr); - #[cfg(all(feature = "graphics"))] + #[cfg(all(graphics))] font_init(__board::GRAPHICS_FONT); boot::print_memory_map(); rust_main(this_apic_id(), info_addr); diff --git a/src/arch/x86_64/graphics.rs b/src/arch/x86_64/graphics.rs index 2097e401f..34367850c 100644 --- a/src/arch/x86_64/graphics.rs +++ b/src/arch/x86_64/graphics.rs @@ -94,18 +94,18 @@ pub fn font_init(psf: &'static [u8]) { cursor_x: 0, cursor_y: 0, max_char_nr_x: (framebuffer.width / font_width) as _, - #[cfg(not(feature = "split_screen"))] + #[cfg(not(split_screen))] max_char_nr_y: (framebuffer.height / psf_header.height) as _, - #[cfg(all(feature = "split_screen"))] + #[cfg(all(split_screen))] max_char_nr_y: (framebuffer.height / 2 / psf_header.height) as _, - #[cfg(not(feature = "split_screen"))] + #[cfg(not(split_screen))] addr: framebuffer.addr as _, - #[cfg(all(feature = "split_screen"))] + #[cfg(all(split_screen))] addr: mid_addr as _, width: framebuffer.width as _, - #[cfg(not(feature = "split_screen"))] + #[cfg(not(split_screen))] height: framebuffer.height as _, - #[cfg(all(feature = "split_screen"))] + #[cfg(all(split_screen))] height: (framebuffer.height / 2) as _, }) }); diff --git a/src/arch/x86_64/hypercall.rs b/src/arch/x86_64/hypercall.rs index 69304786b..8a8953002 100644 --- a/src/arch/x86_64/hypercall.rs +++ b/src/arch/x86_64/hypercall.rs @@ -15,7 +15,6 @@ // Solicey use crate::{ - arch::cpu::this_cpu_id, config::CONFIG_MAGIC_VERSION, cpu_data::this_zone, device::virtio_trampoline::MAX_DEVS, @@ -25,6 +24,18 @@ use crate::{ use spin::RwLock; impl<'a> HyperCall<'a> { + pub fn hv_get_ecam_base(&mut self, ecam_base: *mut u64) -> HyperCallResult { + let ecam_base_pa = self.hv_get_real_pa(ecam_base as u64); + let base = crate::arch::acpi::root_get_config_space_info() + .map(|(base, _)| base as u64) + .unwrap_or(0); + unsafe { + *(ecam_base_pa as *mut u64) = base; + } + debug!("hvisor ecam base: {:#x}", base); + HyperCallResult::Ok(0) + } + pub fn hv_ivc_info(&mut self, ivc_info_ipa: u64) -> HyperCallResult { warn!("hv_ivc_info is not implemented for x86_64"); HyperCallResult::Ok(0) @@ -64,11 +75,6 @@ impl<'a> HyperCall<'a> { HyperCallResult::Ok(0) } - pub fn check_cpu_id(&self) { - let cpuid = this_cpu_id(); - trace!("CPU ID: {} Start Zone", cpuid); - } - pub fn hv_virtio_get_irq(&self, virtio_irq: *mut u32) -> HyperCallResult { let virtio_irq = unsafe { this_zone() diff --git a/src/arch/x86_64/idt.rs b/src/arch/x86_64/idt.rs index 97f284e50..299aa0cbf 100644 --- a/src/arch/x86_64/idt.rs +++ b/src/arch/x86_64/idt.rs @@ -24,6 +24,7 @@ const VECTOR_CNT: usize = 256; #[allow(non_snake_case)] pub mod IdtVector { + pub const I8042_KEYBOARD_VECTOR: u8 = 0x21; pub const VIRT_IPI_VECTOR: u8 = 0xef; pub const APIC_ERROR_VECTOR: u8 = 0xfc; pub const APIC_SPURIOUS_VECTOR: u8 = 0xfd; diff --git a/src/arch/x86_64/ipi.rs b/src/arch/x86_64/ipi.rs index 7de5c2cc1..67a1588d1 100644 --- a/src/arch/x86_64/ipi.rs +++ b/src/arch/x86_64/ipi.rs @@ -144,6 +144,10 @@ pub fn arch_send_event(dest: u64, _: u64) { }; } +pub fn arch_notify_event(dest: u64, vector: u64, _event_id: usize, _queue_was_empty: bool) { + arch_send_event(dest, vector); +} + pub fn handle_virt_ipi() { // this may never return! loop { @@ -164,7 +168,3 @@ pub fn arch_check_events(event: Option) { } } } - -pub fn arch_prepare_send_event(cpu_id: usize, ipi_int_id: usize, event_id: usize) { - debug!("x86_64 arch_prepare_send_event: do nothing now.") -} diff --git a/src/arch/x86_64/mod.rs b/src/arch/x86_64/mod.rs index 352805859..6f775e21a 100644 --- a/src/arch/x86_64/mod.rs +++ b/src/arch/x86_64/mod.rs @@ -43,3 +43,7 @@ pub mod zone; pub use s1pt::Stage1PageTable; pub use s2pt::stage2_mode_detect; pub use s2pt::Stage2PageTable; + +pub fn arch_config_by_args(_cpuid: usize, _host_dtb: usize) { + // Do nothing now. +} diff --git a/src/arch/x86_64/pio.rs b/src/arch/x86_64/pio.rs index f89a55643..229d41005 100644 --- a/src/arch/x86_64/pio.rs +++ b/src/arch/x86_64/pio.rs @@ -27,6 +27,7 @@ pub const UART_COM1_BASE_PORT: u16 = 0x3f8; pub const UART_COM1_PORT: Range = 0x3f8..0x400; pub const PCI_CONFIG_ADDR_PORT: Range = 0xcf8..0xcfc; pub const PCI_CONFIG_DATA_PORT: Range = 0xcfc..0xd00; +pub const I8042_PORT: Range = 0x60..0x65; static mut PIO_BITMAP_MAP: Option> = None; @@ -89,12 +90,12 @@ impl PortIoBitmap { bitmap.set_range_intercept(PCI_CONFIG_DATA_PORT, true); // if zone_id == 0 { - #[cfg(feature = "graphics")] + #[cfg(graphics)] bitmap.set_range_intercept(UART_COM1_PORT, true); // } // i8042, we won't use it, but intercept its ports might block linux init - bitmap.set_range_intercept(0x60..0x65, false); + bitmap.set_range_intercept(I8042_PORT, false); bitmap } diff --git a/src/arch/x86_64/s2pt.rs b/src/arch/x86_64/s2pt.rs index a4fe82ce8..7d62106ca 100644 --- a/src/arch/x86_64/s2pt.rs +++ b/src/arch/x86_64/s2pt.rs @@ -262,8 +262,8 @@ impl PagingInstr for S2PTInstr { unsafe { invs2pt(InvS2PTType::SingleContext, s2ptp) }; // if this cpu is boot cpu and it is running - if this_cpu_data().arch_cpu.power_on && this_cpu_data().boot_cpu { - #[cfg(feature = "intel_vtd")] + if this_cpu_data().vcpu_state.is_running() && this_cpu_data().boot_cpu { + #[cfg(intel_vtd)] iommu::fill_dma_translation_tables(this_zone_id(), root_paddr); } } diff --git a/src/arch/x86_64/trap.rs b/src/arch/x86_64/trap.rs index 9621852d8..7c7fccd4c 100644 --- a/src/arch/x86_64/trap.rs +++ b/src/arch/x86_64/trap.rs @@ -22,6 +22,7 @@ use crate::{ idt::{IdtStruct, IdtVector}, ipi, msr::Msr::{self, *}, + pio::I8042_PORT, s2pt::Stage2PageFaultInfo, vmcs::*, vmx::{VmxCrAccessInfo, VmxExitInfo, VmxExitReason, VmxInterruptInfo, VmxIoExitInfo}, @@ -102,13 +103,16 @@ pub fn arch_handle_trap(tf: &mut TrapFrame) { } fn handle_irq(vector: u8) { + let is_timer = vector == this_cpu_data().arch_cpu.virt_lapic.virt_timer_vector; + match vector { - IdtVector::VIRT_IPI_VECTOR => { + IdtVector::VIRT_IPI_VECTOR if !is_timer => { ipi::handle_virt_ipi(); } - IdtVector::APIC_SPURIOUS_VECTOR | IdtVector::APIC_ERROR_VECTOR => {} + IdtVector::I8042_KEYBOARD_VECTOR if !is_timer => {} + IdtVector::APIC_SPURIOUS_VECTOR | IdtVector::APIC_ERROR_VECTOR if !is_timer => {} _ => { - if vector >= 0x20 && this_cpu_data().arch_cpu.power_on { + if vector >= 0x20 && this_cpu_data().vcpu_state.is_running() { inject_vector(this_cpu_id(), vector, None, false); } } @@ -153,6 +157,12 @@ fn handle_cpuid(arch_cpu: &mut ArchCpu) -> HvResult { res } + CpuIdEax::TscInfo => CpuIdResult { + eax: 1, // Numerator for TSC frequency + ebx: 1, // Denominator for TSC frequency + ecx: hpet::get_tsc_freq_mhz().unwrap_or(0) * 1_000_000, // TSC frequency in Hz + edx: 0, // Reserved, typically 0 + }, CpuIdEax::ProcessorFrequencyInfo => { if let Some(freq_mhz) = hpet::get_tsc_freq_mhz() { CpuIdResult { @@ -215,6 +225,9 @@ fn handle_external_interrupt() -> HvResult { let int_info = VmxInterruptInfo::new()?; trace!("VM-exit: external interrupt: {:#x?}", int_info); assert!(int_info.valid); + if int_info.vector == 0x21 { + // info!("External interrupt: IRQ1 (keyboard)"); + } handle_irq(int_info.vector); Ok(()) } @@ -275,12 +288,14 @@ fn handle_io_instruction(arch_cpu: &mut ArchCpu, exit_info: &VmxExitInfo) -> HvR { handle_pci_config_port_write(&io_info, value); } else if UART_COM1_PORT.contains(&io_info.port) { - virt_console_io_write(io_info.port, value); - } else { - /* info!( - "unhandled port io write {:x} value: {:x}", - io_info.port, value - ); */ + if this_zone_id() == 0 { + virt_console_io_write(io_info.port, value); + } else { + virt_console_io_write(io_info.port, value); + // info!("zone1 uart write from {:x}: {:x}", io_info.port, value); + } + } else if I8042_PORT.contains(&io_info.port) { + // info!("unhandled port io write {:x} value: {:x}", io_info.port, value); } } else { if PCI_CONFIG_ADDR_PORT.contains(&io_info.port) @@ -288,7 +303,15 @@ fn handle_io_instruction(arch_cpu: &mut ArchCpu, exit_info: &VmxExitInfo) -> HvR { value = handle_pci_config_port_read(&io_info); } else if UART_COM1_PORT.contains(&io_info.port) { - value = virt_console_io_read(io_info.port); + if this_zone_id() == 0 { + value = virt_console_io_read(io_info.port); + } else { + value = 0xff; + value = virt_console_io_read(io_info.port); + // info!("zone1 uart read from {:x}: {:x}", io_info.port, value); + } + } else if I8042_PORT.contains(&io_info.port) { + value = 0xff; } else { // info!("unhandled port io read {:x}", io_info.port); value = 0x0; diff --git a/src/arch/x86_64/zone.rs b/src/arch/x86_64/zone.rs index d671fe515..6c4e53d4b 100644 --- a/src/arch/x86_64/zone.rs +++ b/src/arch/x86_64/zone.rs @@ -22,7 +22,7 @@ use crate::{ error::HvResult, memory::{GuestPhysAddr, HostPhysAddr, MemFlags, MemoryRegion, MemorySet}, platform::MEM_TYPE_RESERVED, - zone::Zone, + zone::{zone_boot_mode, Zone}, }; use alloc::vec::Vec; @@ -80,6 +80,10 @@ impl Zone { )); } MEM_TYPE_VIRTIO => { + info!( + "Registering virtio mmio region: physical_start: {:#x}, size: {:#x}", + mem_region.physical_start, mem_region.size + ); inner.mmio_region_register( mem_region.physical_start as _, mem_region.size as _, @@ -101,17 +105,34 @@ impl Zone { /// called after cpu_set is initialized pub fn arch_zone_pre_configuration(&mut self, config: &HvZoneConfig) -> HvResult { + let zone_id = config.zone_id as usize; let inner = self.read(); - inner.cpu_set().iter().for_each(|cpuid| { - let cpu_data = get_cpu_data(cpuid); - // boot cpu - if cpuid == inner.cpu_set().first_cpu().unwrap() { - cpu_data.arch_cpu.set_boot_cpu_vm_launch_regs( - config.arch_config.kernel_entry_gpa as _, - config.arch_config.setup_load_gpa as _, - ); - } - }); + let boot_mode = zone_boot_mode(zone_id); + + if zone_id != 0 && boot_mode.multiboot_enabled != 0 { + info!("[ZONE{}] Using Multiboot2 boot mode", zone_id); + + inner.cpu_set().iter().for_each(|cpuid| { + let cpu_data = get_cpu_data(cpuid); + if cpuid == inner.cpu_set().first_cpu().unwrap() { + cpu_data.arch_cpu.set_multiboot_boot_regs( + boot_mode.multiboot_info_paddr as _, + config.arch_config.kernel_entry_gpa as _, + ); + } + }); + } else { + inner.cpu_set().iter().for_each(|cpuid| { + let cpu_data = get_cpu_data(cpuid); + // boot cpu + if cpuid == inner.cpu_set().first_cpu().unwrap() { + cpu_data.arch_cpu.set_boot_cpu_vm_launch_regs( + config.arch_config.kernel_entry_gpa as _, + config.arch_config.setup_load_gpa as _, + ); + } + }); + } drop(inner); set_msr_bitmap(config.zone_id as _); @@ -148,9 +169,17 @@ impl Zone { self.pci_bars_register(&config.pci_config); }*/ - boot::BootParams::fill(&config, inner.gpm_mut()); + let boot_mode = zone_boot_mode(self.id()); + if boot_mode.multiboot_enabled != 0 { + boot::multiboot2_info_fill( + config, + inner.gpm_mut(), + boot_mode.multiboot_info_paddr as _, + )?; + } else { + boot::BootParams::fill(&config, inner.gpm_mut()); + } acpi::copy_to_guest_memory_region(&config, &inner.cpu_set()); - Ok(()) } diff --git a/src/config.rs b/src/config.rs index aecc2759e..b3c556486 100644 --- a/src/config.rs +++ b/src/config.rs @@ -23,7 +23,7 @@ pub const MEM_TYPE_RAM: u32 = 0; pub const MEM_TYPE_IO: u32 = 1; pub const MEM_TYPE_VIRTIO: u32 = 2; -pub const CONFIG_MAGIC_VERSION: usize = 0x5; +pub const CONFIG_MAGIC_VERSION: usize = 0x6; pub const CONFIG_MAX_MEMORY_REGIONS: usize = 64; pub type BitmapWord = u32; @@ -108,6 +108,14 @@ pub struct HvZoneConfig { pub alloc_pci_devs: [HvPciDevConfig; CONFIG_MAX_PCI_DEV], } +#[repr(C)] +#[derive(Debug, Clone, Copy, Default)] +pub struct HvZoneBootMode { + pub zone_id: u32, + pub multiboot_enabled: u32, + pub multiboot_info_paddr: u64, +} + impl HvZoneConfig { pub fn new( zone_id: u32, @@ -218,17 +226,23 @@ pub struct HvPciDevConfig { pub bus: u8, pub device: u8, pub function: u8, + pub v_bus: u8, + pub v_device: u8, + pub v_function: u8, pub dev_type: VpciDevType, } #[macro_export] macro_rules! pci_dev { - ($domain:expr, $bus:expr, $dev:expr, $func:expr, $dev_type:expr) => { + ($domain:expr, $bus:expr, $dev:expr, $func:expr => $v_bus:expr, $v_dev:expr, $v_func:expr, $dev_type:expr) => { HvPciDevConfig { domain: $domain, bus: $bus, device: $dev, function: $func, + v_bus: $v_bus, + v_device: $v_dev, + v_function: $v_func, dev_type: $dev_type, } }; @@ -257,6 +271,10 @@ pub struct HvDwcAtuConfig { // set 1 if io base use atu0, when hvisor need set mmio for io // normally, when num-viewport less than 4, io_cfg_atu_shared is 1, otherwise is 0 pub io_cfg_atu_shared: u64, + // choose the atu index for io and cfg access, when io_cfg_atu_shared is 1, io and cfg use the same atu index, otherwise use different atu index + pub io_atu_index: u64, + // Shared hardware interrupt ID for this DWC RC MSI block + pub dw_msi_irq: u64, } impl HvDwcAtuConfig { @@ -273,6 +291,8 @@ impl HvDwcAtuConfig { cfg_base: 0, cfg_size: 0, io_cfg_atu_shared: 0, + io_atu_index: 0, + dw_msi_irq: 0, } } } diff --git a/src/consts.rs b/src/consts.rs index 62f93785f..6014fbcfe 100644 --- a/src/consts.rs +++ b/src/consts.rs @@ -28,9 +28,15 @@ use crate::{memory::addr::VirtAddr, platform::BOARD_NCPUS}; use core::arch::global_asm; /// Size of the hypervisor heap. +#[cfg(loongson_3a6000)] +pub const HV_HEAP_SIZE: usize = 8 * 1024 * 1024; // 8 MiB +#[cfg(not(loongson_3a6000))] pub const HV_HEAP_SIZE: usize = 1024 * 1024; // 1 MiB -/// Size of the hypervisor memory pool used for dynamic allocation. +/// Size of the hypervisor memory pool used for dynamic stage-2 page tables. +#[cfg(loongson_3a6000)] +pub const HV_MEM_POOL_SIZE: usize = 0x1000_0000; // 256 MiB +#[cfg(not(loongson_3a6000))] pub const HV_MEM_POOL_SIZE: usize = 64 * 1024 * 1024; // 64 MiB /// Size of the per-CPU data area, including stack and CPU-local data. @@ -88,6 +94,10 @@ pub fn hv_end() -> VirtAddr { pub const IPI_EVENT_CLEAR_INJECT_IRQ: usize = 4; pub const IPI_EVENT_UPDATE_HART_LINE: usize = 5; pub const IPI_EVENT_SEND_IPI: usize = 6; +pub const IPI_EVENT_DWC_MSI_INJECT: usize = 9; +/// ipi events for vcpu management +pub const IPI_EVENT_VCPU_SUSPEND: usize = 7; +pub const IPI_EVENT_VCPU_RESUME: usize = 8; extern "C" { /// Entry point of the hypervisor written in assembly. diff --git a/src/cpu_data.rs b/src/cpu_data.rs index 98b1acecb..fc1519191 100644 --- a/src/cpu_data.rs +++ b/src/cpu_data.rs @@ -21,16 +21,91 @@ use crate::consts::{INVALID_ADDRESS, PER_CPU_ARRAY_PTR, PER_CPU_SIZE}; use crate::memory::addr::VirtAddr; use crate::zone::Zone; use crate::ENTERED_CPUS; -use core::fmt::Debug; -use core::sync::atomic::Ordering; +use core::fmt::{Debug, Formatter, Result}; +use core::sync::atomic::{AtomicU8, Ordering}; // global_asm!(include_str!("./arch/aarch64/page_table.S"),); +/// VCpu lifecycle states +#[repr(u8)] +#[derive(Copy, Clone, Debug, Eq, PartialEq)] +pub enum VcpuState { + /// Initial state or after PSCI CPU_OFF. Not in any run queue. + Stopped = 0, + /// In a pCPU's run queue, waiting to be scheduled. + Ready = 1, + /// Currently executing on a pCPU. + Running = 2, + /// Blocked by WFI/CPU_SUSPEND. Not in any run queue, awaiting interrupt wakeup. + Blocked = 3, +} + +impl VcpuState { + fn from_raw(value: u8) -> Self { + match value { + 0 => Self::Stopped, + 1 => Self::Ready, + 2 => Self::Running, + 3 => Self::Blocked, + _ => panic!("invalid vcpu state {}", value), + } + } +} + +#[repr(transparent)] +pub struct VcpuStateCell { + state: AtomicU8, +} + +impl VcpuStateCell { + pub const fn new(state: VcpuState) -> Self { + Self { + state: AtomicU8::new(state as u8), + } + } + + pub fn load(&self) -> VcpuState { + VcpuState::from_raw(self.state.load(Ordering::Acquire)) + } + + pub fn store(&self, state: VcpuState) { + self.state.store(state as u8, Ordering::Release); + } + + pub fn is_stopped(&self) -> bool { + self.load() == VcpuState::Stopped + } + + pub fn is_ready(&self) -> bool { + self.load() == VcpuState::Ready + } + + pub fn is_running(&self) -> bool { + self.load() == VcpuState::Running + } + + pub fn is_blocked(&self) -> bool { + self.load() == VcpuState::Blocked + } + + /// Logical CPU is up from the hypervisor’s view: not `Stopped` (includes Ready, Running, Blocked). + pub fn is_online(&self) -> bool { + !self.is_stopped() + } +} + +impl Debug for VcpuStateCell { + fn fmt(&self, f: &mut Formatter<'_>) -> Result { + self.load().fmt(f) + } +} + #[repr(C)] pub struct PerCpu { pub id: usize, pub cpu_on_entry: usize, pub dtb_ipa: usize, + pub vcpu_state: VcpuStateCell, pub arch_cpu: ArchCpu, pub zone: Option>, pub ctrl_lock: Mutex<()>, @@ -48,6 +123,7 @@ impl PerCpu { id: arch_cpu.cpuid, cpu_on_entry: INVALID_ADDRESS, dtb_ipa: INVALID_ADDRESS, + vcpu_state: VcpuStateCell::new(VcpuState::Stopped), arch_cpu, zone: None, ctrl_lock: Mutex::new(()), @@ -104,6 +180,54 @@ pub fn this_zone() -> Arc { this_cpu_data().zone.clone().unwrap() } +/// Enter blocked state and wait until another CPU resumes it. +#[allow(unused)] +pub fn vcpu_suspend() { + info!("cpu {} suspending...", this_cpu_data().id); + this_cpu_data().vcpu_state.store(VcpuState::Blocked); + loop { + // TODO: use wfi to optimize the loop + if !this_cpu_data().vcpu_state.is_blocked() { + break; + } + core::hint::spin_loop(); + } + // Remote sets `Ready` to leave Blocked; this hart then marks itself `Running` again. + this_cpu_data().vcpu_state.store(VcpuState::Running); + info!("cpu {} resumed from suspend.", this_cpu_data().id); +} + +/// Wait for other CPUs in the cpu set to enter Blocked state. +#[allow(unused)] +pub fn wait_for_other_vcpus_suspend(cpu_set: CpuSet) { + let this_cpu_id = this_cpu_id(); + for target_cpu_id in cpu_set.iter() { + if target_cpu_id == this_cpu_id { + continue; + } + loop { + if get_cpu_data(target_cpu_id).vcpu_state.is_blocked() { + break; + } + core::hint::spin_loop(); + } + } +} + +/// Signal other CPUs in the cpu set to resume from Blocked. +#[allow(unused)] +pub fn signal_other_vcpus_resume(cpu_set: CpuSet) { + let this_cpu_id = this_cpu_id(); + for target_cpu_id in cpu_set.iter() { + if target_cpu_id == this_cpu_id { + continue; + } + get_cpu_data(target_cpu_id) + .vcpu_state + .store(VcpuState::Ready); + } +} + #[repr(C)] #[derive(Copy, Clone, Debug)] pub struct CpuSet { diff --git a/src/device/iommu/arm_smmu/mod.rs b/src/device/iommu/arm_smmu/mod.rs index b395483b6..8f113f275 100644 --- a/src/device/iommu/arm_smmu/mod.rs +++ b/src/device/iommu/arm_smmu/mod.rs @@ -84,7 +84,13 @@ impl Iommu for ArmSmmu { zone_id ); } - fn viommu_mmio_handler(&self, zone: &mut Zone, viommu_base: usize, viommu_size: usize) { + fn viommu_remove(&self, zone_id: usize) { + todo!( + "ArmSmmu viommu remove for zone id {} not implemented yet.", + zone_id + ); + } + fn viommu_mmio_handler_register(&self, zone: &Zone, _viommu_base: usize, _viommu_size: usize) { todo!( "ArmSmmu viommu handler for zone id {} not implemented yet.", zone.id() diff --git a/src/device/iommu/arm_smmu/smmu_hw.rs b/src/device/iommu/arm_smmu/smmu_hw.rs index fe7b3244a..4b431898a 100644 --- a/src/device/iommu/arm_smmu/smmu_hw.rs +++ b/src/device/iommu/arm_smmu/smmu_hw.rs @@ -194,6 +194,7 @@ impl LinearStreamTable { self.sid_max_bits } + #[allow(clippy::mut_from_ref)] fn ste(&self, sid: usize) -> &mut StreamTableEntry { let base = self.base + sid * STRTAB_STE_SIZE; unsafe { &mut *(base as *mut StreamTableEntry) } @@ -424,9 +425,9 @@ impl Smmuv3 { frame_count, 5 + self.strtab.sid_max_bits ); - if let Ok(frame) = - Frame::new_contiguous_with_base(frame_count, 5 + self.strtab.sid_max_bits) - { + let align_log2 = + (5 + self.strtab.sid_max_bits).saturating_sub(PAGE_SIZE.trailing_zeros() as usize); + if let Ok(frame) = Frame::new_contiguous_with_base(frame_count, align_log2) { self.strtab.init_with_base(frame.start_paddr(), frame); } else { error!("stream table frames alloc err!!!") @@ -529,13 +530,13 @@ impl Smmuv3 { static SMMUV3: spin::Once> = spin::Once::new(); /// iommu feature is disabled. -#[cfg(not(feature = "iommu"))] +#[cfg(not(iommu))] pub fn iommu_init() { info!("aarch64: iommu_init: do nothing now"); } /// smmuv3 init (enabled) -#[cfg(feature = "iommu")] +#[cfg(iommu)] pub fn iommu_init() { info!("Smmuv3 init..."); SMMUV3.call_once(|| Mutex::new(Smmuv3::new())); diff --git a/src/device/iommu/dummy_iommu.rs b/src/device/iommu/dummy_iommu.rs index 4e7f072e8..125d3eb93 100644 --- a/src/device/iommu/dummy_iommu.rs +++ b/src/device/iommu/dummy_iommu.rs @@ -48,7 +48,10 @@ impl Iommu for DummyIommu { fn viommu_init(&self, zone_id: usize) { info!("No IOMMU implementation available, cannot initialize VIOMMU for Zone id {}", zone_id); } - fn viommu_mmio_handler(&self, zone: &mut Zone, _viommu_base: usize, _viommu_size: usize) { + fn viommu_remove(&self, zone_id: usize) { + info!("No IOMMU implementation available, cannot remove VIOMMU for Zone id {}", zone_id); + } + fn viommu_mmio_handler_register(&self, zone: &Zone, _viommu_base: usize, _viommu_size: usize) { info!("No IOMMU implementation available, cannot handle VIOMMU MMIO for Zone id {}", zone.id()); } } diff --git a/src/device/iommu/intel_vtd/mod.rs b/src/device/iommu/intel_vtd/mod.rs index 9470724d1..c99107465 100644 --- a/src/device/iommu/intel_vtd/mod.rs +++ b/src/device/iommu/intel_vtd/mod.rs @@ -85,7 +85,13 @@ impl Iommu for IntelVtd { zone_id ); } - fn viommu_mmio_handler(&self, zone: &mut Zone, viommu_base: usize, viommu_size: usize) { + fn viommu_remove(&self, zone_id: usize) { + todo!( + "IntelVtd viommu remove for zone id {} not implemented yet.", + zone_id + ); + } + fn viommu_mmio_handler_register(&self, zone: &Zone, _viommu_base: usize, _viommu_size: usize) { todo!( "IntelVtd viommu handler for zone id {} not implemented yet.", zone.id() diff --git a/src/device/iommu/iommu_impl.rs b/src/device/iommu/iommu_impl.rs index eac9ea16e..49e0d3698 100644 --- a/src/device/iommu/iommu_impl.rs +++ b/src/device/iommu/iommu_impl.rs @@ -24,17 +24,17 @@ static IOMMU_IMPL: Once> = Once::new(); // Dispatch to the appropriate IOMMU implementation based on hardware support fn iommu_impl_init() -> Box { - #[cfg(feature = "arm_smmu")] + #[cfg(arm_smmu)] return Box::new(super::arm_smmu::ArmSmmu); - #[cfg(feature = "intel_vtd")] + #[cfg(intel_vtd)] return Box::new(super::intel_vtd::IntelVtd); - #[cfg(feature = "riscv_iommu")] + #[cfg(riscv_iommu)] return Box::new(super::riscv_iommu::RiscvIommu); // Default return DummyIommu if no IOMMU support - #[cfg(not(any(feature = "arm_smmu", feature = "intel_vtd", feature = "riscv_iommu",)))] + #[cfg(not(any(arm_smmu, intel_vtd, riscv_iommu)))] return Box::new(super::dummy_iommu::DummyIommu); } diff --git a/src/device/iommu/iommu_trait.rs b/src/device/iommu/iommu_trait.rs index 9cef4b6cc..c992905be 100644 --- a/src/device/iommu/iommu_trait.rs +++ b/src/device/iommu/iommu_trait.rs @@ -36,6 +36,8 @@ pub(crate) trait Iommu { fn interrupt_handler(&self, irq_id: usize); /// Initialize the Virtual IOMMU for the Zone fn viommu_init(&self, zone_id: usize); - /// Virtual IOMMU MMIO handler for the Zone - fn viommu_mmio_handler(&self, zone: &mut Zone, viommu_base: usize, viommu_size: usize); + /// Remove the Virtual IOMMU for the Zone + fn viommu_remove(&self, zone_id: usize); + /// Register the Virtual IOMMU MMIO handler for the Zone + fn viommu_mmio_handler_register(&self, zone: &Zone, viommu_base: usize, viommu_size: usize); } diff --git a/src/device/iommu/mod.rs b/src/device/iommu/mod.rs index 548bc3922..0bb463914 100644 --- a/src/device/iommu/mod.rs +++ b/src/device/iommu/mod.rs @@ -22,16 +22,17 @@ mod iommu_impl; mod iommu_trait; use crate::consts::MAX_ZONE_NUM; +use crate::zone::Zone; use iommu_impl::iommu_impl; use iommu_trait::Iommu; -#[cfg(feature = "arm_smmu")] +#[cfg(arm_smmu)] mod arm_smmu; -#[cfg(not(any(feature = "arm_smmu", feature = "intel_vtd", feature = "riscv_iommu")))] +#[cfg(not(any(arm_smmu, intel_vtd, riscv_iommu)))] mod dummy_iommu; -#[cfg(feature = "intel_vtd")] +#[cfg(intel_vtd)] mod intel_vtd; -#[cfg(feature = "riscv_iommu")] +#[cfg(riscv_iommu)] mod riscv_iommu; fn check_zone_id(zone_id: usize) -> Result<(), &'static str> { @@ -60,32 +61,60 @@ pub fn iommu_add_device_with_root_pt_addr(zone_id: usize, did: usize, root_pt_ad } } +/// Public interface for initializing the Virtual IOMMU for the Zone +pub(crate) fn viommu_init(zone_id: usize) { + match check_zone_id(zone_id) { + Ok(()) => { + iommu_impl().viommu_init(zone_id); + } + Err(e) => { + warn!("{}", e); + } + } +} + +/// Public interface for removing the Virtual IOMMU for the Zone +pub(crate) fn viommu_remove(zone_id: usize) { + match check_zone_id(zone_id) { + Ok(()) => { + iommu_impl().viommu_remove(zone_id); + } + Err(e) => { + warn!("{}", e); + } + } +} + +pub(crate) fn viommu_mmio_handler_register(zone: &Zone, viommu_base: usize, viommu_size: usize) { + iommu_impl().viommu_mmio_handler_register(zone, viommu_base, viommu_size); +} + ///////////////////////////////////////////////////////////////////////// // Below pub apis are used for compatibility for old code(for x86_64) // // These apis will be replaced by IOMMU trait later. // //////////////////////////////////////////////////////////////////////// -#[cfg(feature = "intel_vtd")] +#[cfg(intel_vtd)] pub fn clear_dma_translation_tables(zone_id: usize) { intel_vtd::clear_dma_translation_tables(zone_id); } -#[cfg(feature = "intel_vtd")] +#[cfg(intel_vtd)] pub fn fill_dma_translation_tables(zone_id: usize, zone_s2pt_hpa: crate::memory::HostPhysAddr) { intel_vtd::fill_dma_translation_tables(zone_id, zone_s2pt_hpa); } /// should be called after gpm is activated -#[cfg(feature = "intel_vtd")] +#[cfg(intel_vtd)] pub fn activate() { intel_vtd::activate(); } -#[cfg(feature = "intel_vtd")] +#[cfg(intel_vtd)] pub fn flush(zone_id: usize, bus: u8, dev_func: u8) { intel_vtd::flush(zone_id, bus, dev_func); } -#[cfg(feature = "riscv_iommu")] +#[cfg(riscv_iommu)] pub fn iommu_msi_pt_tlb_invalid(zone_id: u16, msi_gpa: usize) { riscv_iommu::iommu_msi_pt_tlb_invalid(zone_id, msi_gpa); } diff --git a/src/device/iommu/riscv_iommu/cmd.rs b/src/device/iommu/riscv_iommu/cmd.rs index 128881b06..668e96367 100644 --- a/src/device/iommu/riscv_iommu/cmd.rs +++ b/src/device/iommu/riscv_iommu/cmd.rs @@ -16,9 +16,9 @@ #![allow(unused)] -const IOTINVAL_OPCODE: u8 = 1; -const IOFENCE_OPCODE: u8 = 2; -const IODIR_OPCODE: u8 = 3; +pub(super) const IOTINVAL_OPCODE: u8 = 1; +pub(super) const IOFENCE_OPCODE: u8 = 2; +pub(super) const IODIR_OPCODE: u8 = 3; // Dword0 and dword1 are the two 64-bit words that make up the command. #[derive(Clone, Copy, Debug, Default, Eq, PartialEq)] @@ -41,7 +41,7 @@ pub(super) enum IotInvalFunc { } impl IotInvalFunc { - fn raw(self) -> u8 { + pub(super) fn raw(self) -> u8 { match self { Self::Vma => 0, Self::Gvma => 1, @@ -103,7 +103,7 @@ pub(super) enum IoFenceFunc { } impl IoFenceFunc { - fn raw(self) -> u8 { + pub(super) fn raw(self) -> u8 { match self { Self::C => 0, } @@ -150,7 +150,7 @@ pub(super) enum IoDirFunc { } impl IoDirFunc { - fn raw(self) -> u8 { + pub(super) fn raw(self) -> u8 { match self { Self::InvalDdt => 0, Self::InvalPdt => 1, diff --git a/src/device/iommu/riscv_iommu/iommu_hw.rs b/src/device/iommu/riscv_iommu/iommu_hw.rs index 0b1386fd2..97262ac86 100644 --- a/src/device/iommu/riscv_iommu/iommu_hw.rs +++ b/src/device/iommu/riscv_iommu/iommu_hw.rs @@ -113,15 +113,15 @@ fn get_iommu<'a>() -> &'a Mutex { /// Initialize IOMMU with default mode pub fn iommu_init() { - #[cfg(feature = "iommu")] + #[cfg(iommu)] riscv_iommu_init(); - #[cfg(not(feature = "iommu"))] + #[cfg(not(iommu))] info!("RISC-V IOMMU: do nothing now"); } /// Add a device to IOMMU pub fn iommu_add_device(vm_id: usize, device_id: usize, root_pt: usize) { - #[cfg(feature = "iommu")] + #[cfg(iommu)] { info!( "RV IOMMU: Add device, root_pt {:#x}, vm_id {}, device_id {}", @@ -130,13 +130,13 @@ pub fn iommu_add_device(vm_id: usize, device_id: usize, root_pt: usize) { let iommu = get_iommu(); iommu.lock().rv_iommu_add_device(device_id, vm_id, root_pt); } - #[cfg(not(feature = "iommu"))] + #[cfg(not(iommu))] info!("RISC-V: iommu_add_device do nothing now"); } /// Remove a device from IOMMU (reserved for future hot-unplug paths). pub fn iommu_remove_device(vm_id: usize, device_id: usize) { - #[cfg(feature = "iommu")] + #[cfg(iommu)] { info!( "RV IOMMU: Remove device, vm_id {}, device_id {}", @@ -145,12 +145,12 @@ pub fn iommu_remove_device(vm_id: usize, device_id: usize) { let iommu = get_iommu(); iommu.lock().rv_iommu_remove_device(device_id); } - #[cfg(not(feature = "iommu"))] + #[cfg(not(iommu))] info!("RISC-V: iommu_remove_device do nothing now"); } pub fn iommu_msi_pt_tlb_invalid(gscid: u16, msi_gpa: usize) { - #[cfg(feature = "iommu")] + #[cfg(iommu)] { // If software changes a MSI page-table entry identified by interrupt file number I that corresponds to an // untranslated MSI address A then the following invalidations must be performed: @@ -170,10 +170,92 @@ pub fn iommu_msi_pt_tlb_invalid(gscid: u16, msi_gpa: usize) { let iommu = get_iommu(); iommu.lock().rv_iommu_msi_pt_tlb_invalid(gscid, msi_gpa); } - #[cfg(not(feature = "iommu"))] + #[cfg(not(iommu))] info!("RISC-V: iommu_msi_pt_tlb_invalid do nothing now"); } +/// IOMMU register enumeration, used to access IOMMU registers for viommu module. +#[derive(Clone, Copy, Debug, Eq, PartialEq)] +pub(super) enum IommuReg { + Caps, + Fctl, + Cqcsr, + Fqcsr, + Ipsr, + Icvec, +} + +pub(super) fn iommu_read_reg(reg: IommuReg) -> u64 { + let iommu = get_iommu().lock(); + let hw = iommu.iommu(); + + match reg { + IommuReg::Caps => hw.caps.get(), + IommuReg::Fctl => hw.fctl.get() as u64, + IommuReg::Cqcsr => hw.cqcsr.get() as u64, + IommuReg::Fqcsr => hw.fqcsr.get() as u64, + IommuReg::Ipsr => hw.ipsr.get() as u64, + IommuReg::Icvec => hw.icvec.get(), + } +} + +pub(super) fn iommu_write_reg(reg: IommuReg, value: u64) { + let iommu = get_iommu().lock(); + let hw = iommu.iommu(); + + match reg { + IommuReg::Cqcsr => hw.cqcsr.set(value as u32), + IommuReg::Fqcsr => hw.fqcsr.set(value as u32), + IommuReg::Ipsr => hw.ipsr.set(value as u32), + IommuReg::Icvec => hw.icvec.set(value), + IommuReg::Caps | IommuReg::Fctl => { + warn!( + "RV IOMMU: ignore unsupported write to mirrored register {:?}", + reg + ); + } + } +} + +/// Add a raw command to physical IOMMU command queue. +pub(super) fn iommu_add_raw_command(command: RiscvIommuCommand) { + get_iommu().lock().rv_iommu_add_command(command); +} + +/// Device directory table field enumeration, used to access device directory table fields for viommu module. +#[derive(Clone, Copy, Debug, Eq, PartialEq)] +pub(super) enum IommuDdtField { + Iohgatp, + Ta, + Fsc, +} + +/// Read a specific device directory table entry field. +pub(super) fn iommu_read_ddt_field(device_id: usize, field: IommuDdtField) -> Option { + let mut iommu = get_iommu().lock(); + let (entry, _) = iommu.ddt.get_or_alloc_leaf_entry(device_id)?; + + Some(match field { + IommuDdtField::Iohgatp => entry.iohgatp.get(), + IommuDdtField::Ta => entry.ta.get(), + IommuDdtField::Fsc => entry.fsc.get(), + }) +} + +/// Write a specific device directory table entry field. +pub(super) fn iommu_write_ddt_field(device_id: usize, field: IommuDdtField, value: u64) -> bool { + let mut iommu = get_iommu().lock(); + if let Some((entry, _)) = iommu.ddt.get_or_alloc_leaf_entry(device_id) { + match field { + IommuDdtField::Iohgatp => entry.iohgatp.set(value), + IommuDdtField::Ta => entry.ta.set(value), + IommuDdtField::Fsc => entry.fsc.set(value), + } + return true; + } + false +} + /// Initialize RISC-V IOMMU with hardware DDTP probing. fn riscv_iommu_init() { assert!( @@ -240,13 +322,17 @@ impl IommuHw { } fn rv_iommu_check_features(&self) { - let version = self.caps.read(IOMMU_CAPS::VERSION); // Stop and report failure if capabilities.version is not supported. - if version != IOMMU_CAPS::VERSION::VERSION_1_0.value { - panic!( - "RISC-V IOMMU unsupported version: {}, Please check the IOMMU version", - version - ); + match self.caps.read_as_enum(IOMMU_CAPS::VERSION) { + Some(IOMMU_CAPS::VERSION::Value::VERSION_1_0) => { + info!("RISC-V IOMMU version 1.0 supported"); + } + _ => { + panic!( + "RISC-V IOMMU unsupported version: {}, Please check the IOMMU version", + self.caps.read(IOMMU_CAPS::VERSION) + ); + } } // Note: here RISCV-IOMMU and CPU share the same stage-2 page table. let cpu_s2pt_lvl = unsafe { crate::arch::s2pt::GSTAGE_PT_LEVEL }; @@ -264,9 +350,6 @@ impl IommuHw { // Current DDT Entry only supports Extented-for todo!("To support Base-format DDT Entry"); } - if self.caps.read(IOMMU_CAPS::IGS) == IOMMU_CAPS::IGS::MSI.value { - warn!("RISC-V IOMMU HW does not support WSI generation"); - } } fn rv_iommu_init( diff --git a/src/device/iommu/riscv_iommu/mod.rs b/src/device/iommu/riscv_iommu/mod.rs index 5a5f1b8a8..dd8232042 100644 --- a/src/device/iommu/riscv_iommu/mod.rs +++ b/src/device/iommu/riscv_iommu/mod.rs @@ -30,12 +30,16 @@ mod cmd; mod iommu_hw; mod reg_bits; +#[cfg(viommu)] +mod viommu; use super::Iommu; use crate::zone::Zone; use cmd::*; use iommu_hw::*; pub use iommu_hw::{iommu_msi_pt_tlb_invalid, iommu_remove_device}; +#[cfg(viommu)] +use viommu::{viommu_init, viommu_mmio_handler_register, viommu_remove}; pub(super) struct RiscvIommu; @@ -81,15 +85,27 @@ impl Iommu for RiscvIommu { ); } fn viommu_init(&self, zone_id: usize) { - todo!( - "RiscvIommu viommu init for zone id {} not implemented yet.", + #[cfg(viommu)] + viommu_init(zone_id); + #[cfg(not(viommu))] + warn!( + "Virtual IOMMU is not enabled, skipping viommu init for zone {}", zone_id ); } - fn viommu_mmio_handler(&self, zone: &mut Zone, _viommu_base: usize, _viommu_size: usize) { - todo!( - "RiscvIommu viommu handler for zone id {} not implemented yet.", - zone.id() + fn viommu_remove(&self, zone_id: usize) { + #[cfg(viommu)] + viommu_remove(zone_id); + #[cfg(not(viommu))] + warn!( + "Virtual IOMMU is not enabled, skipping viommu remove for zone {}", + zone_id ); } + fn viommu_mmio_handler_register(&self, zone: &Zone, viommu_base: usize, viommu_size: usize) { + #[cfg(viommu)] + viommu_mmio_handler_register(zone, viommu_base, viommu_size); + #[cfg(not(viommu))] + warn!("Virtual IOMMU is not enabled, skipping viommu mmio handler for zone {}, viommu_base {}, viommu_size {}.", zone.id(), viommu_base, viommu_size); + } } diff --git a/src/device/iommu/riscv_iommu/reg_bits.rs b/src/device/iommu/riscv_iommu/reg_bits.rs index 932735893..d4b093b50 100644 --- a/src/device/iommu/riscv_iommu/reg_bits.rs +++ b/src/device/iommu/riscv_iommu/reg_bits.rs @@ -54,7 +54,7 @@ register_bitfields! { NL OFFSET(42) NUMBITS(1) [], S OFFSET(43) NUMBITS(1) [], ], - pub(super) IOMMU_DDTP [ // RISCV-IOMMU Spec Chap6.5 Device-directory table pointer + pub(super) IOMMU_DDTP [ // RISC-V IOMMU Spec Chap6.5 Device-directory table pointer MODE OFFSET(0) NUMBITS(4) [ OFF = 0, BARE = 1, @@ -65,7 +65,7 @@ register_bitfields! { BUSY OFFSET(4) NUMBITS(1) [], PPN OFFSET(10) NUMBITS(44) [] ], - pub(super) DDT_TC [ // RISCV-IOMMU Spec Chap3.1.3.1 Translation Control + pub(super) DDT_TC [ // RISC-V IOMMU Spec Chap3.1.3.1 Translation Control V OFFSET(0) NUMBITS(1) [], EN_ATS OFFSET(1) NUMBITS(1) [], EN_PRI OFFSET(2) NUMBITS(1) [], @@ -79,7 +79,7 @@ register_bitfields! { SBE OFFSET(10) NUMBITS(1) [], SXL OFFSET(11) NUMBITS(1) [] ], - pub(super) DDT_IOHGATP [ // RISCV-IOMMU Spec Chap3.1.3.2 IO hypervisor guest address translation and protection + pub(super) DDT_IOHGATP [ // RISC-V IOMMU Spec Chap3.1.3.2 IO hypervisor guest address translation and protection PPN OFFSET(0) NUMBITS(44) [], GSCID OFFSET(44) NUMBITS(16) [], MODE OFFSET(60) NUMBITS(4) [ @@ -88,12 +88,12 @@ register_bitfields! { SV57X4 = 10 ] ], - pub(super) DDT_TA [ // RISCV-IOMMU Spec Chap3.1.3.3 Translation attributes + pub(super) DDT_TA [ // RISC-V IOMMU Spec Chap3.1.3.3 Translation attributes PS_CID OFFSET(12) NUMBITS(20) [], RCID OFFSET(40) NUMBITS(12) [], MTYPE OFFSET(52) NUMBITS(12) [], ], - pub(super) DDT_FSC [ // RISCV-IOMMU Spec Chap3.1.3.4 First-stage context + pub(super) DDT_FSC [ // RISC-V IOMMU Spec Chap3.1.3.4 First-stage context MODE OFFSET(60) NUMBITS(4) [ BARE = 0, SV39 = 8, @@ -102,12 +102,12 @@ register_bitfields! { ], PPN OFFSET(0) NUMBITS(44) [] ], - pub(super) DDT_DIR [ // RISCV-IOMMU Spec Chap3.1.1 Non-leaf DDT entry + pub(super) DDT_DIR [ // RISC-V IOMMU Spec Chap3.1.1 Non-leaf DDT entry V OFFSET(0) NUMBITS(1) [], PPN OFFSET(10) NUMBITS(44) [] ], pub(super) IOMMU_XQB [ // RISC-V IOMMU Spec Chap6.6 Command-queue base - // RISC-V IOMMU Spec Chap6.9 Fault queue base + // RISC-V IOMMU Spec Chap6.9 Fault queue base LOG2SZ_1 OFFSET(0) NUMBITS(5) [], PPN OFFSET(10) NUMBITS(44) [] ], @@ -123,12 +123,12 @@ register_bitfields! { register_bitfields! { u32, - pub(super) IOMMU_FCTL [ // RISCV-IOMMU Spec Chap6.4 Features-control register + pub(super) IOMMU_FCTL [ // RISC-V IOMMU Spec Chap6.4 Features-control register BE OFFSET(0) NUMBITS(1) [], WSI OFFSET(1) NUMBITS(1) [], GXL OFFSET(2) NUMBITS(1) [], ], - pub(super) IOMMU_CQCSR [ // RISCV-IOMMU Spec Chap6.15 Command-queue CSR + pub(super) IOMMU_CQCSR [ // RISC-V IOMMU Spec Chap6.15 Command-queue CSR CQEN OFFSET(0) NUMBITS(1) [], CIE OFFSET(1) NUMBITS(1) [], CQMF OFFSET(8) NUMBITS(1) [], @@ -138,7 +138,7 @@ register_bitfields! { CQON OFFSET(16) NUMBITS(1) [], BUSY OFFSET(17) NUMBITS(1) [], ], - pub(super) IOMMU_FQCSR [ // RISCV-IOMMU Spec Chap6.16 Fault-queue CSR + pub(super) IOMMU_FQCSR [ // RISC-V IOMMU Spec Chap6.16 Fault-queue CSR FQEN OFFSET(0) NUMBITS(1) [], FIE OFFSET(1) NUMBITS(1) [], FQMF OFFSET(8) NUMBITS(1) [], @@ -146,7 +146,7 @@ register_bitfields! { FQON OFFSET(16) NUMBITS(1) [], BUSY OFFSET(17) NUMBITS(1) [], ], - pub(super) IOMMU_IPSR [ // RISCV-IOMMU Spec Chap6.18 Interrupt pending status register + pub(super) IOMMU_IPSR [ // RISC-V IOMMU Spec Chap6.18 Interrupt pending status register CIP OFFSET(0) NUMBITS(1) [], FIP OFFSET(1) NUMBITS(1) [], PMIP OFFSET(2) NUMBITS(1) [], diff --git a/src/device/iommu/riscv_iommu/viommu.rs b/src/device/iommu/riscv_iommu/viommu.rs new file mode 100644 index 000000000..f22edb624 --- /dev/null +++ b/src/device/iommu/riscv_iommu/viommu.rs @@ -0,0 +1,857 @@ +// Copyright (c) 2025 Syswonder +// hvisor is licensed under Mulan PSL v2. +// You can use this software according to the terms and conditions of the Mulan PSL v2. +// You may obtain a copy of Mulan PSL v2 at: +// http://license.coscl.org.cn/MulanPSL2 +// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR +// FIT FOR A PARTICULAR PURPOSE. +// See the Mulan PSL v2 for more details. +// +// Syswonder Website: +// https://www.syswonder.org +// +// Authors: +// Jingyu Liu for IommuMode { + type Error = (); + + fn try_from(value: usize) -> Result { + match value as u8 { + 0 => Ok(Self::Off), + 1 => Ok(Self::Bare), + 2 => Ok(Self::Ddt1Lvl), + 3 => Ok(Self::Ddt2Lvl), + 4 => Ok(Self::Ddt3Lvl), + _ => Err(()), + } + } +} + +#[derive(Clone, Copy, Debug, Eq, PartialEq)] +enum ViommuRegion { + Regs, + Ddt, +} + +impl ViommuRegion { + fn label(self) -> &'static str { + match self { + Self::Regs => "", + Self::Ddt => "ddt ", + } + } +} + +#[derive(Clone, Copy, Debug, Eq, PartialEq)] +enum MmioAccessType { + Read, + Write, +} + +impl MmioAccessType { + fn from_is_write(is_write: bool) -> Self { + if is_write { + Self::Write + } else { + Self::Read + } + } +} + +lazy_static! { + /// Global viommu array, one viommu instance for each zone. + static ref VIOMMU_ARR: Mutex>>> = + Mutex::new(vec![None; MAX_ZONE_NUM]); +} + +fn validate_zone_id(zone_id: usize) -> bool { + if zone_id >= MAX_ZONE_NUM { + error!("Invalid zone id: {}", zone_id); + return false; + } + true +} + +/// Create one viommu instance for target zone. +pub(super) fn viommu_init(zone_id: usize) { + if !validate_zone_id(zone_id) { + return; + } + + let mut viommu_arr = VIOMMU_ARR.lock(); + if viommu_arr[zone_id].is_some() { + warn!("Zone {}'s Virtual IOMMU already initialized.", zone_id); + return; + } + viommu_arr[zone_id] = Some(Arc::new(VirtualIommu::new())); + info!("Zone {}'s Virtual IOMMU initialized.", zone_id); +} + +/// Remove one viommu instance for target zone and clear its physical DDT side effects. +pub(super) fn viommu_remove(zone_id: usize) { + if !validate_zone_id(zone_id) { + return; + } + + let viommu = { + let mut viommu_arr = VIOMMU_ARR.lock(); + viommu_arr[zone_id].take() + }; + + let Some(viommu) = viommu else { + warn!("Zone {}'s Virtual IOMMU does not exist.", zone_id); + return; + }; + + // Clean some content stored in memory related to this viommu. + viommu.cleanup_physical_ddt(); + info!("Zone {}'s Virtual IOMMU removed.", zone_id); +} + +/// Register viommu mmio handler for target zone. +pub(super) fn viommu_mmio_handler_register(zone: &Zone, viommu_base: usize, viommu_size: usize) { + zone.write() + .mmio_region_register(viommu_base, viommu_size, viommu_emul_handler, zone.id()); +} + +/// Handle Zone's iommu mmio access. +fn viommu_emul_handler(mmio: &mut MMIOAccess, zone_id: usize) -> HvResult { + viommu_mmio_emul_handler(mmio, zone_id, ViommuRegion::Regs) +} + +fn get_viommu_by_zone_id(zone_id: usize) -> Option> { + if !validate_zone_id(zone_id) { + return None; + } + let viommu_array = VIOMMU_ARR.lock(); + // ref, don't move viommu out of the array + match &viommu_array[zone_id] { + Some(viommu) => Some(Arc::clone(viommu)), + None => { + error!("VirtualIommu for Zone {} does not exist!", zone_id); + None + } + } +} + +/// Handle Zone's iommu ddt mmio access. +fn viommu_ddt_emul_handler(mmio: &mut MMIOAccess, zone_id: usize) -> HvResult { + viommu_mmio_emul_handler(mmio, zone_id, ViommuRegion::Ddt) +} + +fn viommu_mmio_emul_handler( + mmio: &mut MMIOAccess, + zone_id: usize, + region: ViommuRegion, +) -> HvResult { + let Some(viommu) = get_viommu_by_zone_id(zone_id) else { + warn!( + "vIOMMU {}mmio access for non-initialized zone {}", + region.label(), + zone_id + ); + return Ok(()); + }; + let Some(zone) = find_zone(zone_id) else { + warn!( + "vIOMMU {}mmio access for unknown zone {}", + region.label(), + zone_id + ); + return Ok(()); + }; + let access = MmioAccessType::from_is_write(mmio.is_write); + let value = match region { + ViommuRegion::Regs => { + viommu.viommu_emul_access(&zone, mmio.address, mmio.size, mmio.value, access) + } + ViommuRegion::Ddt => { + viommu.viommu_ddt_emul_access(&zone, mmio.address, mmio.size, mmio.value, access) + } + }; + if access == MmioAccessType::Read { + mmio.value = value as usize; + } + Ok(()) +} + +/// Virtual IOMMU device structure +struct VirtualIommu { + /// Multithread safe inner structure + inner: Mutex, +} + +/// Virtual IOMMU +struct VirtualIommuInner { + regs: ViommuRegs, + cq: CommandQueueState, + fq: FaultQueueState, + ddt: DdtShadowState, +} + +struct ViommuRegs { + caps: u64, + fctl: u32, + ddtp: u64, +} + +struct CommandQueueState { + base: u64, + head: u32, + tail: u32, + num_entries: u32, + gpa: u64, +} + +struct FaultQueueState { + base: u64, + head: u32, + tail: u32, +} + +/// Device-directory-table shadow state. +/// It affects the device directory table that the zone sees. +struct DdtShadowState { + tc: Vec, + fsc_written: Vec, +} + +impl VirtualIommu { + fn new() -> Self { + Self { + inner: Mutex::new(VirtualIommuInner::new()), + } + } + + /// vIOMMU emul access. + fn viommu_emul_access( + &self, + zone: &Zone, + offset: usize, + size: usize, + value: usize, + access: MmioAccessType, + ) -> u64 { + self.inner + .lock() + .viommu_emul_access(zone, offset, size, value, access) + } + + /// vIOMMU ddt emul access. + fn viommu_ddt_emul_access( + &self, + zone: &Zone, + offset: usize, + size: usize, + value: usize, + access: MmioAccessType, + ) -> u64 { + self.inner + .lock() + .viommu_ddt_emul_access(zone, offset, size, value, access) + } +} + +impl ViommuRegs { + fn new() -> Self { + let mut caps = iommu_read_reg(IommuReg::Caps); + caps &= !VIOMMU_MASKED_CAPS; + // Don't support MSI irq generated by IOMMU self. + caps |= IOMMU_CAPS::IGS::WSI.value; + + Self { + caps, + fctl: 0, + ddtp: 0, + } + } +} + +impl CommandQueueState { + fn new() -> Self { + Self { + base: 0, + head: 0, + tail: 0, + num_entries: 0, + gpa: 0, + } + } +} + +impl FaultQueueState { + fn new() -> Self { + Self { + base: 0, + head: 0, + tail: 0, + } + } +} + +impl DdtShadowState { + fn new() -> Self { + Self { + tc: vec![0; MAX_VIOMMU_DDT_DEVICES], + fsc_written: vec![false; MAX_VIOMMU_DDT_DEVICES], + } + } + + fn mark_fsc_written(&mut self, device_id: usize) { + if let Some(written) = self.fsc_written.get_mut(device_id) { + *written = true; + } + } + + fn fsc_needs_cleanup(&self, device_id: usize) -> bool { + self.fsc_written.get(device_id).copied().unwrap_or(false) + } +} + +impl VirtualIommuInner { + fn new() -> Self { + Self { + regs: ViommuRegs::new(), + cq: CommandQueueState::new(), + fq: FaultQueueState::new(), + ddt: DdtShadowState::new(), + } + } + + /// vIOMMU emul access inner. + fn viommu_emul_access( + &mut self, + zone: &Zone, + offset: usize, + size: usize, + value: usize, + access: MmioAccessType, + ) -> u64 { + // The current emulation dispatches by register range; access width is + // accepted as provided by the common MMIO layer. + let _ = size; + let zone_id = zone.id(); + match access { + MmioAccessType::Read => self.read_reg_access(offset), + MmioAccessType::Write => { + self.write_reg_access(zone, zone_id, offset, value); + 0 + } + } + } + + fn read_reg_access(&self, offset: usize) -> u64 { + match offset { + REG_CAPS_START..=REG_CAPS_END => { + info!("vIOMMU caps: {:#x}", self.regs.caps); + self.regs.caps + } + REG_FCTL_START..=REG_FCTL_END => self.regs.fctl as u64, + REG_DDTP_START..=REG_DDTP_END => self.regs.ddtp, + REG_CQB_START..=REG_CQB_END => self.cq.base, + REG_CQH_START..=REG_CQH_END => self.cq.head as u64, + REG_CQT_START..=REG_CQT_END => self.cq.tail as u64, + REG_FQB_START..=REG_FQB_END => self.fq.base, + REG_FQH_START..=REG_FQH_END => self.fq.head as u64, + REG_FQT_START..=REG_FQT_END => self.fq.tail as u64, + // We only keep minimum compatibility for CSR mirrors now. + REG_CQCSR_START..=REG_CQCSR_END => iommu_read_reg(IommuReg::Cqcsr), + REG_FQCSR_START..=REG_FQCSR_END => iommu_read_reg(IommuReg::Fqcsr), + REG_IPSR_START..=REG_IPSR_END => iommu_read_reg(IommuReg::Ipsr), + REG_ICVEC_START..=REG_ICVEC_END => iommu_read_reg(IommuReg::Icvec), + _ => { + warn!("vIOMMU mmio access offset {:#x} not supported", offset); + 0 + } + } + } + + fn write_reg_access(&mut self, zone: &Zone, zone_id: usize, offset: usize, value: usize) { + match offset { + REG_CAPS_START..=REG_CAPS_END => { + error!("Capabilities register is read-only!"); + } + REG_FCTL_START..=REG_FCTL_END => { + let host_fctl = iommu_read_reg(IommuReg::Fctl); + if value != host_fctl as usize { + error!( + "vIOMMU fctl write value {:#x} not match host fctl {:#x}!", + value, host_fctl + ); + } else { + self.regs.fctl = value as u32; + } + } + REG_DDTP_START..=REG_DDTP_END => { + self.handle_ddtp_write(zone, value); + } + REG_CQB_START..=REG_CQB_END => self.handle_cqb_write(value), + REG_CQH_START..=REG_CQH_END => { + error!("vIOMMU cqh is read-only!"); + } + REG_CQT_START..=REG_CQT_END => self.handle_cqt_write(zone_id, value), + REG_FQB_START..=REG_FQB_END => { + self.fq.base = value as u64; + } + REG_FQH_START..=REG_FQH_END => { + self.fq.head = value as u32; + } + REG_FQT_START..=REG_FQT_END => { + self.fq.tail = value as u32; + } + // We only keep minimum compatibility for CSR mirrors now. + REG_CQCSR_START..=REG_CQCSR_END => iommu_write_reg(IommuReg::Cqcsr, value as u64), + REG_FQCSR_START..=REG_FQCSR_END => iommu_write_reg(IommuReg::Fqcsr, value as u64), + REG_IPSR_START..=REG_IPSR_END => iommu_write_reg(IommuReg::Ipsr, value as u64), + REG_ICVEC_START..=REG_ICVEC_END => iommu_write_reg(IommuReg::Icvec, value as u64), + _ => { + warn!("vIOMMU mmio access offset {:#x} not supported", offset); + } + } + } + + fn handle_ddtp_write(&mut self, zone: &Zone, value: usize) -> bool { + info!("vIOMMU ddtp write value: {:#x}", value); + let mode_raw = ((value as u64 & IOMMU_DDTP::MODE.mask) >> IOMMU_DDTP::MODE.shift) as usize; + match IommuMode::try_from(mode_raw) { + Ok(mode) => { + info!("Guest try to set vIOMMU mode to {:?}", mode); + match mode { + IommuMode::Off | IommuMode::Bare => { + self.regs.ddtp = value as u64; + } + IommuMode::Ddt1Lvl => { + if !self.handle_ddt1lvl_mode(zone, value) { + return false; + } + self.regs.ddtp = value as u64; + } + IommuMode::Ddt2Lvl | IommuMode::Ddt3Lvl => { + info!("vIOMMU ddtp mode {:?} not supported yet!", mode); + } + } + } + Err(_) => { + error!("vIOMMU ddtp mode {:#x} not supported!", mode_raw as u8); + } + } + true + } + + fn handle_ddt1lvl_mode(&mut self, zone: &Zone, value: usize) -> bool { + let mut zone_inner = zone.write(); + let ppn = ((value as u64 & IOMMU_DDTP::PPN.mask) >> IOMMU_DDTP::PPN.shift) as usize; + let ddt_gpa = ppn << DDTP_PPN_TO_GPA_SHIFT; + info!("vIOMMU's DDT Table GPA: {:#x}", ddt_gpa); + + let Some(region) = zone_inner.gpm_mut().get_region(ddt_gpa as GuestPhysAddr) else { + error!("vIOMMU ddtp region not found in gpm!"); + return false; + }; + + // We unmap this page to trigger a page fault when the guest accesses it. + let cpu_set = zone_inner.cpu_set(); + send_event_to_all(cpu_set, 0, IPI_EVENT_VCPU_SUSPEND); + wait_for_other_vcpus_suspend(cpu_set); + + let gpm = zone_inner.gpm_mut(); + if let Err(err) = gpm.delete(region.start, region.size) { + error!("vIOMMU ddtp region delete failed: {:?}", err); + send_event_to_all(cpu_set, 0, IPI_EVENT_VCPU_RESUME); + signal_other_vcpus_resume(cpu_set); + return false; + } + + let region_start = region.start; + let region_end = region.start + region.size; + if region_start < ddt_gpa { + let left_region = MemoryRegion::new_with_offset_mapper( + region_start as GuestPhysAddr, + region_start, + ddt_gpa - region_start, + region.flags, + ); + if let Err(err) = gpm.insert(left_region) { + error!("vIOMMU ddtp left region insert failed: {:?}", err); + send_event_to_all(cpu_set, 0, IPI_EVENT_VCPU_RESUME); + signal_other_vcpus_resume(cpu_set); + return false; + } + } + if region_end > ddt_gpa + VIOMMU_DDT1LVL_SIZE { + // For 1LVL DDT, the region size is one 4KiB page. + let right_start = ddt_gpa + VIOMMU_DDT1LVL_SIZE; + let right_region = MemoryRegion::new_with_offset_mapper( + right_start as GuestPhysAddr, + right_start, + region_end - right_start, + region.flags, + ); + if let Err(err) = gpm.insert(right_region) { + error!("vIOMMU ddtp right region insert failed: {:?}", err); + send_event_to_all(cpu_set, 0, IPI_EVENT_VCPU_RESUME); + signal_other_vcpus_resume(cpu_set); + return false; + } + } + info!("gpm after unmap vIOMMU ddtp region: {:#x?}", gpm); + // SAFETY: flush stage-2 translations after changing guest mappings. + unsafe { riscv_h::asm::hfence_gvma(0, 0) }; + // Keep zone_id as 0 for now to preserve current behavior. + zone_inner.mmio_region_register(ddt_gpa, VIOMMU_DDT1LVL_SIZE, viommu_ddt_emul_handler, 0); + send_event_to_all(cpu_set, 0, IPI_EVENT_VCPU_RESUME); + signal_other_vcpus_resume(cpu_set); + true + } + + fn handle_cqb_write(&mut self, value: usize) { + let value_u64 = value as u64; + let ppn = (value_u64 & IOMMU_XQB::PPN.mask) >> IOMMU_XQB::PPN.shift; + let log2sz_1 = (value_u64 & IOMMU_XQB::LOG2SZ_1.mask) >> IOMMU_XQB::LOG2SZ_1.shift; + let mut num_entries = 1u64 << (log2sz_1 + 1); + let mut new_value = value_u64; + if num_entries > CQ_MAX_ENTRIES { + new_value = (value_u64 & !IOMMU_XQB::LOG2SZ_1.mask) | CQ_LOG2SZ_1_CAP; + num_entries = CQ_MAX_ENTRIES; + } + self.cq.num_entries = num_entries as u32; + self.cq.gpa = ppn << DDTP_PPN_TO_GPA_SHIFT; + self.cq.base = new_value; + info!( + "vIOMMU cqb: {:#x}, cq_gpa: {:#x}, cq_num_entries: {}", + self.cq.base, self.cq.gpa, self.cq.num_entries + ); + } + + fn handle_cqt_write(&mut self, zone_id: usize, value: usize) { + if self.cq.num_entries == 0 { + warn!("vIOMMU cqt write before cqb init, ignoring"); + return; + } + + let new_tail = value as u32 % self.cq.num_entries; + let mut cqh = self.cq.head; + while cqh != new_tail { + let cqe_addr = (self.cq.gpa as usize) + + (cqh as usize % self.cq.num_entries as usize) * CQ_ENTRY_SIZE; + let (dword0, dword1) = Self::read_cq_entry(cqe_addr); + self.dispatch_cq_command(zone_id, dword0, dword1); + cqh = (cqh + 1) % self.cq.num_entries; + } + self.cq.tail = new_tail; + self.cq.head = new_tail; + } + + fn dispatch_cq_command(&self, zone_id: usize, dword0: u64, dword1: u64) { + let opcode = dword0 & CMD_OPCODE_MASK; + let func3 = (dword0 >> CMD_FUNC3_SHIFT) & CMD_FUNC3_MASK; + match opcode { + op if op == u64::from(IOTINVAL_OPCODE) => { + let vma_raw = u64::from(IotInvalFunc::Vma.raw()); + let gvma_raw = u64::from(IotInvalFunc::Gvma.raw()); + if func3 == vma_raw { + // Guest VMA command is always bound to this zone's GSCID. + let mut out0 = dword0; + out0 |= 1u64 << IOTINVAL_GV_SHIFT; + out0 &= !(IOTINVAL_GSCID_MASK << IOTINVAL_GSCID_SHIFT); + out0 |= ((zone_id as u64) & IOTINVAL_GSCID_MASK) << IOTINVAL_GSCID_SHIFT; + iommu_add_raw_command(RiscvIommuCommand { + dword0: out0, + dword1, + }); + } else if func3 == gvma_raw { + iommu_add_raw_command(RiscvIommuCommand { dword0, dword1 }); + } else { + warn!("vIOMMU IOTINVAL func3={} not supported", func3); + } + } + op if op == u64::from(IOFENCE_OPCODE) => { + if func3 != u64::from(IoFenceFunc::C.raw()) { + warn!("vIOMMU IOFENCE func3 unsupported"); + } else { + iommu_add_raw_command(RiscvIommuCommand { dword0, dword1 }); + } + } + op if op == u64::from(IODIR_OPCODE) => { + let inval_ddt_raw = u64::from(IoDirFunc::InvalDdt.raw()); + let inval_pdt_raw = u64::from(IoDirFunc::InvalPdt.raw()); + if func3 == inval_ddt_raw { + iommu_add_raw_command(RiscvIommuCommand { dword0, dword1 }); + } else if func3 == inval_pdt_raw { + warn!("vIOMMU IODIR INVAL_PDT not supported yet"); + } else { + warn!("vIOMMU IODIR func3={} not supported", func3); + } + } + _ => warn!("vIOMMU unknown CQ opcode {}", opcode), + } + } + + fn read_cq_entry(cqe_addr: usize) -> (u64, u64) { + // SAFETY: CQE address comes from guest-provided CQB/CQH state and + // current implementation assumes this memory is directly readable. + let bytes: [u8; 16] = unsafe { ptr::read(cqe_addr as *const [u8; 16]) }; + let dword0 = u64::from_le_bytes(bytes[0..8].try_into().unwrap()); + let dword1 = u64::from_le_bytes(bytes[8..16].try_into().unwrap()); + (dword0, dword1) + } + + /// Handle Zone's iommu ddt mmio access. (now only support 1LVL DDT) + fn viommu_ddt_emul_access( + &mut self, + zone: &Zone, + offset: usize, + size: usize, + value: usize, + access: MmioAccessType, + ) -> u64 { + // DDT entry fields are 8 bytes wide; keep the current tolerant behavior + // and dispatch by field offset rather than rejecting other widths here. + let _ = size; + // A hypervisor that provides such an emulated IOMMU to the guest may + // 1.retain control of the MSI page tables used to direct MSIs to guest interrupt files + // 2.clear the MSI_FLAT and MSI_MRIF fields of the emulated capabilities register. + + // So its Device-Context Format is below: + // - Translation Control (tc) 8bytes + // - IO Hypervisor guest address translation and protection (iohgatp) 8bytes + // - Translation-attributes (ta) 8bytes + // - First-stage-context (fsc) 8bytes + + let ddt_index = offset / DDT_ENTRY_SIZE; // each entry is 32 bytes (base format) + if ddt_index == 0 || ddt_index >= self.ddt.tc.len() { + warn!( + "ddt_index {} is invalid for zone {}, ignore the access", + ddt_index, + zone.id() + ); + return 0; + } + + match offset % DDT_ENTRY_SIZE { + DDT_FIELD_TC_START..=DDT_FIELD_TC_END => { + self.handle_tc_access(ddt_index, value, access) + } + DDT_FIELD_IOHGATP_START..=DDT_FIELD_IOHGATP_END => { + self.handle_iohgatp_access(ddt_index, value, access) + } + DDT_FIELD_TA_START..=DDT_FIELD_TA_END => { + self.handle_ta_access(ddt_index, value, access) + } + DDT_FIELD_FSC_START..=DDT_FIELD_FSC_END => { + self.handle_fsc_access(ddt_index, value, access) + } + _ => { + error!( + "Unexpected offset value: {:#x}. This should never happen!", + offset + ); + 0 + } + } + } + + fn handle_tc_access(&mut self, ddt_index: usize, value: usize, access: MmioAccessType) -> u64 { + match access { + MmioAccessType::Read => self.ddt.tc[ddt_index], + MmioAccessType::Write => { + if value & !DDT_TC_ALLOWED_WRITE_MASK != 0 { + unimplemented!( + "vIOMMU ddt entry {} tc value {:#x} not supported!", + ddt_index, + value + ); + } + self.ddt.tc[ddt_index] = value as u64; + 0 + } + } + } + + fn handle_iohgatp_access(&self, ddt_index: usize, value: usize, access: MmioAccessType) -> u64 { + match access { + MmioAccessType::Read => { + iommu_read_ddt_field(ddt_index, IommuDdtField::Iohgatp).unwrap_or(0) + } + MmioAccessType::Write => { + if value != 0 { + error!( + "vIOMMU ddt entry {} iohgatp value {:#x} not supported!", + ddt_index, value + ); + } + 0 + } + } + } + + fn handle_ta_access(&self, ddt_index: usize, value: usize, access: MmioAccessType) -> u64 { + match access { + MmioAccessType::Read => { + warn!("vIOMMU ddt entry {} ta read not supported yet", ddt_index); + 0 + } + MmioAccessType::Write => { + if !iommu_write_ddt_field(ddt_index, IommuDdtField::Ta, value as u64) { + warn!("vIOMMU ddt entry {} ta write ignored", ddt_index); + } + 0 + } + } + } + + fn handle_fsc_access(&mut self, ddt_index: usize, value: usize, access: MmioAccessType) -> u64 { + match access { + MmioAccessType::Read => { + iommu_read_ddt_field(ddt_index, IommuDdtField::Fsc).unwrap_or(0) + } + MmioAccessType::Write => { + let fsc = value as u64; + let mode = (fsc & DDT_FSC::MODE.mask) >> DDT_FSC::MODE.shift; + let mode_ok = mode == DDT_FSC::MODE::BARE.value + || mode == DDT_FSC::MODE::SV39.value + || mode == DDT_FSC::MODE::SV48.value + || mode == DDT_FSC::MODE::SV57.value; + if !mode_ok { + error!( + "vIOMMU ddt entry {} fsc mode {:#x} not supported!", + ddt_index, mode + ); + return 0; + } + if !iommu_write_ddt_field(ddt_index, IommuDdtField::Fsc, fsc) { + warn!("vIOMMU ddt entry {} fsc write ignored", ddt_index); + } else { + self.ddt.mark_fsc_written(ddt_index); + } + 0 + } + } + } +} + +impl VirtualIommu { + fn cleanup_physical_ddt(&self) { + self.inner.lock().cleanup_physical_ddt(); + } +} + +impl VirtualIommuInner { + fn cleanup_physical_ddt(&mut self) { + for device_id in 1..self.ddt.tc.len() { + if !self.ddt.fsc_needs_cleanup(device_id) { + continue; + } + if iommu_write_ddt_field(device_id, IommuDdtField::Fsc, 0) { + self.ddt.fsc_written[device_id] = false; + info!("vIOMMU cleaned DDT FSC for device {}", device_id); + } else { + warn!("vIOMMU failed to clean DDT FSC for device {}", device_id); + } + } + } +} diff --git a/src/device/irqchip/aia/mod.rs b/src/device/irqchip/aia/mod.rs index b0ba984e8..dbd721c78 100644 --- a/src/device/irqchip/aia/mod.rs +++ b/src/device/irqchip/aia/mod.rs @@ -171,7 +171,7 @@ impl Zone { } /// Initial the virtual IMSIC related to thiz Zone. - pub fn vimsic_init(&mut self, _config: &HvZoneConfig) { + pub fn vimsic_init(&self, _config: &HvZoneConfig) { info!("Zone {} vIMSIC init", self.id()); let msi_pt = vimsic::vimsic_init(self, IMSIC_S_BASE, IMSIC_GUEST_NUM); unsafe { diff --git a/src/device/irqchip/aia/vimsic.rs b/src/device/irqchip/aia/vimsic.rs index f066886fc..b7a1296ae 100644 --- a/src/device/irqchip/aia/vimsic.rs +++ b/src/device/irqchip/aia/vimsic.rs @@ -17,6 +17,7 @@ use alloc::vec::Vec; use crate::consts::PAGE_SIZE; +#[cfg(iommu)] use crate::device::iommu::iommu_msi_pt_tlb_invalid; use crate::memory::Frame; use crate::memory::GuestPhysAddr; @@ -77,6 +78,7 @@ fn msi_pt_fill( // Fill MSI PTE to MSI PT. frame.as_slice_mut()[off..off + MSI_PTE_BYTES].copy_from_slice(&pte); // After change the MSI PTE, invalidate the related TLBs in IOMMU. + #[cfg(iommu)] iommu_msi_pt_tlb_invalid(zone_id as u16, imsic_gpa as usize); } } @@ -94,7 +96,7 @@ fn msi_pt_fill( /// Maps guest IMSIC interrupt files and builds a one-page IOMMU MSI translation table for this zone. /// /// Returns the physical frame backing the MSI PTE array (`start_paddr()` for IOMMU programming). -pub fn vimsic_init(zone: &mut Zone, imsic_base: usize, guest_num: usize) -> Frame { +pub fn vimsic_init(zone: &Zone, imsic_base: usize, guest_num: usize) -> Frame { let size = crate::memory::PAGE_SIZE; let cpu_ids: Vec<_> = zone.cpu_set().iter().collect(); diff --git a/src/device/irqchip/gicv2/gic.rs b/src/device/irqchip/gicv2/gic.rs index 9322b5824..d5e2b6a0e 100644 --- a/src/device/irqchip/gicv2/gic.rs +++ b/src/device/irqchip/gicv2/gic.rs @@ -137,12 +137,9 @@ pub fn inject_irq(irq_id: usize, is_sgi: bool) -> bool { /* inject gruop 0 irq */ // config vint bit 0-9 let mut val = irq_id; - // config pending state bit 31 + // config pending state bit 28 val = val | GICV2_GICH_LR_PENDING_STATE; - if is_sgi { - // config cpu bit 10-12 - val |= 1 << GICV2_GICH_LR_CPUID_SHIFT; - } else { + if !is_sgi { // config pint bit 10-19 val = val | (irq_id << GICV2_GICH_LR_PHYSID_SHIFT); // config hw bit 31 diff --git a/src/device/irqchip/gicv3/gicr.rs b/src/device/irqchip/gicv3/gicr.rs index 045922429..7568461ca 100644 --- a/src/device/irqchip/gicv3/gicr.rs +++ b/src/device/irqchip/gicv3/gicr.rs @@ -14,17 +14,16 @@ // Authors: // -use core::ptr; - -use spin::{mutex::Mutex, Once}; - use crate::{ - arch::cpu::this_cpu_id, + arch::cpu::{cpuid_to_mpidr_affinity, this_cpu_id}, consts::{MAX_CPU_NUM, MAX_ZONE_NUM, PAGE_SIZE}, hypercall::SGI_IPI_ID, memory::Frame, zone::this_zone_id, }; +use alloc::vec::Vec; +use core::ptr; +use spin::{mutex::Mutex, Lazy, Once}; use super::{ gicd::{ @@ -155,3 +154,82 @@ pub fn enable_one_lpi(lpi: usize) { let lpt = LPT.get().unwrap().lock(); lpt.enable_one_lpi(lpi); } + +pub struct GicrBaseLayout { + cpu_bases: Vec, + unused_bases: Vec, +} + +impl GicrBaseLayout { + pub fn cpu_bases(&self) -> Vec { + self.cpu_bases.clone() + } + + pub fn unused_bases(&self) -> Vec { + self.unused_bases.clone() + } +} + +fn cpuid_to_gicr_affinity(cpu_id: usize) -> u64 { + let (aff3, aff2, aff1, aff0) = cpuid_to_mpidr_affinity(cpu_id as u64); + (aff3 << 24) | (aff2 << 16) | (aff1 << 8) | aff0 +} + +fn read_gicr_affinity(base: usize) -> u64 { + let typer = unsafe { + core::ptr::read_volatile( + (base + crate::device::irqchip::gicv3::gicr::GICR_TYPER) as *const u64, + ) + }; + (typer & crate::device::irqchip::gicv3::GICR_TYPER_AFFINITY_VALUE_MASK) + >> crate::device::irqchip::gicv3::GICR_TYPER_AFFINITY_VALUE_SHIFT +} + +fn gicr_base_layout() -> GicrBaseLayout { + // info!("Calculating GICR base layout..."); + let gic = crate::device::irqchip::gicv3::GIC.get().unwrap(); + let possible_num = gic.gicr_size / crate::device::irqchip::gicv3::PER_GICR_SIZE; + let cpu_affinities: [u64; MAX_CPU_NUM] = core::array::from_fn(cpuid_to_gicr_affinity); + + let mut cpu_bases = vec![None; MAX_CPU_NUM]; + let mut unused_bases = Vec::new(); + let mut found_cpus = 0; + let mut curr_base = gic.gicr_base; + + for idx in 0..possible_num { + let affinity = read_gicr_affinity(curr_base); + if let Some(cpu_id) = cpu_affinities.iter().position(|&aff| aff == affinity) { + if cpu_bases[cpu_id].is_none() { + found_cpus += 1; + } + cpu_bases[cpu_id] = Some(curr_base); + } else { + unused_bases.push(curr_base); + } + + curr_base += crate::device::irqchip::gicv3::PER_GICR_SIZE; + + // Once all CPUs are matched, remaining GICR frames are all treated as unused. + if found_cpus == MAX_CPU_NUM { + for _ in (idx + 1)..possible_num { + unused_bases.push(curr_base); + curr_base += crate::device::irqchip::gicv3::PER_GICR_SIZE; + } + break; + } + } + + if found_cpus != MAX_CPU_NUM { + panic!( + "Could not find GICR for all CPUs, only found {}", + found_cpus + ); + } + + GicrBaseLayout { + cpu_bases: cpu_bases.into_iter().map(Option::unwrap).collect(), + unused_bases, + } +} + +pub(super) static GICR_BASE_LAYOUT: Lazy = Lazy::new(gicr_base_layout); diff --git a/src/device/irqchip/gicv3/gits.rs b/src/device/irqchip/gicv3/gits.rs index 1b05b9dab..3ca660c99 100644 --- a/src/device/irqchip/gicv3/gits.rs +++ b/src/device/irqchip/gicv3/gits.rs @@ -15,13 +15,14 @@ // use core::ptr; -use alloc::{sync::Arc, vec::Vec}; -use spin::{mutex::Mutex, Once, RwLock}; - +use crate::device::irqchip::gicv3::msix_backend::msix_intercept_its; +// use crate::pci::vpci_dev::virtio_cap::virtio_pci_intercept_its; use crate::{ consts::MAX_ZONE_NUM, cpu_data::this_zone, device::irqchip::gicv3::gicr::enable_one_lpi, memory::Frame, pci::pci_struct::Bdf, }; +use alloc::{sync::Arc, vec::Vec}; +use spin::{mutex::Mutex, Once, RwLock}; use super::host_gits_base; @@ -153,7 +154,11 @@ pub struct Cmdq { impl Cmdq { fn new() -> Self { - let f = Frame::new_contiguous_with_base(CMDQ_PAGES_NUM, 16).unwrap(); + let f = Frame::new_contiguous_with_base( + CMDQ_PAGES_NUM, + CMDQ_PAGES_NUM.trailing_zeros() as usize, + ) + .unwrap(); let r = Self { phy_addr: f.start_paddr(), readr: 0, @@ -327,13 +332,18 @@ impl Cmdq { } ITS_CMD_MAPTI => { new_cmd[0] = cmd0_tmp; - + let id = (value[0] & 0xffffffff00000000) >> 32; let event = value[1] & 0xffffffff; let intid = value[1] >> 32; let vicid = value[2] & 0xffff; let icid = vicid_to_icid_checked(vicid); set_cmd2_icid(&mut new_cmd[2], icid); enable_one_lpi((intid - 8192) as _); + // Virtio PCI notice + // unsafe { + // virtio_pci_intercept_its(id as usize, event as usize, intid as usize); + // } + msix_intercept_its(id, event, intid); debug!( "MAPTI cmd, for vbdf {:#x}:{:#x}:{:#x}:{:#x} -> {:#x}:{:#x}:{:#x}:{:#x}, event {:#x} -> vicid {:#x} (icid {:#x}) + intid {:#x}", domain, vbus, vdevice, vfunction, diff --git a/src/device/irqchip/gicv3/mod.rs b/src/device/irqchip/gicv3/mod.rs index a8d74c506..4767e678a 100644 --- a/src/device/irqchip/gicv3/mod.rs +++ b/src/device/irqchip/gicv3/mod.rs @@ -18,6 +18,7 @@ pub mod gicd; pub mod gicr; pub mod gits; +pub mod msix_backend; pub mod vgic; use core::arch::asm; @@ -31,9 +32,9 @@ use gits::gits_init; use spin::{Lazy, Mutex, Once}; use self::gicd::{enable_gic_are_ns, GICD_ICACTIVER, GICD_ICENABLER}; -use self::gicr::enable_ipi; +use self::gicr::{enable_ipi, GICR_BASE_LAYOUT}; use crate::arch::aarch64::sysreg::{read_sysreg, smc_arg1, write_sysreg}; -use crate::arch::cpu::{cpuid_to_mpidr_affinity, this_cpu_id}; +use crate::arch::cpu::this_cpu_id; use crate::arch::zone::GicConfig; use crate::config::root_zone_config; use crate::consts::{self, MAX_CPU_NUM}; @@ -44,6 +45,7 @@ use crate::hypercall::SGI_IPI_ID; use crate::zone::Zone; const ICH_HCR_UIE: u64 = 1 << 1; + //TODO: add Distributor init pub fn gicc_init() { //TODO: add Redistributor init @@ -109,6 +111,9 @@ pub fn gicv3_handle_irq_el1() { warn!("skip sgi {}", irq_id); deactivate_irq(irq_id); } else { + #[cfg(all(dwc_pcie, dwc_msi))] + let mut is_dwc_msi_irq = false; + if irq_id == 27 { // virtual timer interrupt TIMER_INTERRUPT_COUNTER.fetch_add(1, core::sync::atomic::Ordering::SeqCst); @@ -127,12 +132,30 @@ pub fn gicv3_handle_irq_el1() { } else if irq_id > 31 { //inject phy irq trace!("*** get spi_irq id = {}", irq_id); + + #[cfg(all(dwc_pcie, dwc_msi))] + { + if let Some(domain_id) = + crate::pci::dwc_msi::get_domain_id_by_irq(irq_id as u32) + { + is_dwc_msi_irq = true; + crate::pci::dwc_msi::dwc_msi_transfer_and_inject(domain_id, irq_id); + } + } } else { warn!("not konw irq id = {}", irq_id); } + + #[cfg(all(dwc_pcie, dwc_msi))] + if irq_id != 25 && !is_dwc_msi_irq { + inject_irq(irq_id, true); + } + + #[cfg(not(all(dwc_pcie, dwc_msi)))] if irq_id != 25 { inject_irq(irq_id, true); } + deactivate_irq(irq_id); } } @@ -351,38 +374,14 @@ pub fn host_gicd_base() -> usize { GIC.get().unwrap().gicd_base } -static CPU_GICR_BASE: Lazy> = Lazy::new(|| { - let mut bases = vec![0; MAX_CPU_NUM]; - let gic = GIC.get().unwrap(); - let base = gic.gicr_base; - let mut found_cpus = 0; - - // Scan through all GICR frames once - let mut curr_base = base; - - for _ in 0..MAX_CPU_NUM { - let typer = - unsafe { core::ptr::read_volatile((curr_base + gicr::GICR_TYPER) as *const u64) }; - let affinity = (typer & GICR_TYPER_AFFINITY_VALUE_MASK) >> GICR_TYPER_AFFINITY_VALUE_SHIFT; - - // Find which CPU this GICR belongs to - if let Some(cpu_id) = (0..MAX_CPU_NUM).position(|cpu_id| { - let (aff3, aff2, aff1, aff0) = cpuid_to_mpidr_affinity(cpu_id as u64); - let aff = (aff3 << 24) | (aff2 << 16) | (aff1 << 8) | aff0; - aff == affinity - }) { - bases[cpu_id] = curr_base; - found_cpus += 1; - } - curr_base += PER_GICR_SIZE; - } +pub static CPU_UNUSED_GICR_BASE: Lazy> = Lazy::new(|| { + let unused_bases = GICR_BASE_LAYOUT.unused_bases(); + debug!("Unused GICR bases: {:#x?}", unused_bases); + unused_bases +}); - if found_cpus != MAX_CPU_NUM { - panic!( - "Could not find GICR for all CPUs, only found {}", - found_cpus - ); - } +static CPU_GICR_BASE: Lazy> = Lazy::new(|| { + let bases = GICR_BASE_LAYOUT.cpu_bases(); info!("GICR bases: {:#x?}", bases); bases }); diff --git a/src/device/irqchip/gicv3/msix_backend.rs b/src/device/irqchip/gicv3/msix_backend.rs new file mode 100644 index 000000000..bef111678 --- /dev/null +++ b/src/device/irqchip/gicv3/msix_backend.rs @@ -0,0 +1,121 @@ +// Copyright (c) 2025 Syswonder +// hvisor is licensed under Mulan PSL v2. +// You can use this software according to the terms and conditions of the Mulan PSL v2. +// You may obtain a copy of Mulan PSL v2 at: +// http://license.coscl.org.cn/MulanPSL2 +// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR +// FIT FOR A PARTICULAR PURPOSE. +// See the Mulan PSL v2 for more details. +// +// Syswonder Website: +// https://www.syswonder.org +// +// Authors: +// + +use alloc::{sync::Arc, vec::Vec}; +use spin::rwlock::RwLock; + +use crate::{ + device::irqchip::inject_irq, + pci::msix::{MsixBackend, MsixTableEntry}, +}; + +type MsixEventID = u64; +type MsixDeviceID = u64; +type MsixIrqID = u64; + +const INACTIVE_IDX: usize = 114514; + +static mut GICV3_MSIX_BACKEND_IDX: usize = INACTIVE_IDX; +static mut GICV3_MSIX_BACKEND_LIST: Vec>> = Vec::new(); + +pub fn get_gicv3_backend() -> Arc> { + unsafe { + let backend = Arc::new(RwLock::new(Gicv3MsixBackend::new( + GICV3_MSIX_BACKEND_LIST.len(), + ))); + GICV3_MSIX_BACKEND_LIST.push(backend.clone()); + backend + } +} + +pub fn get_current_msix_backend() -> Option>> { + unsafe { + if GICV3_MSIX_BACKEND_IDX == INACTIVE_IDX { + return None; + } + Some(GICV3_MSIX_BACKEND_LIST[GICV3_MSIX_BACKEND_IDX].clone()) + } +} + +pub fn msix_intercept_its(device_id: MsixDeviceID, event_id: MsixEventID, irq_id: MsixIrqID) { + // let device_id = device_id >> 32; + match get_current_msix_backend().clone() { + Some(x) => { + x.write().intercept_its(device_id, event_id, irq_id); + } + None => { + //do nothing + } + } +} + +#[derive(Debug)] +pub struct Gicv3MsixBackend { + is_enable: bool, + idx: usize, + irq_info_list: Vec<(MsixDeviceID, MsixEventID, MsixIrqID)>, +} + +impl MsixBackend for Gicv3MsixBackend { + fn activate_irq(&self, device_id: usize, vector: &MsixTableEntry) { + // info!( + // "irq_info_list:{:x?},device_id:0x{:x},vector:{:x?}", + // self.irq_info_list, device_id, vector + // ); + // inject_irq(0x2001, false); + for i in self.irq_info_list.iter() { + if i.0 == device_id as u64 && i.1 == vector.get_msg_data() as u64 { + inject_irq(i.2 as usize, false); + return; + } + } + warn!("can't find corresponding Msix vector irq:{:x?}", vector) + } + + fn disable(&mut self) { + if !self.is_enable { + return; + } + unsafe { GICV3_MSIX_BACKEND_IDX = INACTIVE_IDX } + self.is_enable = false + } + + fn enable(&mut self) { + unsafe { GICV3_MSIX_BACKEND_IDX = self.idx } + self.is_enable = true + } +} + +impl Gicv3MsixBackend { + pub fn new(idx: usize) -> Self { + Self { + is_enable: false, + idx, + irq_info_list: Vec::new(), + } + } + + pub fn intercept_its( + &mut self, + device_id: MsixDeviceID, + event_id: MsixEventID, + irq_id: MsixIrqID, + ) { + if self.is_enable { + self.irq_info_list.push((device_id, event_id, irq_id)); + } + } +} diff --git a/src/device/irqchip/gicv3/vgic.rs b/src/device/irqchip/gicv3/vgic.rs index 8caab2892..b20cf2b71 100644 --- a/src/device/irqchip/gicv3/vgic.rs +++ b/src/device/irqchip/gicv3/vgic.rs @@ -13,8 +13,7 @@ // // Authors: // -use alloc::sync::Arc; - +use super::CPU_UNUSED_GICR_BASE; use super::{gicd::GICD_LOCK, is_spi}; use crate::platform::BOARD_MPIDR_MAPPINGS; use crate::{ @@ -31,6 +30,7 @@ use crate::{ memory::{mmio_perform_access, MMIOAccess}, zone::{this_zone_id, Zone}, }; +use alloc::sync::Arc; pub fn reg_range(base: usize, n: usize, size: usize) -> core::ops::Range { base..(base + n * size) } @@ -75,6 +75,20 @@ impl Zone { cpu, ); } + + for base in CPU_UNUSED_GICR_BASE.iter() { + let unused_gicr_base = base.clone(); + debug!( + "Registering unused GIC Redistributor region at {:#x?}", + unused_gicr_base + ); + inner.mmio_region_register( + unused_gicr_base, + PER_GICR_SIZE, + vgicv3_unused_redist_handler, + unused_gicr_base, + ); + } } } } @@ -170,6 +184,11 @@ fn restrict_bitmask_access( Ok(()) } +pub fn vgicv3_unused_redist_handler(mmio: &mut MMIOAccess, base: usize) -> HvResult { + mmio_perform_access(base, mmio); + HvResult::Ok(()) +} + pub fn vgicv3_redist_handler(mmio: &mut MMIOAccess, cpu: usize) -> HvResult { trace!("gicr({}) mmio = {:#x?}", cpu, mmio); let gicr_base = host_gicr_base(cpu); @@ -309,7 +328,19 @@ pub fn vgicv3_dist_handler(mmio: &mut MMIOAccess, _arg: usize) -> HvResult { match reg { reg if reg_range(GICD_IROUTER, 1024, 8).contains(®) => { - vgicv3_handle_irq_ops(mmio, (reg - GICD_IROUTER) as u32 / 8) + let irq = (reg - GICD_IROUTER) as u32 / 8; + + #[cfg(all(dwc_pcie, dwc_msi))] + { + // For zone0, the domainmsiinfo is empty, but it will always register the intterrupt to cpu0 + // So this remap operation is needed for other zones + if mmio.is_write && crate::pci::dwc_msi::is_dwc_msi_hwirq(irq) { + info!("remap dwc msi hwirq {} to cpu0!", irq); + mmio.value = 0; + } + } + + vgicv3_handle_irq_ops(mmio, irq) } reg if reg_range(GICD_ITARGETSR, 1024, 1).contains(®) => { vgicv3_handle_irq_ops(mmio, (reg - GICD_ITARGETSR) as u32) diff --git a/src/device/irqchip/ls7a2000/chip.rs b/src/device/irqchip/ls7a2000/chip.rs index 0b09350b7..d7c567516 100644 --- a/src/device/irqchip/ls7a2000/chip.rs +++ b/src/device/irqchip/ls7a2000/chip.rs @@ -663,7 +663,7 @@ pub fn extioi_int_enable_all() { CHIP_EXTIOI_ENABLE.extioi_en1.set(0xffff_ffff_ffff_ffff); CHIP_EXTIOI_ENABLE.extioi_en2.set(0xffff_ffff_ffff_ffff); CHIP_EXTIOI_ENABLE.extioi_en3.set(0xffff_ffff_ffff_ffff); - #[cfg(feature = "extioi_debug")] + #[cfg(extioi_debug)] { // dump ht int vector and enable /* diff --git a/src/device/irqchip/ls7a2000/mod.rs b/src/device/irqchip/ls7a2000/mod.rs index b34a766c5..dea50912d 100644 --- a/src/device/irqchip/ls7a2000/mod.rs +++ b/src/device/irqchip/ls7a2000/mod.rs @@ -24,19 +24,16 @@ use crate::{ register::{read_gcsr_estat, write_gcsr_estat}, }, consts::MAX_CPU_NUM, + event::{send_event, IPI_EVENT_VIRTIO_INJECT_IRQ}, + hypercall::SGI_IPI_ID, zone::Zone, }; use chip::*; -use loongArch64::register::tcfg; use spin::Mutex; pub mod chip; pub fn primary_init_early() { - if this_cpu_id() != 0 { - info!("loongarch64: irqchip: primary_init_early: do nothing on secondary cpus"); - return; - } info!("loongarch64: irqchip: primary_init_early: checking iochip configs"); print_chip_info(); csr_disable_new_codec(); @@ -89,8 +86,8 @@ pub fn clock_cpucfg_dump() { pub fn percpu_init() { info!("loongarch64: irqchip: percpu_init: running percpu_init"); - clear_all_ipi(this_cpu_id()); - enable_ipi(this_cpu_id()); + clear_all_ipi(); + enable_ipi(); ecfg_ipi_enable(); clock_cpucfg_dump(); // timer_test_tick(); @@ -110,6 +107,78 @@ const INT_PERF: usize = 10; const INT_TIMER: usize = 11; const INT_IPI: usize = 12; +/// Per-pCPU software HWI bitmap, serialized with GINTC VIP updates. +#[percpu::def_percpu] +static GUEST_HWI_ASSERTED: Mutex = Mutex::new(0); + +// The caller ensures the cpu_id is valid. +#[inline(always)] +fn get_guest_hwi_state(cpu: usize) -> &'static Mutex { + unsafe { GUEST_HWI_ASSERTED.remote_ref_raw(cpu) } +} + +fn sync_guest_irqs_for_cpu(cpu: usize, update: impl FnOnce(&mut u32) -> bool) -> bool { + let mut state = get_guest_hwi_state(cpu).lock(); + let changed = update(&mut state); + + // GINTC.VIP is a per-CPU register, so only the local CPU can apply the + // bitmap immediately. Remote CPUs are kicked after the lock is released. + if cpu == this_cpu_id() { + use crate::arch::register::gintc; + let desired_vip = (*state as usize) & 0xff; + let old_vip = gintc::read().vip(); + if old_vip != desired_vip { + gintc::write_vip(desired_vip); + } + } + changed && cpu != this_cpu_id() +} + +pub fn sync_guest_irqs() { + sync_guest_irqs_for_cpu(this_cpu_id(), |_| false); +} + +pub fn set_guest_irq_line(cpu: usize, irq: usize, asserted: bool) -> bool { + if cpu >= MAX_CPU_NUM || !(INT_HWI0..=INT_HWI7).contains(&irq) { + error!( + "loongarch64: invalid guest IRQ line: cpu={} irq={} asserted={}", + cpu, irq, asserted + ); + return false; + } + + let mask = 1u32 << (irq - INT_HWI0); + let need_remote_sync = sync_guest_irqs_for_cpu(cpu, |state| { + let old = *state; + let new = if asserted { old | mask } else { old & !mask }; + if old == new { + false + } else { + *state = new; + true + } + }); + // Drop the lock before kicking the target; its handler takes the same lock. + if need_remote_sync { + send_event(cpu, SGI_IPI_ID as usize, IPI_EVENT_VIRTIO_INJECT_IRQ); + } + true +} + +pub fn clear_guest_irq_lines(cpu: usize) { + if cpu >= MAX_CPU_NUM { + return; + } + let need_remote_sync = sync_guest_irqs_for_cpu(cpu, |state| { + let old = *state; + *state = 0; + old != 0 + }); + if need_remote_sync { + send_event(cpu, SGI_IPI_ID as usize, IPI_EVENT_VIRTIO_INJECT_IRQ); + } +} + /// inject irq to THIS cpu pub fn inject_irq(_irq: usize, is_hardware: bool) { debug!( @@ -122,41 +191,32 @@ pub fn inject_irq(_irq: usize, is_hardware: bool) { } let bit = 1 << _irq; if _irq >= INT_HWI0 && _irq <= INT_HWI7 { - // use gintc to inject - use crate::arch::register::gintc; - gintc::set_hwis(bit >> INT_HWI0); + set_guest_irq_line(this_cpu_id(), _irq, true); } else { // use gcsr to inject, just set the bit let mut gcsr_estat = read_gcsr_estat(); gcsr_estat |= bit; write_gcsr_estat(gcsr_estat); } - let mut status = GLOBAL_IRQ_INJECT_STATUS.lock(); - status.cpu_status[this_cpu_id()].status = InjectionStatus::Injecting; - - tcfg::set_en(true); // start timer to avoid endless timer injection - // please only enable this for debugging because it may cause overheads for realtime nonroots } -/// clear the injecting irq ctrl bit on THIS cpu -pub fn clear_hwi_injected_irq() { - use crate::arch::register::gintc; - gintc::set_hwis(0); - // gintc::set_hwip(0); - // gintc::set_hwic(0xff); - let mut gintc_raw = 0usize; - use core::arch::asm; - unsafe { - asm!("csrrd {0}, 0x52", out(reg) gintc_raw); +pub fn clear_injected_irq(_irq: usize) { + debug!("loongarch64: clear_injected_irq: _irq: {}", _irq); + if _irq > INT_IPI { + error!( + "loongarch64: clear_injected_irq: _irq > {}, not valid", + INT_IPI + ); + return; + } + let bit = 1 << _irq; + if _irq >= INT_HWI0 && _irq <= INT_HWI7 { + set_guest_irq_line(this_cpu_id(), _irq, false); + } else { + let mut gcsr_estat = read_gcsr_estat(); + gcsr_estat &= !bit; + write_gcsr_estat(gcsr_estat); } - debug!( - "loongarch64: clear_hwi_injected_irq: current gintc: {:#x}", - gintc_raw - ); - let mut status = GLOBAL_IRQ_INJECT_STATUS.lock(); - status.cpu_status[this_cpu_id()].status = InjectionStatus::Idle; - - tcfg::set_en(false); // stop timer } impl Zone { @@ -170,28 +230,3 @@ impl Zone { ); } } - -#[derive(Debug, Clone, Copy, PartialEq)] -pub enum InjectionStatus { - Injecting, - Idle, -} - -#[derive(Debug, Clone, Copy, PartialEq)] -pub struct PercpuInjectionStatus { - pub status: InjectionStatus, - pub irqs: [u32; 32], -} - -#[derive(Debug)] -pub struct GlobalInjectionStatus { - pub cpu_status: [PercpuInjectionStatus; MAX_CPU_NUM], -} - -pub static GLOBAL_IRQ_INJECT_STATUS: Mutex = - Mutex::new(GlobalInjectionStatus { - cpu_status: [PercpuInjectionStatus { - status: InjectionStatus::Idle, - irqs: [0; 32], - }; MAX_CPU_NUM], - }); diff --git a/src/device/irqchip/mod.rs b/src/device/irqchip/mod.rs index 345c4d20b..baa707747 100644 --- a/src/device/irqchip/mod.rs +++ b/src/device/irqchip/mod.rs @@ -17,32 +17,42 @@ use crate::arch::zone::HvArchZoneConfig; use crate::config::HvZoneConfig; use crate::zone::Zone; -#[cfg(all(feature = "gicv2", target_arch = "aarch64"))] +#[cfg(target_arch = "loongarch64")] +pub fn handle_virtio_irq_event() { + ls7a2000::sync_guest_irqs(); +} + +#[cfg(not(target_arch = "loongarch64"))] +pub fn handle_virtio_irq_event() { + crate::device::virtio_trampoline::handle_virtio_irq(); +} + +#[cfg(all(irq_gicv2, target_arch = "aarch64"))] pub mod gicv2; -#[cfg(all(feature = "gicv2", target_arch = "aarch64"))] +#[cfg(all(irq_gicv2, target_arch = "aarch64"))] pub use gicv2::{ gic::inject_irq, gicd::set_ispender, percpu_init, primary_init_early, primary_init_late, vgic::set_sgi_irq, }; -#[cfg(all(feature = "gicv3", target_arch = "aarch64"))] +#[cfg(all(irq_gicv3, target_arch = "aarch64"))] pub mod gicv3; -#[cfg(all(feature = "gicv3", target_arch = "aarch64"))] +#[cfg(all(irq_gicv3, target_arch = "aarch64"))] pub use gicv3::{ gicd::set_ispender, inject_irq, percpu_init, primary_init_early, primary_init_late, }; #[cfg(target_arch = "aarch64")] pub fn gic_handle_irq() { - #[cfg(feature = "gicv2")] + #[cfg(irq_gicv2)] gicv2::gic::gicv2_handle_irq(); - #[cfg(feature = "gicv3")] + #[cfg(irq_gicv3)] gicv3::gicv3_handle_irq_el1(); } #[cfg(target_arch = "aarch64")] pub fn gic_send_event(cpu_id: u64, sgi_num: u64) { - #[cfg(feature = "gicv3")] + #[cfg(irq_gicv3)] { /*Actually, the value passed to ICC_SGI1R_EL1 should be derived from the MPIDR of the target CPU. However, since we cannot access this @@ -63,7 +73,7 @@ pub fn gic_send_event(cpu_id: u64, sgi_num: u64) { write_sysreg!(icc_sgi1r_el1, val); debug!("write sgi sys value = {:#x}", val); } - #[cfg(feature = "gicv2")] + #[cfg(irq_gicv2)] { let sgi_id: u64 = sgi_num; let target_list: u64 = 1 << cpu_id; @@ -73,11 +83,11 @@ pub fn gic_send_event(cpu_id: u64, sgi_num: u64) { impl Zone { pub fn virqc_init(&mut self, _config: &HvZoneConfig) { - #[cfg(all(feature = "plic", target_arch = "riscv64"))] + #[cfg(all(plic, target_arch = "riscv64"))] { self.vplic_init(_config); } - #[cfg(all(feature = "aia", target_arch = "riscv64"))] + #[cfg(all(aia, target_arch = "riscv64"))] { self.vaplic_init(_config); self.vimsic_init(_config); @@ -85,28 +95,28 @@ impl Zone { } pub fn mmio_init(&mut self, hv_config: &HvArchZoneConfig) { - #[cfg(all(feature = "gicv2", target_arch = "aarch64"))] + #[cfg(all(irq_gicv2, target_arch = "aarch64"))] { self.vgicv2_mmio_init(hv_config); self.vgicv2_remap_init(hv_config); } - #[cfg(all(feature = "gicv3", target_arch = "aarch64"))] + #[cfg(all(irq_gicv3, target_arch = "aarch64"))] { self.vgicv3_mmio_init(hv_config); } - #[cfg(all(feature = "plic", target_arch = "riscv64"))] + #[cfg(all(plic, target_arch = "riscv64"))] { self.vplic_mmio_init(hv_config); } - #[cfg(all(feature = "aia", target_arch = "riscv64"))] + #[cfg(all(aia, target_arch = "riscv64"))] { self.vaplic_mmio_init(hv_config); } - #[cfg(all(feature = "eic770x_soc", target_arch = "riscv64"))] + #[cfg(all(hypervisor_v0_6, target_arch = "riscv64"))] { - #[cfg(feature = "sifive_ccache")] + #[cfg(sifive_ccache)] self.virtual_sifive_ccache_mmio_init(); - #[cfg(feature = "eic7700_sysreg")] + #[cfg(eic7700_sysreg)] self.virtual_syscon_mmio_init(); } #[cfg(target_arch = "x86_64")] @@ -117,30 +127,30 @@ impl Zone { } } -#[cfg(all(feature = "aclint", target_arch = "riscv64"))] +#[cfg(all(aclint, target_arch = "riscv64"))] pub mod aclint; -#[cfg(all(feature = "plic", target_arch = "riscv64"))] +#[cfg(all(plic, target_arch = "riscv64"))] pub mod plic; -#[cfg(all(feature = "plic", target_arch = "riscv64"))] +#[cfg(all(plic, target_arch = "riscv64"))] pub use plic::{inject_irq, percpu_init, primary_init_late}; -#[cfg(all(feature = "aia", target_arch = "riscv64"))] +#[cfg(all(aia, target_arch = "riscv64"))] pub mod aia; -#[cfg(all(feature = "aia", target_arch = "riscv64"))] +#[cfg(all(aia, target_arch = "riscv64"))] pub use aia::{host_aplic, inject_irq, percpu_init, primary_init_late}; #[cfg(target_arch = "riscv64")] pub fn primary_init_early() { // aclint is local interrupt controller // plic & aia is global interrupt controller - #[cfg(feature = "plic")] + #[cfg(plic)] plic::primary_init_early(); - #[cfg(feature = "aia")] + #[cfg(aia)] aia::primary_init_early(); - #[cfg(feature = "aclint")] + #[cfg(aclint)] aclint::aclint_init(crate::platform::ACLINT_SSWI_BASE); } diff --git a/src/device/irqchip/pic/ioapic.rs b/src/device/irqchip/pic/ioapic.rs index 75c7b1607..4286698f1 100644 --- a/src/device/irqchip/pic/ioapic.rs +++ b/src/device/irqchip/pic/ioapic.rs @@ -16,12 +16,13 @@ use crate::{ arch::{ - acpi::{get_apic_id, get_cpu_id}, - cpu::this_cpu_id, + acpi::try_get_cpu_id, + cpu::{this_apic_id, this_cpu_id}, idt, ipi, mmio::MMIoDevice, zone::HvArchZoneConfig, }, + cpu_data::this_zone, device::irqchip::pic::inject_vector, error::HvResult, memory::{GuestPhysAddr, MMIOAccess}, @@ -95,6 +96,11 @@ impl VirtIoApic { mut reg => { reg -= IoApicReg::TABLE_BASE; let index = (reg >> 1) as usize; + // info!("ioapic read index: {:x}", index); + if this_zone_id() != 0 && index == 4 { + //FIXME: we do not allow non-root to use uart interrupt + return Ok(0xffff_ffff_ffff_ffff); + } if let Some(entry) = inner.rte.get(index) { if reg % 2 == 0 { Ok((*entry).get_bits(0..=31)) @@ -132,7 +138,26 @@ impl VirtIoApic { if reg % 2 == 0 { entry.set_bits(0..=31, value.get_bits(0..=31)); } else { - entry.set_bits(32..=63, value.get_bits(0..=31)); + let original_dest = value.get_bits(24..=31); + if let Some(dest_cpu) = try_get_cpu_id(original_dest as usize) { + if this_zone().read().cpu_set().contains_cpu(dest_cpu) { + entry.set_bits(56..=63, original_dest); + } else { + let dest = this_apic_id() as u64; + info!( + "redirect irq {:x} to cpu {:x} in another zone! entry: {:x?}", + index, dest, *entry + ); + entry.set_bits(56..=63, dest); + } + } else { + let dest = this_apic_id() as u64; + info!( + "redirect irq {:x} to cpu {:x} in another zone, unknown dest {:x}! entry: {:x?}", + index, dest, original_dest, *entry + ); + entry.set_bits(56..=63, dest); + } /*if zone_id == 0 { // info!("1 write {:x} entry: {:x?}", index, *entry); @@ -153,7 +178,7 @@ impl VirtIoApic { fn get_irq_cpu(&self, irq: usize, zone_id: usize) -> Option { let ioapic = self.inner.get(zone_id).unwrap(); if let Some(entry) = ioapic.lock().rte.get(irq) { - let dest = get_cpu_id(entry.get_bits(56..=63) as usize); + let dest = try_get_cpu_id(entry.get_bits(56..=63) as usize).unwrap_or_else(this_cpu_id); return Some(dest); } None @@ -164,10 +189,9 @@ impl VirtIoApic { let ioapic = self.inner.get(zone_id).unwrap(); if let Some(entry) = ioapic.lock().rte.get(irq) { // TODO: physical & logical mode - let dest = get_cpu_id(entry.get_bits(56..=63) as usize); + let dest = try_get_cpu_id(entry.get_bits(56..=63) as usize).unwrap_or_else(this_cpu_id); let masked = entry.get_bit(16); let vector = entry.get_bits(0..=7) as u8; - // info!("trigger hv: {:x} zone: {:x}", vector, zone_id); if !masked && vector >= 0x20 { inject_vector(dest, vector, None, allow_repeat); } diff --git a/src/device/irqchip/pic/lapic.rs b/src/device/irqchip/pic/lapic.rs index 8ba43c182..2ffd96742 100644 --- a/src/device/irqchip/pic/lapic.rs +++ b/src/device/irqchip/pic/lapic.rs @@ -28,7 +28,8 @@ use crate::{ }; use bit_field::BitField; use core::{ops::Range, u32}; -use x2apic::lapic::{LocalApic, LocalApicBuilder, TimerMode}; +use x2apic::lapic::{LocalApic, LocalApicBuilder}; +use x86::msr::wrmsr; pub struct VirtLocalApic { pub phys_lapic: LocalApic, @@ -96,7 +97,6 @@ impl VirtLocalApic { pub fn wrmsr(&mut self, msr: Msr, value: u64) -> HvResult { match msr { IA32_X2APIC_EOI => { - // info!("eoi"); pop_vector(this_cpu_id()); Ok(()) } @@ -106,28 +106,12 @@ impl VirtLocalApic { Ok(()) } IA32_X2APIC_LVT_TIMER => { + let value = value & 0xffff_ffff; + let vector = value.get_bits(0..=7); self.virt_lvt_timer_bits = value as u32; - let timer = value.get_bits(0..=7) as u8; - if timer != self.virt_timer_vector { - self.virt_timer_vector = timer; - self.phys_lapic = Self::new_phys_lapic( - timer as _, - IdtVector::APIC_ERROR_VECTOR as _, - IdtVector::APIC_SPURIOUS_VECTOR as _, - ) - } + self.virt_timer_vector = vector as u8; unsafe { - self.phys_lapic - .set_timer_mode(match value.get_bits(17..19) { - 0 => TimerMode::OneShot, - 1 => TimerMode::Periodic, - _ => TimerMode::TscDeadline, - }); - if value.get_bit(16) { - self.phys_lapic.disable_timer(); - } else { - self.phys_lapic.enable_timer(); - } + wrmsr(IA32_X2APIC_LVT_TIMER as u32, value); } Ok(()) } diff --git a/src/device/irqchip/pic/mod.rs b/src/device/irqchip/pic/mod.rs index 5ad49ef5c..177785765 100644 --- a/src/device/irqchip/pic/mod.rs +++ b/src/device/irqchip/pic/mod.rs @@ -145,7 +145,7 @@ pub fn primary_init_late() {} impl Zone { pub fn arch_irqchip_reset(&self) { - #[cfg(feature = "intel_vtd")] + #[cfg(intel_vtd)] iommu::clear_dma_translation_tables(self.id()); } } diff --git a/src/device/irqchip/plic/plic.rs b/src/device/irqchip/plic/plic.rs index a7f069bcd..af009b381 100644 --- a/src/device/irqchip/plic/plic.rs +++ b/src/device/irqchip/plic/plic.rs @@ -235,7 +235,7 @@ impl Plic { */ let mut hwirq = 0; - if cfg!(feature = "dp1000_plic") { + if cfg!(dp1000_plic) { let mut ie: [u32; 32] = [0; 32]; // max 1024 irqs hwirq = if self.plic_check_enable_first_pending(context, &mut ie) { self.claim(context) diff --git a/src/device/mod.rs b/src/device/mod.rs index fa5aab22e..7fab9db48 100644 --- a/src/device/mod.rs +++ b/src/device/mod.rs @@ -19,8 +19,8 @@ pub mod irqchip; pub mod uart; pub mod virtio_trampoline; -#[cfg(feature = "eic7700_sysreg")] +#[cfg(eic7700_sysreg)] pub mod eic7700_syscrg; -#[cfg(feature = "sifive_ccache")] +#[cfg(sifive_ccache)] pub mod sifive_ccache; diff --git a/src/device/uart/mod.rs b/src/device/uart/mod.rs index f30f036db..c00081610 100644 --- a/src/device/uart/mod.rs +++ b/src/device/uart/mod.rs @@ -13,23 +13,23 @@ // // Authors: // -// we specified the driver for each platform in the FEATURES environment variable. +// UART driver is selected per board via kconfig/defconfig (see kconfig/cfg_map.toml). #![allow(unused)] -#[cfg(all(feature = "pl011", target_arch = "aarch64"))] +#[cfg(all(pl011, target_arch = "aarch64"))] mod pl011; -#[cfg(all(feature = "pl011", target_arch = "aarch64"))] -pub use pl011::{console_getchar, console_putchar}; +#[cfg(all(pl011, target_arch = "aarch64"))] +pub use pl011::{console_free_check, console_getchar, console_putchar}; -#[cfg(all(feature = "imx_uart", target_arch = "aarch64"))] +#[cfg(all(imx_uart, target_arch = "aarch64"))] mod imx_uart; -#[cfg(all(feature = "imx_uart", target_arch = "aarch64"))] +#[cfg(all(imx_uart, target_arch = "aarch64"))] pub use imx_uart::{console_getchar, console_putchar}; -#[cfg(all(feature = "xuartps", target_arch = "aarch64"))] +#[cfg(all(xuartps, target_arch = "aarch64"))] mod xuartps; -#[cfg(all(feature = "xuartps", target_arch = "aarch64"))] +#[cfg(all(xuartps, target_arch = "aarch64"))] pub use xuartps::{console_getchar, console_putchar}; #[cfg(target_arch = "riscv64")] @@ -37,19 +37,19 @@ pub use crate::arch::riscv64::sbi::{ sbi_console_getchar as console_getchar, sbi_console_putchar as console_putchar, }; -#[cfg(all(feature = "loongson_uart", target_arch = "loongarch64"))] +#[cfg(all(loongson_uart, target_arch = "loongarch64"))] pub mod loongson_uart; -#[cfg(all(feature = "loongson_uart", target_arch = "loongarch64"))] +#[cfg(all(loongson_uart, target_arch = "loongarch64"))] pub use loongson_uart::{console_getchar, console_putchar}; -#[cfg(all(feature = "uart_16550", target_arch = "aarch64"))] +#[cfg(all(uart_16550, target_arch = "aarch64"))] mod uart_16550; -#[cfg(all(feature = "uart_16550", target_arch = "aarch64"))] -pub use uart_16550::{console_getchar, console_putchar}; +#[cfg(all(uart_16550, target_arch = "aarch64"))] +pub use uart_16550::{console_free_check, console_getchar, console_putchar}; -#[cfg(all(feature = "uart16550a", target_arch = "x86_64"))] +#[cfg(all(uart16550a, target_arch = "x86_64"))] mod uart16550a; -#[cfg(all(feature = "uart16550a", target_arch = "x86_64"))] +#[cfg(all(uart16550a, target_arch = "x86_64"))] pub use uart16550a::{ console_getchar, console_putchar, virt_console_io_read, virt_console_io_write, UartReg, }; diff --git a/src/device/uart/pl011.rs b/src/device/uart/pl011.rs index 255a656e7..575dd0995 100644 --- a/src/device/uart/pl011.rs +++ b/src/device/uart/pl011.rs @@ -71,6 +71,10 @@ impl Pl011Uart { self.regs().dr.set(c as u32) } + fn check_fr(&mut self) -> bool { + self.regs().fr.get() & (1 << 3) == 0 + } + fn getchar(&mut self) -> Option { if self.regs().fr.get() & (1 << 4) == 0 { Some(self.regs().dr.get() as u8) @@ -87,3 +91,7 @@ pub fn console_putchar(c: u8) { pub fn console_getchar() -> Option { UART.lock().getchar() } + +pub fn console_free_check() -> bool { + UART.lock().check_fr() +} diff --git a/src/device/uart/uart16550a.rs b/src/device/uart/uart16550a.rs index 144b788b9..e180c0d69 100644 --- a/src/device/uart/uart16550a.rs +++ b/src/device/uart/uart16550a.rs @@ -348,7 +348,7 @@ impl VirtUart16550a { pub fn console_putchar(c: u8) { COM1.lock().putchar(c); - #[cfg(all(feature = "graphics"))] + #[cfg(all(graphics))] fb_putchar(c, 0xffffffff, 0); } diff --git a/src/device/uart/uart_16550.rs b/src/device/uart/uart_16550.rs index 343d7c0bc..ecf2204f3 100644 --- a/src/device/uart/uart_16550.rs +++ b/src/device/uart/uart_16550.rs @@ -73,6 +73,10 @@ impl Uart16550 { self.regs().THR_RBR_DLL.set(c as u32); } + pub fn check_lsr(&mut self) -> bool { + self.regs().LSR.get() & (1 << 6) != 0 + } + #[inline] fn getchar(&mut self) -> Option { todo!() @@ -90,3 +94,7 @@ pub fn console_putchar(c: u8) { pub fn console_getchar() -> Option { unsafe { UART.getchar() } } + +pub fn console_free_check() -> bool { + unsafe { UART.check_lsr() } +} diff --git a/src/device/virtio_trampoline.rs b/src/device/virtio_trampoline.rs index 811bb12bc..4de1a7452 100644 --- a/src/device/virtio_trampoline.rs +++ b/src/device/virtio_trampoline.rs @@ -21,18 +21,22 @@ #![deny(unused)] #[cfg(not(target_arch = "loongarch64"))] +use crate::device::irqchip::inject_irq; use crate::{ arch::cpu::get_target_cpu, event::{send_event, IPI_EVENT_WAKEUP_VIRTIO_DEVICE}, hypercall::SGI_IPI_ID, + platform::IRQ_WAKEUP_VIRTIO_DEVICE, }; use crate::{ - arch::cpu::this_cpu_id, consts::MAX_WAIT_TIMES, device::irqchip::inject_irq, error::HvResult, - memory::MMIOAccess, zone::this_zone_id, + arch::cpu::this_cpu_id, consts::MAX_WAIT_TIMES, error::HvResult, memory::MMIOAccess, + zone::this_zone_id, }; +#[cfg(not(target_arch = "loongarch64"))] use alloc::collections::BTreeMap; use core::{ fmt::{Debug, Formatter, Result}, + mem::size_of, sync::atomic::{fence, AtomicBool, AtomicUsize, Ordering}, }; use spin::{Mutex, MutexGuard}; @@ -42,24 +46,23 @@ use tock_registers::{ }; /// Save the irqs the virtio-device wants to inject. The format is >, and the first elem of List is the valid len of it. +#[cfg(not(target_arch = "loongarch64"))] pub static VIRTIO_IRQS: Mutex> = Mutex::new(BTreeMap::new()); // Controller of the shared memory the root linux's virtio device and hvisor shares. +pub static VIRTIO_PCI_BRIDGE: Mutex = Mutex::new(VirtioPCIBridge::dummy()); pub static VIRTIO_BRIDGE: VirtioBridgeController = VirtioBridgeController::new(); const QUEUE_NOTIFY: usize = 0x50; pub const MAX_REQ: u32 = 32; pub const MAX_DEVS: usize = 8; // Attention: The max virtio-dev number for vm is 8 (loongarch64 needs 3 consoles and 3 disks for zgclab project). pub const MAX_CPUS: usize = 32; -pub const MAX_BACKOFF: usize = 1024; +pub const MAX_VQ: usize = 16; +const MAX_PCI_CONFIG_REQ: usize = 4; +const MAX_PCI_CONFIG_RES: usize = 4; +const MAX_PCI_DATA_REQ: usize = 32; +pub const VIRTIO_PCI_HYPERCALL_VERSION: u16 = 1; -#[cfg(not(target_arch = "loongarch64"))] -use crate::platform::IRQ_WAKEUP_VIRTIO_DEVICE; -// #[cfg(all(not(target_arch = "riscv64"), not(target_arch = "x86_64")))] -// pub const IRQ_WAKEUP_VIRTIO_DEVICE: usize = 32 + 0x20; -// #[cfg(target_arch = "riscv64")] -// pub const IRQ_WAKEUP_VIRTIO_DEVICE: usize = 0x20; -// #[cfg(target_arch = "x86_64")] -// pub const IRQ_WAKEUP_VIRTIO_DEVICE: usize = 0x6; +pub const MAX_BACKOFF: usize = 1024; /// non root zone's virtio request handler pub fn mmio_virtio_handler(mmio: &mut MMIOAccess, base: usize) -> HvResult { @@ -103,10 +106,8 @@ pub fn mmio_virtio_handler(mmio: &mut MMIOAccess, base: usize) -> HvResult { req_agent.push_req(hreq); drop(req_agent); - #[cfg(not(target_arch = "loongarch64"))] let mut is_ipi_sent = false; // If backend is sleep, hvisor needs to send ipi to wake it up. - #[cfg(not(target_arch = "loongarch64"))] check_need_wakeup_and_send_ipi(&mut is_ipi_sent); let mut count: usize = 0; @@ -128,7 +129,6 @@ pub fn mmio_virtio_handler(mmio: &mut MMIOAccess, base: usize) -> HvResult { ); count = 0; } - // check_need_wakeup_and_send_ipi(&mut is_ipi_sent); } if !mmio.is_write { // ensure cfg value is right. @@ -140,7 +140,6 @@ pub fn mmio_virtio_handler(mmio: &mut MMIOAccess, base: usize) -> HvResult { Ok(()) } -#[cfg(not(target_arch = "loongarch64"))] pub fn check_need_wakeup_and_send_ipi(is_send_ipi: &mut bool) { if !(*is_send_ipi) && VIRTIO_BRIDGE.need_wakeup() { debug!("need wakeup (recheck), sending ipi to wake up virtio device"); @@ -155,6 +154,7 @@ pub fn check_need_wakeup_and_send_ipi(is_send_ipi: &mut bool) { /// When virtio req type is notify, root zone will send sgi to non root, \ /// and non root will call this function. +#[cfg(not(target_arch = "loongarch64"))] pub fn handle_virtio_irq() { let mut map = VIRTIO_IRQS.lock(); let irq_list = map.get_mut(&this_cpu_id()).unwrap(); @@ -253,6 +253,7 @@ struct ReqAgent<'a> { } impl<'a> ReqAgent<'a> { + #[allow(clippy::mut_from_ref)] fn region(&self) -> &mut VirtioBridge { unsafe { &mut *(self.base as *mut VirtioBridge) } } @@ -292,6 +293,7 @@ pub struct ResAgent<'a> { } impl<'a> ResAgent<'a> { + #[allow(clippy::mut_from_ref)] fn region(&self) -> &mut VirtioBridge { unsafe { &mut *(self.base as *mut VirtioBridge) } } @@ -328,6 +330,439 @@ impl<'a> ResAgent<'a> { } } +#[repr(C)] +#[derive(Clone, Copy, Debug)] +pub struct VirtqueueAreaInfo { + pub desc_area: u64, + pub avail_area: u64, + pub used_area: u64, + + pub queue_size: u64, +} + +impl VirtqueueAreaInfo { + pub fn new(desc: u64, avail: u64, used: u64, queue_size: u64) -> Self { + Self { + desc_area: desc, + avail_area: avail, + used_area: used, + queue_size, + } + } + + pub fn dummy() -> Self { + Self { + desc_area: 0, + avail_area: 0, + used_area: 0, + queue_size: 0, + } + } +} + +#[repr(C)] +#[derive(Clone, Copy, Debug)] +pub struct VirtioPCIConfigInfo { + features: u64, + dev_id: u16, + num_of_queues: u16, + dtype: u16, + padding: u16, + vqs: [VirtqueueAreaInfo; MAX_VQ], +} + +impl VirtioPCIConfigInfo { + pub fn dummy() -> Self { + Self { + features: 0, + dev_id: 0, + num_of_queues: 0, + dtype: 0, + padding: 0, + vqs: [VirtqueueAreaInfo::dummy(); 16], + } + } + + pub fn set_features(&mut self, val: u64) { + self.features = val; + } + + // pub fn set_dev_id(&mut self, val: u16) { + // self.dev_id = val; + // } + + pub fn set_num_of_queues(&mut self, val: u16) { + self.num_of_queues = val; + } + + pub fn set_dtype(&mut self, val: u16) { + self.dtype = val; + } + + pub fn set_vqs(&mut self, idx: usize, val: VirtqueueAreaInfo) { + if idx >= MAX_VQ { + error!("It's illegal to have idx:0x{:x} exceeding MAX_VQ", idx); + return; + } + self.vqs[idx] = val; + } +} + +#[repr(C)] +#[derive(Clone, Copy, Debug)] +pub struct VirtioPCIConfigReq { + request_id: u32, + padding: u32, + info: VirtioPCIConfigInfo, +} + +impl VirtioPCIConfigReq { + fn new(request_id: u32, info: VirtioPCIConfigInfo) -> Self { + Self { + request_id, + padding: 0, + info, + } + } +} + +#[repr(C)] +#[derive(Clone, Copy, Debug)] +pub struct VirtioPCIConfigRes { + request_id: u32, + status: u32, + dev_id: u16, + padding: u16, +} + +impl VirtioPCIConfigRes { + #[allow(unused)] + pub fn success(request_id: u32, dev_id: u16) -> Self { + Self { + request_id, + status: 0, + dev_id, + padding: 0, + } + } +} + +#[repr(u16)] +#[derive(Clone, Copy, Debug, Eq, PartialEq)] +pub enum VirtioPCIHypercallOp { + None = 0, + ConfigReqComplete = 1, + DataReqComplete = 2, + Reset = 3, +} + +impl TryFrom for VirtioPCIHypercallOp { + type Error = (); + + fn try_from(value: u16) -> core::result::Result { + match value { + 0 => Ok(Self::None), + 1 => Ok(Self::ConfigReqComplete), + 2 => Ok(Self::DataReqComplete), + 3 => Ok(Self::Reset), + _ => Err(()), + } + } +} + +#[repr(C)] +#[derive(Clone, Copy, Debug)] +pub struct VirtioPCIHypercallInfo { + pub version: u16, + pub op: u16, + pub target_cpu: u32, + pub request_id: u32, + pub status: u32, +} + +impl VirtioPCIHypercallInfo { + pub const fn new() -> Self { + Self { + version: VIRTIO_PCI_HYPERCALL_VERSION, + op: VirtioPCIHypercallOp::None as u16, + target_cpu: 0, + request_id: 0, + status: 0, + } + } +} + +#[repr(C)] +#[derive(Copy, Clone, Debug)] +pub struct VirtioPCIDataInfo { + dev_id: u16, + queue_id: u16, + cpu_id: u16, + msix_vector_idx: u16, +} + +impl VirtioPCIDataInfo { + pub fn new(dev_id: u16, queue_id: u16, msix_vector_idx: u16) -> Self { + let cpu_id = this_cpu_id() as u16; + Self { + dev_id, + queue_id, + cpu_id, + msix_vector_idx, + } + } + + pub fn get_identifier(&self) -> u64 { + (self.dev_id as u64) | ((self.queue_id as u64) << 16) | ((self.cpu_id as u64) << 32) + } + + // pub fn from_u64(data_req_id:u64)->Self{ + // let dev_id = data_req_id&0x0000_0000_0000_ffff; + // let msix_vector_idx = data_req_id&0x0000_0000_ffff_0000; + // let cpu_id = data_req_id&0x0000_ffff_0000_0000; + // Self { dev_id: dev_id as u16, msix_vector_idx: msix_vector_idx as u16, cpu_id: cpu_id as u16, _padding: 0x0000 } + // } + + // pub fn get_dev_id(&self)->u16{ + // self.dev_id + // } + + pub fn get_msix_vector_idx(&self) -> u16 { + self.msix_vector_idx + } + + // pub fn get_cpu_id(&self)->u16{ + // self.cpu_id + // } +} + +#[repr(C)] +#[derive(Copy, Clone, Debug)] +pub struct VirtioPCIDataReq { + request_id: u32, + padding: u32, + info: VirtioPCIDataInfo, +} + +impl VirtioPCIDataReq { + fn new(request_id: u32, info: VirtioPCIDataInfo) -> Self { + Self { + request_id, + padding: 0, + info, + } + } +} + +#[repr(C)] +struct VirtioPCIBridgeRegion { + hypercall_info: VirtioPCIHypercallInfo, + config_req_front: ReadWrite, + config_req_rear: ReadWrite, + config_res_front: ReadWrite, + config_res_rear: ReadWrite, + data_req_front: ReadWrite, + data_req_rear: ReadWrite, + config_req_list: [VirtioPCIConfigReq; MAX_PCI_CONFIG_REQ], + config_res_list: [VirtioPCIConfigRes; MAX_PCI_CONFIG_RES], + data_req_list: [VirtioPCIDataReq; MAX_PCI_DATA_REQ], +} + +pub struct VirtioPCIBridge { + base: usize, + next_request_id: u32, +} + +impl VirtioPCIBridge { + pub const fn dummy() -> Self { + Self { + base: 0, + next_request_id: 1, + } + } + + pub fn init(&mut self, addr: usize) { + self.base = addr; + self.next_request_id = 1; + assert!(size_of::() <= crate::consts::PAGE_SIZE); + unsafe { + core::ptr::write_bytes(self.base as *mut u8, 0, size_of::()); + } + self.write_hypercall_info(VirtioPCIHypercallInfo::new()); + } + + fn immut_region(&self) -> &VirtioPCIBridgeRegion { + assert!(self.base != 0, "VirtioPCIBridge not initialized"); + unsafe { &*(self.base as *const VirtioPCIBridgeRegion) } + } + + fn region(&mut self) -> &mut VirtioPCIBridgeRegion { + assert!(self.base != 0, "VirtioPCIBridge not initialized"); + unsafe { &mut *(self.base as *mut VirtioPCIBridgeRegion) } + } + + pub fn write_hypercall_info(&mut self, info: VirtioPCIHypercallInfo) { + let region = self.region(); + unsafe { + core::ptr::write_volatile( + &mut region.hypercall_info as *mut VirtioPCIHypercallInfo, + info, + ); + } + fence(Ordering::Release); + } + + pub fn hypercall_info(&self) -> VirtioPCIHypercallInfo { + let region = self.immut_region(); + fence(Ordering::Acquire); + unsafe { core::ptr::read_volatile(®ion.hypercall_info as *const _) } + } + + fn alloc_request_id(&mut self) -> u32 { + let request_id = self.next_request_id; + self.next_request_id = self.next_request_id.wrapping_add(1); + if self.next_request_id == 0 { + self.next_request_id = 1; + } + request_id + } + + fn is_config_req_full(&self) -> bool { + let region = self.immut_region(); + let front = region.config_req_front.get() as usize; + let rear = region.config_req_rear.get() as usize; + fence(Ordering::Acquire); + ((rear + 1) & (MAX_PCI_CONFIG_REQ - 1)) == front + } + + fn is_data_req_full(&self) -> bool { + let region = self.immut_region(); + let front = region.data_req_front.get() as usize; + let rear = region.data_req_rear.get() as usize; + fence(Ordering::Acquire); + ((rear + 1) & (MAX_PCI_DATA_REQ - 1)) == front + } + + fn is_config_res_empty(&self) -> bool { + let region = self.immut_region(); + let front = region.config_res_front.get(); + let rear = region.config_res_rear.get(); + fence(Ordering::Acquire); + front == rear + } + + fn wait_for_queue_slot(&self, is_full: impl Fn(&Self) -> bool, queue_name: &str) -> HvResult { + let mut count = 0usize; + let mut backoff = 1usize; + while is_full(self) { + for _ in 0..backoff { + core::hint::spin_loop(); + } + count += backoff; + if count >= MAX_WAIT_TIMES { + return hv_result_err!(EBUSY, format!("virtio pci {queue_name} queue is full")); + } + backoff = (backoff << 1).min(MAX_BACKOFF); + } + Ok(()) + } + + pub fn push_config_req(&mut self, config: VirtioPCIConfigInfo) -> HvResult { + self.wait_for_queue_slot(Self::is_config_req_full, "config request")?; + let request_id = self.alloc_request_id(); + let region = self.region(); + let rear = region.config_req_rear.get() as usize; + unsafe { + core::ptr::write_volatile( + &mut region.config_req_list[rear] as *mut VirtioPCIConfigReq, + VirtioPCIConfigReq::new(request_id, config), + ); + } + fence(Ordering::Release); + region + .config_req_rear + .set(((rear + 1) & (MAX_PCI_CONFIG_REQ - 1)) as u32); + Ok(request_id) + } + + pub fn push_data_req(&mut self, data_info: VirtioPCIDataInfo) -> HvResult { + self.wait_for_queue_slot(Self::is_data_req_full, "data request")?; + let request_id = self.alloc_request_id(); + let region = self.region(); + let rear = region.data_req_rear.get() as usize; + unsafe { + core::ptr::write_volatile( + &mut region.data_req_list[rear] as *mut VirtioPCIDataReq, + VirtioPCIDataReq::new(request_id, data_info), + ); + } + fence(Ordering::Release); + region + .data_req_rear + .set(((rear + 1) & (MAX_PCI_DATA_REQ - 1)) as u32); + Ok(request_id) + } + + fn peek_config_res(&self) -> VirtioPCIConfigRes { + let region = self.immut_region(); + let front = region.config_res_front.get() as usize; + fence(Ordering::Acquire); + unsafe { core::ptr::read_volatile(®ion.config_res_list[front] as *const _) } + } + + fn advance_config_res(&mut self) { + let region = self.region(); + let front = region.config_res_front.get() as usize; + fence(Ordering::Release); + region + .config_res_front + .set(((front + 1) & (MAX_PCI_CONFIG_RES - 1)) as u32); + } + + pub fn til_config_finish(&mut self, request_id: u32) -> HvResult { + let mut count = 0usize; + let mut backoff = 1usize; + + loop { + if !self.is_config_res_empty() { + let res = self.peek_config_res(); + self.advance_config_res(); + if res.request_id != request_id { + return hv_result_err!( + EIO, + format!( + "virtio pci config response mismatch: expect {}, got {}", + request_id, res.request_id + ) + ); + } + if res.status != 0 { + return hv_result_err!( + EIO, + format!( + "virtio pci config request {} failed with status {}", + request_id, res.status + ) + ); + } + return Ok(res.dev_id); + } + + for _ in 0..backoff { + core::hint::spin_loop(); + } + count += backoff; + if count >= MAX_WAIT_TIMES { + return hv_result_err!( + EBUSY, + format!("virtio pci config request {} timed out", request_id) + ); + } + backoff = (backoff << 1).min(MAX_BACKOFF); + } + } +} + /// El1 and EL2 shared region for virtio requests and results. #[repr(C)] struct VirtioBridge { diff --git a/src/event.rs b/src/event.rs index f31b11594..6c3947e37 100644 --- a/src/event.rs +++ b/src/event.rs @@ -15,14 +15,21 @@ // #![allow(unused)] use crate::{ - arch::ipi::{arch_check_events, arch_prepare_send_event, arch_send_event}, + arch::cpu::this_cpu_id, + arch::ipi::{arch_check_events, arch_notify_event}, consts::{ - IPI_EVENT_CLEAR_INJECT_IRQ, IPI_EVENT_SEND_IPI, IPI_EVENT_UPDATE_HART_LINE, MAX_CPU_NUM, + IPI_EVENT_CLEAR_INJECT_IRQ, IPI_EVENT_DWC_MSI_INJECT, IPI_EVENT_SEND_IPI, + IPI_EVENT_UPDATE_HART_LINE, IPI_EVENT_VCPU_SUSPEND, MAX_CPU_NUM, }, - cpu_data::this_cpu_data, - device::{irqchip::inject_irq, virtio_trampoline::handle_virtio_irq}, + cpu_data::{this_cpu_data, vcpu_suspend, CpuSet}, + device::irqchip::{handle_virtio_irq_event, inject_irq}, platform::IRQ_WAKEUP_VIRTIO_DEVICE, }; +#[cfg(virtio_pci)] +use crate::{ + pci::msix::activate_msix, + platform::{IRQ_WAKEUP_VIRTIO_PCI_CONFIG, IRQ_WAKEUP_VIRTIO_PCI_DATA}, +}; use alloc::{collections::VecDeque, vec::Vec}; use spin::Mutex; @@ -30,6 +37,9 @@ pub const IPI_EVENT_WAKEUP: usize = 0; pub const IPI_EVENT_SHUTDOWN: usize = 1; pub const IPI_EVENT_VIRTIO_INJECT_IRQ: usize = 2; pub const IPI_EVENT_WAKEUP_VIRTIO_DEVICE: usize = 3; +pub const IPI_EVENT_VIRTIO_PCI_CONFIG: usize = 7; +pub const IPI_EVENT_VIRTIO_PCI_DATA: usize = 8; +pub const IPI_EVENT_VIRTIO_PCI_DONE: usize = 9; #[percpu::def_percpu] static PERCPU_EVENTS: Mutex> = Mutex::new(VecDeque::new()); @@ -40,17 +50,20 @@ fn get_percpu_events(cpu: usize) -> &'static Mutex> { unsafe { PERCPU_EVENTS.remote_ref_raw(cpu) } } -fn add_event(cpu: usize, event_id: usize) -> Option<()> { +/// Enqueue an event and report whether the target queue was previously empty. +/// Architectures can use the transition to coalesce their notification mechanism. +fn add_event(cpu: usize, event_id: usize) -> Option { if cpu >= MAX_CPU_NUM { return None; } let mut e = get_percpu_events(cpu).lock(); + let was_empty = e.is_empty(); if event_id == IPI_EVENT_SHUTDOWN { // If the event is shutdown, we need to clear all previous events, because shutdown will make cpu idle and won't process any events. e.clear(); } e.push_back(event_id); - Some(()) + Some(was_empty) } pub fn fetch_event(cpu: usize) -> Option { @@ -83,71 +96,103 @@ pub fn clear_events(cpu: usize) { get_percpu_events(cpu).lock().clear(); } -pub fn check_events() -> bool { +fn handle_event(event: Option) -> bool { let cpu_data = this_cpu_data(); - let event = fetch_event(cpu_data.id); match event { Some(IPI_EVENT_WAKEUP) => { cpu_data.arch_cpu.run(); false } Some(IPI_EVENT_SHUTDOWN) => { + #[cfg(target_arch = "loongarch64")] + { + // Shutdown coalescing may have discarded the queued IRQ-sync + // event. Apply the cleared software bitmap before idling so the + // next zone cannot inherit stale GINTC.VIP bits. + crate::device::irqchip::ls7a2000::sync_guest_irqs(); + } cpu_data.arch_cpu.idle(); false } Some(IPI_EVENT_VIRTIO_INJECT_IRQ) => { - handle_virtio_irq(); + handle_virtio_irq_event(); true } Some(IPI_EVENT_WAKEUP_VIRTIO_DEVICE) => { inject_irq(IRQ_WAKEUP_VIRTIO_DEVICE, false); true } + Some(IPI_EVENT_DWC_MSI_INJECT) => { + #[cfg(all(target_arch = "aarch64", irq_gicv3, dwc_pcie, dwc_msi))] + { + crate::pci::dwc_msi::handle_dwc_msi_inject_event(); + } + true + } + #[cfg(virtio_pci)] + Some(IPI_EVENT_VIRTIO_PCI_CONFIG) => { + inject_irq(IRQ_WAKEUP_VIRTIO_PCI_CONFIG, false); + true + } + #[cfg(virtio_pci)] + Some(IPI_EVENT_VIRTIO_PCI_DATA) => { + inject_irq(IRQ_WAKEUP_VIRTIO_PCI_DATA, false); + true + } + #[cfg(virtio_pci)] + Some(IPI_EVENT_VIRTIO_PCI_DONE) => { + // Virtio PCI notice + // unsafe { + // VIRTIO_MSIX_MANAGER.write().activate_all_pending_irq(); + // } + activate_msix(); + true + } Some(IPI_EVENT_CLEAR_INJECT_IRQ) | Some(IPI_EVENT_UPDATE_HART_LINE) | Some(IPI_EVENT_SEND_IPI) => { arch_check_events(event); true } - // #[cfg(target_arch = "loongarch64")] - // Some(IPI_EVENT_CLEAR_INJECT_IRQ) => { - // use crate::device::irqchip; - // irqchip::ls7a2000::clear_hwi_injected_irq(); - // true - // } - // #[cfg(all(target_arch = "riscv64", feature = "plic"))] - // Some(IPI_EVENT_UPDATE_HART_LINE) => { - // use crate::device::irqchip; - // info!("cpu {} update hart line", cpu_data.id); - // irqchip::plic::update_hart_line(); - // true - // } - // #[cfg(target_arch = "riscv64")] - // Some(IPI_EVENT_SEND_IPI) => { - // // This event is different from events above, it is used to inject software interrupt. - // // While events above will inject external interrupt. - // use crate::arch::ipi::arch_ipi_handler; - // arch_ipi_handler(); - // true - // } + Some(IPI_EVENT_VCPU_SUSPEND) => { + vcpu_suspend(); + true + } _ => false, } } +pub fn check_events() -> bool { + handle_event(fetch_event(this_cpu_data().id)) +} + +/// Handle one queued event, returning whether an event was present. +pub fn handle_next_event() -> bool { + let event = fetch_event(this_cpu_data().id); + if event.is_none() { + return false; + } + handle_event(event); + true +} + pub fn send_event(cpu_id: usize, ipi_int_id: usize, event_id: usize) { - // #[cfg(target_arch = "loongarch64")] - // { - // // block until the previous event is processed, which means - // // the target queue is empty - // while !fetch_event(cpu_id).is_none() {} - // debug!( - // "loongarch64:: send_event: cpu_id: {}, ipi_int_id: {}, event_id: {}", - // cpu_id, ipi_int_id, event_id - // ); - // } - /// Some arch need do something before send event. - /// Currently, we are not passing parameters, and we will modify the function signature later as needed. - arch_prepare_send_event(cpu_id, ipi_int_id, event_id); - add_event(cpu_id, event_id); - arch_send_event(cpu_id as _, ipi_int_id as _); + if let Some(queue_was_empty) = add_event(cpu_id, event_id) { + arch_notify_event(cpu_id as _, ipi_int_id as _, event_id, queue_was_empty); + } +} + +/// Send event to a cpu set (except self). +pub fn send_event_to_all(cpu_set: CpuSet, ipi_int_id: usize, event_id: usize) { + let this_cpu_id = this_cpu_id(); + for target_cpu_id in cpu_set.iter() { + if target_cpu_id == this_cpu_id { + continue; + } + info!( + "send_event_to_all: send event {} to cpu {}", + event_id, target_cpu_id + ); + send_event(target_cpu_id, ipi_int_id, event_id); + } } diff --git a/src/hypercall/mod.rs b/src/hypercall/mod.rs index e7b4bd55d..36587d3d8 100644 --- a/src/hypercall/mod.rs +++ b/src/hypercall/mod.rs @@ -17,17 +17,24 @@ #![allow(unreachable_patterns)] use crate::arch::cpu::get_target_cpu; -use crate::config::HvZoneConfig; -use crate::consts::{INVALID_ADDRESS, MAX_CPU_NUM, MAX_WAIT_TIMES, PAGE_SIZE}; -use crate::cpu_data::{get_cpu_data, PerCpu}; -use crate::device::virtio_trampoline::{MAX_DEVS, VIRTIO_BRIDGE, VIRTIO_IRQS}; +use crate::config::{HvZoneBootMode, HvZoneConfig}; +use crate::consts::{INVALID_ADDRESS, MAX_WAIT_TIMES, PAGE_SIZE}; +use crate::cpu_data::{get_cpu_data, PerCpu, VcpuState}; +use crate::device::virtio_trampoline::{ + VirtioPCIHypercallOp, VIRTIO_BRIDGE, VIRTIO_PCI_BRIDGE, VIRTIO_PCI_HYPERCALL_VERSION, +}; +#[cfg(not(target_arch = "loongarch64"))] +use crate::device::virtio_trampoline::{MAX_DEVS, VIRTIO_IRQS}; use crate::error::HvResult; use crate::pci::pci_config::GLOBAL_PCIE_LIST; use crate::zone::{ - add_zone, all_zones_info, find_zone, is_this_root_zone, remove_zone, zone_create, ZoneInfo, + add_zone, all_zones_info, clear_zone_boot_mode, find_zone, is_this_root_zone, remove_zone, + set_zone_boot_mode, zone_create, ZoneInfo, }; -use crate::event::{send_event, IPI_EVENT_SHUTDOWN, IPI_EVENT_VIRTIO_INJECT_IRQ, IPI_EVENT_WAKEUP}; +#[cfg(not(target_arch = "loongarch64"))] +use crate::event::IPI_EVENT_VIRTIO_INJECT_IRQ; +use crate::event::{send_event, IPI_EVENT_SHUTDOWN, IPI_EVENT_VIRTIO_PCI_DONE, IPI_EVENT_WAKEUP}; use core::convert::TryFrom; use numeric_enum_macro::numeric_enum; @@ -41,11 +48,17 @@ numeric_enum! { HvZoneStart = 2, HvZoneShutdown = 3, HvZoneList = 4, - HvClearInjectIrq = 20, + HvClearInjectIrq = 11, HvIvcInfo = 5, HvConfigCheck = 6, + HvVirtioPCI = 7, + HvZoneSetBootMode = 8, + HvGetEcamBase = 9, } } +#[cfg(target_arch = "loongarch64")] +pub const SGI_IPI_ID: u64 = crate::arch::ipi::HVISOR_EVENT_DOORBELL as u64; +#[cfg(not(target_arch = "loongarch64"))] pub const SGI_IPI_ID: u64 = 7; pub type HyperCallResult = HvResult; @@ -82,18 +95,13 @@ impl<'a> HyperCall<'a> { HyperCallCode::HvZoneShutdown => self.hv_zone_shutdown(arg0), HyperCallCode::HvZoneList => self.hv_zone_list(&mut *(arg0 as *mut ZoneInfo), arg1), HyperCallCode::HvClearInjectIrq => { - use crate::consts::IPI_EVENT_CLEAR_INJECT_IRQ; - for i in 1..MAX_CPU_NUM { - // if target cpu status is not running, we skip it - if !get_cpu_data(i).arch_cpu.power_on { - continue; - } - send_event(i, SGI_IPI_ID as _, IPI_EVENT_CLEAR_INJECT_IRQ); - } - HyperCallResult::Ok(0) + self.hv_virtio_deassert_irq(arg0 as usize, arg1 as usize) } HyperCallCode::HvIvcInfo => self.hv_ivc_info(arg0), HyperCallCode::HvConfigCheck => self.hv_zone_config_check(arg0 as *mut u64), + HyperCallCode::HvVirtioPCI => self.hv_virtio_pci(arg0, arg1), + HyperCallCode::HvZoneSetBootMode => self.hv_zone_set_boot_mode(arg0, arg1), + HyperCallCode::HvGetEcamBase => self.hv_get_ecam_base(arg0 as *mut u64), _ => { warn!("hypercall id={} unsupported!", code as u64); Ok(0) @@ -111,9 +119,7 @@ impl<'a> HyperCall<'a> { if !is_this_root_zone() { return hv_result_err!(EPERM, "Init virtio over non-root zones: unsupported!"); } - let shared_region_addr_pa = self.hv_get_real_pa(shared_region_addr) as usize; - assert!(shared_region_addr_pa % PAGE_SIZE == 0); // let offset = shared_region_addr_pa & (PAGE_SIZE - 1); // memory::hv_page_table() @@ -141,6 +147,7 @@ impl<'a> HyperCall<'a> { ); } let mut res_agent = VIRTIO_BRIDGE.res_agent(); + #[cfg(not(target_arch = "loongarch64"))] let mut map_irq = VIRTIO_IRQS.lock(); while !res_agent.is_empty() { let (_res_front, irq_id, target_zone) = res_agent.peek_front(); @@ -152,33 +159,116 @@ impl<'a> HyperCall<'a> { } }; - let irq_list = map_irq.entry(target_cpu).or_insert([0; MAX_DEVS + 1]); - - self.wait_for_interrupt(irq_list); - if !irq_list[1..=irq_list[0] as usize].contains(&irq_id) { - let len = irq_list[0] as usize; - assert!(len + 1 < MAX_DEVS); - irq_list[len + 1] = irq_id; - irq_list[0] += 1; - send_event( - target_cpu as _, - SGI_IPI_ID as _, - IPI_EVENT_VIRTIO_INJECT_IRQ, + #[cfg(target_arch = "loongarch64")] + { + crate::device::irqchip::ls7a2000::set_guest_irq_line( + target_cpu, + irq_id as usize, + true, ); + res_agent.advance_front(); + continue; } + #[cfg(not(target_arch = "loongarch64"))] + { + let irq_list = map_irq.entry(target_cpu).or_insert([0; MAX_DEVS + 1]); + self.wait_for_interrupt(irq_list); + if !irq_list[1..=irq_list[0] as usize].contains(&irq_id) { + let len = irq_list[0] as usize; + assert!(len + 1 < MAX_DEVS); + irq_list[len + 1] = irq_id; + irq_list[0] += 1; + send_event( + target_cpu as _, + SGI_IPI_ID as _, + IPI_EVENT_VIRTIO_INJECT_IRQ, + ); + } + } + + #[cfg(not(target_arch = "loongarch64"))] res_agent.advance_front(); } drop(res_agent); HyperCallResult::Ok(0) } + pub fn hv_zone_set_boot_mode( + &mut self, + boot_mode_ipa: u64, + boot_mode_size: u64, + ) -> HyperCallResult { + if !is_this_root_zone() { + return hv_result_err!( + EPERM, + "Set zone boot mode over non-root zones: unsupported!" + ); + } + if boot_mode_size != core::mem::size_of::() as _ { + return hv_result_err!( + EINVAL, + format!( + "hv_zone_set_boot_mode: config size should be {} bytes, but got {}", + core::mem::size_of::(), + boot_mode_size + ) + ); + } + + let boot_mode_pa = self.hv_get_real_pa(boot_mode_ipa); + let boot_mode = unsafe { &*(boot_mode_pa as *const HvZoneBootMode) }; + if boot_mode.zone_id == 0 { + return hv_result_err!(EINVAL, "boot mode is not supported for the root zone"); + } + + set_zone_boot_mode(boot_mode.zone_id as usize, *boot_mode); + info!( + "hv_zone_set_boot_mode: zone_id={}, multiboot_enabled={}, info_paddr={:#x}", + boot_mode.zone_id, boot_mode.multiboot_enabled, boot_mode.multiboot_info_paddr + ); + HyperCallResult::Ok(0) + } + + fn hv_virtio_deassert_irq(&mut self, target_zone: usize, irq_id: usize) -> HyperCallResult { + if !is_this_root_zone() { + return hv_result_err!( + EPERM, + "Virtio deassert operation over non-root zones: unsupported!" + ); + } + if find_zone(target_zone).is_none() { + return hv_result_err!(EINVAL, format!("zone {} does not exist", target_zone)); + } + + let target_cpu = get_target_cpu(irq_id, target_zone); + #[cfg(target_arch = "loongarch64")] + { + if !crate::device::irqchip::ls7a2000::set_guest_irq_line(target_cpu, irq_id, false) { + return hv_result_err!( + EINVAL, + format!( + "invalid LoongArch guest HWI {} for zone {}", + irq_id, target_zone + ) + ); + } + return HyperCallResult::Ok(0); + } + + #[cfg(not(target_arch = "loongarch64"))] + hv_result_err!( + ENOSYS, + "per-IRQ Virtio deassert is not implemented on this architecture" + ) + } + pub fn hv_zone_start(&mut self, config: &HvZoneConfig, config_size: u64) -> HyperCallResult { let config_ipa = config as *const HvZoneConfig as u64; let config_pa = self.hv_get_real_pa(config_ipa); let config = unsafe { &*(config_pa as *const HvZoneConfig) }; - debug!("hv_zone_start: config: {:#x?}", config); + info!("hv_zone_start: config: {:#x?},pa:{:#x}", config, config_pa); if !is_this_root_zone() { return hv_result_err!( EPERM, @@ -195,20 +285,22 @@ impl<'a> HyperCall<'a> { ) ); } - let zone = zone_create(config)?; + let zone_result = zone_create(config); + clear_zone_boot_mode(config.zone_id as usize); + let zone = zone_result?; let boot_cpu = zone.read().cpu_set().first_cpu().unwrap(); let target_data = get_cpu_data(boot_cpu as _); let _lock = target_data.ctrl_lock.lock(); - if !target_data.arch_cpu.power_on { + if target_data.vcpu_state.is_stopped() { info!("boot_cpu: {}", boot_cpu); + target_data.vcpu_state.store(VcpuState::Ready); send_event(boot_cpu, SGI_IPI_ID as _, IPI_EVENT_WAKEUP); } else { error!("hv_zone_start: cpu {} already on", boot_cpu); return hv_result_err!(EBUSY); }; - self.check_cpu_id(); add_zone(zone); drop(_lock); HyperCallResult::Ok(0) @@ -226,6 +318,7 @@ impl<'a> HyperCall<'a> { return hv_result_err!(EINVAL); } // avoid virtio daemon send sgi to the shutdowning zone + #[cfg(not(target_arch = "loongarch64"))] let mut map_irq = VIRTIO_IRQS.lock(); let zone = match find_zone(zone_id as _) { @@ -242,8 +335,11 @@ impl<'a> HyperCall<'a> { zone_w.cpu_set().iter().for_each(|cpu_id| { let _lock = get_cpu_data(cpu_id).ctrl_lock.lock(); get_cpu_data(cpu_id).cpu_on_entry = INVALID_ADDRESS; + #[cfg(target_arch = "loongarch64")] + crate::device::irqchip::ls7a2000::clear_guest_irq_lines(cpu_id); send_event(cpu_id, SGI_IPI_ID as _, IPI_EVENT_SHUTDOWN); // set the virtio irq list's len to 0 + #[cfg(not(target_arch = "loongarch64"))] if let Some(irq_list) = map_irq.get_mut(&cpu_id) { irq_list[0] = 0; } @@ -251,18 +347,18 @@ impl<'a> HyperCall<'a> { let mut count: usize = 0; - // wait all zone's cpus shutdown + // wait all zone's cpus shutdown (Stopped only: includes Blocked / Ready / Running) while zone_w.cpu_set().iter().any(|cpu_id| { let _lock = get_cpu_data(cpu_id).ctrl_lock.lock(); - let power_on = get_cpu_data(cpu_id).arch_cpu.power_on; + let not_stopped = !get_cpu_data(cpu_id).vcpu_state.is_stopped(); count += 1; if count > MAX_WAIT_TIMES { - if power_on { + if not_stopped { error!("cpu {} cannot be shut down", cpu_id); return false; } } - power_on + not_stopped }) {} zone_w.cpu_set().iter().for_each(|cpu_id| { @@ -272,6 +368,10 @@ impl<'a> HyperCall<'a> { drop(zone_w); zone.arch_irqchip_reset(); + + // Remove viommu instance related to this zone. + #[cfg(viommu)] + crate::device::iommu::viommu_remove(zone_id as usize); drop(zone); // Reset zone_id for all devices allocated to this zone @@ -316,4 +416,81 @@ impl<'a> HyperCall<'a> { HyperCallResult::Ok(core::cmp::min(cnt as _, zones_info.len())) } + + fn hv_virtio_pci(&mut self, arg0: u64, arg1: u64) -> HyperCallResult { + const VIRTIO_PCI_INIT: u64 = 0; + const VIRTIO_PCI_DOORBELL: u64 = 1; + + if !is_this_root_zone() { + return hv_result_err!( + EPERM, + "Virtio PCI operation over non-root zones: unsupported!" + ); + } + + match arg0 { + VIRTIO_PCI_INIT => { + let shared_pci_region_addr_pa = self.hv_get_real_pa(arg1) as usize; + assert!(shared_pci_region_addr_pa % PAGE_SIZE == 0); + let mut bridge = VIRTIO_PCI_BRIDGE.lock(); + bridge.init(shared_pci_region_addr_pa); + let info = bridge.hypercall_info(); + if info.version != VIRTIO_PCI_HYPERCALL_VERSION { + return hv_result_err!( + EINVAL, + format!( + "Virtio PCI hypercall version mismatch: expect {}, got {}", + VIRTIO_PCI_HYPERCALL_VERSION, info.version + ) + ); + } + HyperCallResult::Ok(0) + } + VIRTIO_PCI_DOORBELL => { + let bridge = VIRTIO_PCI_BRIDGE.lock(); + let info = bridge.hypercall_info(); + if info.version != VIRTIO_PCI_HYPERCALL_VERSION { + return hv_result_err!( + EINVAL, + format!( + "Virtio PCI hypercall version mismatch: expect {}, got {}", + VIRTIO_PCI_HYPERCALL_VERSION, info.version + ) + ); + } + + let op = VirtioPCIHypercallOp::try_from(info.op).map_err(|_| { + hv_err!( + EINVAL, + format!("Unknown virtio pci hypercall op {}", info.op) + ) + })?; + + match op { + VirtioPCIHypercallOp::None | VirtioPCIHypercallOp::ConfigReqComplete => { + HyperCallResult::Ok(0) + } + VirtioPCIHypercallOp::DataReqComplete => { + send_event( + info.target_cpu as usize, + SGI_IPI_ID as usize, + IPI_EVENT_VIRTIO_PCI_DONE, + ); + HyperCallResult::Ok(0) + } + VirtioPCIHypercallOp::Reset => { + drop(bridge); + VIRTIO_PCI_BRIDGE.lock().write_hypercall_info( + crate::device::virtio_trampoline::VirtioPCIHypercallInfo::new(), + ); + HyperCallResult::Ok(0) + } + } + } + _ => hv_result_err!( + EINVAL, + format!("Unknown virtio pci hypercall mode {}", arg0) + ), + } + } } diff --git a/src/logging.rs b/src/logging.rs index 6f8320c05..c5df83300 100644 --- a/src/logging.rs +++ b/src/logging.rs @@ -38,7 +38,24 @@ impl Write for Stdout { } } +// The number of checks for UART console availability when sequential output is enabled. +// Tips: this may cause a long delay when the console is busy, so it should be set to a small value, +// and the default value is 3000, which is enough for most cases. +pub const CHECK_NUM: u64 = 3000; pub fn print(args: fmt::Arguments) { + #[cfg(sequential_output)] + { + let mut flag = false; + while !flag { + flag = true; + for _i in 1..CHECK_NUM { + if !uart::console_free_check() { + flag = false; + break; + } + } + } + } let _locked = PRINT_LOCK.lock(); Stdout.write_fmt(args).unwrap(); } @@ -133,7 +150,7 @@ pub fn init() { struct SimpleLogger; impl SimpleLogger { - #[cfg(feature = "graphics")] + #[cfg(graphics)] fn print( &self, level: Level, @@ -154,7 +171,7 @@ impl SimpleLogger { ); } - #[cfg(not(feature = "graphics"))] + #[cfg(not(graphics))] fn print( &self, level: Level, @@ -165,7 +182,7 @@ impl SimpleLogger { args_color: ColorCode, record: &Record, ) { - #[cfg(feature = "print_timestamp")] + #[cfg(print_timestamp)] { let time_us: u64 = crate::arch::time::get_time_us(); let sec = time_us / 1_000_000; @@ -180,7 +197,7 @@ impl SimpleLogger { with_color!(args_color, "{}", record.args()), )); } - #[cfg(not(feature = "print_timestamp"))] + #[cfg(not(print_timestamp))] print(with_color!( ColorCode::White, "[{} {}] {} {}\n", diff --git a/src/main.rs b/src/main.rs index 736d209b7..c30abda28 100644 --- a/src/main.rs +++ b/src/main.rs @@ -69,11 +69,11 @@ mod tests; use crate::arch::mm::{arch_post_heap_init, arch_setup_parange}; use crate::consts::{hv_end, mem_pool_start, MAX_CPU_NUM}; use crate::device::iommu::iommu_init; -use arch::{cpu::cpu_start, entry::arch_entry}; +use arch::{arch_config_by_args, cpu::cpu_start, entry::arch_entry}; use config::root_zone_config; use core::sync::atomic::{AtomicI32, AtomicU32, Ordering}; use cpu_data::PerCpu; -#[cfg(feature = "pci")] +#[cfg(all(pci, not(pci_init_delay)))] use pci::pci_config::hvisor_pci_init; static INITED_CPUS: AtomicU32 = AtomicU32::new(0); @@ -132,12 +132,12 @@ fn primary_init_early() { device::irqchip::primary_init_early(); - #[cfg(feature = "iommu")] + #[cfg(iommu)] iommu_init(); let root_config = root_zone_config(); - #[cfg(feature = "pci")] + #[cfg(all(pci, not(pci_init_delay)))] if root_config.num_pci_bus > 0 { let num_pci_bus = root_config.num_pci_bus as usize; let _ = hvisor_pci_init(&root_config.pci_config[..num_pci_bus]); @@ -231,6 +231,7 @@ fn rust_main(cpuid: usize, host_dtb: usize) { if is_primary { primary_init_early(); // create root zone here + arch_config_by_args(cpuid, host_dtb); } else { wait_for_counter(&INIT_EARLY_OK, 1); } diff --git a/src/memory/frame.rs b/src/memory/frame.rs index b7a64f856..54cefcb72 100644 --- a/src/memory/frame.rs +++ b/src/memory/frame.rs @@ -73,6 +73,9 @@ impl FrameAllocator { frame_count: usize, align_log2: usize, ) -> Option { + if frame_count == 0 || align_log2 >= usize::BITS as usize { + return None; + } let ret = self .inner .alloc_contiguous(frame_count, align_log2) @@ -86,6 +89,66 @@ impl FrameAllocator { ret } + /// Allocate contiguous frames whose physical page number has its lower + /// `align_log2` bits cleared. + /// + /// # Safety + /// + /// This function is unsafe because you need to deallocate manually. + unsafe fn alloc_contiguous_with_base( + &mut self, + frame_count: usize, + align_log2: usize, + ) -> Option { + if frame_count == 0 || align_log2 >= usize::BITS as usize { + return None; + } + + let align_pages = 1usize << align_log2; + let align_mask = align_pages - 1; + let base_page = self.base / PAGE_SIZE; + let mut start = 0; + + while start < FrameAlloc::CAP { + // Only an aligned physical page can start a candidate range. + let start_page = base_page.checked_add(start)?; + if start_page & align_mask != 0 { + start += 1; + continue; + } + + // Count consecutive free frames from the aligned start index. + let mut idx = start; + loop { + match self.inner.next(idx) { + Some(next) if next == idx => { + idx += 1; + // Allocate immediately once enough consecutive frames are found. + if idx - start == frame_count { + let start_paddr = + start.checked_mul(PAGE_SIZE)?.checked_add(self.base)?; + self.inner.remove(start..idx); + trace!( + "Allocate {} frames with physical alignment {} pages: {:x}", + frame_count, + align_pages, + start_paddr + ); + return Some(start_paddr); + } + } + Some(next) => { + // Skip the allocated gap and try the next free frame. + start = next; + break; + } + None => return None, + } + } + } + None + } + /// # Safety /// /// This function is unsafe because the frame must have been allocated. @@ -143,36 +206,18 @@ impl Frame { } } - /// allocate contigugous frames, and you can specify the alignment, set the lower `align_log2` bits to 0. + /// Allocate contiguous frames whose physical page number has its lower + /// `align_log2` bits cleared. pub fn new_contiguous_with_base(frame_count: usize, align_log2: usize) -> HvResult { - let align_mask = (1 << align_log2) - 1; - // Create a vector to keep track of attempted frames - let mut attempted_frames = Vec::new(); - loop { - if let Ok(frame) = Frame::new_contiguous(frame_count, 0) { - if frame.start_paddr() & align_mask == 0 { - // info!( - // "new contiguous success!!! start_paddr:0x{:x}", - // frame.start_paddr() - // ); - return Ok(frame); - } else { - let start_paddr = frame.start_paddr(); - let next_aligned_addr = (start_paddr + align_mask) & !align_mask; - let temp_frame_count = (next_aligned_addr - start_paddr) / PAGE_SIZE; - drop(frame); - attempted_frames.push(Frame::new_contiguous(temp_frame_count, 0)); - if let Ok(frame) = Frame::new_contiguous(frame_count, 0) { - // info!( - // "new contiguous success!!! start_paddr:0x{:x}", - // frame.start_paddr() - // ); - return Ok(frame); - } - } - } else { - return Err(hv_err!(ENOMEM)); - } + unsafe { + FRAME_ALLOCATOR + .lock() + .alloc_contiguous_with_base(frame_count, align_log2) + .map(|start_paddr| Self { + start_paddr, + frame_count, + }) + .ok_or(hv_err!(ENOMEM)) } } @@ -190,23 +235,6 @@ impl Frame { } } - pub fn new_16() -> HvResult { - let mut v: Vec = Vec::new(); - loop { - let f = Self::new_zero()?; - if f.start_paddr & 0b11_1111_1111_1111 == 0 { - v.push(f); - break; - } - v.push(f); - } - let f_16 = v.pop().unwrap(); - drop(f_16); - let ret = Self::new_contiguous(4, 0)?; - drop(v); - Ok(ret) - } - /// Get the start physical address of this frame. pub fn start_paddr(&self) -> PhysAddr { self.start_paddr @@ -289,6 +317,8 @@ pub fn init() { } pub fn test() { + const ALIGN_16K: usize = 16 * 1024; + let mut v: Vec = Vec::new(); for _ in 0..5 { let frame = Frame::new().unwrap(); @@ -302,5 +332,10 @@ pub fn test() { v.push(frame); } drop(v); + + let frame = Frame::new_contiguous_with_base(ALIGN_16K / PAGE_SIZE, 2).unwrap(); + assert_eq!(frame.start_paddr() % ALIGN_16K, 0); + assert_eq!(frame.size(), ALIGN_16K); + info!("frame_allocator_test passed!"); } diff --git a/src/memory/mapper.rs b/src/memory/mapper.rs index 0b391bfed..42556b633 100644 --- a/src/memory/mapper.rs +++ b/src/memory/mapper.rs @@ -54,7 +54,6 @@ impl + Into + Copy> MemoryRegion { flags: MemFlags, ) -> Self { let start_vaddr = start_vaddr.into(); - let start_paddr = start_paddr; // bug: vaddr > paddr? let phys_virt_offset = start_vaddr.wrapping_sub(start_paddr); Self::new( diff --git a/src/memory/mm.rs b/src/memory/mm.rs index 26adab8a9..0ba681fb1 100644 --- a/src/memory/mm.rs +++ b/src/memory/mm.rs @@ -93,6 +93,28 @@ where self.pt.root_paddr() } + /// Check whether `[start, start+size)` overlaps with any region in this MemorySet. + pub fn is_range_overlap(&self, start: usize, size: usize) -> bool + where + PT::VA: From, + { + let end = start + size; + let va_start: PT::VA = start.into(); + if let Some((_, before)) = self.regions.range(..va_start).last() { + let before_end: usize = before.start.into() + before.size; + if before_end > start { + return true; + } + } + if let Some((_, after)) = self.regions.range(va_start..).next() { + let after_start: usize = after.start.into(); + if after_start < end { + return true; + } + } + false + } + fn test_free_area(&self, other: &MemoryRegion) -> bool { if let Some((_, before)) = self.regions.range(..other.start).last() { if before.is_overlap_with(other) { @@ -165,6 +187,20 @@ where Ok(()) } + /// Get the memory region which contains the `start` address. + pub fn get_region(&self, start: PT::VA) -> Option> { + // Find a region that completely includes the range [start, end) + for (key, region) in self.regions.range(..=start) { + let region_start = *key; + let region_end = region_start.into() + region.size; + // Return the region contains the start address + if region_start <= start && region_end > start.into() { + return Some(region.clone()); + } + } + None + } + /// Find and remove memory region which starts from `start` and `size` pub fn delete(&mut self, start: PT::VA, size: usize) -> HvResult { if let Entry::Occupied(e) = self.regions.entry(start) { diff --git a/src/memory/mmio.rs b/src/memory/mmio.rs index 1d4771892..f8522da13 100644 --- a/src/memory/mmio.rs +++ b/src/memory/mmio.rs @@ -51,6 +51,13 @@ impl MMIORegion { pub fn contains_region(&self, addr: GuestPhysAddr, sz: usize) -> bool { addr >= self.start && addr + (sz as usize) <= self.start + (self.size as usize) } + + /// Check whether this region overlaps with `other`. + pub fn is_overlap_with(&self, other: &MMIORegion) -> bool { + let self_end = self.start + self.size; + let other_end = other.start + other.size; + !(self_end <= other.start || self.start >= other_end) + } } pub fn mmio_perform_access(base: usize, mmio: &mut MMIOAccess) { diff --git a/src/pci/config_accessors/loongarch64.rs b/src/pci/config_accessors/loongarch64.rs index cf60e4370..43a0ecc67 100644 --- a/src/pci/config_accessors/loongarch64.rs +++ b/src/pci/config_accessors/loongarch64.rs @@ -16,7 +16,7 @@ use alloc::sync::Arc; -use super::{PciConfigAccessor, PciConfigMmio}; +use super::{PciConfigAccessor, PciConfigMmio, PciRegion}; use crate::{ error::HvResult, @@ -40,60 +40,29 @@ impl RootComplex { // LoongArch PCIe accessor implementation #[derive(Debug)] pub struct LoongArchConfigAccessor { - cfg0: PciConfigAddress, - cfg1: PciConfigAddress, + cfg_base: PciConfigAddress, root_bus: u8, } impl LoongArchConfigAccessor { - pub fn new(cfg_base: PciConfigAddress, cfg_size: u64, root_bus: u8) -> Self { - let cfg_size_half = cfg_size / 2; - let cfg0 = cfg_base; - let cfg1 = cfg_base + cfg_size_half; - Self { - cfg0, - cfg1, - root_bus, + pub fn new(cfg_base: PciConfigAddress, _cfg_size: u64, root_bus: u8) -> Self { + Self { cfg_base, root_bus } + } + + fn cfg_map(&self, bdf: Bdf, offset: PciConfigAddress) -> PciConfigAddress { + let devfn = ((bdf.device() as PciConfigAddress) << 3) | bdf.function() as PciConfigAddress; + let mut addroff = (devfn << 8) | (offset & 0xff) | ((offset & 0xf00) << 16); + if bdf.bus() != self.root_bus { + addroff |= 1 << 28; + addroff |= (bdf.bus() as PciConfigAddress) << 16; } + self.cfg_base + addroff } } impl PciConfigAccessor for LoongArchConfigAccessor { fn get_pci_addr_base(&self, bdf: Bdf) -> HvResult { - let bus = bdf.bus() as PciConfigAddress; - let device = bdf.device() as PciConfigAddress; - let function = bdf.function() as PciConfigAddress; - let offset = 0; - - // Extract Offset[11:8] (bits 11-8 of offset) for bits 31-28 - let offset_high = (offset >> 8) & 0xf; - // Extract Offset[7:0] (bits 7-0 of offset) for bits 7-0 - let offset_low = offset & 0xff; - - let address = if bus == self.root_bus as PciConfigAddress { - // Type 0 format (Root Bus): - // Bits 31-28: Offset[11:8] - // Bits 27-16: Reserved (0) - // Bits 15-11: Device Number - // Bits 10-8: Function Number - // Bits 7-0: Offset[7:0] - self.cfg0 + ((offset_high << 24) | (device << 11) | (function << 8) | offset_low) - } else { - // Type 1 format (Other Bus): - // Bits 31-28: Offset[11:8] - // Bits 27-16: Bus Number - // Bits 15-11: Device Number - // Bits 10-8: Function Number - // Bits 7-0: Offset[7:0] - self.cfg1 - + ((offset_high << 24) - | (bus << 16) - | (device << 11) - | (function << 8) - | offset_low) - }; - - Ok(address) + Ok(self.cfg_map(bdf, 0)) } fn get_physical_address( @@ -102,39 +71,7 @@ impl PciConfigAccessor for LoongArchConfigAccessor { offset: PciConfigAddress, _parent_bus: u8, ) -> HvResult { - let bus = bdf.bus() as PciConfigAddress; - let device = bdf.device() as PciConfigAddress; - let function = bdf.function() as PciConfigAddress; - - // Extract Offset[11:8] (bits 11-8 of offset) for bits 31-28 - let offset_high = (offset >> 8) & 0xf; - // Extract Offset[7:0] (bits 7-0 of offset) for bits 7-0 - let offset_low = offset & 0xff; - - let address = if bus == self.root_bus as PciConfigAddress { - // Type 0 format (Root Bus): - // Bits 31-28: Offset[11:8] - // Bits 27-16: Reserved (0) - // Bits 15-11: Device Number - // Bits 10-8: Function Number - // Bits 7-0: Offset[7:0] - self.cfg0 + ((offset_high << 24) | (device << 11) | (function << 8) | offset_low) - } else { - // Type 1 format (Other Bus): - // Bits 31-28: Offset[11:8] - // Bits 27-16: Bus Number - // Bits 15-11: Device Number - // Bits 10-8: Function Number - // Bits 7-0: Offset[7:0] - self.cfg1 - + ((offset_high << 24) - | (bus << 16) - | (device << 11) - | (function << 8) - | offset_low) - }; - - Ok(address) + Ok(self.cfg_map(bdf, offset)) } fn skip_device(&self, _bdf: Bdf) -> bool { @@ -147,6 +84,61 @@ pub const LOONG_HT_PREFIX: u64 = 0xe00_0000_0000; impl PciConfigMmio { pub(crate) fn access(&self, offset: PciConfigAddress) -> *mut T { - (self.base + offset | HV_ADDR_PREFIX | LOONG_HT_PREFIX) as *mut T + let addroff = (offset & 0xff) | ((offset & 0xf00) << 16); + (self.base + addroff | HV_ADDR_PREFIX | LOONG_HT_PREFIX) as *mut T + } + + fn read_u32_aligned(&self, offset: PciConfigAddress) -> u32 { + unsafe { self.access::(offset & !0x3).read_volatile() } + } + + fn write_u32_aligned(&self, offset: PciConfigAddress, value: u32) { + unsafe { self.access::(offset & !0x3).write_volatile(value) } + } + + fn read_aligned_part(&self, offset: PciConfigAddress, size: u32) -> u32 { + let value = self.read_u32_aligned(offset); + let shift = ((offset & 0x3) * 8) as u32; + let mask = (1u32 << (size * 8)) - 1; + + (value >> shift) & mask + } + + fn write_aligned_part(&self, offset: PciConfigAddress, size: u32, value: u32) { + let shift = ((offset & 0x3) * 8) as u32; + let mask = !(((1u32 << (size * 8)) - 1) << shift); + let old = self.read_u32_aligned(offset); + let new = (old & mask) | (value << shift); + + self.write_u32_aligned(offset, new); + } +} + +impl PciRegion for PciConfigMmio { + fn read_u8(&self, offset: PciConfigAddress) -> HvResult { + Ok(self.read_aligned_part(offset, 1) as u8) + } + + fn write_u8(&self, offset: PciConfigAddress, value: u8) -> HvResult { + self.write_aligned_part(offset, 1, value as u32); + Ok(()) + } + + fn read_u16(&self, offset: PciConfigAddress) -> HvResult { + Ok(self.read_aligned_part(offset, 2) as u16) + } + + fn write_u16(&self, offset: PciConfigAddress, value: u16) -> HvResult { + self.write_aligned_part(offset, 2, value as u32); + Ok(()) + } + + fn read_u32(&self, offset: PciConfigAddress) -> HvResult { + Ok(self.read_u32_aligned(offset)) + } + + fn write_u32(&self, offset: PciConfigAddress, value: u32) -> HvResult { + self.write_u32_aligned(offset, value); + Ok(()) } } diff --git a/src/pci/config_accessors/mod.rs b/src/pci/config_accessors/mod.rs index 544505a6a..305a826cb 100644 --- a/src/pci/config_accessors/mod.rs +++ b/src/pci/config_accessors/mod.rs @@ -65,11 +65,7 @@ impl PciRegionMmio { } } -#[cfg(all( - not(feature = "ecam_pcie"), - not(feature = "dwc_pcie"), - not(feature = "loongarch64_pcie") -))] +#[cfg(not(pci))] impl PciConfigMmio { pub fn access(&self, offset: PciConfigAddress) -> *mut T { (self.base + offset) as *mut T @@ -100,6 +96,7 @@ impl PciRegion for PciRegionMmio { } } +#[cfg(not(loongarch64_pcie))] impl PciRegion for PciConfigMmio { fn read_u8(&self, offset: PciConfigAddress) -> HvResult { unsafe { Ok(self.access::(offset).read_volatile() as u8) } @@ -147,13 +144,13 @@ pub enum PciAccessorType { } // Export accessor implementations -#[cfg(feature = "ecam_pcie")] +#[cfg(ecam_pcie)] pub mod ecam; -#[cfg(feature = "dwc_pcie")] +#[cfg(dwc_pcie)] pub mod dwc; -#[cfg(feature = "dwc_pcie")] +#[cfg(dwc_pcie)] pub mod dwc_atu; -#[cfg(feature = "loongarch64_pcie")] +#[cfg(loongarch64_pcie)] pub mod loongarch64; diff --git a/src/pci/dwc_msi.rs b/src/pci/dwc_msi.rs new file mode 100644 index 000000000..bd22abf60 --- /dev/null +++ b/src/pci/dwc_msi.rs @@ -0,0 +1,342 @@ +// Copyright (c) 2025 Syswonder +// hvisor is licensed under Mulan PSL v2. +// You can use this software according to the terms and conditions of the Mulan PSL v2. +// You may obtain a copy of Mulan PSL v2 at: +// http://license.coscl.org.cn/MulanPSL2 +// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR +// FIT FOR A PARTICULAR PURPOSE. +// See the Mulan PSL v2 for more details. +// +// Syswonder Website: +// https://www.syswonder.org +// +// Authors: +// + +use alloc::collections::btree_map::BTreeMap; +#[cfg(all(dwc_pcie, dwc_msi))] +use alloc::collections::VecDeque; +use alloc::vec::Vec; +use spin::{Lazy, Mutex}; + +#[cfg(all(dwc_pcie, dwc_msi))] +use crate::cpu_data::this_cpu_data; +use crate::error::HvResult; +#[cfg(all(dwc_pcie, dwc_msi))] +use crate::event::send_event; +use crate::memory::Frame; +#[cfg(all(dwc_pcie, dwc_msi))] +use crate::{ + consts::{IPI_EVENT_DWC_MSI_INJECT, MAX_CPU_NUM}, + device::irqchip::inject_irq, + hypercall::SGI_IPI_ID, +}; + +// DBI MSI register offsets +pub const PCIE_MSI_ADDR_LO: usize = 0x820; +pub const PCIE_MSI_ADDR_HI: usize = 0x824; +pub const PCIE_MSI_INTR0_ENABLE: usize = 0x828; +pub const PCIE_MSI_INTR0_MASK: usize = 0x82c; +pub const PCIE_MSI_INTR0_STATUS: usize = 0x830; + +/// DesignWare native MSI domain configuration +/// Each PCIe RC (domain) has a set of 32 MSI vectors that can be distributed +/// across multiple VMs. This structure manages the allocation of these vectors +/// and provides storage for the MSI doorbell address. +#[derive(Debug, Copy, Clone)] +pub struct DwMsiBitOwner { + /// Target vCPU used for injection when forwarding this MSI + pub target_cpu: usize, + /// First hardware MSI bit in this allocation + pub start_hwirq_bit: u32, + /// Number of contiguous vectors in this allocation + pub num_vectors: u32, +} + +impl DwMsiBitOwner { + #[inline] + pub fn contains_hwbit(&self, hwbit: u32) -> bool { + hwbit >= self.start_hwirq_bit && hwbit < self.start_hwirq_bit + self.num_vectors + } +} + +#[derive(Debug)] +pub struct DwMsiDomain { + /// Next MSI vector index to allocate (0-31) + /// When a VM allocates N vectors, it gets indices [next_alloc, next_alloc+N) + pub next_alloc: u32, + + /// Physical page frame for the doorbell address + /// Each domain has one unique doorbell that is written by hvisor + pub doorbell_frame: Frame, + + /// Shared physical interrupt line used by this DWC RC MSI block + pub irq: u32, + + /// Per-zone allocation records for fast hwbit -> zone/cpu lookup + pub bit_owners: Vec, +} + +impl DwMsiDomain { + /// Create a new DW MSI domain for a PCIe RC + pub fn new(irq: u32) -> HvResult { + let doorbell_frame = Frame::new_zero()?; + + Ok(Self { + next_alloc: 0, + doorbell_frame, + irq, + bit_owners: Vec::new(), + }) + } + + /// Allocate a contiguous range of MSI vectors for a VM + /// Returns the starting vector index if successful, or error if not enough vectors available + pub fn allocate(&mut self, num_vectors: u32) -> HvResult { + // Check if there are enough vectors left (32 total vectors per domain) + if self.next_alloc + num_vectors > 32 { + return hv_result_err!(EINVAL, "Not enough MSI vectors available in domain"); + } + + let alloc_offset = self.next_alloc; + self.next_alloc += num_vectors; + + Ok(alloc_offset) + } + + /// Allocate MSI vectors for a zone and record the ownership mapping. + pub fn allocate_for_cpu(&mut self, target_cpu: usize, num_vectors: u32) -> HvResult { + let start_hwirq_bit = self.allocate(num_vectors)?; + self.bit_owners.push(DwMsiBitOwner { + target_cpu, + start_hwirq_bit, + num_vectors, + }); + info!( + "DW MSI owner added: cpu {}, vectors {}, range [{}..{}), total_owner_records {}", + target_cpu, + num_vectors, + start_hwirq_bit, + start_hwirq_bit + num_vectors, + self.bit_owners.len() + ); + Ok(start_hwirq_bit) + } + + /// Find the owner record by hardware MSI bit. + pub fn find_owner_by_hwbit(&self, hwbit: u32) -> Option { + self.bit_owners + .iter() + .copied() + .find(|owner| owner.contains_hwbit(hwbit)) + } + + /// Get the physical address of the doorbell for this domain + pub fn doorbell_paddr(&self) -> u64 { + self.doorbell_frame.start_paddr() as u64 + } +} + +/// Global storage for DW MSI domain configurations +/// Indexed by domain ID +pub static DW_MSI_DOMAINS: Lazy>> = + Lazy::new(|| Mutex::new(BTreeMap::new())); + +#[cfg(all(dwc_pcie, dwc_msi))] +static DWC_MSI_IPI_PENDING_IRQS: Lazy>>> = Lazy::new(|| { + let mut queues = Vec::with_capacity(MAX_CPU_NUM); + for _ in 0..MAX_CPU_NUM { + queues.push(VecDeque::new()); + } + Mutex::new(queues) +}); + +/// Initialize DW MSI domain for a given domain ID +pub fn init_dwc_msi_domain(domain_id: u8, irq: u32) -> HvResult<()> { + let domain = DwMsiDomain::new(irq)?; + let doorbell_paddr = domain.doorbell_paddr(); + DW_MSI_DOMAINS.lock().insert(domain_id, domain); + info!( + "Initialized DW MSI domain {} with doorbell at {:#x}, irq {}", + domain_id, doorbell_paddr, irq + ); + Ok(()) +} + +/// Get mutable reference to a DW MSI domain +pub fn get_dwc_msi_domain_mut( + domain_id: u8, +) -> Option>> { + let domains = DW_MSI_DOMAINS.lock(); + if domains.contains_key(&domain_id) { + drop(domains); + Some(DW_MSI_DOMAINS.lock()) + } else { + None + } +} + +/// Get the doorbell physical address for a specific domain +/// Returns 0 if domain not found +pub fn get_domain_doorbell_paddr(domain_id: u8) -> u64 { + let domains = DW_MSI_DOMAINS.lock(); + domains + .get(&domain_id) + .map(|domain| domain.doorbell_paddr()) + .unwrap_or(0) +} + +/// Get the shared hardware MSI IRQ for a specific domain +/// Returns 0 if domain not found +pub fn get_domain_msi_irq(domain_id: u8) -> u32 { + let domains = DW_MSI_DOMAINS.lock(); + domains + .get(&domain_id) + .map(|domain| domain.irq) + .unwrap_or(0) +} + +/// Check whether an IRQ is used as a shared DWC MSI hardware interrupt +pub fn is_dwc_msi_irq(irq: u32) -> bool { + let domains = DW_MSI_DOMAINS.lock(); + domains.values().any(|domain| domain.irq == irq) +} + +/// Check whether an IRQ matches any configured DWC MSI hardware interrupt. +pub fn is_dwc_msi_hwirq(irq: u32) -> bool { + is_dwc_msi_irq(irq) +} + +/// Return all domain IDs that share the specified DWC MSI hardware IRQ. +pub fn get_domains_by_irq(irq: u32) -> Vec { + let domains = DW_MSI_DOMAINS.lock(); + domains + .iter() + .filter_map(|(domain_id, domain)| { + if domain.irq == irq { + Some(*domain_id) + } else { + None + } + }) + .collect() +} + +/// Find bit ownership for a specific domain and hardware MSI bit. +pub fn get_domain_owner_by_hwirq_bit(domain_id: u8, hwbit: u32) -> Option { + let domains = DW_MSI_DOMAINS.lock(); + domains + .get(&domain_id) + .and_then(|domain| domain.find_owner_by_hwbit(hwbit)) +} + +#[cfg(all(dwc_pcie, dwc_msi))] +fn get_domain_dbi_base(domain_id: u8) -> Option { + let ecam_base = crate::platform::ROOT_PCI_CONFIG + .iter() + .find(|cfg| cfg.domain == domain_id) + .map(|cfg| cfg.ecam_base)?; + + crate::platform::ROOT_DWC_ATU_CONFIG + .iter() + .find(|cfg| cfg.ecam_base == ecam_base) + .map(|cfg| cfg.dbi_base as usize) +} + +#[cfg(all(dwc_pcie, dwc_msi))] +fn first_set_bit(mask: u32) -> Option { + if mask == 0 { + None + } else { + Some(mask.trailing_zeros()) + } +} + +#[cfg(all(dwc_pcie, dwc_msi))] +fn find_target_cpu(domain_id: u8, irq_bit: usize) -> Option { + get_domain_owner_by_hwirq_bit(domain_id, irq_bit as u32).map(|owner| owner.target_cpu) +} + +#[cfg(all(dwc_pcie, dwc_msi))] +fn dwc_msi_pending_irq_bit(domain_id: u8) -> Option { + let dbi_base = get_domain_dbi_base(domain_id)?; + let status = + unsafe { core::ptr::read_volatile((dbi_base + PCIE_MSI_INTR0_STATUS) as *const u32) }; + first_set_bit(status) +} + +#[cfg(all(dwc_pcie, dwc_msi))] +pub fn get_domain_id_by_irq(irq: u32) -> Option { + let domains = DW_MSI_DOMAINS.lock(); + domains.iter().find_map(|(domain_id, domain)| { + if domain.irq == irq { + Some(*domain_id) + } else { + None + } + }) +} + +#[cfg(all(dwc_pcie, dwc_msi))] +fn enqueue_dwc_msi_ipi_irq(target_cpu: usize, irq_id: usize) -> bool { + if target_cpu >= MAX_CPU_NUM { + error!( + "DWC MSI enqueue failed: invalid target cpu {}, irq {}", + target_cpu, irq_id + ); + return false; + } + + let mut queues = DWC_MSI_IPI_PENDING_IRQS.lock(); + if let Some(queue) = queues.get_mut(target_cpu) { + queue.push_back(irq_id); + true + } else { + false + } +} + +#[cfg(all(dwc_pcie, dwc_msi))] +fn pop_dwc_msi_ipi_irq(cpu_id: usize) -> Option { + if cpu_id >= MAX_CPU_NUM { + return None; + } + + let mut queues = DWC_MSI_IPI_PENDING_IRQS.lock(); + queues.get_mut(cpu_id).and_then(|queue| queue.pop_front()) +} + +#[cfg(all(dwc_pcie, dwc_msi))] +pub fn dwc_msi_transfer_and_inject(domain_id: u8, irq_id: usize) { + if let Some(irq_bit) = dwc_msi_pending_irq_bit(domain_id) { + if let Some(target_cpu) = find_target_cpu(domain_id, irq_bit as usize) { + if target_cpu == 0 { + inject_irq(irq_id, true); + } else { + if enqueue_dwc_msi_ipi_irq(target_cpu, irq_id) { + send_event(target_cpu, SGI_IPI_ID as usize, IPI_EVENT_DWC_MSI_INJECT); + } else { + error!( + "Failed to enqueue DWC MSI irq {} for target cpu {}", + irq_id, target_cpu + ); + } + } + } else { + error!("No target cpu found for DWC msi irq bit {}!", irq_bit); + } + } else { + error!("No pending DWC msi irq found!"); + } +} + +#[cfg(all(dwc_pcie, dwc_msi))] +pub fn handle_dwc_msi_inject_event() { + let cpu_id = this_cpu_data().id; + if let Some(irq_id) = pop_dwc_msi_ipi_irq(cpu_id) { + inject_irq(irq_id, true); + } else { + warn!("No pending DWC MSI IPI irq for cpu {}", cpu_id); + } +} diff --git a/src/pci/mod.rs b/src/pci/mod.rs index 7217cce55..49113e9ef 100644 --- a/src/pci/mod.rs +++ b/src/pci/mod.rs @@ -17,12 +17,16 @@ #![allow(dead_code)] pub mod config_accessors; pub mod mem_alloc; +pub mod msix; pub mod pci_access; pub mod pci_config; pub mod pci_handler; pub mod pci_struct; pub mod vpci_dev; +#[cfg(all(dwc_msi, dwc_pcie))] +pub mod dwc_msi; + #[cfg(test)] pub mod pci_test; diff --git a/src/pci/msix.rs b/src/pci/msix.rs new file mode 100644 index 000000000..03adbd1f4 --- /dev/null +++ b/src/pci/msix.rs @@ -0,0 +1,454 @@ +// Copyright (c) 2025 Syswonder +// hvisor is licensed under Mulan PSL v2. +// You can use this software according to the terms and conditions of the Mulan PSL v2. +// You may obtain a copy of Mulan PSL v2 at: +// http://license.coscl.org.cn/MulanPSL2 +// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR +// FIT FOR A PARTICULAR PURPOSE. +// See the Mulan PSL v2 for more details. +// +// Syswonder Website: +// https://www.syswonder.org +// +// Authors: +// + +use core::fmt::Debug; + +use alloc::{collections::btree_map::BTreeMap, sync::Arc, vec::Vec}; +use spin::RwLock; + +use crate::{ + arch::cpu::this_cpu_id, + cpu_data::this_zone, + device::{irqchip::inject_irq, virtio_trampoline::VirtioPCIDataInfo}, + error::HvResult, + memory::MMIOAccess, + pci::pci_struct::{AreaInBar, PciCapabilityRegion}, +}; + +pub fn activate_msix() { + // let data_info = VirtioPCIDataInfo::from_u64(data_req_id); + // let dev_id = data_info.get_dev_id(); + let zone = this_zone(); + let zone_lock = zone.read(); + let bus = zone_lock.vpci_bus(); + let msix_backend = match bus.get_msix_backend() { + Some(x) => x, + None => { + // warn!("There is no msix backend in this zone's vpci bus!"); + return; + } + }; + for (_, i) in bus.read_devs() { + // if i.get_bdf().requester_id() == dev_id{ + // i.try_inject_msix_irq(); + // } + i.try_inject_msix_irq(&msix_backend); + } +} + +#[allow(unreachable_code)] +pub fn get_arch_msix_backend() -> Option>> { + #[cfg(all(target_arch = "aarch64", irq_gicv3))] + { + use crate::device::irqchip::gicv3::msix_backend::get_gicv3_backend; + return Some(get_gicv3_backend()); + } + + return None; +} + +pub struct MsixCap { + offset_in_config: usize, + cap_id: u8, + cap_next: u8, + message_control: u16, + table_bar: u8, + table_offset: u32, + pending_bar: u8, + pending_offset: u32, + + msix_table: Arc>, +} + +impl MsixCap { + pub fn new( + offset_in_config: usize, + next: u8, + table_size: u16, + msix_table: Arc>, + ) -> Self { + let mut res = Self { + offset_in_config, + cap_id: 0x11, + cap_next: next, + message_control: 0x0, + table_bar: 0x01, + table_offset: 0x0000_0000, + pending_bar: 0x01, + pending_offset: 0x0000_08000, + msix_table, + }; + res.set_table_size(table_size); + res + } + + pub fn get_table_size(&self) -> usize { + ((self.message_control & 0x07ff) as usize) + 1 + } + + pub fn get_table_mesg(&self) -> u32 { + (self.table_offset << 3) | (self.table_bar as u32) + } + + pub fn get_pending_mesg(&self) -> u32 { + (self.pending_offset << 3) | (self.pending_bar as u32) + } + + pub fn set_table_mesg(&mut self, mesg: u32) { + self.table_offset = mesg >> 3; + self.table_bar = (mesg & 0x0000_0003) as u8; + } + pub fn set_pending_mesg(&mut self, mesg: u32) { + self.pending_offset = mesg >> 3; + self.pending_bar = (mesg & 0x0000_0003) as u8; + } + + pub fn set_table_size(&mut self, size: u16) { + if size == 0 || size > 2048 { + warn!("msix table size must be in 1..=2048"); + return; + } + let mask = 0xf800; + self.message_control &= mask; + self.message_control |= size - 1; + } +} + +impl PciCapabilityRegion for MsixCap { + fn read( + &self, + offset: crate::pci::PciConfigAddress, + size: usize, + ) -> crate::error::HvResult { + if offset as usize % size != 0 { + warn!("cap read is misalign!"); + return Ok(0); + } + if size == 1 { + match offset { + 0x00 => return Ok(self.cap_id as u32), + 0x01 => return Ok(self.cap_next as u32), + _ => { + warn!("read u8 from unexpected area! offset:{}", offset); + return Ok(0); + } + } + }; + if size == 2 { + match offset { + 0x00 => return Ok(self.cap_id as u32 | (self.cap_next as u32) << 8), + 0x02 => return Ok(self.message_control as u32), + _ => { + warn!("read u16 from unexpected area! offset:{}", offset); + return Ok(0); + } + } + }; + if size == 4 { + match offset { + 0x00 => { + return Ok((self.cap_id as u32) + | (self.cap_next as u32) << 8 + | (self.message_control as u32) << 16) + } + 0x04 => return Ok(self.get_table_mesg()), + 0x08 => return Ok(self.get_pending_mesg()), + _ => { + warn!("read u32 from unexpected area! offset:{}", offset); + return Ok(0); + } + } + }; + warn!("size is not any of 1,2,4!"); + Ok(0) + } + + fn write( + &mut self, + offset: crate::pci::PciConfigAddress, + size: usize, + value: u32, + ) -> crate::error::HvResult { + if size == 1 { + warn!("there is no writeable field with size 1!") + } + if size == 2 { + match offset { + 0x02 => self.message_control = value as u16, + _ => { + warn!("write into unexpected area! offset:{}", offset) + } + } + return Ok(()); + } + + if size == 4 { + match offset { + 0x04 => self.set_table_mesg(value), + 0x08 => self.set_pending_mesg(value), + _ => { + warn!("write into unexpected area! offset:{}", offset) + } + } + return Ok(()); + } + Ok(()) + } + + fn get_offset(&self) -> crate::pci::PciConfigAddress { + self.offset_in_config as u64 + } + + fn get_size(&self) -> usize { + 0x0c + } + + fn next_cap(&self) -> crate::error::HvResult { + Ok(self.cap_next as u64) + } + + fn bar_usage(&self) -> Option { + Some(self.table_bar as usize) + } + + fn bar_area(&self) -> Option>> { + Some(self.msix_table.clone()) + } + + fn bar_addr_range(&self) -> Option> { + let table_offset = self.table_offset as usize; + Some(table_offset..table_offset + self.get_table_size() * 16) + } +} + +#[derive(Clone, Debug)] +pub struct MsixTableEntry { + pub message_address: u32, + pub message_upper_address: u32, + pub msg_data: u32, + pub vector_control: u32, + pub intid: Option, +} + +impl MsixTableEntry { + pub fn activate_irq(&self) { + // info!("entry:{:x?}", self); + match self.intid { + Some(x) => { + inject_irq(x, false); + } + None => { + warn!("this msix vector has not gotten a intid:{:x?}", self); + } + } + } + + pub fn get_msg_data(&self) -> u32 { + return self.msg_data; + } +} + +impl MsixTableEntry { + pub fn dummy() -> Self { + Self { + message_address: 0, + message_upper_address: 0, + msg_data: 0, + vector_control: 0, + intid: None, + } + } +} + +#[derive(Debug)] +pub struct MsixTable { + table: Vec, + device_id: usize, + event_id: Vec<(usize, usize)>, + pending_msix_idx: Vec, +} + +impl MsixTable { + pub fn new(size: usize, deviceid: usize) -> Self { + let mut vec = Vec::new(); + vec.resize(size, MsixTableEntry::dummy()); + Self { + table: vec, + device_id: deviceid, + event_id: Vec::new(), + pending_msix_idx: Vec::new(), + } + } + + pub fn get_entry(&self, vector_index: usize) -> Option { + if vector_index >= self.table.len() { + return None; + } + Some(self.table[vector_index].clone()) + } + + pub fn intercept_its(&mut self, deviceid: usize, event_id: usize, intid: usize) { + if deviceid == self.device_id { + warn!("MAPTI's deviceid != current deviceid!"); + } + self.event_id.push((event_id, intid)); + } + + pub fn init_msix_intid(&mut self, index: usize) { + let selected_vector = &mut self.table[index]; + for i in self.event_id.iter() { + if selected_vector.msg_data as usize == i.0 { + selected_vector.intid = Some(i.1); + break; + } + } + } + + pub fn add_pending_msix(&mut self, msix_idx: usize) { + self.pending_msix_idx.push(msix_idx); + } + + pub fn get_pending_msix_vector(&mut self) -> Option> { + if self.pending_msix_idx.is_empty() { + return None; + } + let mut res = Vec::new(); + loop { + let idx = self.pending_msix_idx.pop(); + match idx { + Some(x) => { + res.push(self.table[x].clone()); + } + None => { + break; + } + } + } + return Some(res); + } +} + +impl AreaInBar for MsixTable { + fn read(&mut self, mmio_ac: &mut MMIOAccess) -> HvResult { + let offset = mmio_ac.address; + // 16 is the size of entry + let index = offset / 16; + let offset_in_entry = offset % 16; + if index >= self.table.len() { + warn!("msix table read index {} out of range", index); + return Ok(()); + } + match offset_in_entry { + 0x00 => mmio_ac.value = self.table[index].message_address as usize, + 0x04 => mmio_ac.value = self.table[index].message_upper_address as usize, + 0x08 => mmio_ac.value = self.table[index].msg_data as usize, + 0x0c => mmio_ac.value = self.table[index].vector_control as usize, + _ => { + warn!("access address is misalign!"); + } + } + Ok(()) + } + + fn write(&mut self, mmio_ac: &MMIOAccess) -> HvResult { + if mmio_ac.size != 4 { + warn!("only write with size of 4 would work correctly"); + } + let offset = mmio_ac.address; + let index = offset / 16; + let offset_in_entry = offset % 16; + if index >= self.table.len() { + warn!("msix table write index {} out of range", index); + return Ok(()); + } + let value = mmio_ac.value; + match offset_in_entry { + 0x00 => self.table[index].message_address = value as u32, + 0x04 => self.table[index].message_upper_address = value as u32, + 0x08 => self.table[index].msg_data = value as u32, + 0x0c => self.table[index].vector_control = value as u32, + _ => { + warn!("access address is misalign!"); + } + } + self.init_msix_intid(index); + Ok(()) + } +} + +pub struct VirtioPCIMsixManager { + table: BTreeMap, + pending: Vec, +} + +impl VirtioPCIMsixManager { + pub const fn new() -> Self { + Self { + table: BTreeMap::new(), + pending: Vec::new(), + } + } + + pub fn insert(&mut self, data_info: VirtioPCIDataInfo, entry: MsixTableEntry) { + // info!("Msix Manager insert:{:x?}", data_info); + let data_req_id = data_info.get_identifier(); + self.table.insert(data_req_id, entry); + } + + pub fn add_pending_data_req_id(&mut self, data_req_id: u64) { + // info!("pending data req id add:0x{:x}", data_req_id); + self.pending.push(data_req_id); + } + + pub fn activate_all_pending_irq(&mut self) { + let cpu_id = (this_cpu_id() as u64) << 32; + let mut target = Vec::new(); + let mut i = 0; + while i < self.pending.len() { + if (self.pending[i] & 0x0000_ffff_0000_0000) == cpu_id { + target.push(self.pending.swap_remove(i)); + } else { + i += 1; + } + } + + for j in target { + self.activate_irq(j); + } + } + + pub fn activate_irq(&mut self, data_req_id: u64) { + let entry = self.table.remove(&data_req_id); + // info!( + // "irq activate!!! entry:{:x?},data_req_id:0x{:x}", + // entry, data_req_id + // ); + match entry { + Some(x) => { + x.activate_irq(); + } + None => { + return; + } + } + } +} + +pub trait MsixBackend: Debug + Sync + Send { + fn activate_irq(&self, device_id: usize, vector: &MsixTableEntry); + fn enable(&mut self); + fn disable(&mut self); +} diff --git a/src/pci/pci_access.rs b/src/pci/pci_access.rs index dc891bd96..d7b115b3e 100644 --- a/src/pci/pci_access.rs +++ b/src/pci/pci_access.rs @@ -28,7 +28,7 @@ use super::{ PciConfigAddress, }; -use crate::error::HvResult; +use crate::{cpu_data::this_zone, error::HvResult, memory::MMIOAccess}; pub type VendorId = u16; pub type DeviceId = u16; @@ -111,6 +111,8 @@ impl Debug for PciMemType { } } +pub type PciBARMMIOHanlder = fn(mmio: &mut MMIOAccess, base: usize) -> HvResult; + /* PciMem * virtaul_value: the vaddr guset zone can rw, same with as the corresponding value in virtualconfigspace.space * value: the paddr which hvisor and hw can rw, init when hvisor init the pci bus @@ -119,7 +121,7 @@ impl Debug for PciMemType { * size_read: if software write 0xffff_ffff to bar, size_read will set so next time hvisor can rerturn !(size - 1) indicating size to the software * acutally size_read is not used now, we keep it just in case of possible special register handling in the future */ -#[derive(Default, Clone, Copy)] +#[derive(Default, Clone)] pub struct PciMem { bar_type: PciMemType, virtual_value: u64, @@ -127,9 +129,47 @@ pub struct PciMem { size: u64, prefetchable: bool, size_read: bool, + handler: Option, // cap_handler:Option> } impl PciMem { + pub fn write(&mut self, value: u32) { + if value == 0xffff_ffff { + self.set_size_read(); + } else if value == 0x0 { + // do nothing + } else { + match self.handler { + Some(handler) => { + let zone = this_zone(); + let mut guard = zone.write(); + guard.mmio_region_register( + value as usize, + self.size as usize, + handler, + value as usize, + ); + drop(guard); + self.clear_size_read(); + self.set_virtual_value(value as u64); + } + None => { + warn!("This bar has not register handler!"); + } + } + } + } + + // I don't know if it's correct to make the return value be u64 + pub fn read(&self) -> u64 { + // let bar = &space.get_bararr()[n]; + if self.get_size_read() { + return self.get_size(); + } else { + return self.get_virtual_value() as u64; + } + } + pub fn new_bar(bar_type: PciMemType, value: u64, size: u64, prefetchable: bool) -> Self { Self { bar_type, @@ -138,6 +178,7 @@ impl PciMem { size, prefetchable, size_read: false, + handler: None, } } @@ -149,6 +190,7 @@ impl PciMem { size, prefetchable: false, size_read: false, + handler: None, } } @@ -160,6 +202,7 @@ impl PciMem { size, prefetchable: false, size_read: false, + handler: None, } } @@ -171,6 +214,7 @@ impl PciMem { size, prefetchable: false, size_read: false, + handler: None, } } @@ -212,11 +256,19 @@ impl PciMem { self.prefetchable = prefetchable; } - pub fn config_init(&mut self, bar_type: PciMemType, prefetchable: bool, size: u64, value: u64) { + pub fn config_init( + &mut self, + bar_type: PciMemType, + prefetchable: bool, + size: u64, + value: u64, + handler: Option, + ) { self.set_bar_type(bar_type); self.set_prefetchable(prefetchable); self.set_size(size); self.set_value(value); + self.set_handler(handler); } pub fn is_enabled(&self) -> bool { @@ -243,6 +295,10 @@ impl PciMem { self.value as u64 } + pub fn set_handler(&mut self, handler: Option) { + self.handler = handler + } + /* Automatically add flags */ pub fn set_value(&mut self, address: u64) { let mut val = address; @@ -297,6 +353,7 @@ impl PciMem { } pub fn get_virtual_value(&self) -> u32 { + // info!("get_virtual_value:{:?}", self.bar_type); match self.bar_type { PciMemType::Mem64High => (self.virtual_value >> 32) as u32, _ => self.virtual_value as u32, @@ -335,9 +392,20 @@ impl PciMem { warn!("unkown bar type: {:#?}", self.bar_type); } } - + // info!("self.virtual_value = {}", val); self.virtual_value = val; } + + pub fn get_virtual_addr(&self) -> Option { + match self.bar_type { + PciMemType::Io => Some(((self.virtual_value >> 2) << 2) as u32), + PciMemType::Unused => { + // warn!("get addr from unused bar!"); + None + } + _ => Some(((self.virtual_value >> 4) << 4) as u32), + } + } } impl Debug for PciMem { @@ -396,11 +464,21 @@ impl Debug for PciMem { } } -#[derive(Clone, Copy, Default)] +#[derive(Clone, Default)] pub struct Bar { bararr: [PciMem; 6], } +impl Bar { + pub fn write_bar(&mut self, index: usize, value: u32) { + self.bararr[index].write(value); + } + + pub fn read_bar(&self, index: usize) -> u32 { + self.bararr[index].read() as u32 + } +} + impl Index for Bar { type Output = PciMem; @@ -878,6 +956,7 @@ impl EndpointField { match (offset, size) { (0x00, 4) => EndpointField::ID, (0x04, 2) => EndpointField::Command, + (0x04, 4) => EndpointField::Command, (0x06, 2) => EndpointField::Status, (0x08, 4) => EndpointField::RevisionIDAndClassCode, (0x0c, 1) => EndpointField::CacheLineSize, @@ -898,6 +977,7 @@ impl EndpointField { (0x2e, 2) => EndpointField::SubsystemId, (0x30, 4) => EndpointField::ExpansionRomBar, (0x34, 4) => EndpointField::CapabilityPointer, + (0x34, 1) => EndpointField::CapabilityPointer, (0x3c, 1) => EndpointField::InterruptLine, (0x3d, 1) => EndpointField::InterruptPin, (0x3e, 1) => EndpointField::MinGnt, @@ -987,11 +1067,12 @@ pub enum BridgeField { LatencyTime, HeaderType, Bist, - Bar, + Bar(usize), PrimaryBusNumber, SecondaryBusNumber, SubordinateBusNumber, SecondaryLatencyTimer, + BusNumbers, IOBase, IOLimit, SecondaryStatus, @@ -1023,11 +1104,12 @@ impl Debug for BridgeField { BridgeField::LatencyTime => write!(f, "LatencyTime"), BridgeField::HeaderType => write!(f, "HeaderType"), BridgeField::Bist => write!(f, "Bist"), - BridgeField::Bar => write!(f, "Bar"), + BridgeField::Bar(slot) => write!(f, "Bar({})", slot), BridgeField::PrimaryBusNumber => write!(f, "PrimaryBusNumber"), BridgeField::SecondaryBusNumber => write!(f, "SecondaryBusNumber"), BridgeField::SubordinateBusNumber => write!(f, "SubordinateBusNumber"), BridgeField::SecondaryLatencyTimer => write!(f, "SecondaryLatencyTimer"), + BridgeField::BusNumbers => write!(f, "BusNumbers"), BridgeField::IOBase => write!(f, "IOBase"), BridgeField::IOLimit => write!(f, "IOLimit"), BridgeField::SecondaryStatus => write!(f, "SecondaryStatus"), @@ -1061,11 +1143,12 @@ impl PciField for BridgeField { BridgeField::LatencyTime => 0x0d, BridgeField::HeaderType => 0x0e, BridgeField::Bist => 0x0f, - BridgeField::Bar => 0x10, + BridgeField::Bar(slot) => 0x10 + slot * 4, BridgeField::PrimaryBusNumber => 0x18, BridgeField::SecondaryBusNumber => 0x19, BridgeField::SubordinateBusNumber => 0x1a, BridgeField::SecondaryLatencyTimer => 0x1b, + BridgeField::BusNumbers => 0x18, BridgeField::IOBase => 0x1c, BridgeField::IOLimit => 0x1d, BridgeField::SecondaryStatus => 0x1e, @@ -1096,11 +1179,12 @@ impl PciField for BridgeField { BridgeField::LatencyTime => 1, BridgeField::HeaderType => 1, BridgeField::Bist => 1, - BridgeField::Bar => 4, + BridgeField::Bar(_) => 4, BridgeField::PrimaryBusNumber => 1, BridgeField::SecondaryBusNumber => 1, BridgeField::SubordinateBusNumber => 1, BridgeField::SecondaryLatencyTimer => 1, + BridgeField::BusNumbers => 4, BridgeField::IOBase => 1, BridgeField::IOLimit => 1, BridgeField::SecondaryStatus => 2, @@ -1133,11 +1217,13 @@ impl BridgeField { (0x0d, 1) => BridgeField::LatencyTime, (0x0e, 1) => BridgeField::HeaderType, (0x0f, 1) => BridgeField::Bist, - (0x10, 4) | (0x14, 4) => BridgeField::Bar, + (0x10, 4) => BridgeField::Bar(0), + (0x14, 4) => BridgeField::Bar(1), (0x18, 1) => BridgeField::PrimaryBusNumber, (0x19, 1) => BridgeField::SecondaryBusNumber, (0x1a, 1) => BridgeField::SubordinateBusNumber, (0x1b, 1) => BridgeField::SecondaryLatencyTimer, + (0x18, 4) => BridgeField::BusNumbers, (0x1c, 1) => BridgeField::IOBase, (0x1d, 1) => BridgeField::IOLimit, (0x1e, 2) => BridgeField::SecondaryStatus, diff --git a/src/pci/pci_config.rs b/src/pci/pci_config.rs index 56f6b7f93..18c5a7909 100644 --- a/src/pci/pci_config.rs +++ b/src/pci/pci_config.rs @@ -20,37 +20,32 @@ use spin::{Lazy, Mutex}; use crate::{ config::{HvPciConfig, HvPciDevConfig, CONFIG_MAX_PCI_DEV, CONFIG_PCI_BUS_MAXNUM}, error::HvResult, - pci::pci_struct::{ArcRwLockVirtualPciConfigSpace, Bdf}, + pci::{ + msix::get_arch_msix_backend, + pci_struct::{ArcRwLockVirtualPciConfigSpace, Bdf}, + }, zone::Zone, }; -#[cfg(feature = "loongarch64_pcie")] +#[cfg(loongarch64_pcie)] use alloc::vec::Vec; -#[cfg(any( - all(feature = "iommu", target_arch = "aarch64"), - all(feature = "iommu", target_arch = "riscv64"), - target_arch = "x86_64" -))] +#[cfg(iommu)] use crate::device::iommu::iommu_add_device_with_root_pt_addr; -#[cfg(feature = "ecam_pcie")] +#[cfg(ecam_pcie)] use crate::pci::{ pci_struct::VirtualPciConfigSpace, vpci_dev::{get_handler, VpciDevType}, }; -#[cfg(any( - feature = "ecam_pcie", - feature = "dwc_pcie", - feature = "loongarch64_pcie" -))] +#[cfg(pci)] use crate::pci::{mem_alloc::BaseAllocator, pci_struct::RootComplex}; -#[cfg(feature = "ecam_pcie")] +#[cfg(ecam_pcie)] use crate::pci::{config_accessors::ecam::EcamConfigAccessor, pci_handler::mmio_vpci_handler}; -#[cfg(feature = "dwc_pcie")] +#[cfg(dwc_pcie)] use crate::{ memory::mmio_generic_handler, pci::{ @@ -63,7 +58,7 @@ use crate::{ platform, }; -#[cfg(feature = "loongarch64_pcie")] +#[cfg(loongarch64_pcie)] use crate::pci::{ config_accessors::loongarch64::LoongArchConfigAccessor, pci_handler::mmio_vpci_direct_handler, }; @@ -77,11 +72,11 @@ pub static GLOBAL_PCIE_LIST: Lazy HvResult { warn!("begin {:#x?}", pci_config); - #[cfg(any( - feature = "ecam_pcie", - feature = "dwc_pcie", - feature = "loongarch64_pcie" - ))] + // Track domains that have been initialized for DW MSI + #[cfg(all(dwc_msi, dwc_pcie))] + let mut initialized_domains: alloc::vec::Vec = alloc::vec::Vec::new(); + + #[cfg(pci)] for (_index, rootcomplex_config) in pci_config.iter().enumerate() { /* empty config */ if rootcomplex_config.ecam_base == 0 { @@ -99,12 +94,12 @@ pub fn hvisor_pci_init(pci_config: &[HvPciConfig]) -> HvResult { // TODO: refactor // in x86, we do not take the initiative to reallocate BAR space - #[cfg(feature = "no_pcie_bar_realloc")] + #[cfg(no_pcie_bar_realloc)] let allocator_opt: Option = None; - #[cfg(not(feature = "no_pcie_bar_realloc"))] + #[cfg(not(no_pcie_bar_realloc))] let allocator_opt: Option = Some(allocator); - // #[cfg(feature = "loongarch64_pcie")] + // #[cfg(loongarch64_pcie)] // let allocator_opt: Option = { // let mut allocator = LoongArchAllocator::default(); // allocator.set_mem( @@ -119,7 +114,7 @@ pub fn hvisor_pci_init(pci_config: &[HvPciConfig]) -> HvResult { // }; let mut rootcomplex = { - #[cfg(feature = "dwc_pcie")] + #[cfg(dwc_pcie)] { // warn!("dwc pcie"); let ecam_base = rootcomplex_config.ecam_base; @@ -140,7 +135,7 @@ pub fn hvisor_pci_init(pci_config: &[HvPciConfig]) -> HvResult { RootComplex::new_dwc(rootcomplex_config.ecam_base, atu_config, root_bus) } - #[cfg(feature = "loongarch64_pcie")] + #[cfg(loongarch64_pcie)] { let root_bus = rootcomplex_config.bus_range_begin as u8; RootComplex::new_loongarch( @@ -150,7 +145,7 @@ pub fn hvisor_pci_init(pci_config: &[HvPciConfig]) -> HvResult { ) } - #[cfg(feature = "ecam_pcie")] + #[cfg(ecam_pcie)] { RootComplex::new_ecam(rootcomplex_config.ecam_base) } @@ -162,10 +157,30 @@ pub fn hvisor_pci_init(pci_config: &[HvPciConfig]) -> HvResult { let e = rootcomplex.enumerate(Some(range), domain, allocator_opt); info!("begin enumerate {:#x?}", e); for node in e { - info!("node {:#?}", node); - GLOBAL_PCIE_LIST - .lock() - .insert(node.get_bdf(), ArcRwLockVirtualPciConfigSpace::new(node)); + // info!("node {:#?}", node); + let sriov_vfs = rootcomplex.create_sriov_vfs(&node); + + { + let mut global_pcie_list = GLOBAL_PCIE_LIST.lock(); + global_pcie_list.insert(node.get_bdf(), ArcRwLockVirtualPciConfigSpace::new(node)); + for vf in sriov_vfs { + global_pcie_list.insert(vf.get_bdf(), ArcRwLockVirtualPciConfigSpace::new(vf)); + } + } + } + + // Initialize DW MSI domain for this domain ID (only once per domain) + #[cfg(all(dwc_msi, dwc_pcie))] + { + if !initialized_domains.contains(&domain) { + let msi_irq = platform::ROOT_DWC_ATU_CONFIG + .iter() + .find(|cfg| cfg.ecam_base == rootcomplex_config.ecam_base) + .map(|cfg| cfg.dw_msi_irq as u32) + .unwrap_or(0); + crate::pci::dwc_msi::init_dwc_msi_domain(domain, msi_irq)?; + initialized_domains.push(domain); + } } } info!("hvisor pci init done \n{:#?}", GLOBAL_PCIE_LIST); @@ -182,7 +197,7 @@ impl Zone { _num_pci_config: usize, ) -> HvResult { let mut inner = self.write(); - let mut guard = GLOBAL_PCIE_LIST.lock(); + let guard = GLOBAL_PCIE_LIST.lock(); for target_pci_config in pci_config { // Skip empty config if target_pci_config.ecam_base == 0 { @@ -195,7 +210,7 @@ impl Zone { let bus_range_begin = target_pci_config.bus_range_begin as u8; // Create accessor for VirtualRootComplex, similar to RootComplex - #[cfg(feature = "dwc_pcie")] + #[cfg(dwc_pcie)] { use alloc::sync::Arc; let atu_config = platform::ROOT_DWC_ATU_CONFIG @@ -215,7 +230,7 @@ impl Zone { } } - #[cfg(feature = "loongarch64_pcie")] + #[cfg(loongarch64_pcie)] { use alloc::sync::Arc; let root_bus = bus_range_begin; @@ -227,7 +242,7 @@ impl Zone { inner.vpci_bus_mut().set_accessor(accessor); } - #[cfg(feature = "ecam_pcie")] + #[cfg(ecam_pcie)] { use alloc::sync::Arc; let accessor = Arc::new(EcamConfigAccessor::new(ecam_base)); @@ -254,10 +269,14 @@ impl Zone { .then_with(|| a.function.cmp(&b.function)) }); - let mut vbus_pre = bus_range_begin; - let mut bus_pre = bus_range_begin; - let mut device_pre = 0u8; + let mut domain_msi_count: u32 = 0; + let mut vdevice_pre = 0u8; + let msix_backend = get_arch_msix_backend(); + if let Some(x) = msix_backend.clone() { + x.write().enable(); + } + inner.vpci_bus_mut().set_msix_backend(msix_backend.clone()); /* * To allow Linux to successfully recognize the devices we add, hvisor needs @@ -275,57 +294,16 @@ impl Zone { */ for dev_config in &filtered_devices { let bdf = Bdf::new_from_config(*dev_config); - // let bus = bdf.bus(); - // let device = bdf.device(); - // let function = bdf.function(); - - // /* - // * vfunction = if (bus != bus_pre || device != device_pre) && function != 0 - // * In practice, remapping is performed only for new devices whose function is not 0; - // * however, the check for function != 0 does not affect the final result. - // */ - // let vfunction = if bus != bus_pre || device != device_pre { - // 0 - // } else { - // function - // }; - - // let vbus = if bus > bus_pre { - // vbus_pre += 1; - // vbus_pre - // } else { - // vbus_pre - // }; - - // // Remap device number to be contiguous, starting from 0 - // let vdevice = if bus != bus_pre || device != device_pre { - // // New bus or new device, increment device counter - // if bus != bus_pre { - // vdevice_pre = 0; - // } else { - // vdevice_pre += 1; - // } - // vdevice_pre - // } else { - // // Same bus and device, keep the same virtual device number - // vdevice_pre - // }; - - // let vbdf = Bdf::new(bdf.domain(), vbus, vdevice, vfunction); - - // device_pre = device; - // bus_pre = bus; - - // TODO: adjust vbdf will cause line interrupt injecet error, so remove it temporarily - let vbdf = bdf; + let vbdf = Bdf::new( + bdf.domain(), + dev_config.v_bus, + dev_config.v_device, + dev_config.v_function, + ); info!("set bdf {:#?} to vbdf {:#?}", bdf, vbdf); - #[cfg(any( - all(feature = "iommu", target_arch = "aarch64"), - all(feature = "iommu", target_arch = "riscv64"), - target_arch = "x86_64" - ))] + #[cfg(iommu)] { let iommu_pt_addr = if inner.iommu_pt().is_some() { inner.iommu_pt().unwrap().root_paddr() @@ -335,13 +313,13 @@ impl Zone { let device_id = (dev_config.bus as usize) << 8 | (dev_config.device as usize) << 3 | dev_config.function as usize; - #[cfg(feature = "share_s2pt")] + #[cfg(share_s2pt)] iommu_add_device_with_root_pt_addr( _zone_id, device_id as _, inner.gpm().root_paddr(), ); - #[cfg(not(feature = "share_s2pt"))] + #[cfg(not(share_s2pt))] iommu_add_device_with_root_pt_addr(_zone_id, device_id as _, iommu_pt_addr); } @@ -353,18 +331,42 @@ impl Zone { }) { let mut vdev = dev.read().config_space.clone(); - vdev.set_vbdf(vbdf); + vdev.set_vbdf_with_bus_map( + vbdf, + target_pci_config.bus_range_end as u8, + &filtered_devices, + ); + let msi_count = vdev.get_msi_count(); + domain_msi_count += msi_count; inner.vpci_bus_mut().insert(vbdf, vdev); } else { - // Check if device is already allocated to another zone - if dev.get_zone_id().is_none() { - dev.set_zone_id(Some(_zone_id as u32)); - let mut vdev_inner = dev.read().config_space.clone(); - vdev_inner.set_vbdf(vbdf); - inner.vpci_bus_mut().insert(vbdf, vdev_inner); + // Allow allocation if zone_id is None (unassigned), or if zone_id is + // Some(0) and the device is a SRIOV VF (initially assigned to root zone + // during enumeration, can be reassigned to a guest zone). + let is_sriov_vf_from_root = dev.get_zone_id() == Some(0) + && dev.read().get_sriov_vf_info().is_some(); + let is_pf = dev.read().get_sriov_info().is_some(); + if dev.get_zone_id().is_none() || is_sriov_vf_from_root { + if is_pf && _zone_id != 0 { + warn!( + "The SR-IOV PF {:#x?} can only be assigned to the root VM", + bdf + ); + } else { + dev.set_zone_id(Some(_zone_id as u32)); + let mut vdev_inner = dev.read().config_space.clone(); + vdev_inner.set_vbdf_with_bus_map( + vbdf, + target_pci_config.bus_range_end as u8, + &filtered_devices, + ); + let msi_count = vdev_inner.get_msi_count(); + domain_msi_count += msi_count; + inner.vpci_bus_mut().insert(vbdf, vdev_inner); + } } else { warn!( - "Device {:#?} is already allocated to zone {:?}", + "Device {:#x?} is already allocated to zone {:?}", bdf, dev.get_zone_id() ); @@ -372,21 +374,25 @@ impl Zone { } } else { warn!("can not find dev {:#?} in GLOBAL_PCIE_LIST (not detected during enumeration)", bdf); - #[cfg(feature = "ecam_pcie")] + #[cfg(ecam_pcie)] { let dev_type = dev_config.dev_type; + warn!("dev_type:{:?}", dev_config); match dev_type { VpciDevType::Physical => { warn!("can not find dev {:#?}", bdf); } _ => { if let Some(_handler) = get_handler(dev_type) { + use crate::pci::vpci_dev::virt_dev_init; let base = ecam_base + ((bdf.bus() as u64) << 20) + ((bdf.device() as u64) << 15) + ((bdf.function() as u64) << 12); - let dev = VirtualPciConfigSpace::virt_dev(bdf, base, dev_type); - inner.vpci_bus_mut().insert(vbdf, dev); + let dev = virt_dev_init(bdf, base, dev_type); + if let Some(x) = dev { + inner.vpci_bus_mut().insert(vbdf, x); + } } else { warn!("can not find dev {:#?}, unknown device type", bdf); } @@ -395,6 +401,48 @@ impl Zone { } } } + + // After processing all devices for this domain, allocate hardware MSI bits + if domain_msi_count > 0 { + #[cfg(all(dwc_msi, dwc_pcie))] + { + // Get the DW MSI domain allocator and allocate hwbit + if let Some(mut domain_lock) = + crate::pci::dwc_msi::get_dwc_msi_domain_mut(target_domain) + { + if let Some(domain_msi) = domain_lock.get_mut(&target_domain) { + let zone_cpu_set = inner.cpu_set(); + let target_cpu = zone_cpu_set.first_cpu().unwrap_or(0); + match domain_msi.allocate_for_cpu(target_cpu, domain_msi_count) { + Ok(hwirq_bit) => { + // Register the MSI info for this domain + inner.vpci_bus_mut().add_msi_count_for_domain( + target_domain, + domain_msi_count, + hwirq_bit, + ); + } + Err(e) => { + warn!( + "Failed to allocate MSI for domain {}: {:?}", + target_domain, e + ); + } + } + } + } + } + + #[cfg(not(dwc_msi))] + { + // Without dwc_msi feature, just register without hardware bit allocation + inner.vpci_bus_mut().add_msi_count_for_domain( + target_domain, + domain_msi_count, + 0, // hwirq_bit is 0 when not using dwc_msi + ); + } + } } info!("vpci bus init done\n {:#x?}", inner.vpci_bus()); Ok(()) @@ -405,16 +453,17 @@ impl Zone { pci_rootcomplex_config: &[HvPciConfig; CONFIG_PCI_BUS_MAXNUM], _num_pci_config: usize, ) { - #[cfg(feature = "loongarch64_pcie")] + #[cfg(loongarch64_pcie)] let mut emergency_map_regions: Vec<(usize, usize)> = Vec::new(); let mut inner = self.write(); for rootcomplex_config in pci_rootcomplex_config { /* empty config */ + if rootcomplex_config.ecam_base == 0 { continue; } - #[cfg(feature = "ecam_pcie")] + #[cfg(ecam_pcie)] { // use crate::pci::pci_handler::mmio_vpci_direct_handler; inner.mmio_region_register( @@ -425,13 +474,18 @@ impl Zone { rootcomplex_config.ecam_base as usize, ); } - #[cfg(feature = "dwc_pcie")] + #[cfg(dwc_pcie)] { + // Encode domain_id into the arg parameter: arg = ecam_base + domain_id + // Since ecam_base is 4KB aligned, its low 12 bits are 0 + // domain_id (0-15) fits in the low bits without interfering + let encoded_arg = + rootcomplex_config.ecam_base as usize + (rootcomplex_config.domain as usize); inner.mmio_region_register( rootcomplex_config.ecam_base as usize, rootcomplex_config.ecam_size as usize, mmio_vpci_handler_dbi, - rootcomplex_config.ecam_base as usize, + encoded_arg, ); let extend_config = platform::ROOT_DWC_ATU_CONFIG @@ -495,13 +549,17 @@ impl Zone { extend_config.cfg_base as PciConfigAddress, rootcomplex_config.ecam_base as usize, ); + inner.atu_configs_mut().insert_cfg_base_mapping( + cfg1_base as PciConfigAddress, + rootcomplex_config.ecam_base as usize, + ); inner.atu_configs_mut().insert_io_base_mapping( rootcomplex_config.io_base as PciConfigAddress, rootcomplex_config.ecam_base as usize, ); } } - #[cfg(feature = "loongarch64_pcie")] + #[cfg(loongarch64_pcie)] { inner.mmio_region_register( rootcomplex_config.ecam_base as usize, @@ -514,11 +572,7 @@ impl Zone { rootcomplex_config.ecam_size as usize, )); } - #[cfg(not(any( - feature = "ecam_pcie", - feature = "dwc_pcie", - feature = "loongarch64_pcie" - )))] + #[cfg(not(pci))] { warn!( "No extend config found for base 0x{:x}", @@ -527,7 +581,7 @@ impl Zone { } } - #[cfg(feature = "loongarch64_pcie")] + #[cfg(loongarch64_pcie)] { drop(inner); for (base, size) in emergency_map_regions { diff --git a/src/pci/pci_handler.rs b/src/pci/pci_handler.rs index af3c42b1f..f6d05036b 100644 --- a/src/pci/pci_handler.rs +++ b/src/pci/pci_handler.rs @@ -14,38 +14,60 @@ // Authors: // +#[cfg(all(dwc_pcie, pci_init_delay))] +use alloc::collections::btree_map::BTreeMap; use alloc::string::String; +use alloc::vec::Vec; +#[cfg(all(dwc_pcie, pci_init_delay))] +use spin::Lazy; +#[cfg(all(dwc_pcie, pci_init_delay))] +use spin::Mutex; use crate::cpu_data::this_zone; use crate::error::HvResult; -use crate::memory::MMIOAccess; +use crate::memory::{mmio_perform_access, MMIOAccess}; use crate::memory::{GuestPhysAddr, HostPhysAddr, MemFlags, MemoryRegion}; +use crate::pci::pci_struct::{ + CapabilityType, SRIOV_CAP_SIZE, SRIOV_VF_BAR_END, SRIOV_VF_BAR_OFFSET, +}; use crate::zone::is_this_root_zone; use super::pci_access::{BridgeField, EndpointField, HeaderType, PciField, PciMemType}; use super::pci_config::GLOBAL_PCIE_LIST; -use super::pci_struct::{ArcRwLockVirtualPciConfigSpace, BIT_LENTH}; +use super::pci_struct::{ArcRwLockVirtualPciConfigSpace, Bdf, BIT_LENTH}; use super::vpci_dev::VpciDevType; use super::PciConfigAddress; #[cfg(target_arch = "x86_64")] use crate::zone::this_zone_id; -#[cfg(feature = "dwc_pcie")] -use crate::{ - memory::mmio_perform_access, - pci::config_accessors::{ - dwc::DwcConfigRegionBackend, - dwc_atu::{ - AtuType, AtuUnroll, ATU_BASE, ATU_ENABLE_BIT, ATU_REGION_SIZE, PCIE_ATU_UNR_LIMIT, - PCIE_ATU_UNR_LOWER_BASE, PCIE_ATU_UNR_LOWER_TARGET, PCIE_ATU_UNR_REGION_CTRL1, - PCIE_ATU_UNR_REGION_CTRL2, PCIE_ATU_UNR_UPPER_BASE, PCIE_ATU_UNR_UPPER_LIMIT, - PCIE_ATU_UNR_UPPER_TARGET, - }, - PciRegionMmio, +#[cfg(dwc_pcie)] +use crate::pci::config_accessors::{ + dwc::DwcConfigRegionBackend, + dwc_atu::{ + AtuType, AtuUnroll, ATU_BASE, ATU_ENABLE_BIT, ATU_REGION_SIZE, PCIE_ATU_UNR_LIMIT, + PCIE_ATU_UNR_LOWER_BASE, PCIE_ATU_UNR_LOWER_TARGET, PCIE_ATU_UNR_REGION_CTRL1, + PCIE_ATU_UNR_REGION_CTRL2, PCIE_ATU_UNR_UPPER_BASE, PCIE_ATU_UNR_UPPER_LIMIT, + PCIE_ATU_UNR_UPPER_TARGET, }, + PciRegionMmio, +}; + +#[cfg(all(dwc_msi, dwc_pcie))] +use super::dwc_msi::{ + PCIE_MSI_ADDR_HI, PCIE_MSI_ADDR_LO, PCIE_MSI_INTR0_ENABLE, PCIE_MSI_INTR0_MASK, + PCIE_MSI_INTR0_STATUS, }; +#[cfg(not(dwc_msi))] +const PCIE_MSI_ADDR_LO: usize = 0x820; +#[cfg(not(dwc_msi))] +const PCIE_MSI_INTR0_STATUS: usize = 0x830; + +const SRIOV_CTRL_OFFSET: PciConfigAddress = 0x08; +const SRIOV_NUM_VFS_OFFSET: PciConfigAddress = 0x10; +const SRIOV_CTRL_VF_ENABLE: u16 = 1 << 0; + macro_rules! pci_log { ($($arg:tt)*) => { // info!($($arg)*); @@ -54,94 +76,499 @@ macro_rules! pci_log { }; } -fn handle_virt_pci_request( +fn handle_virtio_pci_request( dev: ArcRwLockVirtualPciConfigSpace, offset: PciConfigAddress, size: usize, value: usize, is_write: bool, - dev_type: VpciDevType, ) -> HvResult> { - pci_log!( - "virt pci standard rw offset {:#x}, size {:#x}", - offset, - size - ); + // info!( + // "offset:0x{:x},size:0x{:x},value:0x{:x},is_write:{}", + // offset, size, value, is_write + // ); + let res = if is_write { + handle_virtio_pci_write(dev, offset, size, value) + } else { + handle_virtio_pci_read(dev, offset, size) + }; + // info!("result:{:x?}", res); + res +} - /* - * The capability is located in the upper part of the configuration space, - * and there is no other message. So the max cap_offset which is less than - * offset is the correct cap we need. - */ - let result = dev.with_cap(|capabilities| { - if let Some((cap_offset, cap)) = capabilities.range(..=offset).next_back() { - pci_log!( - "find cap at offset {:#x}, cap {:#?}", - cap_offset, - cap.get_type() - ); - let end = *cap_offset + cap.get_size() as u64; - if offset >= end { - return hv_result_err!( - ERANGE, - format!( - "virt pci cap rw offset {:#x} out of range [{:#x}..{:#x})", - offset, *cap_offset, end - ) - ); +fn handle_virtio_pci_read( + dev: ArcRwLockVirtualPciConfigSpace, + offset: PciConfigAddress, + size: usize, +) -> HvResult> { + match EndpointField::from(offset as usize, size) { + EndpointField::ID => dev.with_config_value(|x| { + let id = x.get_id(); + let res = ((id.0 as usize) << 16) | (id.1 as usize); + Ok(Some(res)) + }), + + EndpointField::Bar(n) => dev.with_bar_ref(n, |x| Ok(Some(x.read() as usize))), + + EndpointField::Status => { + // enable capability list + Ok(Some(0x0010)) + } + + EndpointField::Command => { + // This is necessary for virtio pci + Ok(Some(0x0010_0406)) + } + + EndpointField::RevisionIDAndClassCode => Ok(Some(0xff00_0000)), + + EndpointField::CapabilityPointer => { + dev.with_cap(|x| Ok(Some(x.get_capability_pointer() as usize))) + } + + _ => { + dev.with_cap(|x| Ok(x.try_read_cap(offset, size))) + // Ok(None) + } + } +} + +fn handle_virtio_pci_write( + dev: ArcRwLockVirtualPciConfigSpace, + offset: PciConfigAddress, + size: usize, + value: usize, +) -> HvResult> { + match EndpointField::from(offset as usize, size) { + EndpointField::Bar(n) => dev.with_bar_ref_mut(n, |x| { + x.write(value as u32); + Ok(Some(0)) + }), + _ => { + // TODO: Add some warning here in case try write cap failed + dev.with_cap(|x| Ok(x.try_write_cap(offset, size, value))) + // Ok(None) + } + } +} + +// fn handle_virt_pci_request( +// dev: ArcRwLockVirtualPciConfigSpace, +// offset: PciConfigAddress, +// size: usize, +// value: usize, +// is_write: bool, +// dev_type: VpciDevType, +// ) -> HvResult> { +// /* +// * The capability is located in the upper part of the configuration space, +// * and there is no other message. So the max cap_offset which is less than +// * offset is the correct cap we need. +// */ +// let result = dev.with_cap(|capabilities| { +// if let Some((cap_offset, cap)) = capabilities +// .cap_in_config_ref() +// .range(..=offset) +// .next_back() +// { +// let end = *cap_offset + cap.get_size() as u64; +// if offset >= end { +// return hv_result_err!( +// ERANGE, +// format!( +// "virt pci cap rw offset {:#x} out of range [{:#x}..{:#x})", +// offset, *cap_offset, end +// ) +// ); +// } +// let relative_offset = offset - *cap_offset; + +// if is_write { +// cap.with_region_mut(|region| { +// match region.write(relative_offset, size, value as u32) { +// Ok(()) => Ok(0), +// Err(e) => { +// warn!( +// "Failed to write capability at offset 0x{:x}: {:?}", +// offset, e +// ); +// Err(e) +// } +// } +// }) +// } else { +// cap.with_region(|region| match region.read(relative_offset, size) { +// Ok(val) => Ok(val), +// Err(e) => { +// warn!( +// "Failed to read capability at offset 0x{:x}: {:?}", +// offset, e +// ); +// Err(e) +// } +// }) +// } +// } else { +// hv_result_err!(ENOENT) +// } +// }); + +// match result { +// Ok(val) => { +// if !is_write { +// Ok(Some(val as usize)) +// } else { +// Ok(None) +// } +// } +// Err(_) => { +// if is_write { +// super::vpci_dev::vpci_dev_write_cfg(dev_type, dev.clone(), offset, size, value)?; +// Ok(None) +// } else { +// Ok(Some(super::vpci_dev::vpci_dev_read_cfg( +// dev_type, +// dev.clone(), +// offset, +// size, +// )?)) +// } +// } +// } +// } + +fn collect_vf_device_copies( + vf_host_bdf: super::pci_struct::Bdf, +) -> Vec { + let mut devices = Vec::new(); + + { + let zone = this_zone(); + let guard = zone.read(); + let vbus = guard.vpci_bus(); + for dev in vbus.devs_ref().values() { + if dev.get_bdf() == vf_host_bdf { + devices.push(dev.clone()); } - let relative_offset = offset - *cap_offset; + } + } + + if let Some(dev) = GLOBAL_PCIE_LIST.lock().get(&vf_host_bdf).cloned() { + devices.push(dev); + } + + devices +} + +fn sync_sriov_vf_bar_state( + pf_dev: ArcRwLockVirtualPciConfigSpace, + offset: PciConfigAddress, + size: usize, + value: usize, +) -> HvResult { + if size != 4 { + return Ok(false); + } + + let Some((cap_offset, vf_bdfs)) = + pf_dev.with_sriov_info(|sriov_info| (sriov_info.cap_offset, sriov_info.vf_bdfs.clone())) + else { + return Ok(false); + }; + + let vf_bar_start = cap_offset + SRIOV_VF_BAR_OFFSET; + if offset < vf_bar_start || offset >= cap_offset + SRIOV_VF_BAR_END { + return Ok(false); + } + + let relative = offset - vf_bar_start; + if (relative & 0x3) != 0 { + return Ok(false); + } + let slot = (relative / 4) as usize; + + let Some((bar_type, bar_size)) = pf_dev.with_sriov_info(|sriov_info| { + ( + sriov_info.vf_bars[slot].get_type(), + sriov_info.vf_bars[slot].get_size(), + ) + }) else { + return Ok(false); + }; + + if (value & 0xfffffff0) == 0xfffffff0 { + // PF-side SR-IOV BAR probing only queries the template in the ext cap. + // VF BAR state is meaningful only after PF programs a valid BAR value. + return Ok(true); + } + + let pf_value = match bar_type { + PciMemType::Mem64Low => { + let low = pf_dev.read_hw(offset, size)? as u64; + let high = pf_dev.read_hw(offset + 4, size)? as u64; + (low | (high << 32)) & !0xf + } + PciMemType::Mem64High => { + let low = pf_dev.read_hw(offset - 4, size)? as u64; + let high = pf_dev.read_hw(offset, size)? as u64; + (low | (high << 32)) & !0xf + } + PciMemType::Io => (pf_dev.read_hw(offset, size)? as u64) & !0x3, + PciMemType::Mem32 => (pf_dev.read_hw(offset, size)? as u64) & !0xf, + _ => return Ok(false), + }; + + for (vf_index, vf_bdf) in vf_bdfs.into_iter().enumerate() { + let vf_value = pf_value.saturating_add((vf_index as u64).saturating_mul(bar_size)); + let propagated_value = match bar_type { + PciMemType::Mem64Low => vf_value as u32 as usize, + PciMemType::Mem64High => (vf_value >> 32) as u32 as usize, + PciMemType::Io | PciMemType::Mem32 => vf_value as u32 as usize, + _ => continue, + }; + + for vf_dev in collect_vf_device_copies(vf_bdf) { + let is_root = is_this_root_zone(); + let is_dev_belong_to_zone = { + let base = vf_dev.read().get_base(); + let zone = this_zone(); + let mut guard = zone.write(); + let vbus = guard.vpci_bus_mut(); + vbus.get_device_by_base(base).is_some() + }; + + // let vf_id = vf_dev + // .read() + // .get_sriov_vf_info() + // .map(|vf_info| vf_info.vf_index) + // .unwrap_or(vf_index as u16); + + let _ = handle_endpoint_access( + vf_dev, + EndpointField::Bar(slot), + propagated_value, + true, + true, + is_root, + is_dev_belong_to_zone, + )?; + } + } + + Ok(true) +} +fn handle_cap_access( + dev: ArcRwLockVirtualPciConfigSpace, + offset: PciConfigAddress, + size: usize, + value: usize, + is_write: bool, + is_dev_belong_to_zone: bool, +) -> HvResult> { + // Handle capability region access (offset >= 0x34) + if offset == 0x34 { + // Cap Pointer register (may be accessed as different sizes) + if is_dev_belong_to_zone { + // Direct pass through to hardware if is_write { - cap.with_region_mut(|region| { - match region.write(relative_offset, size, value as u32) { - Ok(()) => Ok(0), - Err(e) => { - warn!( - "Failed to write capability at offset 0x{:x}: {:?}", - offset, e - ); - Err(e) - } - } - }) + dev.write_hw(offset, size, value)?; + Ok(None) } else { - cap.with_region(|region| match region.read(relative_offset, size) { - Ok(val) => Ok(val), - Err(e) => { - warn!( - "Failed to read capability at offset 0x{:x}: {:?}", - offset, e - ); - Err(e) - } - }) + Ok(Some(dev.read_hw(offset, size)?)) } } else { - hv_result_err!(ENOENT) + // Device not belong to zone, return 0 (no capability) + if is_write { + Ok(None) + } else { + Ok(Some(0)) + } } - }); + } else if offset >= 0x100 { + #[cfg(sriov)] + if let Some(cap_offset) = dev.with_sriov_info(|sriov_info| sriov_info.cap_offset) { + if offset >= cap_offset && offset < cap_offset + SRIOV_CAP_SIZE { + if is_write { + dev.write_hw(offset, size, value)?; - match result { - Ok(val) => { - if !is_write { - Ok(Some(val as usize)) - } else { - Ok(None) + let _ = sync_sriov_vf_bar_state(dev.clone(), offset, size, value)?; + return Ok(None); + } + let read_value = dev.read_hw(offset, size)?; + return Ok(Some(read_value)); + } + } + + // When `sriov` feature is disabled, hide the SR-IOV extended capability + // from guest VMs by patching the ext-cap linked list on the fly. + #[cfg(not(sriov))] + if let Some(hide) = dev.with_hide_sriov(|h| h.clone()) { + use bit_field::BitField; + // Accesses inside the SR-IOV cap range: return 0 / silently drop writes. + if offset >= hide.sriov_cap_offset && offset < hide.sriov_cap_offset + SRIOV_CAP_SIZE { + if is_write { + return Ok(None); + } else { + return Ok(Some(0)); + } + } + + // Access to the first DWORD of the preceding cap node: patch the + // `next` pointer so it skips over the SR-IOV cap. + if let Some(prev_offset) = hide.prev_cap_offset { + if offset >= prev_offset && offset < prev_offset + 4 { + if is_write { + // Pass writes through unchanged; the physical `next` + // pointer still points to SR-IOV which is fine for host. + dev.write_hw(offset, size, value)?; + return Ok(None); + } else { + // Always read the full DWORD, patch bits[31:20], then + // return the sub-slice the guest asked for. + let mut dw = dev.read_hw(prev_offset, 4)? as u32; + dw.set_bits(20..32, hide.sriov_cap_next as u32); + let byte_offset = (offset - prev_offset) as usize; + let result = match size { + 1 => ((dw >> (byte_offset * 8)) & 0xFF) as usize, + 2 => ((dw >> (byte_offset * 8)) & 0xFFFF) as usize, + _ => dw as usize, + }; + return Ok(Some(result)); + } + } } + // If SR-IOV is the first ext cap (prev_cap_offset == None) and the + // guest reads offset 0x100, the cap header has already been zeroed + // above so the guest sees no extended capabilities at all. + } + + if is_write { + dev.write_hw(offset, size, value)?; + Ok(None) + } else { + Ok(Some(dev.read_hw(offset, size)?)) } - Err(_) => { + } else { + // Other capability region offsets + // Try to find the capability that contains this offset + let cap_info = dev.with_cap(|capabilities| { + capabilities + .cap_in_config_ref() + .range(..=offset as u64) + .next_back() + .map(|(cap_offset, cap)| (*cap_offset, cap.get_type())) + }); + + if let Some((cap_offset, cap_type)) = cap_info { + let cap_offset = cap_offset as usize; + let relative_offset = offset as usize - cap_offset; + + if cap_type == CapabilityType::Msi { + let vbdf = dev.get_vbdf(); + let _domain_id = vbdf.domain(); + + let is_msi_64 = dev.with_cap(|capabilities| { + capabilities + .cap_in_config_ref() + .get(&(cap_offset as u64)) + .and_then(|cap| cap.with_region(|region| region.read(0x02, 2).ok())) + .map(|ctrl| (ctrl & (1 << 7)) != 0) + .unwrap_or(false) + }); + + let _is_addr_low = matches!(relative_offset, 4 | 5 | 6 | 7); + let _is_addr_high = is_msi_64 && matches!(relative_offset, 8 | 9 | 10 | 11); + let _is_msg_data = if is_msi_64 { + matches!(relative_offset, 12 | 13) + } else { + matches!(relative_offset, 8 | 9) + }; + + #[cfg(all(dwc_msi, dwc_pcie))] + { + if is_write { + if _is_addr_low { + dev.with_msi_info_mut(|msi_info| { + let current = msi_info.msi_doorbell & 0xffffffff00000000; + msi_info.set_doorbell(current | (value as u64)); + }); + let hw_paddr = + crate::pci::dwc_msi::get_domain_doorbell_paddr(_domain_id); + dev.write_hw(offset, size, (hw_paddr & 0xffffffff) as usize)?; + return Ok(None); + } + if _is_addr_high { + dev.with_msi_info_mut(|msi_info| { + let current = msi_info.msi_doorbell & 0xffffffff; + msi_info.set_doorbell(current | ((value as u64) << 32)); + }); + let hw_paddr = + crate::pci::dwc_msi::get_domain_doorbell_paddr(_domain_id); + dev.write_hw(offset, size, ((hw_paddr >> 32) & 0xffffffff) as usize)?; + return Ok(None); + } + if _is_msg_data { + let zone = this_zone(); + let guard = zone.read(); + let vbus = guard.vpci_bus(); + if let Some(domain_msi_info) = vbus.domain_msi_info().get(&_domain_id) { + let hw_value = + (value as u32).wrapping_add(domain_msi_info.hwirq_bit); + dev.write_hw(offset, size, hw_value as usize)?; + } else { + dev.write_hw(offset, size, value)?; + } + return Ok(None); + } + } else { + if _is_addr_low { + let vm_doorbell = dev + .read() + .get_msi_info() + .map(|msi_info| msi_info.msi_doorbell) + .unwrap_or(0); + return Ok(Some((vm_doorbell & 0xffffffff) as usize)); + } + if _is_addr_high { + let vm_doorbell = dev + .read() + .get_msi_info() + .map(|msi_info| msi_info.msi_doorbell) + .unwrap_or(0); + return Ok(Some(((vm_doorbell >> 32) & 0xffffffff) as usize)); + } + if _is_msg_data { + let hw_value = dev.read_hw(offset, size)?; + let zone = this_zone(); + let guard = zone.read(); + let vbus = guard.vpci_bus(); + if let Some(domain_msi_info) = vbus.domain_msi_info().get(&_domain_id) { + let hwirq_bit = domain_msi_info.hwirq_bit; + let hw_vec = hw_value as u32; + let virq_bit = if hw_vec >= hwirq_bit { + hw_vec - hwirq_bit + } else { + hw_vec + }; + return Ok(Some(virq_bit as usize)); + } + return Ok(Some(hw_value)); + } + } + } + } + + // Direct pass through to hardware for all cap access if is_write { - super::vpci_dev::vpci_dev_write_cfg(dev_type, dev.clone(), offset, size, value)?; + dev.write_hw(offset, size, value)?; Ok(None) } else { - Ok(Some(super::vpci_dev::vpci_dev_read_cfg( - dev_type, - dev.clone(), - offset, - size, - )?)) + Ok(Some(dev.read_hw(offset, size)?)) } + } else { + // No capability found at this offset + Ok(None) } } } @@ -208,6 +635,30 @@ fn handle_endpoint_access( * as previously described */ let bar_type = dev.with_bar_ref(slot, |bar| bar.get_type()); + + // Check if this BAR contains MSIX table (only when dwc_msi feature is enabled) + #[cfg(all(dwc_msi, dwc_pcie))] + let is_msix_bar = { + let msix_check_slot = if bar_type == PciMemType::Mem64High && slot > 0 { + slot - 1 + } else { + slot + }; + + dev.read() + .get_msi_info() + .and_then(|msi_info| { + msi_info + .msix_info + .as_ref() + .map(|msix| msix.bar_id == msix_check_slot as u8) + }) + .unwrap_or(false) + }; + + #[cfg(not(dwc_msi))] + let is_msix_bar = false; + if bar_type != PciMemType::default() { if is_write { if is_direct && is_root { @@ -222,22 +673,34 @@ fn handle_endpoint_access( value, )?; if (bar_type == PciMemType::Mem32) + | (bar_type == PciMemType::Mem64Low) | (bar_type == PciMemType::Mem64High) | (bar_type == PciMemType::Io) { + let old_vaddr = + dev.with_bar_ref(slot, |bar| bar.get_virtual_value64()) & !0xf; let new_vaddr = { - if bar_type == PciMemType::Mem64High { - /* last 4bit is flag, not address and need ignore - * flag will auto add when set_value and set_virtual_value - * Read from config_value.bar_value cache instead of space - */ - let low_value = dev - .with_config_value(|cv| cv.get_bar_value(slot - 1)) - as u64; - let high_value = (value as u32 as u64) << 32; - (low_value | high_value) & !0xf - } else { - (value as u64) & !0xf + match bar_type { + PciMemType::Mem64Low => { + let low_value = value as u32 as u64; + let high_value = (dev + .with_config_value(|cv| cv.get_bar_value(slot + 1)) + as u64) + << 32; + (low_value | high_value) & !0xf + } + PciMemType::Mem64High => { + /* last 4bit is flag, not address and need ignore + * flag will auto add when set_value and set_virtual_value + * Read from config_value.bar_value cache instead of space + */ + let low_value = dev + .with_config_value(|cv| cv.get_bar_value(slot - 1)) + as u64; + let high_value = (value as u32 as u64) << 32; + (low_value | high_value) & !0xf + } + _ => (value as u64) & !0xf, } }; @@ -247,12 +710,104 @@ fn handle_endpoint_access( dev.with_bar_ref_mut(slot - 1, |bar| { bar.set_virtual_value(new_vaddr) }); + } else if bar_type == PciMemType::Mem64Low { + dev.with_bar_ref_mut(slot + 1, |bar| { + bar.set_virtual_value(new_vaddr) + }); } // set value dev.with_bar_ref_mut(slot, |bar| bar.set_value(new_vaddr)); if bar_type == PciMemType::Mem64High { dev.with_bar_ref_mut(slot - 1, |bar| bar.set_value(new_vaddr)); + } else if bar_type == PciMemType::Mem64Low { + dev.with_bar_ref_mut(slot + 1, |bar| bar.set_value(new_vaddr)); + } + + let paddr = { + let raw = dev.with_bar_ref(slot, |bar| bar.get_value64()) + as HostPhysAddr; + if bar_type == PciMemType::Io { + raw & !0x3 + } else { + raw & !0xf + } + }; + + if is_msix_bar { + let msix_slot = if bar_type == PciMemType::Mem64High { + slot - 1 + } else { + slot + }; + dev.with_msi_info_mut(|msi_info| { + if let Some(msix) = msi_info.msix_info.as_mut() { + if msix.bar_id as usize == msix_slot { + msix.bar_paddr = paddr as u64; + } + } + }); + } + + let bar_size = { + let size = dev.with_bar_ref(slot, |bar| bar.get_size()); + if crate::memory::addr::is_aligned(size as usize) { + size + } else { + crate::memory::PAGE_SIZE as u64 + } + }; + let new_vaddr_aligned = + if !crate::memory::addr::is_aligned(new_vaddr as usize) { + crate::memory::addr::align_up(new_vaddr as usize) as u64 + } else { + new_vaddr as u64 + }; + + let zone = this_zone(); + let mut guard = zone.write(); + + if is_msix_bar { + guard.mmio_region_remove(old_vaddr as GuestPhysAddr); + guard.mmio_region_register( + new_vaddr_aligned as GuestPhysAddr, + bar_size as usize, + mmio_msix_table_handler, + paddr as usize, + ); + } else { + let gpm = guard.gpm_mut(); + if !gpm + .try_delete( + old_vaddr.try_into().unwrap(), + bar_size as usize, + ) + .is_ok() + {} + guard.insert_passthrough_region_quiet( + MemoryRegion::new_with_offset_mapper( + new_vaddr_aligned as GuestPhysAddr, + paddr as HostPhysAddr, + bar_size as _, + MemFlags::READ | MemFlags::WRITE, + ), + )?; + } + drop(guard); + #[cfg(target_arch = "aarch64")] + unsafe { + core::arch::asm!("isb"); + core::arch::asm!("tlbi vmalls12e1is"); + core::arch::asm!("dsb nsh"); + } + #[cfg(all(target_arch = "x86_64", intel_vtd))] + { + let vbdf = dev.get_vbdf(); + crate::device::iommu::flush( + this_zone_id(), + vbdf.bus, + (vbdf.device << 3) + vbdf.function, + ); } } } @@ -263,24 +818,34 @@ fn handle_endpoint_access( }); if (value & 0xfffffff0) != 0xfffffff0 { if (bar_type == PciMemType::Mem32) + | (bar_type == PciMemType::Mem64Low) | (bar_type == PciMemType::Mem64High) | (bar_type == PciMemType::Io) { let old_vaddr = dev.with_bar_ref(slot, |bar| bar.get_virtual_value64()) & !0xf; let new_vaddr = { - if bar_type == PciMemType::Mem64High { - /* last 4bit is flag, not address and need ignore - * flag will auto add when set_value and set_virtual_value - * Read from config_value.bar_value cache instead of space - */ - let low_value = dev - .with_config_value(|cv| cv.get_bar_value(slot - 1)) - as u64; - let high_value = (value as u32 as u64) << 32; - (low_value | high_value) & !0xf - } else { - (value as u64) & !0xf + match bar_type { + PciMemType::Mem64Low => { + let low_value = value as u32 as u64; + let high_value = (dev + .with_config_value(|cv| cv.get_bar_value(slot + 1)) + as u64) + << 32; + (low_value | high_value) & !0xf + } + PciMemType::Mem64High => { + /* last 4bit is flag, not address and need ignore + * flag will auto add when set_value and set_virtual_value + * Read from config_value.bar_value cache instead of space + */ + let low_value = dev + .with_config_value(|cv| cv.get_bar_value(slot - 1)) + as u64; + let high_value = (value as u32 as u64) << 32; + (low_value | high_value) & !0xf + } + _ => (value as u64) & !0xf, } }; @@ -291,10 +856,36 @@ fn handle_endpoint_access( dev.with_bar_ref_mut(slot - 1, |bar| { bar.set_virtual_value(new_vaddr) }); + } else if bar_type == PciMemType::Mem64Low { + dev.with_bar_ref_mut(slot + 1, |bar| { + bar.set_virtual_value(new_vaddr) + }); } - let paddr = - dev.with_bar_ref(slot, |bar| bar.get_value64()) as HostPhysAddr; + let paddr = { + let raw = dev.with_bar_ref(slot, |bar| bar.get_value64()) + as HostPhysAddr; + if bar_type == PciMemType::Io { + raw & !0x3 + } else { + raw & !0xf + } + }; + + if is_msix_bar { + dev.with_msi_info_mut(|msi_info| { + if let Some(msix) = msi_info.msix_info.as_mut() { + let msix_slot = if bar_type == PciMemType::Mem64High { + slot - 1 + } else { + slot + }; + if msix.bar_id as usize == msix_slot { + msix.bar_paddr = paddr as u64; + } + } + }); + } let bar_size = { let size = dev.with_bar_ref(slot, |bar| bar.get_size()); if crate::memory::addr::is_aligned(size as usize) { @@ -312,20 +903,39 @@ fn handle_endpoint_access( let zone = this_zone(); let mut guard = zone.write(); - let gpm = guard.gpm_mut(); - if !gpm - .try_delete(old_vaddr.try_into().unwrap(), bar_size as usize) - .is_ok() - { - // warn!("delete bar {}: can not found 0x{:x}", slot, old_vaddr); - } - gpm.try_insert_quiet(MemoryRegion::new_with_offset_mapper( - new_vaddr as GuestPhysAddr, - paddr as HostPhysAddr, - bar_size as _, - MemFlags::READ | MemFlags::WRITE, - ))?; + if is_msix_bar { + // Remove old MSIX handler if it exists + guard.mmio_region_remove(old_vaddr as GuestPhysAddr); + // Register new MSIX handler at new address + guard.mmio_region_register( + new_vaddr as GuestPhysAddr, + bar_size as usize, + mmio_msix_table_handler, + paddr as usize, + ); + } else { + // Delete old gpm mapping if it exists + let gpm = guard.gpm_mut(); + if !gpm + .try_delete( + old_vaddr.try_into().unwrap(), + bar_size as usize, + ) + .is_ok() + { + // warn!("delete bar {}: can not found 0x{:x}", slot, old_vaddr); + } + // Insert new gpm mapping at new address + guard.insert_passthrough_region_quiet( + MemoryRegion::new_with_offset_mapper( + new_vaddr as GuestPhysAddr, + paddr as HostPhysAddr, + bar_size as _, + MemFlags::READ | MemFlags::WRITE, + ), + )?; + } drop(guard); /* after update gpm, mem barrier is needed */ @@ -338,7 +948,7 @@ fn handle_endpoint_access( /* after update gpm, need to flush iommu table * in x86_64 */ - #[cfg(all(target_arch = "x86_64", feature = "intel_vtd"))] + #[cfg(all(target_arch = "x86_64", intel_vtd))] { let vbdf = dev.get_vbdf(); crate::device::iommu::flush( @@ -411,76 +1021,574 @@ fn handle_endpoint_access( configvalue.set_rom_value(value as u32); }); - if value & 0xfffff800 != 0xfffff800 { + // Check if this is size probe (all 1s in BA field, bits 31-11) + let is_size_probe = (value & 0xfffff800) == 0xfffff800; + // Check if ROM enable bit (bit 0) is set + let rom_enabled = (value & 0x1) != 0; + + if !is_size_probe { let old_vaddr = dev.with_rom_ref(|rom| rom.get_virtual_value64()) & !0xf; let new_vaddr = (value as u64) & !0xf; - dev.with_rom_ref_mut(|rom| rom.set_virtual_value(new_vaddr)); + // Only perform mapping operations if ROM enable bit is set + if rom_enabled { + // set new_value not new_vaddr, because `set_virtual_value` will not add enable flag automatically + dev.with_rom_ref_mut(|rom| rom.set_virtual_value(value as _)); + + // Write to hardware with enable bit set + // Get the current ROM value from hardware and set bit 0 + // And not to use rom.set_value() + let hw_value = dev.with_rom_ref(|rom| rom.get_value64()); + let hw_value_enabled = hw_value | 0x1; // Set enable bit + dev.write_hw( + field.to_offset() as PciConfigAddress, + field.size(), + hw_value_enabled as usize, + )?; + dev.with_rom_ref_mut(|rom| rom.set_value(hw_value_enabled)); - let paddr = if is_root { - dev.with_rom_ref_mut(|rom| rom.set_value(new_vaddr)); - new_vaddr as HostPhysAddr - } else { - dev.with_rom_ref(|rom| rom.get_value64()) as HostPhysAddr - }; + let paddr = + dev.with_rom_ref(|rom| rom.get_value64()) as HostPhysAddr; - let rom_size = { - let size = dev.with_rom_ref(|rom| rom.get_size()); - if crate::memory::addr::is_aligned(size as usize) { - size - } else { - crate::memory::PAGE_SIZE as u64 - } - }; - let new_vaddr = if !crate::memory::addr::is_aligned(new_vaddr as usize) - { - crate::memory::addr::align_up(new_vaddr as usize) as u64 - } else { - new_vaddr as u64 - }; + let rom_size = { + let size = dev.with_rom_ref(|rom| rom.get_size()); + if crate::memory::addr::is_aligned(size as usize) { + size + } else { + crate::memory::PAGE_SIZE as u64 + } + }; + let new_vaddr_aligned = + if !crate::memory::addr::is_aligned(new_vaddr as usize) { + crate::memory::addr::align_up(new_vaddr as usize) as u64 + } else { + new_vaddr as u64 + }; - let zone = this_zone(); - let mut guard = zone.write(); - let gpm = guard.gpm_mut(); + let zone = this_zone(); + let mut guard = zone.write(); + let gpm = guard.gpm_mut(); - if !gpm - .try_delete(old_vaddr.try_into().unwrap(), rom_size as usize) - .is_ok() - { - // warn!("delete rom bar: can not found 0x{:x}", old_vaddr); - } - gpm.try_insert_quiet(MemoryRegion::new_with_offset_mapper( - new_vaddr as GuestPhysAddr, - paddr as HostPhysAddr, - rom_size as _, - MemFlags::READ | MemFlags::WRITE, - ))?; - drop(guard); - /* after update gpm, mem barrier is needed - */ - #[cfg(target_arch = "aarch64")] - unsafe { - core::arch::asm!("isb"); - core::arch::asm!("tlbi vmalls12e1is"); - core::arch::asm!("dsb nsh"); - } - /* after update gpm, need to flush iommu table - * in x86_64 - */ - #[cfg(all(target_arch = "x86_64", feature = "intel_vtd"))] - { - let vbdf = dev.get_vbdf(); - crate::device::iommu::flush( - this_zone_id(), - vbdf.bus, - (vbdf.device << 3) + vbdf.function, - ); - } - #[cfg(target_arch = "riscv64")] - unsafe { - // TOOD: add remote fence support (using sbi rfence spec?) - core::arch::asm!("hfence.gvma"); + if !gpm + .try_delete(old_vaddr.try_into().unwrap(), rom_size as usize) + .is_ok() + { + // warn!("delete rom bar: can not found 0x{:x}", old_vaddr); + } + guard.insert_passthrough_region_quiet( + MemoryRegion::new_with_offset_mapper( + new_vaddr_aligned as GuestPhysAddr, + paddr as HostPhysAddr, + rom_size as _, + MemFlags::READ | MemFlags::WRITE, + ), + )?; + drop(guard); + /* after update gpm, mem barrier is needed + */ + #[cfg(target_arch = "aarch64")] + unsafe { + core::arch::asm!("isb"); + core::arch::asm!("tlbi vmalls12e1is"); + core::arch::asm!("dsb nsh"); + } + /* after update gpm, need to flush iommu table + * in x86_64 + */ + #[cfg(all(target_arch = "x86_64", intel_vtd))] + { + let vbdf = dev.get_vbdf(); + crate::device::iommu::flush( + this_zone_id(), + vbdf.bus, + (vbdf.device << 3) + vbdf.function, + ); + } + #[cfg(target_arch = "riscv64")] + unsafe { + // TOOD: add remote fence support (using sbi rfence spec?) + core::arch::asm!("hfence.gvma"); + } + } else { + // ROM disabled + } + } + } + Ok(None) + } else { + // read rom bar + if (dev.with_config_value(|configvalue| configvalue.get_rom_value())) + & 0xfffff800 + == 0xfffff800 + { + /* + * config_value being 0xFFFF_FFFF means that Linux is attempting to determine the ROM size. + * The value is used directly here because Linux will rewrite this register later, + * so the Hvisor does not need to preserve any additional state. + */ + Ok(Some( + dev.with_rom_ref(|rom| rom.get_size_with_flag()) as usize + )) + } else { + Ok(Some( + dev.with_config_value(|configvalue| configvalue.get_rom_value()) + as usize, + )) + } + } + } else { + Ok(None) + } + } + _ => Ok(None), + } +} + +fn handle_pci_bridge_access( + dev: ArcRwLockVirtualPciConfigSpace, + field: BridgeField, + value: usize, + is_write: bool, + is_direct: bool, + is_root: bool, + is_dev_belong_to_zone: bool, +) -> HvResult> { + match field { + BridgeField::Bar(slot) => { + let bar_type = dev.with_bar_ref(slot, |bar| bar.get_type()); + + // Check if this BAR contains MSIX table (only when dwc_msi feature is enabled) + #[cfg(all(dwc_msi, dwc_pcie))] + let is_msix_bar = { + let msix_check_slot = if bar_type == PciMemType::Mem64High && slot > 0 { + slot - 1 + } else { + slot + }; + + dev.read() + .get_msi_info() + .and_then(|msi_info| { + msi_info + .msix_info + .as_ref() + .map(|msix| msix.bar_id == msix_check_slot as u8) + }) + .unwrap_or(false) + }; + + #[cfg(not(dwc_msi))] + let is_msix_bar = false; + + if bar_type != PciMemType::default() { + if is_write { + if is_direct && is_root { + // direct mode and root zone, update resources directly + dev.with_config_value_mut(|configvalue| { + configvalue.set_bar_value(slot, value as u32); + }); + if (value & 0xfffffff0) != 0xfffffff0 { + dev.write_hw( + field.to_offset() as PciConfigAddress, + field.size(), + value, + )?; + if (bar_type == PciMemType::Mem32) + | (bar_type == PciMemType::Mem64High) + | (bar_type == PciMemType::Io) + { + let old_vaddr = + dev.with_bar_ref(slot, |bar| bar.get_virtual_value64()) & !0xf; + let new_vaddr = { + if bar_type == PciMemType::Mem64High { + let low_value = dev + .with_config_value(|cv| cv.get_bar_value(slot - 1)) + as u64; + let high_value = (value as u32 as u64) << 32; + (low_value | high_value) & !0xf + } else { + (value as u64) & !0xf + } + }; + + // set virt_value + dev.with_bar_ref_mut(slot, |bar| bar.set_virtual_value(new_vaddr)); + if bar_type == PciMemType::Mem64High { + dev.with_bar_ref_mut(slot - 1, |bar| { + bar.set_virtual_value(new_vaddr) + }); + } + + // set value + dev.with_bar_ref_mut(slot, |bar| bar.set_value(new_vaddr)); + if bar_type == PciMemType::Mem64High { + dev.with_bar_ref_mut(slot - 1, |bar| bar.set_value(new_vaddr)); + } + + let paddr = { + let raw = dev.with_bar_ref(slot, |bar| bar.get_value64()) + as HostPhysAddr; + if bar_type == PciMemType::Io { + raw & !0x3 + } else { + raw & !0xf + } + }; + + if is_msix_bar { + let msix_slot = if bar_type == PciMemType::Mem64High { + slot - 1 + } else { + slot + }; + dev.with_msi_info_mut(|msi_info| { + if let Some(msix) = msi_info.msix_info.as_mut() { + if msix.bar_id as usize == msix_slot { + msix.bar_paddr = paddr as u64; + } + } + }); + } + + let bar_size = { + let size = dev.with_bar_ref(slot, |bar| bar.get_size()); + if crate::memory::addr::is_aligned(size as usize) { + size + } else { + crate::memory::PAGE_SIZE as u64 + } + }; + let new_vaddr_aligned = + if !crate::memory::addr::is_aligned(new_vaddr as usize) { + crate::memory::addr::align_up(new_vaddr as usize) as u64 + } else { + new_vaddr as u64 + }; + + let zone = this_zone(); + let mut guard = zone.write(); + + if is_msix_bar { + guard.mmio_region_remove(old_vaddr as GuestPhysAddr); + guard.mmio_region_register( + new_vaddr_aligned as GuestPhysAddr, + bar_size as usize, + mmio_msix_table_handler, + paddr as usize, + ); + } else { + let gpm = guard.gpm_mut(); + if !gpm + .try_delete( + old_vaddr.try_into().unwrap(), + bar_size as usize, + ) + .is_ok() + {} + guard.insert_passthrough_region_quiet( + MemoryRegion::new_with_offset_mapper( + new_vaddr_aligned as GuestPhysAddr, + paddr as HostPhysAddr, + bar_size as _, + MemFlags::READ | MemFlags::WRITE, + ), + )?; + } + drop(guard); + #[cfg(target_arch = "aarch64")] + unsafe { + core::arch::asm!("isb"); + core::arch::asm!("tlbi vmalls12e1is"); + core::arch::asm!("dsb nsh"); + } + #[cfg(all(target_arch = "x86_64", intel_vtd))] + { + let vbdf = dev.get_vbdf(); + crate::device::iommu::flush( + this_zone_id(), + vbdf.bus, + (vbdf.device << 3) + vbdf.function, + ); + } + } + } + } else if is_dev_belong_to_zone { + // normal mode, update virt resources + dev.with_config_value_mut(|configvalue| { + configvalue.set_bar_value(slot, value as u32); + }); + if (value & 0xfffffff0) != 0xfffffff0 { + if (bar_type == PciMemType::Mem32) + | (bar_type == PciMemType::Mem64High) + | (bar_type == PciMemType::Io) + { + let old_vaddr = + dev.with_bar_ref(slot, |bar| bar.get_virtual_value64()) & !0xf; + let new_vaddr = { + if bar_type == PciMemType::Mem64High { + let low_value = dev + .with_config_value(|cv| cv.get_bar_value(slot - 1)) + as u64; + let high_value = (value as u32 as u64) << 32; + (low_value | high_value) & !0xf + } else { + (value as u64) & !0xf + } + }; + + dev.with_bar_ref_mut(slot, |bar| bar.set_virtual_value(new_vaddr)); + if bar_type == PciMemType::Mem64High { + dev.with_bar_ref_mut(slot - 1, |bar| { + bar.set_virtual_value(new_vaddr) + }); + } + + let paddr = { + let raw = dev.with_bar_ref(slot, |bar| bar.get_value64()) + as HostPhysAddr; + if bar_type == PciMemType::Io { + raw & !0x3 + } else { + raw & !0xf + } + }; + + if is_msix_bar { + dev.with_msi_info_mut(|msi_info| { + if let Some(msix) = msi_info.msix_info.as_mut() { + let msix_slot = if bar_type == PciMemType::Mem64High { + slot - 1 + } else { + slot + }; + if msix.bar_id as usize == msix_slot { + msix.bar_paddr = paddr as u64; + } + } + }); + } + let bar_size = { + let size = dev.with_bar_ref(slot, |bar| bar.get_size()); + if crate::memory::addr::is_aligned(size as usize) { + size + } else { + crate::memory::PAGE_SIZE as u64 + } + }; + let new_vaddr_aligned = + if !crate::memory::addr::is_aligned(new_vaddr as usize) { + crate::memory::addr::align_up(new_vaddr as usize) as u64 + } else { + new_vaddr as u64 + }; + + let zone = this_zone(); + let mut guard = zone.write(); + + if is_msix_bar { + // Remove old MSIX handler if it exists + guard.mmio_region_remove(old_vaddr as GuestPhysAddr); + // Register new MSIX handler at new address + guard.mmio_region_register( + new_vaddr_aligned as GuestPhysAddr, + bar_size as usize, + mmio_msix_table_handler, + paddr as usize, + ); + } else { + // Delete old gpm mapping if it exists + let gpm = guard.gpm_mut(); + if !gpm + .try_delete( + old_vaddr.try_into().unwrap(), + bar_size as usize, + ) + .is_ok() + { + // warn!("delete bar {}: can not found 0x{:x}", slot, old_vaddr); + } + // Insert new gpm mapping at new address + guard.insert_passthrough_region_quiet( + MemoryRegion::new_with_offset_mapper( + new_vaddr_aligned as GuestPhysAddr, + paddr as HostPhysAddr, + bar_size as _, + MemFlags::READ | MemFlags::WRITE, + ), + )?; + } + drop(guard); + /* after update gpm, mem barrier is needed + */ + #[cfg(target_arch = "aarch64")] + unsafe { + core::arch::asm!("isb"); + core::arch::asm!("tlbi vmalls12e1is"); + core::arch::asm!("dsb nsh"); + } + /* after update gpm, need to flush iommu table + * in x86_64 + */ + #[cfg(all(target_arch = "x86_64", intel_vtd))] + { + let vbdf = dev.get_vbdf(); + crate::device::iommu::flush( + this_zone_id(), + vbdf.bus, + (vbdf.device << 3) + vbdf.function, + ); + } + } + } + } + Ok(None) + } else { + // read bar + if (dev.with_config_value(|configvalue| configvalue.get_bar_value(slot)) + & 0xfffffff0) + == 0xfffffff0 + { + /* + * tmp_value being 0xFFFF_FFFF means that Linux is attempting to determine the BAR size. + * The value of tmp_value is used directly here because Linux will rewrite this register later, + * so the Hvisor does not need to preserve any additional state. + */ + Ok(Some( + dev.with_bar_ref(slot, |bar| bar.get_size_with_flag()) as usize + )) + } else { + Ok(Some( + dev.with_config_value(|configvalue| configvalue.get_bar_value(slot)) + as usize, + )) + } + } + } else { + Ok(None) + } + } + BridgeField::ExpansionRomBar => { + // rom is same with bar + let rom_type = dev.with_rom_ref(|rom| rom.get_type()); + if rom_type == PciMemType::Rom { + if is_write { + if is_direct && is_root { + dev.with_config_value_mut(|configvalue| { + configvalue.set_rom_value(value as u32); + }); + if value & 0xfffff800 != 0xfffff800 { + dev.write_hw( + field.to_offset() as PciConfigAddress, + field.size(), + value, + )?; + + let new_vaddr = (value as u64) & !0xf; + + // set virt_value + dev.with_rom_ref_mut(|rom| rom.set_virtual_value(new_vaddr)); + + // set value + dev.with_rom_ref_mut(|rom| rom.set_value(new_vaddr)); + } + } else if is_dev_belong_to_zone { + // normal mode, update virt resources + dev.with_config_value_mut(|configvalue| { + configvalue.set_rom_value(value as u32); + }); + + // Check if this is size probe (all 1s in BA field, bits 31-11) + let is_size_probe = (value & 0xfffff800) == 0xfffff800; + // Check if ROM enable bit (bit 0) is set + let rom_enabled = (value & 0x1) != 0; + + if !is_size_probe { + let old_vaddr = + dev.with_rom_ref(|rom| rom.get_virtual_value64()) & !0xf; + let new_vaddr = (value as u64) & !0xf; + + // Only perform mapping operations if ROM enable bit is set + if rom_enabled { + // set new_value not new_vaddr, because `set_virtual_value` will not add enable flag automatically + dev.with_rom_ref_mut(|rom| rom.set_virtual_value(value as _)); + + // Write to hardware with enable bit set + // Get the current ROM value from hardware and set bit 0 + // And not to use rom.set_value() + let hw_value = dev.with_rom_ref(|rom| rom.get_value64()); + let hw_value_enabled = hw_value | 0x1; // Set enable bit + dev.write_hw( + field.to_offset() as PciConfigAddress, + field.size(), + hw_value_enabled as usize, + )?; + dev.with_rom_ref_mut(|rom| rom.set_value(hw_value_enabled)); + + let paddr = + dev.with_rom_ref(|rom| rom.get_value64()) as HostPhysAddr; + + let rom_size = { + let size = dev.with_rom_ref(|rom| rom.get_size()); + if crate::memory::addr::is_aligned(size as usize) { + size + } else { + crate::memory::PAGE_SIZE as u64 + } + }; + let new_vaddr_aligned = + if !crate::memory::addr::is_aligned(new_vaddr as usize) { + crate::memory::addr::align_up(new_vaddr as usize) as u64 + } else { + new_vaddr as u64 + }; + + let zone = this_zone(); + let mut guard = zone.write(); + let gpm = guard.gpm_mut(); + + if !gpm + .try_delete(old_vaddr.try_into().unwrap(), rom_size as usize) + .is_ok() + { + // warn!("delete rom bar: can not found 0x{:x}", old_vaddr); + } + guard.insert_passthrough_region_quiet( + MemoryRegion::new_with_offset_mapper( + new_vaddr_aligned as GuestPhysAddr, + paddr as HostPhysAddr, + rom_size as _, + MemFlags::READ | MemFlags::WRITE, + ), + )?; + drop(guard); + /* after update gpm, mem barrier is needed + */ + #[cfg(target_arch = "aarch64")] + unsafe { + core::arch::asm!("isb"); + core::arch::asm!("tlbi vmalls12e1is"); + core::arch::asm!("dsb nsh"); + } + /* after update gpm, need to flush iommu table + * in x86_64 + */ + #[cfg(all(target_arch = "x86_64", intel_vtd))] + { + let vbdf = dev.get_vbdf(); + crate::device::iommu::flush( + this_zone_id(), + vbdf.bus, + (vbdf.device << 3) + vbdf.function, + ); + } + #[cfg(target_arch = "riscv64")] + unsafe { + // TOOD: add remote fence support (using sbi rfence spec?) + core::arch::asm!("hfence.gvma"); + } + } else { + // ROM disabled } } } @@ -510,18 +1618,42 @@ fn handle_endpoint_access( Ok(None) } } + BridgeField::PrimaryBusNumber + | BridgeField::SecondaryBusNumber + | BridgeField::SubordinateBusNumber + | BridgeField::SecondaryLatencyTimer => { + let reg_offset = field.to_offset() as usize; + if is_write { + if is_dev_belong_to_zone || (is_direct && is_root) { + dev.with_config_value_mut(|cv| { + let mut reg = cv.get_bridge_bus_reg(); + let shift = (reg_offset - 0x18) * 8; + reg = (reg & !((0xffu32) << shift)) | (((value as u32) & 0xff) << shift); + cv.set_bridge_bus_reg(reg); + }); + } + Ok(None) + } else { + let reg = dev.with_config_value(|cv| cv.get_bridge_bus_reg()); + Ok(Some(((reg >> ((reg_offset - 0x18) * 8)) & 0xff) as usize)) + } + } + BridgeField::BusNumbers => { + if is_write { + if is_dev_belong_to_zone || (is_direct && is_root) { + dev.with_config_value_mut(|cv| cv.set_bridge_bus_reg(value as u32)); + } + Ok(None) + } else { + Ok(Some( + dev.with_config_value(|cv| cv.get_bridge_bus_reg()) as usize + )) + } + } _ => Ok(None), } } -fn handle_pci_bridge_access( - _dev: ArcRwLockVirtualPciConfigSpace, - _field: BridgeField, - _is_write: bool, -) -> HvResult> { - Ok(None) -} - /* * is_direct: if true, root can allocate resource for device belonging * to ohter zone but can't drive it @@ -553,6 +1685,13 @@ fn handle_config_space_access( let vbdf = dev.get_bdf(); let dev_type = dev.get_dev_type(); + if !is_root && dev.read().get_sriov_vf_info().is_some() { + if offset == 0x100 { + mmio.value = 0x0; + return Ok(()); + } + } + if is_root || is_dev_belong_to_zone { match dev.access(offset, size) { false => { @@ -592,25 +1731,63 @@ fn handle_config_space_access( let config_type = dev.get_config_type(); match config_type { HeaderType::Endpoint => { - if let Some(val) = handle_endpoint_access( - dev, - EndpointField::from(offset as usize, size), - value, - is_write, - is_direct, - is_root, - is_dev_belong_to_zone, - )? { - mmio.value = val; + // Check if this is capability region access (offset >= 0x40) + if (offset >= 0x40 && offset < 0x100) + || (offset == 0x34) + || (offset >= 0x100) + { + if let Some(val) = handle_cap_access( + dev, + offset, + size, + value, + is_write, + is_dev_belong_to_zone, + )? { + mmio.value = val; + } + } else { + if let Some(val) = handle_endpoint_access( + dev, + EndpointField::from(offset as usize, size), + value, + is_write, + is_direct, + is_root, + is_dev_belong_to_zone, + )? { + mmio.value = val; + } } } HeaderType::PciBridge => { - if let Some(val) = handle_pci_bridge_access( - dev, - BridgeField::from(offset as usize, size), - is_write, - )? { - mmio.value = val; + // Check if this is capability region access (offset >= 0x40) + if (offset >= 0x40 && offset < 0x100) + || (offset == 0x34) + || (offset >= 0x100) + { + if let Some(val) = handle_cap_access( + dev, + offset, + size, + value, + is_write, + is_dev_belong_to_zone, + )? { + mmio.value = val; + } + } else { + if let Some(val) = handle_pci_bridge_access( + dev, + BridgeField::from(offset as usize, size), + value, + is_write, + is_direct, + is_root, + is_dev_belong_to_zone, + )? { + mmio.value = val; + } } } _ => { @@ -621,10 +1798,15 @@ fn handle_config_space_access( _ => { // virt pci dev if let Some(val) = - handle_virt_pci_request(dev, offset, size, value, is_write, dev_type)? + handle_virtio_pci_request(dev, offset, size, value, is_write)? { - mmio.value = val; + mmio.value = val } + // if let Some(val) = + // handle_virt_pci_request(dev, offset, size, value, is_write, dev_type)? + // { + // mmio.value = val; + // } } } } @@ -679,7 +1861,7 @@ pub fn mmio_vpci_handler(mmio: &mut MMIOAccess, _base: usize) -> HvResult { Ok(()) } -#[cfg(feature = "dwc_pcie")] +#[cfg(dwc_pcie)] pub fn mmio_dwc_io_handler(mmio: &mut MMIOAccess, _base: usize) -> HvResult { { let zone = this_zone(); @@ -720,7 +1902,7 @@ pub fn mmio_dwc_io_handler(mmio: &mut MMIOAccess, _base: usize) -> HvResult { Ok(()) } -#[cfg(feature = "dwc_pcie")] +#[cfg(dwc_pcie)] pub fn mmio_dwc_cfg_handler(mmio: &mut MMIOAccess, _base: usize) -> HvResult { // info!("mmio_dwc_cfg_handler {:#x}", mmio.address + _base); let zone = this_zone(); @@ -741,6 +1923,7 @@ pub fn mmio_dwc_cfg_handler(mmio: &mut MMIOAccess, _base: usize) -> HvResult { if let Some((atu, ecam_base)) = atu_config { // Get dbi_base from platform config (usually dbi_base == ecam_base) use crate::platform; + let pci_target = atu.pci_target(); if let Some(extend_config) = platform::ROOT_DWC_ATU_CONFIG .iter() .find(|cfg| cfg.ecam_base == ecam_base as u64) @@ -751,22 +1934,63 @@ pub fn mmio_dwc_cfg_handler(mmio: &mut MMIOAccess, _base: usize) -> HvResult { let dbi_region = PciRegionMmio::new(dbi_base, dbi_size); let dbi_backend = DwcConfigRegionBackend::new(dbi_region); - // warn!("atu config {:#?}", atu); + let target_bus = ((pci_target >> 24) & 0xff) as u8; + let target_device = ((pci_target >> 19) & 0x1f) as u8; + let target_function = ((pci_target >> 16) & 0x7) as u8; + + let mapped_target = { + let zone_guard = zone.read(); + let vbus = zone_guard.vpci_bus(); + vbus.devs_ref().values().find_map(|dev| { + let vbdf = dev.get_vbdf(); + if vbdf.bus() == target_bus + && vbdf.device() == target_device + && vbdf.function() == target_function + { + Some(dev.get_bdf()) + } else { + None + } + }) + }; + + let mut hw_pci_target = pci_target; + let mut atu_type = atu.atu_type(); + let mut config_base = atu.cpu_base(); + let mut cpu_limit = atu.cpu_limit(); + if let Some(host_bdf) = mapped_target { + hw_pci_target = ((host_bdf.bus() as u64) << 24) + + ((host_bdf.device() as u64) << 19) + + ((host_bdf.function() as u64) << 16); + let half = extend_config.cfg_size / 2; + config_base = _base as u64; + atu_type = if config_base >= extend_config.cfg_base + half { + AtuType::Cfg1 + } else { + AtuType::Cfg0 + }; + cpu_limit = config_base + half - 1; + } - // Call AtuUnroll to program the ATU - AtuUnroll::dw_pcie_prog_outbound_atu_unroll(&dbi_backend, &atu)?; + // Program hardware ATU only when host/guest BDF remapping is required. + if hw_pci_target != pci_target { + let mut hw_atu = atu; + hw_atu.set_pci_target(hw_pci_target); + hw_atu.set_atu_type(atu_type); + hw_atu.set_cpu_base(config_base); + hw_atu.set_cpu_limit(cpu_limit); + AtuUnroll::dw_pcie_prog_outbound_atu_unroll(&dbi_backend, &hw_atu)?; + } } let offset = (mmio.address & 0xfff) as PciConfigAddress; let zone = this_zone(); let mut is_dev_belong_to_zone = false; - let base = mmio.address as PciConfigAddress - offset + atu.pci_target(); - let dev: Option = { let mut guard = zone.write(); let vbus = guard.vpci_bus_mut(); - if let Some(dev) = vbus.get_device_by_base(base) { + if let Some(dev) = vbus.get_device_by_base(pci_target) { is_dev_belong_to_zone = true; Some(dev) } else { @@ -775,13 +1999,26 @@ pub fn mmio_dwc_cfg_handler(mmio: &mut MMIOAccess, _base: usize) -> HvResult { // This avoids holding multiple locks simultaneously let dev_clone = { let global_pcie_list = GLOBAL_PCIE_LIST.lock(); - global_pcie_list - .values() - .find(|dev| { - let dev_guard = dev.read(); - dev_guard.get_base() == base - }) - .cloned() + let domain = platform::ROOT_PCI_CONFIG + .iter() + .find(|cfg| cfg.ecam_base as usize == ecam_base) + .map(|cfg| cfg.domain) + .unwrap_or(0); + let target_bdf = Bdf::new( + domain, + ((pci_target >> 24) & 0xff) as u8, + ((pci_target >> 19) & 0x1f) as u8, + ((pci_target >> 16) & 0x7) as u8, + ); + global_pcie_list.get(&target_bdf).cloned().or_else(|| { + global_pcie_list + .values() + .find(|dev| { + let dev_guard = dev.read(); + dev_guard.get_base() == pci_target + }) + .cloned() + }) }; dev_clone } @@ -798,195 +2035,586 @@ pub fn mmio_dwc_cfg_handler(mmio: &mut MMIOAccess, _base: usize) -> HvResult { let is_root = is_this_root_zone(); let is_direct = true; // dwc_cfg_handler uses direct mode - handle_config_space_access(dev, mmio, offset, is_direct, is_root, is_dev_belong_to_zone)?; + handle_config_space_access( + dev.clone(), + mmio, + offset, + is_direct, + is_root, + is_dev_belong_to_zone, + )?; } else { warn!("No ATU config yet, do nothing"); } Ok(()) } -#[cfg(feature = "dwc_pcie")] +#[cfg(dwc_pcie)] pub fn mmio_vpci_handler_dbi(mmio: &mut MMIOAccess, _base: usize) -> HvResult { // info!("mmio_vpci_handler_dbi {:#x}", mmio.address); - /* 0x0-0x100 is outbound atu0 reg - * 0x100-0x200 is inbound atu0 reg just handle outbound right now - * so MAX is ATU_BASE + ATU_REGION_SIZE/2 - */ - if mmio.address >= ATU_BASE && mmio.address < ATU_BASE + ATU_REGION_SIZE / 2 { - let zone = this_zone(); - let mut guard = zone.write(); - let ecam_base = _base; - let atu_offset = mmio.address - ATU_BASE; + use crate::platform; + + // Decode domain_id and ecam_base from arg: + // arg = ecam_base + domain_id + // Since ecam_base is 4KB aligned (low 12 bits are 0), + // low bits contain domain_id, high bits contain ecam_base + let domain_id = (_base & 0xF) as u8; + let ecam_base = _base - (domain_id as usize); + + #[cfg(all(pci_init_delay, dwc_pcie))] + { + // Delay mode semantics: + // - Before init-done, accesses to non-zero DBI regs are normally passed through. + // - For dwc_msi, MSI_ADDR_LO/HI are intercepted early so VM doorbell writes are cached. + // - Access to DBI reg 0 triggers hvisor PCI init, then normal DBI virtualization continues. + if !is_pci_init_done(domain_id) { + if mmio.address != 0 { + #[cfg(dwc_msi)] + match mmio.address { + PCIE_MSI_ADDR_LO | PCIE_MSI_ADDR_HI => { + let zone = this_zone(); + let mut guard = zone.write(); + let vbus = guard.vpci_bus_mut(); + + if vbus.domain_msi_info().get(&domain_id).is_none() { + vbus.add_msi_count_for_domain(domain_id, 1, 0); + } + + if let Some(domain_msi_info) = + vbus.domain_msi_info_mut().get_mut(&domain_id) + { + if mmio.is_write { + let vm_doorbell = domain_msi_info.get_vm_doorbell(); + let new_val = if mmio.address == PCIE_MSI_ADDR_LO { + (vm_doorbell & 0xffffffff00000000) | (mmio.value as u64) + } else { + (vm_doorbell & 0xffffffff) | ((mmio.value as u64) << 32) + }; + domain_msi_info.set_vm_doorbell(new_val); + } else { + let vm_doorbell = domain_msi_info.get_vm_doorbell(); + mmio.value = if mmio.address == PCIE_MSI_ADDR_LO { + (vm_doorbell & 0xffffffff) as usize + } else { + ((vm_doorbell >> 32) & 0xffffffff) as usize + }; + } + } + + return Ok(()); + } + _ => {} + } + + mmio_perform_access(ecam_base, mmio); + return Ok(()); + } + + let root_config = platform::platform_root_zone_config(); + let num_pci_bus = root_config.num_pci_bus as usize; + + let zone = crate::zone::root_zone(); + let mut inner = zone.write(); + inner.virtual_pci_mmio_init_delay(&root_config.pci_config, num_pci_bus, domain_id); + drop(inner); + + if let Some(domain_cfg) = root_config.pci_config[..num_pci_bus] + .iter() + .find(|cfg| cfg.domain == domain_id && cfg.ecam_base != 0) + { + crate::pci::pci_config::hvisor_pci_init(core::slice::from_ref(domain_cfg))?; + } else { + warn!("No PCI config found for domain {}", domain_id); + } + + let mut inner = zone.write(); + inner.guest_pci_init_delay( + 0, + &root_config.alloc_pci_devs, + root_config.num_pci_devs, + &root_config.pci_config, + num_pci_bus, + domain_id, + )?; + + #[cfg(dwc_msi)] + { + // Why this is inside init-delay only: + // before init-done, VM may have already written MSI_ADDR_LO/HI and those writes were + // cached (virtual doorbell) but did not program final hardware state. + // After hvisor_pci_init() completes, force HW LO/HI to hvisor-allocated doorbell. + // In non-delay mode, writes go through the normal MSI register handler below, + // and first LO/HI writes are translated/synced there, so this extra sync is unnecessary. + let hw_paddr = crate::pci::dwc_msi::get_domain_doorbell_paddr(domain_id); + if hw_paddr != 0 { + let mut hw_lo_write = MMIOAccess { + address: PCIE_MSI_ADDR_LO, + value: (hw_paddr & 0xffffffff) as usize, + size: 4, + is_write: true, + }; + let mut hw_hi_write = MMIOAccess { + address: PCIE_MSI_ADDR_HI, + value: ((hw_paddr >> 32) & 0xffffffff) as usize, + size: 4, + is_write: true, + }; + mmio_perform_access(ecam_base, &mut hw_lo_write); + mmio_perform_access(ecam_base, &mut hw_hi_write); + } + } + + set_pci_init_done(domain_id); + info!( + "Hvisor PCI initialization complete for domain {}", + domain_id + ); + } + } + + // Read extend_config to get io_atu_index + let extend_config = platform::ROOT_DWC_ATU_CONFIG + .iter() + .find(|cfg| cfg.ecam_base == ecam_base as u64); + + if let Some(extend_config) = extend_config { + let io_atu_index = extend_config.io_atu_index as usize; + let atu_base = ATU_BASE + io_atu_index * ATU_REGION_SIZE; + + /* Calculate outbound atu registers address range based on io_atu_index + * Each ATU has: 0x0-0x100 for outbound, 0x100-0x200 for inbound + * We only handle outbound now, so MAX is atu_base + ATU_REGION_SIZE/2 + */ + if mmio.address >= atu_base && mmio.address < atu_base + ATU_REGION_SIZE / 2 { + let zone = this_zone(); + let mut guard = zone.write(); + let atu_offset = mmio.address - atu_base; - // warn!("set atu0 register {:#X} value {:#X}", atu_offset, mmio.value); + // warn!("set atu{} register {:#X} value {:#X}", io_atu_index, atu_offset, mmio.value); - let atu = guard - .atu_configs_mut() - .get_atu_by_ecam_mut(ecam_base) - .unwrap(); + let atu = guard + .atu_configs_mut() + .get_atu_by_ecam_mut(ecam_base) + .unwrap(); - // info!("atu config write {:#?}", atu); + // info!("atu config write {:#?}", atu); - if mmio.is_write { - if mmio.size == 4 { + if mmio.is_write { + if mmio.size == 4 { + match atu_offset { + PCIE_ATU_UNR_REGION_CTRL1 => { + // info!("set atu{} region ctrl1 value {:#X}", io_atu_index, mmio.value); + atu.set_atu_type(AtuType::from_u8((mmio.value & 0xff) as u8)); + } + PCIE_ATU_UNR_REGION_CTRL2 => { + // Enable bit is written here, but we just track it + // The actual enable is handled by the driver + } + PCIE_ATU_UNR_LOWER_BASE => { + // info!("set atu{} lower base value {:#X}", io_atu_index, mmio.value); + atu.set_cpu_base( + (atu.cpu_base() & !0xffffffff) | (mmio.value as PciConfigAddress), + ); + } + PCIE_ATU_UNR_UPPER_BASE => { + // info!("set atu{} upper base value {:#X}", io_atu_index, mmio.value); + atu.set_cpu_base( + (atu.cpu_base() & 0xffffffff) + | ((mmio.value as PciConfigAddress) << 32), + ); + } + PCIE_ATU_UNR_LIMIT => { + // info!("set atu{} limit value {:#X}", io_atu_index, mmio.value); + atu.set_cpu_limit( + (atu.cpu_limit() & !0xffffffff) | (mmio.value as PciConfigAddress), + ); + } + PCIE_ATU_UNR_UPPER_LIMIT => { + // Update the upper 32 bits of cpu_limit + atu.set_cpu_limit( + (atu.cpu_limit() & 0xffffffff) + | ((mmio.value as PciConfigAddress) << 32), + ); + } + PCIE_ATU_UNR_LOWER_TARGET => { + // info!("set atu{} lower target value {:#X}", io_atu_index, mmio.value); + atu.set_pci_target( + (atu.pci_target() & !0xffffffff) | (mmio.value as PciConfigAddress), + ); + } + PCIE_ATU_UNR_UPPER_TARGET => { + // info!("set atu{} upper target value {:#X}", io_atu_index, mmio.value); + atu.set_pci_target( + (atu.pci_target() & 0xffffffff) + | ((mmio.value as PciConfigAddress) << 32), + ); + } + _ => { + warn!( + "invalid atu{} write {:#x} + {:#x}", + io_atu_index, atu_offset, mmio.size + ); + } + } + } else { + warn!("invalid atu{} read size {:#x}", io_atu_index, mmio.size); + } + } else { + // Read from virtual ATU + // warn!("read atu{} {:#x}", io_atu_index, atu_offset); match atu_offset { PCIE_ATU_UNR_REGION_CTRL1 => { - // info!("set atu0 region ctrl1 value {:#X}", mmio.value); - atu.set_atu_type(AtuType::from_u8((mmio.value & 0xff) as u8)); + mmio.value = atu.atu_type() as usize; } PCIE_ATU_UNR_REGION_CTRL2 => { - // Enable bit is written here, but we just track it - // The actual enable is handled by the driver + mmio.value = ATU_ENABLE_BIT as usize; } PCIE_ATU_UNR_LOWER_BASE => { - // info!("set atu0 lower base value {:#X}", mmio.value); - atu.set_cpu_base( - (atu.cpu_base() & !0xffffffff) | (mmio.value as PciConfigAddress), - ); + mmio.value = (atu.cpu_base() & 0xffffffff) as usize; } PCIE_ATU_UNR_UPPER_BASE => { - // info!("set atu0 upper base value {:#X}", mmio.value); - atu.set_cpu_base( - (atu.cpu_base() & 0xffffffff) - | ((mmio.value as PciConfigAddress) << 32), - ); + mmio.value = ((atu.cpu_base() >> 32) & 0xffffffff) as usize; } PCIE_ATU_UNR_LIMIT => { - // info!("set atu0 limit value {:#X}", mmio.value); - atu.set_cpu_limit( - (atu.cpu_limit() & !0xffffffff) | (mmio.value as PciConfigAddress), - ); + let limit_value = (atu.cpu_limit() & 0xffffffff) as usize; + mmio.value = if limit_value == 0 { + atu.limit_hw_value() as usize + } else { + limit_value + }; } PCIE_ATU_UNR_UPPER_LIMIT => { - // Update the upper 32 bits of cpu_limit - atu.set_cpu_limit( - (atu.cpu_limit() & 0xffffffff) - | ((mmio.value as PciConfigAddress) << 32), - ); + let upper_limit = ((atu.cpu_limit() >> 32) & 0xffffffff) as usize; + mmio.value = if upper_limit == 0xffffffff { + atu.upper_limit_hw_value() as usize + } else { + upper_limit + }; } PCIE_ATU_UNR_LOWER_TARGET => { - // info!("set atu0 lower target value {:#X}", mmio.value); - atu.set_pci_target( - (atu.pci_target() & !0xffffffff) | (mmio.value as PciConfigAddress), - ); + mmio.value = (atu.pci_target() & 0xffffffff) as usize; } PCIE_ATU_UNR_UPPER_TARGET => { - // info!("set atu0 upper target value {:#X}", mmio.value); - atu.set_pci_target( - (atu.pci_target() & 0xffffffff) - | ((mmio.value as PciConfigAddress) << 32), - ); + mmio.value = ((atu.pci_target() >> 32) & 0xffffffff) as usize; } _ => { - warn!("invalid atu0 write {:#x} + {:#x}", atu_offset, mmio.size); + warn!("invalid atu{} read {:#x}", io_atu_index, atu_offset); + mmio_perform_access(_base, mmio); } } - } else { - warn!("invalid atu0 read size {:#x}", mmio.size); - } - } else { - // Read from virtual ATU - // warn!("read atu0 {:#x}", atu_offset); - match atu_offset { - PCIE_ATU_UNR_REGION_CTRL1 => { - mmio.value = atu.atu_type() as usize; - } - PCIE_ATU_UNR_REGION_CTRL2 => { - mmio.value = ATU_ENABLE_BIT as usize; - } - PCIE_ATU_UNR_LOWER_BASE => { - mmio.value = (atu.cpu_base() & 0xffffffff) as usize; - } - PCIE_ATU_UNR_UPPER_BASE => { - mmio.value = ((atu.cpu_base() >> 32) & 0xffffffff) as usize; - } - PCIE_ATU_UNR_LIMIT => { - let limit_value = (atu.cpu_limit() & 0xffffffff) as usize; - mmio.value = if limit_value == 0 { - atu.limit_hw_value() as usize - } else { - limit_value - }; - } - PCIE_ATU_UNR_UPPER_LIMIT => { - let upper_limit = ((atu.cpu_limit() >> 32) & 0xffffffff) as usize; - mmio.value = if upper_limit == 0xffffffff { - atu.upper_limit_hw_value() as usize - } else { - upper_limit - }; - } - PCIE_ATU_UNR_LOWER_TARGET => { - mmio.value = (atu.pci_target() & 0xffffffff) as usize; - } - PCIE_ATU_UNR_UPPER_TARGET => { - mmio.value = ((atu.pci_target() >> 32) & 0xffffffff) as usize; - } - _ => { - warn!("invalid atu0 read {:#x}", atu_offset); - mmio_perform_access(_base, mmio); - } } - } - } else if mmio.address > ATU_BASE + ATU_REGION_SIZE / 2 { - mmio_perform_access(_base, mmio); - } else if mmio.address >= BIT_LENTH { - // dbi read - mmio_perform_access(_base, mmio); - } else { - warn!("mmio_vpci_handler_dbi read {:#x}", mmio.address); - let offset = (mmio.address & 0xfff) as PciConfigAddress; - let zone = this_zone(); - let mut is_dev_belong_to_zone = false; + } else if mmio.address > ATU_BASE { + mmio_perform_access(ecam_base, mmio); + } else if mmio.address >= BIT_LENTH + && !(mmio.address >= PCIE_MSI_ADDR_LO && mmio.address <= PCIE_MSI_INTR0_STATUS) + { + // dbi read + mmio_perform_access(ecam_base, mmio); + } else if mmio.address >= PCIE_MSI_ADDR_LO && mmio.address <= PCIE_MSI_INTR0_STATUS { + // Handle MSI registers - virtuize only if dwc_msi feature enabled + #[cfg(all(dwc_msi, dwc_pcie))] + { + // Non-delay path (or delay after init-done) uses this handler for MSI DBI regs. + // LO/HI writes are virtualized and synchronized with hvisor-managed doorbell here. + // Handle MSI registers + let dbi_offset = mmio.address; + let zone = this_zone(); + + let mut guard = zone.write(); + let vbus = guard.vpci_bus_mut(); + + if let Some(domain_msi_info) = vbus.domain_msi_info_mut().get_mut(&domain_id) { + match dbi_offset { + PCIE_MSI_ADDR_LO => { + if mmio.is_write { + // VM writes low 32 bits of doorbell address + let new_doorbell = (domain_msi_info.get_vm_doorbell() + & 0xffffffff00000000) + | (mmio.value as u64); + domain_msi_info.set_vm_doorbell(new_doorbell); + + // Check if hardware doorbell matches hvisor's allocation from DW_MSI_DOMAINS + // Read current hardware ADDR_LO and ADDR_HI to get full doorbell address + let mut hw_hi_mmio = MMIOAccess { + address: PCIE_MSI_ADDR_HI, + value: 0, + size: 4, + is_write: false, + }; + // After VM writes LO, hardware still has old LO value + // We'll use the new LO from VM write and existing HI from hardware + mmio_perform_access(ecam_base, &mut hw_hi_mmio); + let hw_doorbell = + ((hw_hi_mmio.value as u64) << 32) | (mmio.value as u64); + + // Get the authoritative doorbell from DW_MSI_DOMAINS + // Actually vm set the doorbell only when this board doesn't support arch MSI + let hw_paddr = + crate::pci::dwc_msi::get_domain_doorbell_paddr(domain_id); + + // If hardware doorbell doesn't match hvisor's allocation, sync it + if hw_doorbell != hw_paddr && hw_paddr != 0 { + let hw_paddr_lo = (hw_paddr & 0xffffffff) as u32; + let hw_paddr_hi = ((hw_paddr >> 32) & 0xffffffff) as u32; + + // Write hvisor's doorbell LO + let mut hw_lo_write = MMIOAccess { + address: PCIE_MSI_ADDR_LO, + value: hw_paddr_lo as usize, + size: 4, + is_write: true, + }; + mmio_perform_access(ecam_base, &mut hw_lo_write); + + // Write hvisor's doorbell HI (only if needed) + if hw_paddr_hi != (hw_hi_mmio.value as u32) { + let mut hw_hi_write = MMIOAccess { + address: PCIE_MSI_ADDR_HI, + value: hw_paddr_hi as usize, + size: 4, + is_write: true, + }; + mmio_perform_access(ecam_base, &mut hw_hi_write); + } + } + } else { + // Return the low 32 bits of VM doorbell + mmio.value = + (domain_msi_info.get_vm_doorbell() & 0xffffffff) as usize; + } + } + PCIE_MSI_ADDR_HI => { + if mmio.is_write { + // VM writes high 32 bits of doorbell address + let new_doorbell = (domain_msi_info.get_vm_doorbell() & 0xffffffff) + | ((mmio.value as u64) << 32); + domain_msi_info.set_vm_doorbell(new_doorbell); + + // Check if hardware doorbell matches hvisor's allocation from DW_MSI_DOMAINS + // Read current hardware ADDR_LO and ADDR_HI to get full doorbell address + let mut hw_lo_mmio = MMIOAccess { + address: PCIE_MSI_ADDR_LO, + value: 0, + size: 4, + is_write: false, + }; + mmio_perform_access(ecam_base, &mut hw_lo_mmio); + let hw_doorbell = + ((mmio.value as u64) << 32) | (hw_lo_mmio.value as u64); + + // Get the authoritative doorbell from DW_MSI_DOMAINS + let hw_paddr = + crate::pci::dwc_msi::get_domain_doorbell_paddr(domain_id); + + // If hardware doorbell doesn't match hvisor's allocation, sync it + if hw_doorbell != hw_paddr && hw_paddr != 0 { + let hw_paddr_lo = (hw_paddr & 0xffffffff) as u32; + let hw_paddr_hi = ((hw_paddr >> 32) & 0xffffffff) as u32; + + // Write hvisor's doorbell HI + let mut hw_hi_write = MMIOAccess { + address: PCIE_MSI_ADDR_HI, + value: hw_paddr_hi as usize, + size: 4, + is_write: true, + }; + mmio_perform_access(ecam_base, &mut hw_hi_write); + + // Write hvisor's doorbell LO (only if needed) + if hw_paddr_lo != (hw_lo_mmio.value as u32) { + let mut hw_lo_write = MMIOAccess { + address: PCIE_MSI_ADDR_LO, + value: hw_paddr_lo as usize, + size: 4, + is_write: true, + }; + mmio_perform_access(ecam_base, &mut hw_lo_write); + } + } + } else { + // Return the high 32 bits of VM doorbell + mmio.value = ((domain_msi_info.get_vm_doorbell() >> 32) + & 0xffffffff) + as usize; + } + } + PCIE_MSI_INTR0_ENABLE | PCIE_MSI_INTR0_MASK | PCIE_MSI_INTR0_STATUS => { + // All three registers use the same bit shifting and masking logic + let hwirq_bit = domain_msi_info.hwirq_bit; + let vm_mask = domain_msi_info.get_msi_mask(); + + if mmio.is_write { + // VM writes from virqbit 0-based perspective + // Convert to hardware perspective by left-shifting by hwirq_bit + let hw_value_vm = + (mmio.value as u32 & vm_mask).wrapping_shl(hwirq_bit); + + if dbi_offset == PCIE_MSI_INTR0_STATUS { + // Status register: write 1 to clear semantics + // Mask first to ensure VM can only clear its own bits + // No need to read hardware value - just write the mapped bits + // Hardware will clear only the bits we write as 1 + // Other domains' pending interrupts remain unaffected + let mut hw_mmio_write = MMIOAccess { + address: mmio.address, + value: hw_value_vm as usize, + size: 4, + is_write: true, + }; + mmio_perform_access(ecam_base, &mut hw_mmio_write); + } else { + // For ENABLE/MASK registers: need to preserve other domain's bits + // Read current hardware value + let mut hw_mmio = MMIOAccess { + address: mmio.address, + value: 0, + size: 4, + is_write: false, + }; + mmio_perform_access(ecam_base, &mut hw_mmio); + let hw_value = hw_mmio.value as u32; - let base = mmio.address as PciConfigAddress - offset + _base as PciConfigAddress; + // Create mask for this domain's MSI bits + let domain_mask = vm_mask.wrapping_shl(hwirq_bit); - let dev: Option = { - let mut guard = zone.write(); - let vbus = guard.vpci_bus_mut(); - if let Some(dev) = vbus.get_device_by_base(base) { - is_dev_belong_to_zone = true; - Some(dev) - } else { - drop(guard); - // Clone Arc first while holding GLOBAL_PCIE_LIST lock, then release it - // This avoids holding multiple locks simultaneously - let dev_clone = { - let global_pcie_list = GLOBAL_PCIE_LIST.lock(); - global_pcie_list - .values() - .find(|dev| { - let dev_guard = dev.read(); - dev_guard.get_base() == base - }) - .cloned() - }; - dev_clone - } - }; + // Update hardware value: clear domain bits, then set new ones + let new_hw_value = + (hw_value & !domain_mask) | (hw_value_vm & domain_mask); - let dev = match dev { - Some(dev) => dev, - None => { - handle_device_not_found(mmio, offset); - return Ok(()); + let mut hw_mmio_write = MMIOAccess { + address: mmio.address, + value: new_hw_value as usize, + size: 4, + is_write: true, + }; + mmio_perform_access(ecam_base, &mut hw_mmio_write); + } + } else { + // Read and convert from hardware perspective to VM perspective + // Read hardware value + let mut hw_mmio = MMIOAccess { + address: mmio.address, + value: 0, + size: 4, + is_write: false, + }; + mmio_perform_access(ecam_base, &mut hw_mmio); + let hw_value = hw_mmio.value as u32; + + // Right shift to get VM perspective and mask + let vm_value = hw_value.wrapping_shr(hwirq_bit) & vm_mask; + mmio.value = vm_value as usize; + } + } + _ => { + // Other DBI registers + mmio_perform_access(ecam_base, mmio); + } + } + } else { + warn!("No MSI domain info found for domain {}", domain_id); + mmio_perform_access(ecam_base, mmio); + } } - }; - let is_root = is_this_root_zone(); - let is_direct = true; // dbi handler uses direct mode + #[cfg(not(dwc_msi))] + { + // Without dwc_msi feature, directly pass through MSI register access + mmio_perform_access(ecam_base, mmio); + } + } else { + // warn!("mmio_vpci_handler_dbi read {:#x}", mmio.address); + let offset = (mmio.address & 0xfff) as PciConfigAddress; + let zone = this_zone(); + let mut is_dev_belong_to_zone = false; + + let base = mmio.address as PciConfigAddress - offset + ecam_base as PciConfigAddress; + + let dev: Option = { + let mut guard = zone.write(); + let vbus = guard.vpci_bus_mut(); + if let Some(dev) = vbus.get_device_by_base(base) { + is_dev_belong_to_zone = true; + Some(dev) + } else { + drop(guard); + // Clone Arc first while holding GLOBAL_PCIE_LIST lock, then release it + // This avoids holding multiple locks simultaneously + let dev_clone = { + let global_pcie_list = GLOBAL_PCIE_LIST.lock(); + global_pcie_list + .values() + .find(|dev| { + let dev_guard = dev.read(); + dev_guard.get_base() == base + }) + .cloned() + }; + dev_clone + } + }; - handle_config_space_access(dev, mmio, offset, is_direct, is_root, is_dev_belong_to_zone)?; + let dev = match dev { + Some(dev) => dev, + None => { + handle_device_not_found(mmio, offset); + return Ok(()); + } + }; + + let is_root = is_this_root_zone(); + let is_direct = true; // dbi handler uses direct mode + + handle_config_space_access( + dev, + mmio, + offset, + is_direct, + is_root, + is_dev_belong_to_zone, + )?; + } + } else { + warn!("No extend config found for ecam_base {:#x}", _base); } Ok(()) } +#[cfg(all(dwc_pcie, pci_init_delay))] +static DBI_PCI_INIT_DONE: Lazy>> = + Lazy::new(|| Mutex::new(BTreeMap::new())); + +#[cfg(all(dwc_pcie, pci_init_delay))] +pub fn is_pci_init_done(domain_id: u8) -> bool { + DBI_PCI_INIT_DONE + .lock() + .get(&domain_id) + .copied() + .unwrap_or(false) +} + +#[cfg(all(dwc_pcie, pci_init_delay))] +fn set_pci_init_done(domain_id: u8) { + DBI_PCI_INIT_DONE.lock().insert(domain_id, true); +} + pub fn mmio_vpci_direct_handler(mmio: &mut MMIOAccess, _base: usize) -> HvResult { let zone = this_zone(); - let offset = (mmio.address & 0xfff) as PciConfigAddress; - let base = mmio.address as PciConfigAddress - offset + _base as PciConfigAddress; + #[cfg(loongarch64_pcie)] + let (offset, base) = { + let access_addr = mmio.address as PciConfigAddress + _base as PciConfigAddress; + let offset = (access_addr & 0xff) | ((access_addr >> 16) & 0xf00); + let addroff = (offset & 0xff) | ((offset & 0xf00) << 16); + (offset, access_addr - addroff) + }; + #[cfg(not(loongarch64_pcie))] + let (offset, base) = { + let offset = (mmio.address & 0xfff) as PciConfigAddress; + let base = mmio.address as PciConfigAddress - offset + _base as PciConfigAddress; + (offset, base) + }; let mut is_dev_belong_to_zone = false; let dev: Option = { @@ -1020,3 +2648,192 @@ pub fn mmio_vpci_direct_handler(mmio: &mut MMIOAccess, _base: usize) -> HvResult Ok(()) } + +/// Handle MMIO access to MSIX table in BAR memory +pub fn mmio_msix_table_handler(mmio: &mut MMIOAccess, base: usize) -> HvResult { + let access_offset = mmio.address as u64; + let base_aligned = (base as u64) & !0xf; + + // Find the device matching this BAR's physical address and get domain_id from BDF + let (device_info, _domain_id) = { + let zone = this_zone(); + let guard = zone.read(); + let vbus = guard.vpci_bus(); + + // Find the device whose MSIX BAR paddr matches the handler base + let mut result = None; + let mut domain_id = 0xFF; + for dev in vbus.devs_ref().values() { + if let Some(msi_info) = dev.read().get_msi_info() { + if let Some(msix) = &msi_info.msix_info { + let msix_bar_aligned = msix.bar_paddr & !0xf; + if msix_bar_aligned == base_aligned { + // Get domain_id from device's BDF + domain_id = dev.read().get_bdf().domain(); + result = Some((dev.clone(), msix.offset, msix.entry_count)); + break; + } + } + } + } + + if result.is_none() { + panic!( + "MSIX table handler could not find device in current zone vPCI bus for BAR base {:#x}", + base_aligned + ); + } + (result, domain_id) + }; + + // Check if this access is within the MSIX table range + if let Some((dev, msix_offset, entry_count)) = device_info { + // let vbdf = dev.get_vbdf(); + + let msix_table_size = (entry_count as u64) * 16; // Each entry is 16 bytes + let msix_table_end = msix_offset + msix_table_size; + + if access_offset >= msix_offset && access_offset < msix_table_end { + // This is a MSIX table access, record it with detailed information + let offset_in_entry = access_offset - msix_offset; + // let entry_index = offset_in_entry / 16; + let field_offset = offset_in_entry % 16; + // let host_bdf = dev.get_bdf(); + // let field_name = match field_offset { + // 0..=3 => "msg_addr_lo", + // 4..=7 => "msg_addr_hi", + // 8..=11 => "msg_data", + // 12..=15 => "vector_ctrl", + // _ => "unknown", + // }; + + if mmio.is_write { + // let vm_value = mmio.value; + match field_offset { + 0..=3 => { + // Save VM's doorbell low 32 bits + dev.with_msi_info_mut(|msi_info| { + let current = msi_info.msi_doorbell & 0xffffffff00000000; + msi_info.set_doorbell(current | (mmio.value as u64)); + }); + + // Replace with hvisor's doorbell before writing to hardware + #[cfg(all(dwc_msi, dwc_pcie))] + { + if _domain_id != 0xFF { + let hw_paddr = + crate::pci::dwc_msi::get_domain_doorbell_paddr(_domain_id); + let hw_doorbell_lo = (hw_paddr & 0xffffffff) as usize; + mmio.value = hw_doorbell_lo; + } + } + } + 4..=7 => { + // Save VM's doorbell high 32 bits + dev.with_msi_info_mut(|msi_info| { + let current = msi_info.msi_doorbell & 0xffffffff; + msi_info.set_doorbell(current | ((mmio.value as u64) << 32)); + }); + + // Replace with hvisor's doorbell before writing to hardware + #[cfg(all(dwc_msi, dwc_pcie))] + { + if _domain_id != 0xFF { + let hw_paddr = + crate::pci::dwc_msi::get_domain_doorbell_paddr(_domain_id); + let hw_doorbell_hi = ((hw_paddr >> 32) & 0xffffffff) as usize; + mmio.value = hw_doorbell_hi; + } + } + } + 8..=11 => { + // Convert VM vector index to hardware vector index. + #[cfg(all(dwc_msi, dwc_pcie))] + { + if _domain_id != 0xFF { + let zone = this_zone(); + let guard = zone.read(); + let vbus = guard.vpci_bus(); + if let Some(domain_msi_info) = + vbus.domain_msi_info().get(&_domain_id) + { + let virq_bit = mmio.value as u32; + let hwirq_bit = domain_msi_info.hwirq_bit; + let hw_value = virq_bit.wrapping_add(hwirq_bit); + mmio.value = hw_value as usize; + } + } + } + } + 12..=15 => {} + _ => {} + } + + mmio_perform_access(base, mmio); + return Ok(()); + } else { + let mut hw_mmio = MMIOAccess { + address: mmio.address, + value: 0, + size: mmio.size, + is_write: false, + }; + mmio_perform_access(base, &mut hw_mmio); + let hw_value = hw_mmio.value; + + match field_offset { + 0..=3 => { + let dev_vm_doorbell = dev + .read() + .get_msi_info() + .map(|msi| msi.msi_doorbell) + .unwrap_or(0); + mmio.value = (dev_vm_doorbell & 0xffffffff) as usize; + } + 4..=7 => { + let dev_vm_doorbell = dev + .read() + .get_msi_info() + .map(|msi| msi.msi_doorbell) + .unwrap_or(0); + mmio.value = ((dev_vm_doorbell >> 32) & 0xffffffff) as usize; + } + 8..=11 => { + mmio.value = hw_value; + #[cfg(all(dwc_msi, dwc_pcie))] + { + if _domain_id != 0xFF { + let zone = this_zone(); + let guard = zone.read(); + let vbus = guard.vpci_bus(); + if let Some(domain_msi_info) = + vbus.domain_msi_info().get(&_domain_id) + { + let hwirq_bit = domain_msi_info.hwirq_bit; + let hw_vec = hw_value as u32; + let virq_bit = if hw_vec >= hwirq_bit { + hw_vec - hwirq_bit + } else { + hw_vec + }; + mmio.value = virq_bit as usize; + } + } + } + } + 12..=15 => { + mmio.value = hw_value; + } + _ => { + mmio.value = hw_value; + } + } + return Ok(()); + } + } + } + + mmio_perform_access(base, mmio); + + Ok(()) +} diff --git a/src/pci/pci_struct.rs b/src/pci/pci_struct.rs index 87fdf70b6..7541f8db5 100644 --- a/src/pci/pci_struct.rs +++ b/src/pci/pci_struct.rs @@ -26,7 +26,7 @@ use core::{ use spin::RwLock; use super::{ - config_accessors::{PciConfigAccessor, PciConfigMmio}, + config_accessors::{PciConfigAccessor, PciConfigMmio, PciRegion}, mem_alloc::BarAllocator, pci_access::{ Bar, EndpointField, EndpointHeader, HeaderType, PciBarRW, PciBridgeHeader, PciCommand, @@ -38,8 +38,13 @@ use super::{ use crate::{ config::HvPciDevConfig, + device::virtio_trampoline::VirtioPCIDataInfo, error::{HvErrorNum, HvResult}, - pci::vpci_dev::VpciDevType, + memory::MMIOAccess, + pci::{ + msix::{MsixBackend, MsixTable, MsixTableEntry}, + vpci_dev::VpciDevType, + }, }; type VirtualPciConfigBits = BitArr!(for BIT_LENTH, in u8, Lsb0); @@ -50,6 +55,8 @@ pub struct ConfigValue { class_and_revision_id: (BaseClass, SubClass, Interface, DeviceRevision), bar_value: [u32; 6], rom_value: u32, + bridge_bus_reg: u32, + firmware_bridge_bus_reg: Option, } impl Default for ConfigValue { @@ -59,6 +66,8 @@ impl Default for ConfigValue { class_and_revision_id: (0xFFu8, 0u8, 0u8, 0u8), bar_value: [0; 6], rom_value: 0, + bridge_bus_reg: 0, + firmware_bridge_bus_reg: None, } } } @@ -73,6 +82,8 @@ impl ConfigValue { class_and_revision_id, bar_value: [0; 6], rom_value: 0, + bridge_bus_reg: 0, + firmware_bridge_bus_reg: None, } } @@ -138,6 +149,22 @@ impl ConfigValue { pub fn set_rom_value(&mut self, value: u32) { self.rom_value = value; } + + pub fn get_bridge_bus_reg(&self) -> u32 { + self.bridge_bus_reg + } + + pub fn set_bridge_bus_reg(&mut self, value: u32) { + self.bridge_bus_reg = value; + } + + pub fn get_firmware_bridge_bus_reg(&self) -> Option { + self.firmware_bridge_bus_reg + } + + pub fn set_firmware_bridge_bus_reg(&mut self, value: u32) { + self.firmware_bridge_bus_reg = Some(value); + } } const MAX_DEVICE: u8 = 31; @@ -150,6 +177,24 @@ const PCI_EXP_TYPE_ROOT_PORT: u16 = 4; const PCI_EXP_TYPE_UPSTREAM: u16 = 5; const PCI_EXP_TYPE_DOWNSTREAM: u16 = 6; const PCI_EXP_TYPE_PCIE_BRIDGE: u16 = 8; +const PCIE_DEVICE_CAPABILITIES_2_OFFSET: PciConfigAddress = 0x24; +const PCIE_DEVICE_CONTROL_2_OFFSET: PciConfigAddress = 0x28; +const PCIE_ARI_FORWARDING: u32 = 1 << 5; + +pub(crate) const SRIOV_CAP_SIZE: PciConfigAddress = 0x40; +const SRIOV_CTRL_OFFSET: PciConfigAddress = 0x08; +const SRIOV_INITIAL_VFS_OFFSET: PciConfigAddress = 0x0c; +const SRIOV_TOTAL_VFS_OFFSET: PciConfigAddress = 0x0e; +const SRIOV_NUM_VFS_OFFSET: PciConfigAddress = 0x10; +const SRIOV_FIRST_VF_OFFSET: PciConfigAddress = 0x14; +const SRIOV_VF_STRIDE_OFFSET: PciConfigAddress = 0x16; +const SRIOV_VF_DEVICE_ID_OFFSET: PciConfigAddress = 0x1a; +const SRIOV_SUPPORTED_PAGE_SIZE_OFFSET: PciConfigAddress = 0x1c; +const SRIOV_SYSTEM_PAGE_SIZE_OFFSET: PciConfigAddress = 0x20; +pub(crate) const SRIOV_VF_BAR_OFFSET: PciConfigAddress = 0x24; +pub(crate) const SRIOV_VF_BAR_END: PciConfigAddress = SRIOV_VF_BAR_OFFSET + 6 * 4; +const SRIOV_CTRL_VF_ENABLE: u16 = 1 << 0; +const SRIOV_CTRL_ARI_CAPABLE_HIERARCHY: u16 = 1 << 4; #[derive(Clone, Copy, Eq, PartialEq, Default)] pub struct Bdf { @@ -189,6 +234,25 @@ impl Bdf { self.function } + pub fn routing_id(&self) -> u16 { + ((self.bus as u16) << 8) | ((self.device as u16) << 3) | (self.function as u16) + } + + pub fn from_routing_id(domain: u8, routing_id: u16) -> Self { + Self { + domain, + bus: ((routing_id >> 8) & 0xff) as u8, + device: ((routing_id >> 3) & 0x1f) as u8, + function: (routing_id & 0x7) as u8, + } + } + + pub fn add_routing_id_offset(&self, offset: u16) -> Option { + self.routing_id() + .checked_add(offset) + .map(|routing_id| Self::from_routing_id(self.domain, routing_id)) + } + pub fn is_host_bridge(&self, bus_begin: u8) -> bool { if (self.bus, self.device, self.function) == (bus_begin, 0, 0) { true @@ -196,6 +260,13 @@ impl Bdf { false } } + + pub fn requester_id(&self) -> u16 { + let bus = self.bus as u16; + let device = self.device as u16; + let function = self.function as u16; + bus << 8 | device << 3 | function + } } impl Ord for Bdf { @@ -261,6 +332,70 @@ impl Debug for Bdf { } } +fn default_bridge_bus_reg(primary: u8, domain_bus_range_end: u8) -> u32 { + let secondary = primary.saturating_add(1); + ((domain_bus_range_end as u32) << 16) | ((secondary as u32) << 8) | (primary as u32) +} + +#[cfg(no_pcie_bar_realloc)] +pub(crate) fn translate_bridge_bus_reg( + firmware_reg: u32, + bdf: Bdf, + vbdf: Bdf, + bus_map: &[HvPciDevConfig], + domain_bus_range_end: u8, +) -> u32 { + let physical_primary = firmware_reg as u8; + let physical_secondary = (firmware_reg >> 8) as u8; + let physical_subordinate = (firmware_reg >> 16) as u8; + + // Device/function remapping does not change bridge routing. If every bus + // visible through this bridge keeps its number, preserve the full firmware + // value, including reserved subordinate ranges and the latency byte. + let mut visible_bus_mappings = bus_map + .iter() + .filter(|config| { + config.domain == bdf.domain() + && (config.bus == physical_primary + || (config.bus >= physical_secondary && config.bus <= physical_subordinate)) + }) + .peekable(); + let identity_bus_map = physical_primary == bdf.bus() + && bdf.bus() == vbdf.bus() + && visible_bus_mappings.peek().is_some() + && visible_bus_mappings.all(|config| config.bus == config.v_bus); + if identity_bus_map { + return firmware_reg; + } + + let mapped_bus = |physical_bus: u8| { + bus_map + .iter() + .find(|config| config.domain == bdf.domain() && config.bus == physical_bus) + .map(|config| config.v_bus) + }; + + let virtual_primary = vbdf.bus(); + let virtual_secondary = + mapped_bus(physical_secondary).unwrap_or_else(|| virtual_primary.saturating_add(1)); + let virtual_subordinate = bus_map + .iter() + .filter(|config| { + config.domain == bdf.domain() + && config.bus >= physical_secondary + && config.bus <= physical_subordinate + }) + .map(|config| config.v_bus) + .max() + .unwrap_or(domain_bus_range_end) + .max(virtual_secondary); + + (firmware_reg & 0xff00_0000) + | ((virtual_subordinate as u32) << 16) + | ((virtual_secondary as u32) << 8) + | virtual_primary as u32 +} + /* 0: ro; * 1: rw */ @@ -309,14 +444,20 @@ impl VirtualPciAccessBits { let mut bits = BitArray::ZERO; bits[0x0..0x4].fill(true); // ID bits[0x08..0x0c].fill(true); // CLASS - bits[0x10..0x34].fill(true); //bar and rom + bits[0x10..0x34].fill(true); // BARs and ROM + bits[0x34..0x38].fill(true); // Capability Pointer + bits[0x40..0x100].fill(true); // Capability region (caps start at 0x40) Self { bits } } pub fn bridge() -> Self { - Self { - bits: BitArray::ZERO, - } + let mut bits = BitArray::ZERO; + bits[0x10..0x18].fill(true); // BARs + bits[0x18..0x1c].fill(true); // Primary/Secondary/Subordinate bus + latency + bits[0x38..0x3c].fill(true); // ROM + bits[0x34..0x38].fill(true); // Capability Pointer + bits[0x40..0x100].fill(true); // Capability region (caps start at 0x40) + Self { bits } } pub fn host_bridge() -> Self { @@ -336,6 +477,106 @@ impl VirtualPciAccessBits { } } +#[derive(Clone, Copy, Debug)] +pub struct MsixInfo { + pub bar_id: u8, + pub offset: u64, + pub entry_count: u32, // number of MSIX table entries + pub bar_paddr: u64, // physical address of the BAR +} + +#[derive(Clone, Debug)] +pub struct MsiInfo { + pub msi_count: u32, + // doorbell vm write to trigger interrupt + pub msi_doorbell: u64, + pub msix_info: Option, +} + +impl MsiInfo { + pub fn new(msi_count: u32) -> Self { + Self { + msi_count, + msi_doorbell: 0, + msix_info: None, + } + } + + pub fn set_doorbell(&mut self, doorbell: u64) { + self.msi_doorbell = doorbell; + } + + pub fn set_msix_info(&mut self, bar_id: u8, offset: u64, entry_count: u32, bar_paddr: u64) { + self.msix_info = Some(MsixInfo { + bar_id, + offset, + entry_count, + bar_paddr, + }); + } +} + +#[derive(Clone, Copy, Debug)] +pub struct SriovVfInfo { + pub pf_bdf: Bdf, + pub vf_index: u16, +} + +#[derive(Clone, Debug)] +pub struct SriovInfo { + pub cap_offset: PciConfigAddress, + pub initial_vfs: u16, + pub total_vfs: u16, + pub enabled_vfs: u16, + pub first_vf_offset: u16, + pub vf_stride: u16, + pub vf_device_id: DeviceId, + pub vf_bars: Bar, + pub vf_bdfs: Vec, +} + +impl SriovInfo { + pub fn new( + cap_offset: PciConfigAddress, + initial_vfs: u16, + total_vfs: u16, + first_vf_offset: u16, + vf_stride: u16, + vf_device_id: DeviceId, + vf_bars: Bar, + vf_bdfs: Vec, + ) -> Self { + Self { + cap_offset, + initial_vfs, + total_vfs, + enabled_vfs: 0, + first_vf_offset, + vf_stride, + vf_device_id, + vf_bars, + vf_bdfs, + } + } +} + +/// Information needed to splice the SR-IOV extended capability out of the +/// PCIe ext-cap linked list when presenting config space to a guest VM. +/// Populated during `ext_capability_enumerate` when the `sriov` feature is +/// disabled so that the SR-IOV cap is invisible to guests. +#[derive(Clone, Debug)] +pub struct HideSriovInfo { + /// Absolute config-space offset of the SR-IOV extended capability header. + pub sriov_cap_offset: PciConfigAddress, + /// The `next` pointer stored inside the SR-IOV cap header (bits\[31:20\]). + /// This is the cap that should follow SR-IOV in the list. + pub sriov_cap_next: PciConfigAddress, + /// Offset of the preceding ext-cap node (the one whose `next` pointer + /// currently points to `sriov_cap_offset`). `None` when SR-IOV is the + /// first extended capability (at offset 0x100). + pub prev_cap_offset: Option, +} + /* VirtualPciConfigSpace * bdf: the bdf hvisor seeing(same with the bdf without hvisor) * vbdf: the bdf zone seeing, it can set just you like without sr-iov @@ -348,6 +589,7 @@ impl VirtualPciAccessBits { pub struct VirtualPciConfigSpace { host_bdf: Bdf, parent_bdf: Bdf, + parent_bus: u8, bdf: Bdf, vbdf: Bdf, config_type: HeaderType, @@ -363,8 +605,22 @@ pub struct VirtualPciConfigSpace { bararr: Bar, rom: PciMem, capabilities: PciCapabilityList, + ext_capabilities: PciExtCapabilityList, dev_type: VpciDevType, + + // MSI/MSIX info for this device + msi_info: Option, + + // for SR-IOV PF + sriov_info: Option, + + // for SR-IOV VF + sriov_vf_info: Option, + + // SR-IOV cap hide info (populated when `sriov` feature is disabled) + hide_sriov: Option, + msix_table: Option>>, } #[derive(Clone)] @@ -425,6 +681,14 @@ impl ArcRwLockVirtualPciConfigSpace { self.read().get_vbdf() } + pub fn get_parent_bdf(&self) -> Bdf { + self.read().get_parent_bdf() + } + + pub fn get_parent_bus(&self) -> u8 { + self.read().get_parent_bus() + } + pub fn get_dev_type(&self) -> VpciDevType { self.read().get_dev_type() } @@ -533,6 +797,46 @@ impl ArcRwLockVirtualPciConfigSpace { f(&guard.capabilities) } + pub fn with_msi_info(&self, f: F) -> Option + where + F: FnOnce(&MsiInfo) -> R, + { + let guard = self.0.read(); + guard.msi_info.as_ref().map(|msi_info| f(msi_info)) + } + + pub fn with_msi_info_mut(&self, f: F) -> Option + where + F: FnOnce(&mut MsiInfo) -> R, + { + let mut guard = self.0.write(); + guard.msi_info.as_mut().map(|msi_info| f(msi_info)) + } + + pub fn with_sriov_info(&self, f: F) -> Option + where + F: FnOnce(&SriovInfo) -> R, + { + let guard = self.0.read(); + guard.sriov_info.as_ref().map(|sriov_info| f(sriov_info)) + } + + pub fn with_sriov_info_mut(&self, f: F) -> Option + where + F: FnOnce(&mut SriovInfo) -> R, + { + let mut guard = self.0.write(); + guard.sriov_info.as_mut().map(|sriov_info| f(sriov_info)) + } + + pub fn with_hide_sriov(&self, f: F) -> Option + where + F: FnOnce(&HideSriovInfo) -> R, + { + let guard = self.0.read(); + guard.hide_sriov.as_ref().map(|info| f(info)) + } + pub fn read(&self) -> spin::RwLockReadGuard<'_, VirtualPciConfigSpaceWithZone> { self.0.read() } @@ -540,6 +844,18 @@ impl ArcRwLockVirtualPciConfigSpace { pub fn write(&self) -> spin::RwLockWriteGuard<'_, VirtualPciConfigSpaceWithZone> { self.0.write() } + + pub fn is_my_bar_addr(&self, addr: usize) -> Option { + self.0.read().is_my_bar_addr(addr) + } + + pub fn bar_mmio_distribute(&self, bar: usize, mmio_ac: &mut MMIOAccess) -> HvResult { + self.0.read().bar_mmio_distribute(bar, mmio_ac) + } + + pub fn try_inject_msix_irq(&self, msix_backend: &Arc>) { + self.0.read().inject_msix_irq(msix_backend); + } } impl Debug for ArcRwLockVirtualPciConfigSpace { @@ -571,6 +887,292 @@ impl Debug for ArcRwLockVirtualPciConfigSpace { // } impl VirtualPciConfigSpace { + fn find_ext_cap_offset(&self, cap_type: ExtCapabilityType) -> Option { + self.ext_capabilities + .iter() + .find_map(|(offset, cap)| (cap.cap_type == cap_type).then_some(*offset)) + } + + fn sriov_write_system_page_size(&self, cap_offset: PciConfigAddress) -> HvResult<()> { + let supported = self + .backend + .read(cap_offset + SRIOV_SUPPORTED_PAGE_SIZE_OFFSET, 4)? as u32; + if supported == 0 { + return Ok(()); + } + + let page_size = supported & supported.wrapping_neg(); + self.backend.write( + cap_offset + SRIOV_SYSTEM_PAGE_SIZE_OFFSET, + 4, + page_size as usize, + ) + } + + fn sriov_latch_routing_fields( + &self, + cap_offset: PciConfigAddress, + num_vfs: u16, + ) -> HvResult<(u16, u16)> { + self.backend + .write(cap_offset + SRIOV_NUM_VFS_OFFSET, 2, num_vfs as usize)?; + let first_vf_offset = self.backend.read(cap_offset + SRIOV_FIRST_VF_OFFSET, 2)? as u16; + let vf_stride = self.backend.read(cap_offset + SRIOV_VF_STRIDE_OFFSET, 2)? as u16; + Ok((first_vf_offset, vf_stride)) + } + + fn parse_sriov_vf_bars(&self, cap_offset: PciConfigAddress) -> HvResult { + let mut bararr = Bar::default(); + let mut slot = 0usize; + + while slot < 6 { + let bar_offset = cap_offset + SRIOV_VF_BAR_OFFSET + (slot as PciConfigAddress) * 4; + let value = self.backend.read(bar_offset, 4)? as u32; + + if !value.get_bit(0) { + let prefetchable = value.get_bit(3); + + match value.get_bits(1..3) { + 0b00 => { + let size = { + self.backend.write(bar_offset, 4, 0xffff_ffffusize)?; + let mut readback = self.backend.read(bar_offset, 4)? as u32; + self.backend.write(bar_offset, 4, value as usize)?; + + if readback == 0 { + slot += 1; + continue; + } + + readback.set_bits(0..4, 0); + 1u64 << readback.trailing_zeros() + }; + + bararr[slot] = + PciMem::new_bar(PciMemType::Mem32, value as u64, size, prefetchable); + } + 0b10 => { + if slot == 5 { + warn!("SR-IOV VF BAR64 low part appears in BAR5"); + break; + } + + let high_offset = bar_offset + 4; + let value_high = self.backend.read(high_offset, 4)? as u32; + let size = { + self.backend.write(bar_offset, 4, 0xffff_ffffusize)?; + self.backend.write(high_offset, 4, 0xffff_ffffusize)?; + let mut readback_low = self.backend.read(bar_offset, 4)? as u32; + let readback_high = self.backend.read(high_offset, 4)? as u32; + self.backend.write(bar_offset, 4, value as usize)?; + self.backend.write(high_offset, 4, value_high as usize)?; + + readback_low.set_bits(0..4, 0); + + if readback_low != 0 { + 1u64 << readback_low.trailing_zeros() + } else { + 1u64 << (readback_high.trailing_zeros() + 32) + } + }; + let value64 = (value as u64) | ((value_high as u64) << 32); + + bararr[slot] = + PciMem::new_bar(PciMemType::Mem64Low, value64, size, prefetchable); + bararr[slot + 1] = + PciMem::new_bar(PciMemType::Mem64High, value64, size, prefetchable); + slot += 1; + } + _ => { + warn!( + "unsupported SR-IOV VF BAR type bits {:b}", + value.get_bits(1..3) + ); + } + } + } else { + let size = { + self.backend.write(bar_offset, 4, 0xffff_ffffusize)?; + let mut readback = self.backend.read(bar_offset, 4)? as u32; + self.backend.write(bar_offset, 4, value as usize)?; + + readback.set_bit(0, false); + if readback == 0 { + slot += 1; + continue; + } + + 1u64 << readback.trailing_zeros() + }; + bararr[slot] = PciMem::new_io(value as u64, size); + } + + slot += 1; + } + + Ok(bararr) + } + + pub fn build_sriov_info(&mut self, upstream: Option<&Bridge>) -> HvResult<()> { + let Some(cap_offset) = self.find_ext_cap_offset(ExtCapabilityType::SingleRootIov) else { + return Ok(()); + }; + + let initial_vfs = self + .backend + .read(cap_offset + SRIOV_INITIAL_VFS_OFFSET, 2)? as u16; + let total_vfs = self.backend.read(cap_offset + SRIOV_TOTAL_VFS_OFFSET, 2)? as u16; + let vf_device_id = self + .backend + .read(cap_offset + SRIOV_VF_DEVICE_ID_OFFSET, 2)? as u16; + + if total_vfs == 0 { + return Ok(()); + } + + let ari_forwarding = + upstream.is_some_and(|bridge| bridge.enable_ari_forwarding().unwrap_or(false)); + + let mut ctrl = self.backend.read(cap_offset + SRIOV_CTRL_OFFSET, 2)? as u16; + if ctrl & SRIOV_CTRL_VF_ENABLE != 0 { + self.backend.write(cap_offset + SRIOV_CTRL_OFFSET, 2, 0)?; + ctrl = 0; + } + self.backend + .write(cap_offset + SRIOV_NUM_VFS_OFFSET, 2, 0)?; + + let sriov_ctrl = if ari_forwarding { + ctrl | SRIOV_CTRL_ARI_CAPABLE_HIERARCHY + } else { + ctrl & !SRIOV_CTRL_ARI_CAPABLE_HIERARCHY + }; + self.sriov_write_system_page_size(cap_offset)?; + self.backend + .write(cap_offset + SRIOV_CTRL_OFFSET, 2, sriov_ctrl as usize)?; + + let (first_vf_offset, vf_stride) = + self.sriov_latch_routing_fields(cap_offset, total_vfs)?; + if first_vf_offset == 0 || vf_stride == 0 { + warn!( + "SR-IOV on {:#?}: invalid routing fields offset={:#x} stride={} InitialVFs={} TotalVFs={} ari={} ctrl={:#x}", + self.bdf, + first_vf_offset, + vf_stride, + initial_vfs, + total_vfs, + ari_forwarding, + sriov_ctrl + ); + return Ok(()); + } + + let confirmed_ctrl = self.backend.read(cap_offset + SRIOV_CTRL_OFFSET, 2)? as u16; + if ari_forwarding && confirmed_ctrl & SRIOV_CTRL_ARI_CAPABLE_HIERARCHY == 0 { + warn!( + "SR-IOV ARI hierarchy bit did not stick for {:#?}: ctrl={:#x}", + self.bdf, confirmed_ctrl + ); + } else if !ari_forwarding { + warn!( + "SR-IOV on {:#?}: upstream ARI forwarding is not enabled; VF routing may use non-ARI offsets", + self.bdf + ); + } + + info!( + "SR-IOV on {:#?}: latched offset={:#x} stride={} NumVFs={} InitialVFs={} TotalVFs={} ari={} ctrl={:#x}", + self.bdf, + first_vf_offset, + vf_stride, + total_vfs, + initial_vfs, + total_vfs, + ari_forwarding, + confirmed_ctrl + ); + + let vf_bars = self.parse_sriov_vf_bars(cap_offset)?; + + let mut vf_bdfs = Vec::with_capacity(total_vfs as usize); + for vf_index in 0..total_vfs { + let route_offset = match first_vf_offset.checked_add(vf_stride.saturating_mul(vf_index)) + { + Some(offset) => offset, + None => break, + }; + if let Some(vf_bdf) = self.bdf.add_routing_id_offset(route_offset) { + vf_bdfs.push(vf_bdf); + } else { + break; + } + } + + if vf_bdfs.is_empty() { + return Ok(()); + } + + self.with_access_mut(|access| { + access.set_bits(cap_offset as usize..(cap_offset as usize + 0x40)); + }); + + self.backend.write( + cap_offset + SRIOV_CTRL_OFFSET, + 2, + (sriov_ctrl | SRIOV_CTRL_VF_ENABLE) as usize, + )?; + + let mut sriov_info = SriovInfo::new( + cap_offset, + initial_vfs, + total_vfs, + first_vf_offset, + vf_stride, + vf_device_id, + vf_bars, + vf_bdfs, + ); + sriov_info.enabled_vfs = sriov_info.vf_bdfs.len() as u16; + self.sriov_info = Some(sriov_info); + + Ok(()) + } + + pub fn create_sriov_vf( + &self, + vf_bdf: Bdf, + vf_index: u16, + backend_base: PciConfigAddress, + pci_addr_base: PciConfigAddress, + ) -> Option { + let sriov_info = self.sriov_info.as_ref()?; + let mut vf = Self::endpoint( + vf_bdf, + pci_addr_base, + Arc::new(EndpointHeader::new_with_region(PciConfigMmio::new( + backend_base, + CONFIG_LENTH, + ))), + sriov_info.vf_bars.clone(), + PciMem::default(), + self.config_value.get_class_and_revision_id(), + (sriov_info.vf_device_id, self.config_value.get_id().1), + ); + + vf.set_host_bdf(vf_bdf); + vf.set_parent_bdf(self.bdf); + vf.set_parent_bus(self.bdf.bus()); + vf.set_sriov_vf_info(Some(SriovVfInfo { + pf_bdf: self.bdf, + vf_index, + })); + vf.config_value_init(); + vf.capability_enumerate(); + vf.ext_capability_enumerate(); + vf.build_msi_info(); + + Some(vf) + } + /* false: some bits ro */ pub fn writable(&self, offset: PciConfigAddress, size: usize) -> bool { self.control.bits[offset as usize..offset as usize + size] @@ -586,7 +1188,7 @@ impl VirtualPciConfigSpace { } pub fn get_bararr(&self) -> Bar { - self.bararr + self.bararr.clone() } pub fn get_bar_ref(&self, slot: usize) -> &PciMem { @@ -614,7 +1216,7 @@ impl VirtualPciConfigSpace { } pub fn get_rom(&self) -> PciMem { - self.rom + self.rom.clone() } pub fn get_dev_type(&self) -> VpciDevType { @@ -669,14 +1271,95 @@ impl VirtualPciConfigSpace { _ => {} } } + + pub fn is_my_bar_addr(&self, addr: usize) -> Option { + let mut index = 0; + for i in &self.bararr { + if let Some(res) = i.get_virtual_addr() { + // warn!("get res:{:x}",res); + if res as usize == addr { + return Some(index); + } + } + index += 1; + // if i.get_virtual_addr() == addr as u32{ + // return true; + // } + } + None + } + + pub fn bar_mmio_distribute(&self, bar: usize, mmio_ac: &mut MMIOAccess) -> HvResult { + self.capabilities.handle_bar_read(bar, mmio_ac) + } + + // pub fn get_msix_backend(&self) -> Option>> { + // self.msix_backend.clone() + // } + + pub fn get_msix_entry(&self, data_info: VirtioPCIDataInfo) -> Option { + // let data_info=VirtioPCIDataInfo::from_u64(data_req_id); + let msix_idx = data_info.get_msix_vector_idx(); + let msix_table = self.msix_table.clone()?; + let entry = msix_table.read().get_entry(msix_idx as usize); + entry + } + + pub fn get_pending_msix(&self) -> Option> { + let msix_table = self.msix_table.clone()?; + let res = msix_table.write().get_pending_msix_vector(); + res + } + + pub fn inject_msix_irq(&self, msix_backend: &Arc>) { + // let data_info = VirtioPCIDataInfo::from_u64(data_req_id); + // let msix_entry = match self.get_msix_entry(data_info){ + // Some(x)=>x, + // None=>{ + // warn!("can't find corresponding msix entry!"); + // return; + // } + // }; + // let msix_backend = match self.get_msix_backend() { + // Some(x) => x, + // None => { + // // warn!("There is no msix backend in this device!"); + // return; + // } + // }; + + let msix_entries = match self.get_pending_msix() { + Some(x) => x, + None => { + // warn!("can't find corresponding msix entry!"); + return; + } + }; + for i in msix_entries { + msix_backend + .read() + .activate_irq(self.bdf.requester_id() as usize, &i); + } + } } impl Debug for VirtualPciConfigSpace { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { write!( f, - "\n bdf {:#?}\n base {:#x}\n type {:#?}\n {:#?}\n {:#?}\n {:#?}", - self.bdf, self.base, self.config_type, self.bararr, self.rom, self.capabilities + "\n bdf {:#?}\n parent_bdf {:#?}\n base {:#x}\n type {:#?}\n msi_info {:#x?}\n sriov_info {:#x?}\n sriov_vf_info {:#x?}\n hide_sriov {:#x?}\n {:#?}\n {:#?}\n {:#?}\n {:#?}", + self.bdf, + self.parent_bdf, + self.base, + self.config_type, + self.msi_info, + self.sriov_info, + self.sriov_vf_info, + self.hide_sriov, + self.bararr, + self.rom, + self.capabilities, + self.ext_capabilities ) } } @@ -688,10 +1371,12 @@ impl VirtualPciConfigSpace { dev_type: VpciDevType, config_value: ConfigValue, bararr: Bar, + msix_table: Option>>, ) -> Self { Self { host_bdf: Bdf::default(), parent_bdf: Bdf::default(), + parent_bus: 0, bdf, vbdf: bdf, config_type: HeaderType::Endpoint, @@ -706,13 +1391,16 @@ impl VirtualPciConfigSpace { bararr, rom: PciMem::default(), capabilities: PciCapabilityList::new(), + ext_capabilities: PciExtCapabilityList::new(), dev_type, + msi_info: None, + sriov_info: None, + sriov_vf_info: None, + hide_sriov: None, + msix_table, } } - pub fn virt_dev(bdf: Bdf, base: PciConfigAddress, dev_type: VpciDevType) -> Self { - crate::pci::vpci_dev::virt_dev_init(bdf, base, dev_type) - } pub fn endpoint( bdf: Bdf, base: PciConfigAddress, @@ -725,6 +1413,7 @@ impl VirtualPciConfigSpace { Self { host_bdf: Bdf::default(), parent_bdf: Bdf::default(), + parent_bus: 0, bdf, vbdf: Bdf::default(), config_type: HeaderType::Endpoint, @@ -736,7 +1425,13 @@ impl VirtualPciConfigSpace { bararr, rom, capabilities: PciCapabilityList::new(), + ext_capabilities: PciExtCapabilityList::new(), dev_type: VpciDevType::Physical, + msi_info: None, + sriov_info: None, + sriov_vf_info: None, + hide_sriov: None, + msix_table: None, } } @@ -752,6 +1447,7 @@ impl VirtualPciConfigSpace { Self { host_bdf: Bdf::default(), parent_bdf: Bdf::default(), + parent_bus: 0, bdf, vbdf: Bdf::default(), config_type: HeaderType::PciBridge, @@ -763,10 +1459,20 @@ impl VirtualPciConfigSpace { bararr, rom, capabilities: PciCapabilityList::new(), + ext_capabilities: PciExtCapabilityList::new(), dev_type: VpciDevType::Physical, + msi_info: None, + sriov_info: None, + sriov_vf_info: None, + hide_sriov: None, + msix_table: None, } } + pub fn set_backend(&mut self, backend: Arc) { + self.backend = backend + } + pub fn unknown( bdf: Bdf, base: PciConfigAddress, @@ -776,6 +1482,7 @@ impl VirtualPciConfigSpace { Self { host_bdf: Bdf::default(), parent_bdf: Bdf::default(), + parent_bus: 0, bdf, vbdf: Bdf::default(), config_type: HeaderType::Endpoint, @@ -788,7 +1495,13 @@ impl VirtualPciConfigSpace { bararr: Bar::default(), rom: PciMem::default(), capabilities: PciCapabilityList::new(), + ext_capabilities: PciExtCapabilityList::new(), dev_type: VpciDevType::Physical, + msi_info: None, + sriov_info: None, + sriov_vf_info: None, + hide_sriov: None, + msix_table: None, } } @@ -801,6 +1514,7 @@ impl VirtualPciConfigSpace { Self { host_bdf: bdf, parent_bdf: bdf, + parent_bus: bdf.bus(), bdf: bdf, vbdf: bdf, config_type: HeaderType::Endpoint, @@ -812,7 +1526,13 @@ impl VirtualPciConfigSpace { bararr: Bar::default(), rom: PciMem::default(), capabilities: PciCapabilityList::new(), + ext_capabilities: PciExtCapabilityList::new(), dev_type: VpciDevType::Physical, + msi_info: None, + sriov_info: None, + sriov_vf_info: None, + hide_sriov: None, + msix_table: None, } } @@ -828,6 +1548,10 @@ impl VirtualPciConfigSpace { self.parent_bdf = parent_bdf; } + pub fn set_parent_bus(&mut self, parent_bus: u8) { + self.parent_bus = parent_bus; + } + pub fn get_bdf(&self) -> Bdf { self.bdf } @@ -836,18 +1560,157 @@ impl VirtualPciConfigSpace { self.vbdf } + pub fn get_parent_bdf(&self) -> Bdf { + self.parent_bdf + } + + pub fn get_parent_bus(&self) -> u8 { + self.parent_bus + } + pub fn get_config_type(&self) -> HeaderType { self.config_type } - pub fn set_vbdf(&mut self, vbdf: Bdf) { + pub fn set_vbdf(&mut self, vbdf: Bdf, domain_bus_range_end: u8) { + self.vbdf = vbdf; + if self.config_type == HeaderType::PciBridge { + self.init_bridge_bus_reg(domain_bus_range_end, None); + } + } + + pub fn set_vbdf_with_bus_map( + &mut self, + vbdf: Bdf, + domain_bus_range_end: u8, + bus_map: &[HvPciDevConfig], + ) { self.vbdf = vbdf; + if self.config_type == HeaderType::PciBridge { + self.init_bridge_bus_reg(domain_bus_range_end, Some(bus_map)); + } + } + + fn init_bridge_bus_reg( + &mut self, + domain_bus_range_end: u8, + bus_map: Option<&[HvPciDevConfig]>, + ) { + #[cfg(not(no_pcie_bar_realloc))] + let _ = bus_map; + + #[cfg(no_pcie_bar_realloc)] + if self.dev_type == VpciDevType::Physical { + if let Some(firmware_reg) = self.config_value.get_firmware_bridge_bus_reg() { + let value = if let Some(bus_map) = bus_map { + translate_bridge_bus_reg( + firmware_reg, + self.bdf, + self.vbdf, + bus_map, + domain_bus_range_end, + ) + } else if self.bdf.bus() == self.vbdf.bus() { + firmware_reg + } else { + default_bridge_bus_reg(self.vbdf.bus(), domain_bus_range_end) + }; + self.config_value.set_bridge_bus_reg(value); + return; + } + } + + self.config_value.set_bridge_bus_reg(default_bridge_bus_reg( + self.vbdf.bus(), + domain_bus_range_end, + )); } pub fn get_base(&self) -> PciConfigAddress { self.base } + pub fn get_msi_count(&self) -> u32 { + self.msi_info + .as_ref() + .map(|info| info.msi_count) + .unwrap_or(0) + } + + /// Build MSI/MSIX info structure based on device capabilities + pub fn build_msi_info(&mut self) { + let mut msi_count = 0u32; + let mut msix_count = 0u32; + let mut msix_bar_id = 0u8; + let mut msix_offset = 0u64; + let mut has_msix = false; + + // Check if the device has MSI or MSIX capability and calculate both + for (_offset, cap) in self.capabilities.cap_in_config_ref().iter() { + match cap.get_type() { + CapabilityType::Msi => { + // For MSI: read offset+2, Message Control bits 3:1 contain MMC + // Supported messages = 2^MMC + if let Ok(val) = cap.with_region(|region| region.read(0x02, 2)) { + let mmc = (val & 0x0E) >> 1; // bits 3:1 + msi_count = 1u32 << mmc; + } + } + CapabilityType::MsiX => { + // For MSIX: read offset+2, bits 10-0 contain table size + // Supported messages = table_size + 1 + if let Ok(val) = cap.with_region(|region| region.read(0x02, 2)) { + let table_size = (val & 0x07FF) as u32; // bits 10-0 + msix_count = table_size + 1; + } + + // Extract MSIX table location (offset+4) + // Bits 2-0: BAR ID (0-5), Bits 31-3: table offset + if let Ok(table_info) = cap.with_region(|region| region.read(0x04, 4)) { + msix_bar_id = (table_info & 0x07) as u8; + msix_offset = ((table_info >> 3) as u64) << 3; // multiply by 8 since offset is in 8-byte increments + has_msix = true; + } + } + _ => {} + } + } + + // Create MsiInfo if device has MSI or MSIX capability + let interrupt_count = core::cmp::max(msi_count, msix_count); + if interrupt_count > 0 { + let mut msi_info = MsiInfo::new(interrupt_count); + + if has_msix { + // Read the BAR's physical address + let bar_paddr = self.bararr[msix_bar_id as usize].get_value64() & !0xf; + msi_info.set_msix_info(msix_bar_id, msix_offset, msix_count, bar_paddr); + } + + self.msi_info = Some(msi_info); + } + } + + pub fn get_msi_info(&self) -> Option<&MsiInfo> { + self.msi_info.as_ref() + } + + pub fn get_sriov_info(&self) -> Option<&SriovInfo> { + self.sriov_info.as_ref() + } + + pub fn get_sriov_vf_info(&self) -> Option { + self.sriov_vf_info + } + + pub fn set_sriov_info(&mut self, sriov_info: Option) { + self.sriov_info = sriov_info; + } + + pub fn set_sriov_vf_info(&mut self, sriov_vf_info: Option) { + self.sriov_vf_info = sriov_vf_info; + } + /* now the space_init just with bar * Note: space field removed, bar values are cached in config_value.bar_value */ @@ -857,6 +1720,28 @@ impl VirtualPciConfigSpace { let bar_value = self.bararr[slot].get_value(); self.config_value.set_bar_value(slot, bar_value as u32); } + + // With BAR reallocation disabled, enumeration follows the topology + // already programmed by firmware. Cache the bridge bus register here + // so every backend can later preserve or translate the same topology. + #[cfg(no_pcie_bar_realloc)] + if self.config_type == HeaderType::PciBridge && self.dev_type == VpciDevType::Physical { + match self.backend.read(0x18, 4) { + Ok(value) => { + let value = value as u32; + self.config_value.set_firmware_bridge_bus_reg(value); + self.config_value.set_bridge_bus_reg(value); + } + Err(_) => warn!( + "PCI bridge {:#?}: failed to preserve firmware bus numbers, using virtual defaults", + self.bdf + ), + } + } + } + + pub fn set_msix_table(&mut self, msix_table: Arc>) { + self.msix_table = Some(msix_table) } } @@ -1071,7 +1956,7 @@ impl PciIterator { } let mut ep = EndpointHeader::new_with_region(region); - let rom = Self::rom_init(&mut ep); + let rom = Self::rom_init(&mut self.allocator, &mut ep); let bararr = Self::bar_mem_init(ep.bar_limit().into(), &mut self.allocator, &mut ep); @@ -1090,14 +1975,23 @@ impl PciIterator { ); let _ = node.capability_enumerate(); + node.ext_capability_enumerate(); + #[cfg(sriov)] + { + let upstream = self.stack.last().filter(|b| !b.mmio.is_placeholder()); + let _ = node.build_sriov_info(upstream); + } + // Build MSI/MSIX info once during device discovery + node.build_msi_info(); + node.config_value_init(); + node.set_vbdf(bdf, self.bus_range.end as u8); Some(node) } HeaderType::PciBridge => { // For bridge: don't push host_bridge, it will be handled in Iterator::next() - warn!("bridge"); let mut bridge = PciBridgeHeader::new_with_region(region); - let rom = Self::rom_init(&mut bridge); + let rom = Self::rom_init(&mut self.allocator, &mut bridge); let bararr = Self::bar_mem_init(bridge.bar_limit().into(), &mut self.allocator, &mut bridge); @@ -1114,27 +2008,56 @@ impl PciIterator { ); let _ = node.capability_enumerate(); + node.ext_capability_enumerate(); + #[cfg(sriov)] + { + let upstream = self.stack.last().filter(|b| !b.mmio.is_placeholder()); + let _ = node.build_sriov_info(upstream); + } + // Build MSI/MSIX info once during device discovery + node.build_msi_info(); + node.config_value_init(); + node.set_vbdf(bdf, self.bus_range.end as u8); Some(node) } _ => { warn!("unknown type"); let pci_header = Arc::new(pci_header); - Some(VirtualPciConfigSpace::unknown( + let mut node = VirtualPciConfigSpace::unknown( bdf, pci_addr_base, pci_header, (device_id, vender_id), - )) + ); + node.config_value_init(); + Some(node) } } } - fn rom_init(dev: &mut D) -> PciMem { + fn rom_init( + allocator: &mut Option, + dev: &mut D, + ) -> PciMem { let mut rom = dev.parse_rom(); if rom.get_type() == PciMemType::Rom { - rom.set_value(rom.get_value() as u64); - rom.set_virtual_value(rom.get_value() as u64); + if let Some(a) = allocator { + let value = a.alloc_memory32(rom.get_size() as u64).unwrap(); + rom.set_value(value); + rom.set_virtual_value(value); + // Do not enable ROM yet, write 0 (ROM disabled) + // VM will enable it later by writing address + enable bit + // info!( + // "allocated rom address: {:#x}, write 0 (disabled) to hardware", + // value + // ); + let _ = dev.write(dev.rom_offset(), 4, 0 as _); + } else { + let value = rom.get_value() as u64; + rom.set_value(value); + rom.set_virtual_value(value); + } } rom } @@ -1146,7 +2069,7 @@ impl PciIterator { ) -> Bar { let mut bararr = dev.parse_bar(); - info!("{:#?}", bararr); + // info!("{:#?}", bararr); if let Some(a) = allocator { dev.update_command(|mut cmd| { @@ -1227,7 +2150,7 @@ impl PciIterator { fn next_device_not_ok(&mut self) -> bool { if let Some(parent) = self.stack.last_mut() { // only one child and skip this bus - if parent.has_secondary_link { + if parent.has_only_one_child { parent.device = MAX_DEVICE; } @@ -1292,7 +2215,6 @@ impl Iterator for PciIterator { fn next(&mut self) -> Option { while !self.is_finish { if let Some(mut node) = self.get_node() { - node.config_value_init(); let bus_begin = self.bus_range.start as u8; let domain = self.domain; /* @@ -1312,9 +2234,10 @@ impl Iterator for PciIterator { let parent = self.stack.last().unwrap(); // Safe because we just ensured it exists let host_bdf = Bdf::new(domain, bus_begin, 0, 0); let parent_bdf = Bdf::new(domain, parent.bus, parent.device, 0); - let parent_bus = parent.primary_bus; + let _parent_bus = parent.primary_bus; node.set_host_bdf(host_bdf); node.set_parent_bdf(parent_bdf); + node.set_parent_bus(_parent_bus); self.next(match node.config_value.get_class().0 { // class code 0x6 is bridge and class.1 0x0 is host bridge 0x6 if node.config_value.get_class().1 == 0x4 => { @@ -1323,14 +2246,9 @@ impl Iterator for PciIterator { // (UEFI/BIOS) may skip bus numbers for subordinate bus reservation, // causing calculated bus numbers to diverge from actual hardware // bus assignments — making devices behind bridges invisible. - #[cfg(feature = "no_pcie_bar_realloc")] + #[cfg(no_pcie_bar_realloc)] let next_bus = { - let bridge_base = node.get_base(); - let bus_reg = unsafe { - let ptr = PciConfigMmio::new(bridge_base, CONFIG_LENTH) - .access::(0x18); - ptr.read_volatile() - }; + let bus_reg = node.config_value.get_bridge_bus_reg(); let fw_secondary = ((bus_reg >> 8) & 0xFF) as u8; let fw_subordinate = ((bus_reg >> 16) & 0xFF) as u8; info!( @@ -1358,19 +2276,12 @@ impl Iterator for PciIterator { parent.subordinate_bus + 1 } }; - #[cfg(not(feature = "no_pcie_bar_realloc"))] + #[cfg(not(no_pcie_bar_realloc))] let next_bus = parent.subordinate_bus + 1; - let bdf = Bdf::new(domain, next_bus, 0, 0); - // Use the current bridge's own bus as the immediate parent bus for - // CFG address computation. For multi-level bridges (especially on - // DWC), using parent.primary_bus (the upstream of the *parent*) - // would select the wrong CFG0/CFG1 path and fail to reach devices - // behind deeper bridges. - let immediate_parent_bus = parent.bus; Some(self.get_bridge().next_bridge( - self.address(immediate_parent_bus, bdf), - node.has_secondary_link(), + node.get_base(), + node.has_only_one_child(), self.is_mulitple_function, self.function, next_bus, @@ -1396,7 +2307,7 @@ pub struct Bridge { secondary_bus: u8, primary_bus: u8, mmio: PciConfigMmio, - has_secondary_link: bool, + has_only_one_child: bool, is_mulitple_function: bool, } @@ -1412,7 +2323,7 @@ impl Bridge { secondary_bus: 0, primary_bus: 0, mmio: PciConfigMmio::new(0, 0), // Dummy mmio for placeholder - has_secondary_link: false, + has_only_one_child: false, is_mulitple_function: false, } } @@ -1431,7 +2342,7 @@ impl Bridge { secondary_bus: bus_begin, primary_bus: bus_begin, mmio: PciConfigMmio::new(address, CONFIG_LENTH), - has_secondary_link: false, + has_only_one_child: false, is_mulitple_function, } } @@ -1439,7 +2350,7 @@ impl Bridge { pub fn next_bridge( &self, address: PciConfigAddress, - has_secondary_link: bool, + has_only_one_child: bool, is_mulitple_function: bool, function: u8, target_bus: u8, @@ -1453,11 +2364,59 @@ impl Bridge { secondary_bus: target_bus, primary_bus: self.bus, mmio, - has_secondary_link, + has_only_one_child, is_mulitple_function, } } + fn find_pcie_cap_offset(&self) -> Option { + if self.mmio.is_placeholder() { + return None; + } + + let mut offset = (self.mmio.read_u8(0x34).ok()? as PciConfigAddress) & !0x3; + for _ in 0..48 { + if offset < 0x40 || offset >= CONFIG_LENTH { + return None; + } + + let cap_id = self.mmio.read_u8(offset).ok()? as PciConfigAddress; + if cap_id == CapabilityType::PciExpress.to_id() { + return Some(offset); + } + + let next = (self.mmio.read_u8(offset + 1).ok()? as PciConfigAddress) & !0x3; + if next == 0 || next == offset { + return None; + } + offset = next; + } + + None + } + + pub fn enable_ari_forwarding(&self) -> HvResult { + let Some(pcie_cap_offset) = self.find_pcie_cap_offset() else { + return Ok(false); + }; + + let dev_cap2 = self + .mmio + .read_u32(pcie_cap_offset + PCIE_DEVICE_CAPABILITIES_2_OFFSET)?; + if (dev_cap2 & PCIE_ARI_FORWARDING) == 0 { + return Ok(false); + } + + let dev_ctrl2_offset = pcie_cap_offset + PCIE_DEVICE_CONTROL_2_OFFSET; + let dev_ctrl2 = self.mmio.read_u16(dev_ctrl2_offset)?; + let ari_ctrl2 = dev_ctrl2 | (PCIE_ARI_FORWARDING as u16); + if ari_ctrl2 != dev_ctrl2 { + self.mmio.write_u16(dev_ctrl2_offset, ari_ctrl2)?; + } + + Ok(true) + } + pub fn update_bridge_bus(&mut self) { // Skip update for placeholder bridges (they don't have real mmio) if self.mmio.is_placeholder() { @@ -1465,10 +2424,10 @@ impl Bridge { } // When no_pcie_bar_realloc is enabled, firmware already assigned correct bus // numbers — don't overwrite them. - #[cfg(feature = "no_pcie_bar_realloc")] + #[cfg(no_pcie_bar_realloc)] return; - #[cfg(not(feature = "no_pcie_bar_realloc"))] + #[cfg(not(no_pcie_bar_realloc))] { // we need to update the bridge bus number if we want linux not to update bus number unsafe { @@ -1482,8 +2441,8 @@ impl Bridge { } } - pub fn set_has_secondary_link(&mut self, value: bool) { - self.has_secondary_link = value; + pub fn set_has_only_one_child(&mut self, value: bool) { + self.has_only_one_child = value; } } @@ -1523,13 +2482,84 @@ impl RootComplex { ) -> PciIterator { self.__enumerate(range, domain, bar_alloc) } + + pub fn create_sriov_vfs(&self, pf: &VirtualPciConfigSpace) -> Vec { + let Some(sriov_info) = pf.get_sriov_info() else { + return Vec::new(); + }; + + if sriov_info.enabled_vfs == 0 { + return Vec::new(); + } + + sriov_info + .vf_bdfs + .iter() + .copied() + .take(sriov_info.enabled_vfs as usize) + .enumerate() + .filter_map(|(vf_index, vf_bdf)| { + let backend_base = self + .accessor + .get_physical_address(vf_bdf, 0, pf.get_bdf().bus()) + .unwrap_or(0); + let pci_addr_base = self.accessor.get_pci_addr_base(vf_bdf).unwrap_or(0); + pf.create_sriov_vf(vf_bdf, vf_index as u16, backend_base, pci_addr_base) + }) + .collect() + } +} + +#[derive(Debug)] +/// MSI information for a specific domain in a VM +/// Tracks the MSI interrupts needed for this domain and the hardware base interrupt bit +pub struct DomainMsiInfo { + /// Total number of MSI interrupts needed for all devices in this domain + pub msi_count: u32, + /// Hardware MSI base bit index (allocated from domain allocator) + pub hwirq_bit: u32, + /// Virtual doorbell address set by the VM (PCIE_MSI_ADDR_LO + PCIE_MSI_ADDR_HI) + pub vm_doorbell_addr: u64, +} + +impl DomainMsiInfo { + pub fn new(msi_count: u32, hwirq_bit: u32) -> Self { + Self { + msi_count, + hwirq_bit, + vm_doorbell_addr: 0, + } + } + + /// Set the virtual doorbell address (from VM) + pub fn set_vm_doorbell(&mut self, addr: u64) { + self.vm_doorbell_addr = addr; + } + + /// Get the virtual doorbell address + pub fn get_vm_doorbell(&self) -> u64 { + self.vm_doorbell_addr + } + + /// Get MSI mask based on msi_count + /// Returns a mask with msi_count bits set (0-based, e.g. msi_count=4 -> mask=0xf) + pub fn get_msi_mask(&self) -> u32 { + if self.msi_count >= 32 { + 0xffffffff + } else { + (1u32 << self.msi_count) - 1 + } + } } #[derive(Debug)] pub struct VirtualRootComplex { devs: BTreeMap, base_to_bdf: BTreeMap, + // MSI interrupt information per domain (domain_id -> DomainMsiInfo) + domain_msi_info: BTreeMap, accessor: Option>, + msix_backend: Option>>, } impl VirtualRootComplex { @@ -1537,7 +2567,9 @@ impl VirtualRootComplex { Self { devs: BTreeMap::new(), base_to_bdf: BTreeMap::new(), + domain_msi_info: BTreeMap::new(), accessor: None, + msix_backend: None, } } @@ -1545,15 +2577,23 @@ impl VirtualRootComplex { self.accessor = Some(accessor); } + pub fn accessor(&self) -> Option<&Arc> { + self.accessor.as_ref() + } + pub fn insert( &mut self, bdf: Bdf, dev: VirtualPciConfigSpace, ) -> Option { - let parent_bus = dev.parent_bdf.bus(); - let offset = 0; + let _parent_bus = dev.parent_bdf.bus(); + let _offset = 0; let base = if let Some(accessor) = &self.accessor { - match accessor.get_physical_address(bdf, offset, parent_bus) { + #[cfg(dwc_pcie)] + let addr = accessor.get_pci_addr_base(bdf); + #[cfg(not(dwc_pcie))] + let addr = accessor.get_physical_address(bdf, _offset, _parent_bus); + match addr { Ok(addr) => addr, Err(_) => { warn!("can not get physical address for device {:#?}(vbdf), reset device base same to hardware", bdf); @@ -1568,12 +2608,73 @@ impl VirtualRootComplex { self.base_to_bdf.insert(base, bdf); self.devs .insert(bdf, ArcRwLockVirtualPciConfigSpace::new(dev)) + + // let base = dev.get_base(); + // let host_bdf = dev.get_bdf(); + // let vbdf = dev.get_vbdf(); + + // #[cfg(dwc_pcie)] + // let key = { + // let bus = bdf.bus() as PciConfigAddress; + // let device = bdf.device() as PciConfigAddress; + // let function = bdf.function() as PciConfigAddress; + // let pci_addr = (bus << 24) + (device << 19) + (function << 16); + // if bus != 0 { + // pci_addr + // } else { + // base + // } + // }; + + // #[cfg(not(dwc_pcie))] + // let key = base; + + // #[cfg(dwc_pcie)] + // { + // let bus = bdf.bus() as PciConfigAddress; + // let device = bdf.device() as PciConfigAddress; + // let function = bdf.function() as PciConfigAddress; + // let pci_addr = (bus << 24) + (device << 19) + (function << 16); + // info!( + // "vpci insert: base_to_bdf[{:#x}] = key_bdf {:#?}, source {}, base {:#x}, pci_addr {:#x}, dev_host_bdf {:#?}, dev_vbdf {:#?}, remapped {}", + // key, + // bdf, + // if key == pci_addr { "pci_addr" } else { "base" }, + // base, + // pci_addr, + // host_bdf, + // vbdf, + // host_bdf != vbdf + // ); + // } + + // #[cfg(not(dwc_pcie))] + // info!( + // "vpci insert: base_to_bdf[{:#x}] = key_bdf {:#?}, source base, base {:#x}, dev_host_bdf {:#?}, dev_vbdf {:#?}, remapped {}", + // key, + // bdf, + // base, + // host_bdf, + // vbdf, + // host_bdf != vbdf + // ); + // self.base_to_bdf.insert(key, bdf); + // self.devs + // .insert(bdf, ArcRwLockVirtualPciConfigSpace::new(dev)) } pub fn devs(&mut self) -> &mut BTreeMap { &mut self.devs } + pub fn devs_ref(&self) -> &BTreeMap { + &self.devs + } + + pub fn read_devs(&self) -> &BTreeMap { + &self.devs + } + pub fn get(&self, bdf: &Bdf) -> Option<&ArcRwLockVirtualPciConfigSpace> { self.devs.get(bdf) } @@ -1590,6 +2691,42 @@ impl VirtualRootComplex { let bdf = self.base_to_bdf.get(&base).copied()?; self.devs.get(&bdf).cloned() } + + /// Add MSI count for a specific domain with allocated hardware interrupt bit + pub fn add_msi_count_for_domain(&mut self, domain: u8, msi_count: u32, hwirq_bit: u32) { + let vm_doorbell = self + .domain_msi_info + .get(&domain) + .map(|info| info.get_vm_doorbell()) + .unwrap_or(0); + + let mut info = DomainMsiInfo::new(msi_count, hwirq_bit); + info.set_vm_doorbell(vm_doorbell); + self.domain_msi_info.insert(domain, info); + } + + /// Get MSI info for a specific domain + pub fn get_domain_msi_info(&self, domain: u8) -> Option<&DomainMsiInfo> { + self.domain_msi_info.get(&domain) + } + + /// Get reference to domain MSI info map + pub fn domain_msi_info(&self) -> &BTreeMap { + &self.domain_msi_info + } + + /// Get mutable reference to domain MSI info map + pub fn domain_msi_info_mut(&mut self) -> &mut BTreeMap { + &mut self.domain_msi_info + } + + pub fn get_msix_backend(&self) -> Option>> { + self.msix_backend.clone() + } + + pub fn set_msix_backend(&mut self, backend: Option>>) { + self.msix_backend = backend + } } #[derive(Debug)] @@ -1756,10 +2893,248 @@ impl CapabilityType { } } +// ---- PCIe Extended Capabilities (config space 0x100–0xFFF) ---- + +/// PCIe Extended Capability IDs (PCI-SIG ECN). +#[derive(Clone, Copy, PartialEq, Eq)] +pub enum ExtCapabilityType { + /// Advanced Error Reporting, ID = 0x0001 + AdvancedErrorReporting, + /// Virtual Channel, ID = 0x0002 + VirtualChannel, + /// Device Serial Number, ID = 0x0003 + DeviceSerialNumber, + /// Power Budgeting, ID = 0x0004 + PowerBudgeting, + /// Root Complex Link Declaration, ID = 0x0005 + RootComplexLinkDeclaration, + /// Root Complex Internal Link Control, ID = 0x0006 + RootComplexInternalLinkControl, + /// Root Complex Event Collector Endpoint Association, ID = 0x0007 + RootComplexEventCollector, + /// Multi-Function Virtual Channel, ID = 0x0008 + MultiFunctionVirtualChannel, + /// VC in Multi-Function Device, ID = 0x0009 + VirtualChannelMFVC, + /// Root Complex Register Block, ID = 0x000A + RootComplexRegisterBlock, + /// Vendor-Specific Extended Capability, ID = 0x000B + VendorSpecific, + /// Configuration Access Correlation, ID = 0x000C + ConfigurationAccessCorrelation, + /// Access Control Services, ID = 0x000D + AccessControlServices, + /// Alternative Routing-ID Interpretation, ID = 0x000E + AlternativeRoutingId, + /// Address Translation Services, ID = 0x000F + AddressTranslationServices, + /// Single Root I/O Virtualization (SR-IOV), ID = 0x0010 + SingleRootIov, + /// Multi-Root I/O Virtualization (MR-IOV), ID = 0x0011 + MultiRootIov, + /// Multicast, ID = 0x0012 + Multicast, + /// Page Request Interface, ID = 0x0013 + PageRequestInterface, + /// Resizable BAR, ID = 0x0015 + ResizableBar, + /// Dynamic Power Allocation, ID = 0x0016 + DynamicPowerAllocation, + /// TPH Requester, ID = 0x0017 + TphRequester, + /// Latency Tolerance Reporting, ID = 0x0018 + LatencyToleranceReporting, + /// Secondary PCI Express, ID = 0x0019 + SecondaryPciExpress, + /// Protocol Multiplexing, ID = 0x001A + ProtocolMultiplexing, + /// Process Address Space ID (PASID), ID = 0x001B + ProcessAddressSpaceId, + /// LN Requester, ID = 0x001C + LnRequester, + /// Downstream Port Containment, ID = 0x001D + DownstreamPortContainment, + /// L1 PM Substates, ID = 0x001E + L1PmSubstates, + /// Precision Time Measurement, ID = 0x001F + PrecisionTimeMeasurement, + /// Designated Vendor-Specific, ID = 0x0023 + DesignatedVendorSpecific, + /// VF Resizable BAR, ID = 0x0024 + VfResizableBar, + /// Data Link Feature, ID = 0x0025 + DataLinkFeature, + /// Physical Layer 16.0 GT/s, ID = 0x0026 + PhysicalLayer16Gts, + /// Lane Margining at the Receiver, ID = 0x0027 + LaneMargining, + /// Physical Layer 32.0 GT/s, ID = 0x002A + PhysicalLayer32Gts, + /// Unknown or reserved extended capability + Unknown(u16), +} + +impl ExtCapabilityType { + pub fn from_id(id: u16) -> Self { + match id { + 0x0001 => ExtCapabilityType::AdvancedErrorReporting, + 0x0002 => ExtCapabilityType::VirtualChannel, + 0x0003 => ExtCapabilityType::DeviceSerialNumber, + 0x0004 => ExtCapabilityType::PowerBudgeting, + 0x0005 => ExtCapabilityType::RootComplexLinkDeclaration, + 0x0006 => ExtCapabilityType::RootComplexInternalLinkControl, + 0x0007 => ExtCapabilityType::RootComplexEventCollector, + 0x0008 => ExtCapabilityType::MultiFunctionVirtualChannel, + 0x0009 => ExtCapabilityType::VirtualChannelMFVC, + 0x000A => ExtCapabilityType::RootComplexRegisterBlock, + 0x000B => ExtCapabilityType::VendorSpecific, + 0x000C => ExtCapabilityType::ConfigurationAccessCorrelation, + 0x000D => ExtCapabilityType::AccessControlServices, + 0x000E => ExtCapabilityType::AlternativeRoutingId, + 0x000F => ExtCapabilityType::AddressTranslationServices, + 0x0010 => ExtCapabilityType::SingleRootIov, + 0x0011 => ExtCapabilityType::MultiRootIov, + 0x0012 => ExtCapabilityType::Multicast, + 0x0013 => ExtCapabilityType::PageRequestInterface, + 0x0015 => ExtCapabilityType::ResizableBar, + 0x0016 => ExtCapabilityType::DynamicPowerAllocation, + 0x0017 => ExtCapabilityType::TphRequester, + 0x0018 => ExtCapabilityType::LatencyToleranceReporting, + 0x0019 => ExtCapabilityType::SecondaryPciExpress, + 0x001A => ExtCapabilityType::ProtocolMultiplexing, + 0x001B => ExtCapabilityType::ProcessAddressSpaceId, + 0x001C => ExtCapabilityType::LnRequester, + 0x001D => ExtCapabilityType::DownstreamPortContainment, + 0x001E => ExtCapabilityType::L1PmSubstates, + 0x001F => ExtCapabilityType::PrecisionTimeMeasurement, + 0x0023 => ExtCapabilityType::DesignatedVendorSpecific, + 0x0024 => ExtCapabilityType::VfResizableBar, + 0x0025 => ExtCapabilityType::DataLinkFeature, + 0x0026 => ExtCapabilityType::PhysicalLayer16Gts, + 0x0027 => ExtCapabilityType::LaneMargining, + 0x002A => ExtCapabilityType::PhysicalLayer32Gts, + other => ExtCapabilityType::Unknown(other), + } + } + + pub fn to_id(&self) -> u16 { + match self { + ExtCapabilityType::AdvancedErrorReporting => 0x0001, + ExtCapabilityType::VirtualChannel => 0x0002, + ExtCapabilityType::DeviceSerialNumber => 0x0003, + ExtCapabilityType::PowerBudgeting => 0x0004, + ExtCapabilityType::RootComplexLinkDeclaration => 0x0005, + ExtCapabilityType::RootComplexInternalLinkControl => 0x0006, + ExtCapabilityType::RootComplexEventCollector => 0x0007, + ExtCapabilityType::MultiFunctionVirtualChannel => 0x0008, + ExtCapabilityType::VirtualChannelMFVC => 0x0009, + ExtCapabilityType::RootComplexRegisterBlock => 0x000A, + ExtCapabilityType::VendorSpecific => 0x000B, + ExtCapabilityType::ConfigurationAccessCorrelation => 0x000C, + ExtCapabilityType::AccessControlServices => 0x000D, + ExtCapabilityType::AlternativeRoutingId => 0x000E, + ExtCapabilityType::AddressTranslationServices => 0x000F, + ExtCapabilityType::SingleRootIov => 0x0010, + ExtCapabilityType::MultiRootIov => 0x0011, + ExtCapabilityType::Multicast => 0x0012, + ExtCapabilityType::PageRequestInterface => 0x0013, + ExtCapabilityType::ResizableBar => 0x0015, + ExtCapabilityType::DynamicPowerAllocation => 0x0016, + ExtCapabilityType::TphRequester => 0x0017, + ExtCapabilityType::LatencyToleranceReporting => 0x0018, + ExtCapabilityType::SecondaryPciExpress => 0x0019, + ExtCapabilityType::ProtocolMultiplexing => 0x001A, + ExtCapabilityType::ProcessAddressSpaceId => 0x001B, + ExtCapabilityType::LnRequester => 0x001C, + ExtCapabilityType::DownstreamPortContainment => 0x001D, + ExtCapabilityType::L1PmSubstates => 0x001E, + ExtCapabilityType::PrecisionTimeMeasurement => 0x001F, + ExtCapabilityType::DesignatedVendorSpecific => 0x0023, + ExtCapabilityType::VfResizableBar => 0x0024, + ExtCapabilityType::DataLinkFeature => 0x0025, + ExtCapabilityType::PhysicalLayer16Gts => 0x0026, + ExtCapabilityType::LaneMargining => 0x0027, + ExtCapabilityType::PhysicalLayer32Gts => 0x002A, + ExtCapabilityType::Unknown(id) => *id, + } + } +} + +impl core::fmt::Debug for ExtCapabilityType { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + match self { + ExtCapabilityType::AdvancedErrorReporting => { + write!(f, "AdvancedErrorReporting(0x0001)") + } + ExtCapabilityType::VirtualChannel => write!(f, "VirtualChannel(0x0002)"), + ExtCapabilityType::DeviceSerialNumber => write!(f, "DeviceSerialNumber(0x0003)"), + ExtCapabilityType::PowerBudgeting => write!(f, "PowerBudgeting(0x0004)"), + ExtCapabilityType::RootComplexLinkDeclaration => { + write!(f, "RootComplexLinkDeclaration(0x0005)") + } + ExtCapabilityType::RootComplexInternalLinkControl => { + write!(f, "RootComplexInternalLinkControl(0x0006)") + } + ExtCapabilityType::RootComplexEventCollector => { + write!(f, "RootComplexEventCollector(0x0007)") + } + ExtCapabilityType::MultiFunctionVirtualChannel => { + write!(f, "MultiFunctionVirtualChannel(0x0008)") + } + ExtCapabilityType::VirtualChannelMFVC => write!(f, "VirtualChannelMFVC(0x0009)"), + ExtCapabilityType::RootComplexRegisterBlock => { + write!(f, "RootComplexRegisterBlock(0x000A)") + } + ExtCapabilityType::VendorSpecific => write!(f, "VendorSpecific(0x000B)"), + ExtCapabilityType::ConfigurationAccessCorrelation => { + write!(f, "ConfigurationAccessCorrelation(0x000C)") + } + ExtCapabilityType::AccessControlServices => write!(f, "AccessControlServices(0x000D)"), + ExtCapabilityType::AlternativeRoutingId => write!(f, "AlternativeRoutingId(0x000E)"), + ExtCapabilityType::AddressTranslationServices => { + write!(f, "AddressTranslationServices(0x000F)") + } + ExtCapabilityType::SingleRootIov => write!(f, "SingleRootIov(SR-IOV)(0x0010)"), + ExtCapabilityType::MultiRootIov => write!(f, "MultiRootIov(MR-IOV)(0x0011)"), + ExtCapabilityType::Multicast => write!(f, "Multicast(0x0012)"), + ExtCapabilityType::PageRequestInterface => write!(f, "PageRequestInterface(0x0013)"), + ExtCapabilityType::ResizableBar => write!(f, "ResizableBar(0x0015)"), + ExtCapabilityType::DynamicPowerAllocation => { + write!(f, "DynamicPowerAllocation(0x0016)") + } + ExtCapabilityType::TphRequester => write!(f, "TphRequester(0x0017)"), + ExtCapabilityType::LatencyToleranceReporting => { + write!(f, "LatencyToleranceReporting(0x0018)") + } + ExtCapabilityType::SecondaryPciExpress => write!(f, "SecondaryPciExpress(0x0019)"), + ExtCapabilityType::ProtocolMultiplexing => write!(f, "ProtocolMultiplexing(0x001A)"), + ExtCapabilityType::ProcessAddressSpaceId => write!(f, "ProcessAddressSpaceId(0x001B)"), + ExtCapabilityType::LnRequester => write!(f, "LnRequester(0x001C)"), + ExtCapabilityType::DownstreamPortContainment => { + write!(f, "DownstreamPortContainment(0x001D)") + } + ExtCapabilityType::L1PmSubstates => write!(f, "L1PmSubstates(0x001E)"), + ExtCapabilityType::PrecisionTimeMeasurement => { + write!(f, "PrecisionTimeMeasurement(0x001F)") + } + ExtCapabilityType::DesignatedVendorSpecific => { + write!(f, "DesignatedVendorSpecific(0x0023)") + } + ExtCapabilityType::VfResizableBar => write!(f, "VfResizableBar(0x0024)"), + ExtCapabilityType::DataLinkFeature => write!(f, "DataLinkFeature(0x0025)"), + ExtCapabilityType::PhysicalLayer16Gts => write!(f, "PhysicalLayer16Gts(0x0026)"), + ExtCapabilityType::LaneMargining => write!(f, "LaneMargining(0x0027)"), + ExtCapabilityType::PhysicalLayer32Gts => write!(f, "PhysicalLayer32Gts(0x002A)"), + ExtCapabilityType::Unknown(id) => write!(f, "Unknown({:#06x})", id), + } + } +} + #[derive(Clone)] pub struct PciCapability { cap_type: CapabilityType, region: Arc>, + // bar_usage:Option>> } impl PciCapability { @@ -1799,6 +3174,7 @@ impl PciCapability { return Some(PciCapability { cap_type: CapabilityType::Msi, region, + // bar_usage:None, }); } _ => { @@ -1808,16 +3184,26 @@ impl PciCapability { Some(PciCapability { cap_type: CapabilityType::from_id(id), region, + // bar_usage:None, }) } } } - pub fn new_virt( - cap_type: CapabilityType, - region: Arc>, - ) -> Self { - Self { cap_type, region } + pub fn new_virt(region: Arc>) -> Self { + Self { + cap_type: CapabilityType::Vendor, + region, + // bar_usage:None, + } + } + + pub fn new_cap(cap_type: CapabilityType, region: Arc>) -> Self { + Self { + cap_type, + region, + // bar_usage:None + } } pub fn get_offset(&self) -> PciConfigAddress { @@ -1831,6 +3217,10 @@ impl PciCapability { fn next_cap(&self) -> HvResult { self.with_region(|region| region.next_cap()) } + + // fn set_bar_area(&mut self,bar_area:Arc>){ + // self.bar_usage = Some(bar_area) + // } } impl Debug for PciCapability { @@ -1861,6 +3251,20 @@ pub trait PciCapabilityRegion: Send + Sync { let next_offset = (value as u16).get_bits(8..16) as PciConfigAddress; Ok(next_offset) } + + fn bar_area(&self) -> Option>> { + None + } + + fn bar_usage(&self) -> Option { + None + } + + fn bar_addr_range(&self) -> Option> { + None + } + + fn set_bar_area(&mut self, _bar_area: Arc>) {} } pub struct StandardPciCapabilityRegion { @@ -1901,42 +3305,257 @@ impl PciCapabilityRegion for StandardPciCapabilityRegion { } #[derive(Clone)] -pub struct PciCapabilityList(BTreeMap); +pub struct PciCapabilityList { + capability_ptr: u8, + cap_in_config: BTreeMap, + // cap_in_bar: Arc>, +} impl PciCapabilityList { pub fn new() -> Self { - Self(BTreeMap::new()) + Self { + capability_ptr: 0, + cap_in_config: BTreeMap::new(), + // cap_in_bar: Arc::new(RwLock::new(BarAreaManager::new())), + } + } + + pub fn get_capability_pointer(&self) -> u8 { + self.capability_ptr } + + pub fn set_capability_pointer(&mut self, ptr: u8) { + self.capability_ptr = ptr; + } + + pub fn try_read_cap(&self, offset: PciConfigAddress, size: usize) -> Option { + let cap = self.which_cap(offset)?; + let relative_offset = offset - cap.get_offset(); + match cap.region.clone().read().read(relative_offset, size) { + Ok(res) => Some(res as usize), + Err(_) => None, + } + } + + pub fn try_write_cap( + &self, + offset: PciConfigAddress, + size: usize, + value: usize, + ) -> Option { + let cap = self.which_cap(offset)?; + let relative_offset = offset - cap.get_offset(); + match cap + .region + .clone() + .write() + .write(relative_offset, size, value as u32) + { + Ok(_) => Some(0), + Err(_) => None, + } + } + + pub fn which_cap(&self, offset: PciConfigAddress) -> Option { + let kv_pair = self.cap_in_config.range(..=offset).next_back()?; + Some(kv_pair.1.clone()) + } + + pub fn insert_cap( + &mut self, + // addr: PciConfigAddress, + cap: PciCapability, + ) -> Option { + // cap.get_offset() + self.cap_in_config.insert(cap.get_offset(), cap) + } + + // pub fn register_bar_area( + // &mut self, + // bar: usize, + // bar_relative_addr: GuestPhysAddr, + // size_in_bar: usize, + // data: Arc>, + // ) { + // self.cap_in_bar + // .write() + // .insert(bar, bar_relative_addr, size_in_bar, data); + // } + + pub fn cap_in_config_ref(&self) -> &BTreeMap { + &self.cap_in_config + } + + fn find_cap_by_bar(&self, bar: usize, addr: usize) -> Option { + for i in self.cap_in_config.values() { + if bar != i.region.read().bar_usage()? { + continue; + } + if i.region.read().bar_addr_range()?.contains(&addr) { + return Some(i.clone()); + } + } + None + } + + pub fn handle_bar_read(&self, bar: usize, mmio_ac: &mut MMIOAccess) -> HvResult { + let addr = mmio_ac.address; + let cap = self.find_cap_by_bar(bar, addr); + match cap { + Some(x) => { + let bar = x + .region + .read() + .bar_area() + .expect("This bar area should not be none"); + if mmio_ac.is_write { + return bar.write().write(mmio_ac); + } else { + return bar.write().read(mmio_ac); + } + } + None => { + warn!("can't find this addr:0x{:x} in bar:{}", addr, bar); + return Ok(()); + } + } + // self.cap_in_bar.read().handle_bar_access(bar, mmio_ac) + } + + // pub fn get_msix_table(&self)->Option{ + // for (_,i) in self.cap_in_config.iter(){ + // if i.cap_type == CapabilityType::MsiX{ + // return Some(i.clone()); + // } + // } + // return None; + // } } -// impl Default for PciCapabilityList { -// fn default() -> Self { -// Self::new() -// } -// } +impl Debug for PciCapabilityList { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "PciCapabilityList {{\n")?; + for (offset, capability) in &self.cap_in_config { + write!(f, "0x{:x} {:?}\n", offset, capability)?; + } + write!(f, "}}")?; + Ok(()) + } +} + +// ---- PCIe Extended Capability types ---- + +/// A single PCIe extended capability entry (config space 0x100–0xFFF). +#[derive(Clone, Copy, Debug)] +pub struct PciExtCapability { + pub cap_type: ExtCapabilityType, + /// Absolute offset of this extended capability header in config space. + pub offset: PciConfigAddress, + /// Capability structure version (bits 19:16 of the header DWORD). + pub version: u8, +} + +/// Iterator over PCIe extended capabilities starting at offset 0x100. +/// +/// Each header DWORD layout: +/// - bits\[15:0\] Extended Capability ID +/// - bits\[19:16\] Capability Version +/// - bits\[31:20\] Next Capability Offset (0 = end of list) +pub struct ExtCapabilityIterator { + backend: Arc, + offset: PciConfigAddress, +} -impl Deref for PciCapabilityList { - type Target = BTreeMap; +impl ExtCapabilityIterator { + const EXT_CAP_START: PciConfigAddress = 0x100; + const EXT_CAP_END: PciConfigAddress = 0x1000; +} + +impl Iterator for ExtCapabilityIterator { + type Item = PciExtCapability; + + fn next(&mut self) -> Option { + // offset must be DWORD-aligned and leave room for a 4-byte DWORD read + if self.offset < Self::EXT_CAP_START + || self.offset > Self::EXT_CAP_END - 4 + || (self.offset & 3) != 0 + { + return None; + } + + let header = match self.backend.read(self.offset, 4) { + Ok(v) => v as u32, + Err(_) => return None, + }; + + // A null DWORD (0x00000000) or all-ones DWORD (0xFFFFFFFF, config space + // not implemented) both mean there are no (more) extended caps. + if header == 0 || header == 0xFFFFFFFF { + self.offset = Self::EXT_CAP_END; + return None; + } + + let id = (header & 0xFFFF) as u16; + let version = ((header >> 16) & 0xF) as u8; + let next_offset = ((header >> 20) & 0xFFF) as PciConfigAddress; + + let cap = PciExtCapability { + cap_type: ExtCapabilityType::from_id(id), + offset: self.offset, + version, + }; + + // next_offset == 0 means this is the last cap in the list. + // Validate: must be DWORD-aligned, within [EXT_CAP_START, EXT_CAP_END-4]. + // Any value outside this range (including 0xFFF etc.) stops iteration. + self.offset = if next_offset >= Self::EXT_CAP_START + && next_offset <= Self::EXT_CAP_END - 4 + && (next_offset & 3) == 0 + { + next_offset + } else { + Self::EXT_CAP_END // sentinel – stops iteration on the next call + }; + + Some(cap) + } +} + +/// Ordered map of PCIe extended capabilities keyed by config-space offset. +#[derive(Clone)] +pub struct PciExtCapabilityList(BTreeMap); + +impl PciExtCapabilityList { + pub fn new() -> Self { + Self(BTreeMap::new()) + } +} + +impl Deref for PciExtCapabilityList { + type Target = BTreeMap; fn deref(&self) -> &Self::Target { &self.0 } } -impl DerefMut for PciCapabilityList { +impl DerefMut for PciExtCapabilityList { fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } -impl Debug for PciCapabilityList { +impl Debug for PciExtCapabilityList { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - write!(f, "PciCapabilityList {{\n")?; - for (offset, capability) in &self.0 { - write!(f, "0x{:x} {:?}\n", offset, capability)?; + write!(f, "PciExtCapabilityList {{\n")?; + for (offset, cap) in &self.0 { + write!( + f, + " 0x{:x} {:?} (v{})\n", + offset, cap.cap_type, cap.version + )?; } - write!(f, "}}")?; - Ok(()) + write!(f, "}}") } } @@ -1957,42 +3576,120 @@ impl VirtualPciConfigSpace { CapabilityType::PciExpress => {} _ => {} } - capabilities.insert(capability.get_offset(), capability); + capabilities + .cap_in_config + .insert(capability.get_offset(), capability); } - info!("capability {:#?}", capabilities); + // info!("capability {:#?}", capabilities); self.capabilities = capabilities; } - //TODO: check secondary link by read cap - pub fn has_secondary_link(&self) -> bool { + fn _ext_capability_enumerate(&self, backend: Arc) -> ExtCapabilityIterator { + ExtCapabilityIterator { + backend, + offset: ExtCapabilityIterator::EXT_CAP_START, + } + } + + /// Walk the PCIe extended configuration space (0x100–0xFFF) and record all + /// extended capabilities found. No further parsing is performed. + pub fn ext_capability_enumerate(&mut self) { + let mut ext_caps = PciExtCapabilityList::new(); + for cap in self._ext_capability_enumerate(self.backend.clone()) { + ext_caps.insert(cap.offset, cap); + } + // info!("ext_capability {:#?}", ext_caps); + + // When the `sriov` feature is disabled, record info needed to splice + // the SR-IOV cap out of the ext-cap linked list for guest VMs. + #[cfg(not(sriov))] + { + use bit_field::BitField; + let sriov_offset = ext_caps + .values() + .find(|c| c.cap_type == ExtCapabilityType::SingleRootIov) + .map(|c| c.offset); + + if let Some(sriov_cap_offset) = sriov_offset { + // Read the SR-IOV cap header DWORD to get its own `next` pointer. + let sriov_cap_next = self + .backend + .read(sriov_cap_offset, 4) + .ok() + .map(|dw| ((dw as u32).get_bits(20..32)) as PciConfigAddress) + .unwrap_or(0); + + // The preceding node is the one with the largest offset that is + // still less than sriov_cap_offset. + let prev_cap_offset = ext_caps + .range(..sriov_cap_offset) + .next_back() + .map(|(off, _)| *off); + + self.hide_sriov = Some(HideSriovInfo { + sriov_cap_offset, + sriov_cap_next, + prev_cap_offset, + }); + + // Mark these ranges as "emulated" so accesses go through + // handle_cap_access rather than the hardware direct path. + // + // SR-IOV cap range: we return 0 to hide it from the guest. + self.access.set_bits( + sriov_cap_offset as usize + ..(sriov_cap_offset as usize + SRIOV_CAP_SIZE as usize), + ); + // First DWORD of the preceding node: we patch the `next` pointer. + if let Some(prev) = prev_cap_offset { + self.access.set_bits(prev as usize..prev as usize + 4); + } + } + } + + self.ext_capabilities = ext_caps; + } + + // detect whether this bridge secondary bus can have only one child device. + pub fn has_only_one_child(&self) -> bool { match self.config_type { HeaderType::PciBridge => { - // Find PciExpress capability - // warn!("has_secondary_link {:#?}", self.capabilities); - // for (_, capability) in &self.capabilities { - // if capability.cap_type == CapabilityType::PciExpress { - // // Read PCIe Capability Register at offset + 0x00 - // // Bits 4:0 contain the Device/Port Type - // let offset = capability.get_offset(); - // if let Ok(cap_reg) = self.backend.read(offset, 2) { - // let type_val = (cap_reg as u16).get_bits(0..5); - // if type_val == PCI_EXP_TYPE_ROOT_PORT || type_val == PCI_EXP_TYPE_PCIE_BRIDGE { - // return true; - // } else if type_val == PCI_EXP_TYPE_UPSTREAM || type_val == PCI_EXP_TYPE_DOWNSTREAM { - // // Parent check is not implemented, set to false for now - // return false; - // } - // } - // break; - // } - // } - // false - // #[cfg(feature = "dwc_pcie")] - // return true; - // #[cfg(not(feature = "dwc_pcie"))] - return false; + // Parse PCIe Device/Port Type from PCI Express Capability Register + // (capability offset + 0x02, bits 7:4). + for capability in self._capability_enumerate(self.backend.clone()) { + if capability.get_type() != CapabilityType::PciExpress { + continue; + } + + let offset = capability.get_offset(); + if let Ok(cap_reg) = self.backend.read(offset + 0x2, 2) { + let port_type = (cap_reg as u16).get_bits(4..8) as u16; + return match port_type { + // Root Port / Downstream Port: secondary bus has a single downstream link. + PCI_EXP_TYPE_ROOT_PORT | PCI_EXP_TYPE_DOWNSTREAM => true, + // Upstream Port / PCIe-to-PCI bridge can have multiple children behind it. + PCI_EXP_TYPE_UPSTREAM | PCI_EXP_TYPE_PCIE_BRIDGE => false, + _ => false, + }; + } + + // Capability exists but cannot be read safely. + return false; + } + + // Non-PCIe bridge (or no PCIe capability): keep full secondary-bus scan. + false } _ => false, } } } + +/// Bar area is just a MMIO memory area +/// There are many virtio capability structures such as commoncfg being put in bar +/// Any structure put in bar has to implement this trait and be registered by function 'register_bar_area' +pub trait AreaInBar: Send + Sync + Debug { + fn read(&mut self, mmio_ac: &mut MMIOAccess) -> HvResult; + + fn write(&mut self, mmio_ac: &MMIOAccess) -> HvResult; +} diff --git a/src/pci/pci_test.rs b/src/pci/pci_test.rs index 182a614de..629697181 100644 --- a/src/pci/pci_test.rs +++ b/src/pci/pci_test.rs @@ -25,7 +25,7 @@ use super::{ pci_struct::{Bdf, VirtualPciConfigSpace, CONFIG_LENTH}, }; -#[cfg(feature = "ecam_pcie")] +#[cfg(ecam_pcie)] use super::{mem_alloc::BaseAllocator, pci_struct::RootComplex}; use crate::{ @@ -40,7 +40,7 @@ pub static GLOBAL_PCIE_LIST_TEST: Lazy Self { + Self { + offset_in_bar: VIRTIO_BLK_CFG_OFFSET, + capacity_sectors: VIRTIO_BLK_CAPACITY_SECTORS, + blk_size: VIRTIO_BLK_SECTOR_SIZE, + } + } + + fn read_field(&self, offset: usize, size: usize) -> usize { + let Some(offset) = offset.checked_sub(self.offset_in_bar) else { + warn!( + "virtio-blk device cfg read below range: offset={offset:#x} base={:#x} size={size}", + self.offset_in_bar + ); + return 0; + }; + let mut buf = [0u8; 24]; + buf[0..8].copy_from_slice(&self.capacity_sectors.to_le_bytes()); + buf[8..12].copy_from_slice(&0u32.to_le_bytes()); // size_max + buf[12..16].copy_from_slice(&0u32.to_le_bytes()); // seg_max + buf[20..24].copy_from_slice(&self.blk_size.to_le_bytes()); + + let end = offset.saturating_add(size); + if end > buf.len() { + warn!("virtio-blk device cfg read out of range: offset={offset:#x} size={size}"); + return 0; + } + + match size { + 1 => buf[offset] as usize, + 2 => u16::from_le_bytes([buf[offset], buf[offset + 1]]) as usize, + 4 => u32::from_le_bytes([ + buf[offset], + buf[offset + 1], + buf[offset + 2], + buf[offset + 3], + ]) as usize, + 8 => u64::from_le_bytes([ + buf[offset], + buf[offset + 1], + buf[offset + 2], + buf[offset + 3], + buf[offset + 4], + buf[offset + 5], + buf[offset + 6], + buf[offset + 7], + ]) as usize, + _ => { + warn!("virtio-blk device cfg unsupported read size {size}"); + 0 + } + } + } +} + +impl AreaInBar for VirtioBlkCfg { + fn read(&mut self, mmio_ac: &mut MMIOAccess) -> HvResult { + mmio_ac.value = self.read_field(mmio_ac.address, mmio_ac.size); + Ok(()) + } + + fn write(&mut self, mmio_ac: &MMIOAccess) -> HvResult { + warn!( + "virtio-blk device cfg is read-only: addr={:#x} size={}", + mmio_ac.address, mmio_ac.size + ); + Ok(()) + } +} + +pub struct VirtioBlkHandler; + +impl VpciDeviceHandler for VirtioBlkHandler { + fn vdev_init(&self, mut dev: VirtualPciConfigSpace) -> VirtualPciConfigSpace { + let id: (DeviceId, VendorId) = (0x1042, 0x1af4); + let revision: DeviceRevision = 0xFFu8; + let base_class: BaseClass = 0x01; + let sub_class: SubClass = 0x80; + let interface: Interface = 0x00; + dev.with_config_value_mut(|config_value| { + config_value.set_id(id); + config_value.set_class_and_revision_id((base_class, sub_class, interface, revision)); + }); + dev.with_bararr_mut(|bararr| { + bararr[1].config_init( + PciMemType::Mem32, + false, + 0x4000, + 0x0, + Some(blk_mmio_handler), + ); + bararr[4].config_init( + PciMemType::Mem64Low, + true, + 0x10000, + 0x0, + Some(blk_mmio_handler), + ); + bararr[5].config_init( + PciMemType::Mem64High, + true, + 0x0, + 0x0, + Some(blk_mmio_handler), + ); + }); + + let commoncfg_bar = arc_rwlock!(VirtioPciCommonCfg::new(3)); + let commoncfg_cap = arc_rwlock!(VirtioPciCap::new( + 0x40, + super::virtio_cap::VirtioCfgType::CommonCfg, + 0, + 0x10, + 0x04, + 0x0, + 0x1000, + commoncfg_bar.clone() + )); + let commoncfg = PciCapability::new_virt(commoncfg_cap); + + let isr_bar: Arc> = Arc::new(RwLock::new(VirtioISRCap::new())); + let isr_cap = arc_rwlock!(VirtioPciCap::new( + 0x50, + super::virtio_cap::VirtioCfgType::IsrCfg, + 0x40, + 0x10, + 0x04, + 0x1000, + 0x1000, + isr_bar.clone() + )); + let isr = PciCapability::new_virt(isr_cap); + isr_bar.write().set_isr(0); + + let msix_table: Arc> = Arc::new(RwLock::new(MsixTable::new( + 0x10, + dev.get_bdf().requester_id() as usize, + ))); + let msix_cap = arc_rwlock!(MsixCap::new(0x74, 0x60, 0x10, msix_table.clone())); + let msix = PciCapability::new_cap(CapabilityType::MsiX, msix_cap); + + let notify_bar = arc_rwlock!(VirtioNotifyCap::new(msix_table.clone())); + let notify_cap = arc_rwlock!(VirtioPciCap::new( + 0x60, + crate::pci::vpci_dev::virtio_cap::VirtioCfgType::NotifyCfg(0x04), + 0x50, + 0x14, + 0x04, + 0x2000, + 0x1000, + notify_bar.clone() + )); + let notify = PciCapability::new_virt(notify_cap); + + let devcfg_bar = arc_rwlock!(VirtioBlkCfg::new()); + let devcfg_cap = arc_rwlock!(VirtioPciCap::new( + 0x88, + crate::pci::vpci_dev::virtio_cap::VirtioCfgType::DeviceCfg, + 0x74, + 0x10, + 0x04, + VIRTIO_BLK_CFG_OFFSET as u32, + 0x1000, + devcfg_bar + )); + let devcfg = PciCapability::new_virt(devcfg_cap); + + dev.set_msix_table(msix_table.clone()); + + dev.with_cap_mut(|capabilities| { + capabilities.insert_cap(commoncfg); + capabilities.insert_cap(isr); + capabilities.insert_cap(notify); + capabilities.insert_cap(msix); + capabilities.insert_cap(devcfg); + capabilities.set_capability_pointer(0x88); + }); + + dev.with_access_mut(|access| { + access.set_bits(0x34..0x38); + access.set_bits(0x40..0x50); + access.set_bits(0x50..0x60); + access.set_bits(0x60..0x70); + access.set_bits(0x70..0x90); + access.set_bits(0x88..0x98); + }); + + let vq: Arc> = arc_rwlock!(Virtqueue::new(0)); + commoncfg_bar.write().insert_queue(vq.clone()); + notify_bar.write().insert_queue(vq, 0x2000, 0x04); + dev + } +} + +pub const HANDLER: VirtioBlkHandler = VirtioBlkHandler; + +pub fn blk_mmio_handler(mmio: &mut MMIOAccess, base: usize) -> HvResult { + let zone = this_zone(); + let zone_lock = zone.read(); + let bus = zone_lock.vpci_bus(); + let (mut dev, mut bar) = (None, 0); + for (_, i) in bus.read_devs() { + if let Some(res) = i.is_my_bar_addr(base) { + dev = Some(i.clone()); + bar = res; + break; + } + } + if let Some(found_dev) = dev { + return found_dev.bar_mmio_distribute(bar, mmio); + } + Ok(()) +} diff --git a/src/pci/vpci_dev/mod.rs b/src/pci/vpci_dev/mod.rs index 091a402f1..f9fe2d710 100644 --- a/src/pci/vpci_dev/mod.rs +++ b/src/pci/vpci_dev/mod.rs @@ -15,16 +15,9 @@ // use crate::error::HvResult; -use crate::pci::pci_access::{Bar, EndpointField}; -use crate::pci::pci_struct::{ - ArcRwLockVirtualPciConfigSpace, Bdf, CapabilityType, ConfigValue, PciCapabilityRegion, - VirtualPciConfigSpace, -}; +use crate::pci::pci_struct::{ArcRwLockVirtualPciConfigSpace, Bdf, VirtualPciConfigSpace}; use crate::pci::PciConfigAddress; -use bitvec::array::BitArray; -use bitvec::{order::Lsb0, BitArr}; - macro_rules! pci_virt_log { ($($arg:tt)*) => { // info!($($arg)*); @@ -33,38 +26,18 @@ macro_rules! pci_virt_log { }; } -// Standard virtual device configuration space defaults -pub(crate) const STANDARD_CFG_SIZE: usize = 0x80; -pub(crate) const DEFAULT_CSPACE_U32: [u32; STANDARD_CFG_SIZE / 4] = { - const STANDARD_VENDOR_ID: u16 = 0x110a; - const STANDARD_DEVICE_ID: u16 = 0x4106; - const PCI_STS_CAPS: u16 = 0x10; - const PCI_DEV_CLASS_OTHER: u8 = 0xff; - const PCI_CFG_CAPS: usize = 0x34; - const PCI_CAP_ID_VNDR: u8 = 0x09; - const PCI_CAP_ID_MSIX: u8 = 0x11; - const STANDARD_CFG_VNDR_CAP: u8 = 0x40; - const STANDARD_CFG_VNDR_LEN: u8 = 0x20; - const STANDARD_CFG_MSIX_CAP: usize = 0x98; - const STANDARD_MSIX_VECTORS: u16 = 16; - - let mut arr = [0u32; STANDARD_CFG_SIZE / 4]; - arr[0x00 / 4] = (STANDARD_DEVICE_ID as u32) << 16 | STANDARD_VENDOR_ID as u32; - arr[0x04 / 4] = (PCI_STS_CAPS as u32) << 16; - arr[0x08 / 4] = (PCI_DEV_CLASS_OTHER as u32) << 24; - arr[0x2c / 4] = (STANDARD_DEVICE_ID as u32) << 16 | STANDARD_VENDOR_ID as u32; - // arr[PCI_CFG_CAPS / 4] = STANDARD_CFG_VNDR_CAP as u32; - // arr[STANDARD_CFG_VNDR_CAP as usize / 4] = (STANDARD_CFG_VNDR_LEN as u32) << 16 - // | (STANDARD_CFG_MSIX_CAP as u32) << 8 - // | PCI_CAP_ID_VNDR as u32; - // arr[STANDARD_CFG_MSIX_CAP / 4] = (0x00u32) << 8 | PCI_CAP_ID_MSIX as u32; - // arr[(STANDARD_CFG_MSIX_CAP + 0x4) / 4] = 1; - // arr[(STANDARD_CFG_MSIX_CAP + 0x8) / 4] = ((0x10 * STANDARD_MSIX_VECTORS) as u32) | 1; - arr -}; +macro_rules! arc_rwlock { + ($val:expr) => { + Arc::new(RwLock::new($val)) + }; +} +mod blk; +mod rng; pub mod standard; - +pub mod tools; +mod virtio_cap; +mod virtio_queue; /* * PciConfigAccessStatus is used to return the result of the config space access * Done(usize): the value is returned in usize @@ -84,23 +57,29 @@ pub enum VpciDevType { #[default] Physical = 0, StandardVdev = 1, + VirtioRng = 2, + VirtioBlk = 3, // Add new device types here } pub trait VpciDeviceHandler: Sync + Send { fn read_cfg( &self, - dev: ArcRwLockVirtualPciConfigSpace, - offset: PciConfigAddress, - size: usize, - ) -> HvResult; + _dev: ArcRwLockVirtualPciConfigSpace, + _offset: PciConfigAddress, + _size: usize, + ) -> HvResult { + return Ok(PciConfigAccessStatus::Default); + } fn write_cfg( &self, - dev: ArcRwLockVirtualPciConfigSpace, - offset: PciConfigAddress, - size: usize, - value: usize, - ) -> HvResult; + _dev: ArcRwLockVirtualPciConfigSpace, + _offset: PciConfigAddress, + _size: usize, + _value: usize, + ) -> HvResult { + return Ok(PciConfigAccessStatus::Default); + } fn vdev_init(&self, dev: VirtualPciConfigSpace) -> VirtualPciConfigSpace; } @@ -110,8 +89,11 @@ pub trait VpciDeviceHandler: Sync + Send { * 1. Add the variant to VpciDevType enum above * 2. Add the handler registration here: (&module::HANDLER, VpciDevType::YourType) */ -static HANDLERS: &[(&dyn VpciDeviceHandler, VpciDevType)] = - &[(&standard::HANDLER, VpciDevType::StandardVdev)]; +static HANDLERS: &[(&dyn VpciDeviceHandler, VpciDevType)] = &[ + (&standard::HANDLER, VpciDevType::StandardVdev), + (&rng::HANDLER, VpciDevType::VirtioRng), + (&blk::HANDLER, VpciDevType::VirtioBlk), +]; pub(crate) fn get_handler(dev_type: VpciDevType) -> Option<&'static dyn VpciDeviceHandler> { HANDLERS @@ -120,281 +102,48 @@ pub(crate) fn get_handler(dev_type: VpciDevType) -> Option<&'static dyn VpciDevi .map(|(handler, _)| *handler) } -pub(super) fn vpci_dev_read_cfg( - dev_type: VpciDevType, - node: ArcRwLockVirtualPciConfigSpace, - offset: PciConfigAddress, - size: usize, -) -> HvResult { - match dev_type { - VpciDevType::Physical => { - warn!("vpci_dev_read_cfg: physical device is not supported"); - Ok(0xFFFF_FFFF) - } - _ => { - if let Some(handler) = get_handler(dev_type) { - match handler.read_cfg(node.clone(), offset, size) { - Ok(status) => { - match status { - PciConfigAccessStatus::Done(value) => Ok(value), - PciConfigAccessStatus::Default => { - // If this is a standard virtual device, read from DEFAULT_CSPACE_U32 - pci_virt_log!("vpci_dev_read_cfg: default config space read, offset {:#x}, size {:#x}", offset, size); - if offset < STANDARD_CFG_SIZE as PciConfigAddress { - let u32_offset = (offset as usize) / 4; - let u32_value = DEFAULT_CSPACE_U32[u32_offset]; - - // Extract the appropriate bytes based on size and offset within the u32 - let byte_offset_in_u32 = (offset as usize) % 4; - let value = match size { - 1 => { - ((u32_value >> (byte_offset_in_u32 * 8)) & 0xFF) - as usize - } - 2 => { - ((u32_value >> (byte_offset_in_u32 * 8)) & 0xFFFF) - as usize - } - 4 => u32_value as usize, - _ => { - warn!("vpci_dev_read_cfg: invalid size {size}, try read from emu"); - let field = EndpointField::from(offset as usize, size); - return node.write().read_emu(field); - } - }; - return Ok(value); - } - // For other device types or out of range, use read_emu - let field = EndpointField::from(offset as usize, size); - let r = node.write().read_emu(field)?; - Ok(r) - } - PciConfigAccessStatus::Reject => { - // warn!("vpci_dev_read_cfg: operation rejected"); - Ok(0xFFFF_FFFF) - } - } - } - Err(e) => { - warn!("vpci_dev_read_cfg error: {:?}", e); - Ok(0xFFFF_FFFF) - } - } - } else { - warn!("vpci_dev_read_cfg: unknown device type"); - Ok(0xFFFF_FFFF) - } - } - } -} - -pub(super) fn vpci_dev_write_cfg( - dev_type: VpciDevType, - node: ArcRwLockVirtualPciConfigSpace, - offset: PciConfigAddress, - size: usize, - value: usize, -) -> HvResult { - match dev_type { - VpciDevType::Physical => { - warn!("vpci_dev_write_cfg: physical device is not supported"); - Ok(()) - } - _ => { - if let Some(handler) = get_handler(dev_type) { - match handler.write_cfg(node.clone(), offset, size, value) { - Ok(status) => match status { - PciConfigAccessStatus::Done(_) => Ok(()), - PciConfigAccessStatus::Default => { - warn!("vpci_dev_write_cfg: Default"); - Ok(()) - } - PciConfigAccessStatus::Reject => { - warn!("vpci_dev_write_cfg: operation rejected"); - Ok(()) - } - }, - Err(e) => { - warn!("vpci_dev_write_cfg error: {:?}", e); - Err(e) - } - } - } else { - warn!("vpci_dev_write_cfg: unknown device type"); - Ok(()) - } - } - } -} - +#[allow(unused_variables)] pub(super) fn virt_dev_init( bdf: Bdf, base: PciConfigAddress, dev_type: VpciDevType, -) -> VirtualPciConfigSpace { - // Create initial VirtualPciConfigSpace with default values - let initial_dev = VirtualPciConfigSpace::virt_dev_init_default( - bdf, - base, - dev_type, - ConfigValue::default(), - Bar::default(), - ); - - match dev_type { - VpciDevType::Physical => { - // Physical devices use default values - warn!("virt_dev_init: physical device is not supported"); - initial_dev - } - _ => { - if let Some(handler) = get_handler(dev_type) { - // Let handler modify and return the device - handler.vdev_init(initial_dev) - } else { - warn!("virt_dev_init: unknown device type"); - initial_dev - } - } - } -} - -pub struct VirtMsiCap { - offset: PciConfigAddress, - next_cap_pointer: u16, - control_bits: BitArr!(for 16, in u16, Lsb0), - message_address_lower: u32, - message_address_upper: u32, - message_data: u16, -} - -impl PciCapabilityRegion for VirtMsiCap { - fn read(&self, offset: PciConfigAddress, size: usize) -> HvResult { - match (offset, size) { - (0x0, 2) => { - Ok((CapabilityType::Msi.to_id() as u32) | (self.next_cap_pointer << 8) as u32) - } - (0x2, 2) => Ok(self.control_bits.as_raw_slice()[0] as u32), - (0x4, 4) => Ok(self.message_address_lower), - (0x8, 4) => Ok(self.message_address_upper), - (0xC, 2) => Ok(self.message_data as u32), - _ => { - warn!( - "VirtMsiCap invalid read offset 0x{:x} size {}", - offset, size - ); - Ok(0) - } - } - } - fn write(&mut self, offset: PciConfigAddress, size: usize, value: u32) -> HvResult { - match (offset, size) { - (0x2, 2) => self.control_bits = BitArray::new([value as u16]), - (0x4, 4) => self.message_address_lower = value, - (0x8, 4) => self.message_address_upper = value, - (0xC, 2) => self.message_data = value as u16, - _ => { - warn!( - "VirtMsiCap invalid write offset 0x{:x} size {}", - offset, size - ); - } - } - Ok(()) - } - fn get_offset(&self) -> PciConfigAddress { - self.offset - } - fn get_size(&self) -> usize { - 128 - } -} - -impl VirtMsiCap { - pub fn new(offset: PciConfigAddress) -> Self { - let mut bits = BitArray::ZERO; - bits.set(0, true); - Self { - offset, - next_cap_pointer: 0, - control_bits: bits, - message_address_lower: 0, - message_address_upper: 0, - message_data: 0, - } - } - - pub fn set_next_cap_pointer(&mut self, next_cap_pointer: u16) { - self.next_cap_pointer = next_cap_pointer; - } -} - -pub struct VirtMsiXCap { - offset: PciConfigAddress, - next_cap_pointer: u16, - control_bits: BitArr!(for 16, in u16, Lsb0), - table: u32, - pba: u32, -} - -impl PciCapabilityRegion for VirtMsiXCap { - fn read(&self, offset: PciConfigAddress, size: usize) -> HvResult { - match (offset, size) { - (0x0, 4) => Ok(((CapabilityType::MsiX.to_id() as u32) - | (self.next_cap_pointer << 8) as u32) - | (((self.control_bits.as_raw_slice()[0] as u32) << 16) as u32)), - (0x0, 2) => { - Ok((CapabilityType::MsiX.to_id() as u32) | (self.next_cap_pointer << 8) as u32) +) -> Option { + #[cfg(virtio_pci)] + { + // Create initial VirtualPciConfigSpace with default values + + use crate::pci::{pci_access::Bar, pci_struct::ConfigValue}; + let initial_dev = VirtualPciConfigSpace::virt_dev_init_default( + bdf, + base, + dev_type, + ConfigValue::default(), + Bar::default(), + None, + ); + + match dev_type { + VpciDevType::Physical => { + // Physical devices use default values + warn!("virt_dev_init: physical device is not supported"); + Some(initial_dev) } - (0x2, 2) => Ok(self.control_bits.as_raw_slice()[0] as u32), - (0x4, 4) => Ok(self.table), - (0x8, 4) => Ok(self.pba), _ => { - warn!( - "VirtMsiXCap invalid read offset 0x{:x} size {}", - offset, size - ); - Ok(0) - } - } - } - fn write(&mut self, offset: PciConfigAddress, size: usize, value: u32) -> HvResult { - match (offset, size) { - (0x2, 2) => self.control_bits = BitArray::new([value as u16]), - (0x4, 4) => self.table = value, - (0x8, 4) => self.pba = value, - _ => { - warn!( - "VirtMsiXCap invalid write offset 0x{:x} size {}", - offset, size - ); + if let Some(handler) = get_handler(dev_type) { + // Let handler modify and return the device + Some(handler.vdev_init(initial_dev)) + } else { + warn!("virt_dev_init: unknown device type"); + Some(initial_dev) + } } } - - Ok(()) } - - fn get_offset(&self) -> PciConfigAddress { - self.offset - } - fn get_size(&self) -> usize { - 96 - } -} - -impl VirtMsiXCap { - pub fn new(offset: PciConfigAddress) -> Self { - let bits = BitArray::ZERO; - Self { - offset, - next_cap_pointer: 0, - control_bits: bits, - table: 1, - pba: ((0x10 * 16) as u32) | 1, - } - } - - pub fn set_next_cap_pointer(&mut self, next_cap_pointer: u16) { - self.next_cap_pointer = next_cap_pointer; + #[cfg(not(virtio_pci))] + { + warn!( + "Try to initialize a virtual virtio pci device when feature virtio-pci is not enabled" + ); + None } } diff --git a/src/pci/vpci_dev/rng.rs b/src/pci/vpci_dev/rng.rs new file mode 100644 index 000000000..b5bb407ea --- /dev/null +++ b/src/pci/vpci_dev/rng.rs @@ -0,0 +1,158 @@ +// Copyright (c) 2025 Syswonder +// hvisor is licensed under Mulan PSL v2. +// You can use this software according to the terms and conditions of the Mulan PSL v2. +// You may obtain a copy of Mulan PSL v2 at: +// http://license.coscl.org.cn/MulanPSL2 +// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR +// FIT FOR A PARTICULAR PURPOSE. +// See the Mulan PSL v2 for more details. +// +// Syswonder Website: +// https://www.syswonder.org +// +// Authors: +// + +use alloc::sync::Arc; +use spin::rwlock::RwLock; + +use super::VpciDeviceHandler; +use crate::cpu_data::this_zone; +use crate::memory::MMIOAccess; +use crate::pci::msix::{MsixCap, MsixTable}; +use crate::pci::pci_access::{ + BaseClass, DeviceId, DeviceRevision, Interface, PciMemType, SubClass, VendorId, +}; +use crate::pci::pci_struct::{CapabilityType, PciCapability}; +use crate::pci::vpci_dev::virtio_cap::{ + VirtioISRCap, VirtioNotifyCap, VirtioPciCap, VirtioPciCommonCfg, Virtqueue, +}; +use crate::{error::HvResult, pci::pci_struct::VirtualPciConfigSpace}; + +pub struct VirtioRngHandler; + +impl VpciDeviceHandler for VirtioRngHandler { + fn vdev_init(&self, mut dev: VirtualPciConfigSpace) -> VirtualPciConfigSpace { + let id: (DeviceId, VendorId) = (0x1044, 0x1af4); + let revision: DeviceRevision = 0xFFu8; + let base_class: BaseClass = 0x0; + let sub_class: SubClass = 0x0; + let interface: Interface = 0x0; + dev.with_config_value_mut(|config_value| { + config_value.set_id(id); + config_value.set_class_and_revision_id((base_class, sub_class, interface, revision)); + }); + dev.with_bararr_mut(|bararr| { + bararr[1].config_init( + PciMemType::Mem32, + false, + 0x4000, + 0x0, + Some(rng_mmio_handler), + ); + bararr[4].config_init( + PciMemType::Mem64Low, + true, + 0x10000, + 0x0, + Some(rng_mmio_handler), + ); + bararr[5].config_init( + PciMemType::Mem64High, + true, + 0x0, + 0x0, + Some(rng_mmio_handler), + ); + }); + let commoncfg_bar = arc_rwlock!(VirtioPciCommonCfg::new(4)); + let commoncfg_cap = arc_rwlock!(VirtioPciCap::new( + 0x40, + super::virtio_cap::VirtioCfgType::CommonCfg, + 0, + 0x10, + 0x04, + 0x0, + 0x1000, + commoncfg_bar.clone() + )); + let commoncfg = PciCapability::new_virt(commoncfg_cap); + + let isr_bar: Arc> = Arc::new(RwLock::new(VirtioISRCap::new())); + let isr_cap = arc_rwlock!(VirtioPciCap::new( + 0x50, + super::virtio_cap::VirtioCfgType::IsrCfg, + 0x40, + 0x10, + 0x04, + 0x1000, + 0x1000, + isr_bar.clone() + )); + let isr = PciCapability::new_virt(isr_cap); + + isr_bar.write().set_isr(0); + + let msix_table: Arc> = Arc::new(RwLock::new(MsixTable::new( + 0x10, + dev.get_bdf().requester_id() as usize, + ))); + let msix_cap = arc_rwlock!(MsixCap::new(0x74, 0x60, 0x10, msix_table.clone())); + let msix = PciCapability::new_cap(CapabilityType::MsiX, msix_cap); + let notify_bar = arc_rwlock!(VirtioNotifyCap::new(msix_table.clone())); + let notify_cap = arc_rwlock!(VirtioPciCap::new( + 0x60, + crate::pci::vpci_dev::virtio_cap::VirtioCfgType::NotifyCfg(0x04), + 0x50, + 0x14, + 0x04, + 0x2000, + 0x1000, + notify_bar.clone() + )); + let notify = PciCapability::new_virt(notify_cap.clone()); + dev.set_msix_table(msix_table.clone()); + + dev.with_cap_mut(|capabilities| { + capabilities.insert_cap(commoncfg); + capabilities.insert_cap(isr); + capabilities.insert_cap(notify); + capabilities.insert_cap(msix); + capabilities.set_capability_pointer(0x74); + }); + + dev.with_access_mut(|access| { + access.set_bits(0x34..0x38); + access.set_bits(0x40..0x50); + access.set_bits(0x50..0x60); + access.set_bits(0x60..0x70); + access.set_bits(0x70..0x90); + }); + + let vq: Arc> = arc_rwlock!(Virtqueue::new(0)); + commoncfg_bar.write().insert_queue(vq.clone()); + notify_bar.write().insert_queue(vq, 0x2000, 0x04); + dev + } +} + +pub const HANDLER: VirtioRngHandler = VirtioRngHandler; + +pub fn rng_mmio_handler(mmio: &mut MMIOAccess, base: usize) -> HvResult { + let zone = this_zone(); + let zone_lock = zone.read(); + let bus = zone_lock.vpci_bus(); + let (mut dev, mut bar) = (None, 0); + for (_, i) in bus.read_devs() { + if let Some(res) = i.is_my_bar_addr(base) { + dev = Some(i.clone()); + bar = res; + break; + } + } + if let Some(found_dev) = dev { + return found_dev.bar_mmio_distribute(bar, mmio); + } + Ok(()) +} diff --git a/src/pci/vpci_dev/standard.rs b/src/pci/vpci_dev/standard.rs index 6a7e3bc80..478bd1846 100644 --- a/src/pci/vpci_dev/standard.rs +++ b/src/pci/vpci_dev/standard.rs @@ -14,8 +14,12 @@ // Authors: // +use alloc::sync::Arc; +use spin::RwLock; + use super::{PciConfigAccessStatus, VpciDeviceHandler}; use crate::error::HvResult; +use crate::pci::msix::{MsixCap, MsixTable}; use crate::pci::pci_access::{ BaseClass, DeviceId, DeviceRevision, EndpointField, Interface, SubClass, VendorId, }; @@ -26,10 +30,7 @@ use crate::cpu_data::this_zone; use crate::memory::MMIOAccess; use crate::pci::pci_access::PciMemType; use crate::pci::pci_struct::ArcRwLockVirtualPciConfigSpace; -use crate::pci::pci_struct::PciCapabilityRegion; -use crate::pci::vpci_dev::VirtMsiXCap; -use alloc::sync::Arc; -use spin::RwLock; +// use crate::pci::vpci_dev::VirtMsiXCap; /// Handler for standard virtual PCI devices pub struct StandardHandler; @@ -126,7 +127,7 @@ impl VpciDeviceHandler for StandardHandler { fn vdev_init(&self, mut dev: VirtualPciConfigSpace) -> VirtualPciConfigSpace { // Set config_value - let id: (DeviceId, VendorId) = (0x110a, 0x4106); + let id: (DeviceId, VendorId) = (0x110b, 0x4106); let revision: DeviceRevision = 0xFFu8; let base_class: BaseClass = 0x0; let sub_class: SubClass = 0x0; @@ -140,25 +141,32 @@ impl VpciDeviceHandler for StandardHandler { let your_addr = 0x0; let size = 0x1000; dev.with_bararr_mut(|bararr| { - bararr[0].config_init(PciMemType::Mem32, false, size as u64, your_addr); + bararr[0].config_init(PciMemType::Mem32, false, size as u64, your_addr, None); }); // 0x98 is an arbitrary value, used here only for demonstration purposes // please don't forget to set next cap pointer if next cap exists - let msi_cap_offset = 0x98; - let mut msi_cap = VirtMsiXCap::new(msi_cap_offset); - msi_cap.set_next_cap_pointer(0x00); + let msix_cap_offset = 0x98; + + let msix_table: Arc> = Arc::new(RwLock::new(MsixTable::new( + 0x10, + dev.get_bdf().requester_id() as usize, + ))); + let msix_cap = arc_rwlock!(MsixCap::new( + msix_cap_offset, + 0x00, + 0x10, + msix_table.clone() + )); + let msix = PciCapability::new_cap(CapabilityType::MsiX, msix_cap); + // let mut msi_cap = ::new(msi_cap_offset); + // msi_cap.set_next_cap_pointer(0x00); dev.with_access_mut(|access| { - access.set_bits( - (msi_cap_offset as usize)..(msi_cap_offset as usize + msi_cap.get_size()) as usize, - ); + access.set_bits((msix_cap_offset as usize)..(msix_cap_offset as usize + 0x10) as usize); }); dev.with_cap_mut(|capabilities| { - capabilities.insert( - msi_cap_offset, - PciCapability::new_virt(CapabilityType::MsiX, Arc::new(RwLock::new(msi_cap))), - ); + capabilities.insert_cap(msix); }); dev.with_access_mut(|access| { diff --git a/src/pci/vpci_dev/tools.rs b/src/pci/vpci_dev/tools.rs new file mode 100644 index 000000000..8ea8e7a93 --- /dev/null +++ b/src/pci/vpci_dev/tools.rs @@ -0,0 +1,120 @@ +// Copyright (c) 2025 Syswonder +// hvisor is licensed under Mulan PSL v2. +// You can use this software according to the terms and conditions of the Mulan PSL v2. +// You may obtain a copy of Mulan PSL v2 at: +// http://license.coscl.org.cn/MulanPSL2 +// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR +// FIT FOR A PARTICULAR PURPOSE. +// See the Mulan PSL v2 for more details. +// +// Syswonder Website: +// https://www.syswonder.org +// +// Authors: +// + +use core::{marker::PhantomData, mem::size_of}; + +#[derive(Clone, Copy, Debug)] +pub struct GuestMemory { + ptr: usize, + size: usize, +} + +impl GuestMemory { + pub const fn dummy() -> Self { + Self { ptr: 0, size: 0 } + } + + pub fn new(ptr: usize, size: usize) -> Self { + Self { ptr, size } + } + + pub fn set_ptr(&mut self, ptr: usize) { + self.ptr = ptr; + } + + pub fn set_len(&mut self, len: usize) { + self.size = len; + } + + pub fn read_obj(&self, offset: u64) -> T { + // warn!("read from :0x{:x},offset:{:x}",self.ptr,offset); + let obj_ptr = self.translate(offset) as *const T; + unsafe { core::ptr::read_volatile(obj_ptr) } + } + + pub fn write_obj(&self, offset: u64, val: T) { + // warn!("write into :0x{:x},offset:{:x}",self.ptr,offset); + let obj_ptr = self.translate(offset) as *mut T; + unsafe { + core::ptr::write_unaligned(obj_ptr, val); + } + } + + fn translate(&self, offset: u64) -> *mut u8 { + assert!(offset < self.size as u64); + unsafe { + let ptr = self.ptr as *mut u8; + ptr.add(offset as usize) + } + } +} + +#[derive(Clone, Copy, Debug)] +pub struct GuestSlice { + mem: GuestMemory, + // base: u64, + len: usize, + _phantom: core::marker::PhantomData, +} + +impl<'a, T: Copy> GuestSlice { + pub const fn dummy() -> Self { + Self { + mem: GuestMemory::dummy(), + len: 0, + _phantom: PhantomData, + } + } + + pub fn new(base: usize, len: usize) -> Self { + let memory_size = len * core::mem::size_of::(); + let mem = GuestMemory::new(base, memory_size); + Self { + mem, + len, + _phantom: PhantomData, + } + } + + pub fn set_ptr(&mut self, ptr: usize) { + self.mem.set_ptr(ptr); + } + + pub fn set_memory(&mut self, ptr: usize, len: usize) { + self.mem.set_ptr(ptr); + self.mem.set_len(len * size_of::()); + self.len = len; + } + + pub fn get_addr(&self) -> usize { + self.mem.ptr + } + + pub fn get(&self, index: usize) -> T { + assert!(index < self.len); + + let offset = index * core::mem::size_of::(); + self.mem.read_obj::(offset as u64) + } + + pub fn set(&self, index: usize, val: T) { + // info!("current len:{:x},index:{:x}",self.mem.size,index); + assert!(index < self.len); + + let offset = index * core::mem::size_of::(); + self.mem.write_obj(offset as u64, val); + } +} diff --git a/src/pci/vpci_dev/virtio_cap.rs b/src/pci/vpci_dev/virtio_cap.rs new file mode 100644 index 000000000..9ae3c721d --- /dev/null +++ b/src/pci/vpci_dev/virtio_cap.rs @@ -0,0 +1,745 @@ +// Copyright (c) 2025 Syswonder +// hvisor is licensed under Mulan PSL v2. +// You can use this software according to the terms and conditions of the Mulan PSL v2. +// You may obtain a copy of Mulan PSL v2 at: +// http://license.coscl.org.cn/MulanPSL2 +// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR +// FIT FOR A PARTICULAR PURPOSE. +// See the Mulan PSL v2 for more details. +// +// Syswonder Website: +// https://www.syswonder.org +// +// Authors: +// + +use core::{fmt::Debug, sync::atomic::fence}; + +// use aarch64_cpu::registers::VTCR_EL2::SH0::Non; +use alloc::{sync::Arc, vec::Vec}; +use spin::rwlock::RwLock; + +use crate::{ + device::virtio_trampoline::{ + VirtioPCIConfigInfo, VirtioPCIDataInfo, VirtqueueAreaInfo, MAX_DEVS, VIRTIO_PCI_BRIDGE, + }, + error::HvResult, + event::{send_event, IPI_EVENT_VIRTIO_PCI_CONFIG, IPI_EVENT_VIRTIO_PCI_DATA}, + hypercall::SGI_IPI_ID, + memory::MMIOAccess, + pci::{ + msix::MsixTable, + pci_struct::{AreaInBar, PciCapabilityRegion}, + vpci_dev::virtio_queue::{AvailRing, DescriptorTable, VirtqUsed}, + }, +}; + +pub type PciCapabilityHandler = fn(&mut MMIOAccess, usize) -> HvResult; + +struct VirtioPCIInterface {} + +const VIRTQ_DESC_F_NEXT: u16 = 1; +const VIRTIO_F_VERSION_1: usize = 32; + +// #[allow(unused_variables)] +// pub unsafe fn virtio_pci_intercept_its(deviceid: usize, event_id: usize, intid: usize) { +// #[cfg(virtio_pci)] +// unsafe { +// use crate::pci::msix::MAPTI_INTERCEPTOR; + +// if let Some(x) = MAPTI_INTERCEPTOR.clone() { +// x.write().intercept_its(deviceid, event_id, intid); +// } +// } +// } + +// #[allow(unused_variables)] +// pub unsafe fn virtio_pci_add_pending_data_req_id(data_req_id: u64) { +// #[cfg(virtio_pci)] +// unsafe { +// use crate::pci::msix::VIRTIO_MSIX_MANAGER; + +// VIRTIO_MSIX_MANAGER +// .write() +// .add_pending_data_req_id(data_req_id); +// } +// } + +// #[allow(unused_variables)] +// pub unsafe fn virtio_pci_activate_all_pending_irq() { +// #[cfg(virtio_pci)] +// unsafe { +// use crate::pci::msix::VIRTIO_MSIX_MANAGER; + +// VIRTIO_MSIX_MANAGER.write().activate_all_pending_irq(); +// } +// } + +fn put_together(src: (u8, u8, u8, u8)) -> u32 { + let a = (src.0 as u32) << 24 | (src.1 as u32) << 16 | (src.2 as u32) << 8 | (src.3 as u32); + a +} + +#[derive(Clone, Copy, Debug)] +pub enum VirtioCfgType { + CommonCfg, + NotifyCfg(u32), + IsrCfg, + DeviceCfg, + PciCfg, + SharedMemoryCfg, + VendorCfg, +} + +impl From for u8 { + fn from(value: VirtioCfgType) -> Self { + match value { + VirtioCfgType::CommonCfg => 1, + VirtioCfgType::NotifyCfg(_) => 2, + VirtioCfgType::IsrCfg => 3, + VirtioCfgType::DeviceCfg => 4, + VirtioCfgType::PciCfg => 5, + VirtioCfgType::SharedMemoryCfg => 8, + VirtioCfgType::VendorCfg => 9, + } + } +} + +/// Corresponding to the struct 'virtio_pci_cap' defined in virtio manual(virtio-v1.2-csd01) +#[derive(Debug)] +pub struct VirtioPciCap { + offset_in_config: usize, + cap_vndr: u8, + cap_next: u8, + cap_len: u8, + cfg_type: VirtioCfgType, + bar: u8, + id: u8, + padding: [u8; 2], + offset: u32, + length: u32, + + bar_usage: Arc>, +} + +impl PciCapabilityRegion for VirtioPciCap { + fn read( + &self, + offset: crate::pci::PciConfigAddress, + size: usize, + ) -> crate::error::HvResult { + // info!("read cap:{:x},size:{}", offset, size); + if offset as usize % size != 0 { + warn!("cap read is misalign!"); + return Ok(0); + } + + // if the capability read is the notifycfg, then we have to provide a multiplier field in the capability space + // Refer to virtio-v1.2-csd01(Session 4.1.4.4:Notification structure layout) + if let VirtioCfgType::NotifyCfg(multiplier) = self.cfg_type { + if (offset, size) == (16, 4) { + return Ok(multiplier); + } + } + // match self.cfg_type { + // VirtioCfgType::NotifyCfg(multiplier) => { + // if (offset, size) == (16, 4) { + // // warn!("read multiplier!!!"); + // return Ok(multiplier); + // } + // } + // _ => (), + // }; + if size == 1 { + match offset { + 0 => return Ok(self.cap_vndr as u32), + 1 => return Ok(self.cap_next as u32), + 2 => return Ok(self.cap_len as u32), + 3 => return Ok(u8::from(self.cfg_type) as u32), + 4 => return Ok(self.bar as u32), + 5 => return Ok(self.id as u32), + _ => { + warn!("read u8 from unexpected area! offset:{}", offset); + return Ok(0); + } + } + }; + if size == 2 { + match offset { + 0 => return Ok(put_together((0, 0, self.cap_next, self.cap_vndr))), + 2 => return Ok(put_together((0, 0, self.cfg_type.into(), self.cap_len))), + 4 => return Ok(put_together((0, 0, self.id, self.bar))), + _ => { + warn!("read u16 from unexpected area! offset:{}", offset); + return Ok(0); + } + } + }; + if size == 4 { + match offset { + 0 => { + return Ok(put_together(( + self.cfg_type.into(), + self.cap_len, + self.cap_next, + self.cap_vndr, + ))) + } + 4 => return Ok(put_together((0, 0, self.id, self.bar))), + 8 => return Ok(self.offset), + 12 => return Ok(self.length), + _ => { + warn!("read u32 from unexpected area! offset:{}", offset); + return Ok(0); + } + } + }; + warn!("size is not any of 1,2,4!"); + Ok(0) + } + + // All fields in virtio pci cap is read-only for guest, thus we need not to implement any write function + fn write( + &mut self, + _offset: crate::pci::PciConfigAddress, + _size: usize, + _value: u32, + ) -> crate::error::HvResult { + Ok(()) + } + + fn get_offset(&self) -> crate::pci::PciConfigAddress { + self.offset_in_config as u64 + } + + fn get_size(&self) -> usize { + self.cap_len as usize + } + + fn next_cap(&self) -> crate::error::HvResult { + Ok(self.cap_next as u64) + } + + fn bar_area(&self) -> Option>> { + Some(self.bar_usage.clone()) + } + + fn set_bar_area(&mut self, _bar_area: Arc>) { + self.bar_usage = _bar_area + } + + fn bar_usage(&self) -> Option { + Some(self.bar as usize) + } + + fn bar_addr_range(&self) -> Option> { + Some((self.offset as usize)..(self.offset + self.length) as usize) + } +} + +impl VirtioPciCap { + pub fn new( + offset_in_config: usize, + config_type: VirtioCfgType, + cap_next: u8, + cap_len: u8, + bar: u8, + offset: u32, + length: u32, + bar_usage: Arc>, + ) -> Self { + // According to virtio-v1.2-csd01, every capability specially defined by virtio specification is a vender-specific capability,thus the cap_vndr is 0x09 + // Currently, most usage of bar from virtio capabilities is 0x04, but it seems doesn't matter which bar you use + // Some device types would use multiple capabilities of a certain type, this field is intended to distinguish these capabilities. + // If you don't have multiple capabilities of a certain type in single device, this field is useless + Self { + cap_vndr: 0x09, + cap_next, + cap_len, + cfg_type: config_type, + bar, + id: 0x00, + padding: [0, 0], + offset, + length, + offset_in_config, + bar_usage, + } + } +} + +#[derive(Debug)] +pub struct Virtqueue { + queue_size: u16, + queue_msix_vector: u16, + queue_enable: u16, + queue_notify_off: u16, + queue_desc: u64, + queue_driver: u64, + queue_device: u64, + queue_notify_data: u16, + queue_reset: u16, + + this_dev_id: u16, + queue_id: u16, + // msix_table: Arc>, + desc_table: Option, + used_area: Option, + avail_area: Option, + last_avail: usize, +} + +impl Virtqueue { + pub fn new(queue_id: u16) -> Self { + Self { + queue_size: 256, + queue_msix_vector: u16::MAX, + queue_enable: 0, + queue_notify_off: 0, + queue_desc: 0, + queue_driver: 0, + queue_device: 0, + queue_notify_data: 0, + queue_reset: 0, + + this_dev_id: MAX_DEVS as u16, + queue_id, + // msix_table: msix, + desc_table: None, + used_area: None, + avail_area: None, + last_avail: 0, + } + } + + pub fn set_dev_id(&mut self, dev_id: u16) { + self.this_dev_id = dev_id; + } + + pub fn set_queue_id(&mut self, queue_id: u16) { + self.queue_id = queue_id; + } + + // pub fn notify_driver(&self) { + // self.msix_table + // .read() + // .inject_irq(self.queue_msix_vector as usize); + // } + + pub fn set_desc_area(&mut self) { + let base = self.queue_desc as usize; + match self.desc_table { + Some(ref mut x) => { + warn!("this arm should not be entered"); + x.set_ptr(base); + } + None => { + let desc = DescriptorTable::new(base, self.queue_size as usize); + self.desc_table = Some(desc); + } + } + } + + pub fn set_avail_area(&mut self) { + let base = self.queue_driver as usize; + match self.avail_area { + Some(ref mut x) => { + warn!("this arm should not be entered"); + x.set_ptr(base); + } + None => { + let avail = AvailRing::new(base, self.queue_size); + self.avail_area = Some(avail); + } + } + } + + pub fn set_used_area(&mut self) { + let base = self.queue_device as usize; + match self.used_area { + Some(ref mut x) => { + warn!("this arm should not be entered"); + x.set_ptr(base); + } + None => { + let desc = VirtqUsed::new(base, self.queue_size); + self.used_area = Some(desc); + } + } + } + + pub fn get_area_info(&self) -> VirtqueueAreaInfo { + VirtqueueAreaInfo::new( + self.queue_desc, + self.queue_driver, + self.queue_device, + self.queue_size as u64, + ) + } + + pub fn get_data_info(&self) -> VirtioPCIDataInfo { + VirtioPCIDataInfo::new(self.this_dev_id, self.queue_id, self.queue_msix_vector) + } +} + +#[derive(Debug)] +pub struct VirtioPciCommonCfg { + device_feature_select: u32, + device_feature: (u32, u32), + driver_feature_select: u32, + driver_feature: (u32, u32), + dtype: u16, + config_msix_vector: u16, + num_queue: u16, + device_status: u8, + config_generation: u8, + + queue_select: usize, + queue_list: Vec>>, + config_changed: bool, +} + +impl VirtioPciCommonCfg { + pub fn new(dtype: u16) -> Self { + let cfg = VirtioPciCommonCfg { + device_feature_select: 0, + device_feature: (0, 65), + // device_feature:(0,1), + driver_feature_select: 0, + driver_feature: (0, 0), + dtype, + config_msix_vector: u16::MAX, + num_queue: 0, + device_status: 0, + config_generation: 0, + queue_select: 0, + queue_list: Vec::new(), + config_changed: false, + }; + cfg + } + + pub fn insert_queue(&mut self, qu: Arc>) { + self.queue_list.push(qu); + self.num_queue += 1; + } +} + +impl VirtioPciCommonCfg { + // This function initialize the virtqueue in root linux + pub fn init_virtqueue_shared_space(&self) -> HvResult { + // info!("queue_info:{:x?}", queue_info); + let mut config_info = VirtioPCIConfigInfo::dummy(); + config_info.set_features(self.get_features()); + config_info.set_dtype(self.dtype); + config_info.set_num_of_queues(self.num_queue); + for i in 0..self.num_queue as usize { + config_info.set_vqs(i, self.queue_list[i].read().get_area_info()); + } + let mut pci_bridge = VIRTIO_PCI_BRIDGE.lock(); + let request_id = pci_bridge.push_config_req(config_info)?; + send_event(0, SGI_IPI_ID as usize, IPI_EVENT_VIRTIO_PCI_CONFIG); + let dev_id = pci_bridge.til_config_finish(request_id)?; + for i in self.queue_list.iter() { + i.write().set_dev_id(dev_id); + } + Ok(()) + } + + fn get_features(&self) -> u64 { + (self.driver_feature.1 as u64) << 32 | (self.driver_feature.0 as u64) + } + + pub fn write_into(&mut self, mmio_ac: &MMIOAccess) -> bool { + let addr = mmio_ac.address; + let size = mmio_ac.size; + let value = mmio_ac.value; + if size == 1 { + match addr { + 0x14 => { + // we use FEATURES_OK to confirm that initialization is completed + if value & 0x04 != 0 { + if let Err(err) = self.init_virtqueue_shared_space() { + error!("virtio pci queue init failed: {:?}", err); + return false; + } + } + self.device_status = value as u8; + return true; + } + _ => { + warn!("write:size is misalign!"); + return false; + } + } + } + + if size == 2 { + match addr { + 0x10 => { + self.config_msix_vector = value as u16; + return true; + } + 0x16 => { + self.queue_select = value; + return true; + } + 0x18 => { + self.queue_list[self.queue_select].write().queue_size = value as u16; + return true; + } + 0x1a => { + // info!( + // "queue No.{} has msix vector: 0x{:x}", + // self.queue_select, value + // ); + self.queue_list[self.queue_select].write().queue_msix_vector = value as u16; + return true; + } + 0x1c => { + self.queue_list[self.queue_select].write().queue_enable = value as u16; + } + // 0x1e is read-only for driver + _ => { + return false; + } + } + } + + if size == 4 { + match addr { + 0x00 => { + self.device_feature_select = value as u32; + return true; + } + 0x08 => { + self.driver_feature_select = value as u32; + return true; + } + 0x0c => { + if self.driver_feature_select == 0 { + self.driver_feature.0 = value as u32; + } else { + self.driver_feature.1 = value as u32; + } + return true; + } + 0x20 => { + let mut queue = self.queue_list[self.queue_select].write(); + queue.queue_desc = value as u64; + return true; + } + 0x24 => { + let mut queue = self.queue_list[self.queue_select].write(); + queue.queue_desc |= (value as u64) << 32; + queue.set_desc_area(); + return true; + } + 0x28 => { + self.queue_list[self.queue_select].write().queue_driver = value as u64; + return true; + } + 0x2c => { + let mut queue = self.queue_list[self.queue_select].write(); + queue.queue_driver |= (value as u64) << 32; + queue.set_avail_area(); + return true; + } + 0x30 => { + self.queue_list[self.queue_select].write().queue_device = value as u64; + return true; + } + 0x34 => { + let mut queue = self.queue_list[self.queue_select].write(); + queue.queue_device |= (value as u64) << 32; + queue.set_used_area(); + return true; + } + _ => { + warn!("write:not implement yet!addr:{:x}", addr); + return false; + } + } + } + false + } +} + +impl AreaInBar for VirtioPciCommonCfg { + fn read(&mut self, mmio_ac: &mut MMIOAccess) -> HvResult { + let addr = mmio_ac.address; + let size = mmio_ac.size; + if size == 1 { + match addr { + 0x14 => { + mmio_ac.value = self.device_status as usize; + } + 0x15 => { + mmio_ac.value = self.config_generation as usize; + } + _ => { + warn!("read:size is misalign!"); + return Ok(()); + } + } + // info!("read from common cfg:0x{:x}",mmio_ac.value); + } + + if size == 2 { + match addr { + 0x10 => { + mmio_ac.value = self.config_msix_vector as usize; + } + 0x12 => { + mmio_ac.value = self.num_queue as usize; + } + 0x18 => { + mmio_ac.value = self.queue_list[self.queue_select].read().queue_size as usize; + } + 0x1a => { + mmio_ac.value = + self.queue_list[self.queue_select].read().queue_msix_vector as usize; + } + 0x1c => { + mmio_ac.value = self.queue_list[self.queue_select].read().queue_enable as usize; + } + 0x1e => { + mmio_ac.value = + self.queue_list[self.queue_select].read().queue_notify_off as usize; + } + _ => { + warn!("read:size is misalign!"); + return Ok(()); + } + } + // info!("read from common cfg:0x{:x}",mmio_ac.value); + } + + if size == 4 { + match addr { + 0x04 => { + if self.device_feature_select == 0 { + mmio_ac.value = self.device_feature.0 as usize; + } else { + mmio_ac.value = self.device_feature.1 as usize; + } + } + _ => { + warn!("read:not implement yet!addr:{:x}", mmio_ac.value); + return Ok(()); + } + } + // info!("read from common cfg:0x{:x}",mmio_ac.value); + } + Ok(()) + } + + fn write(&mut self, mmio_ac: &MMIOAccess) -> HvResult { + if self.write_into(mmio_ac) { + return Ok(()); + } + warn!("the write has not reached the common config!"); + Ok(()) + } +} + +#[derive(Debug)] +pub struct VirtioISRCap { + isr: u32, +} + +impl VirtioISRCap { + pub fn new() -> Self { + Self { isr: 0 } + } + + pub fn set_isr(&mut self, value: u32) { + self.isr = value + } +} + +impl AreaInBar for VirtioISRCap { + fn read(&mut self, mmio_ac: &mut MMIOAccess) -> HvResult { + let offset = mmio_ac.address; + match offset { + 0x00 => { + mmio_ac.value = self.isr as usize; + self.isr = 0; + } + _ => { + warn!("illegal isr address"); + } + }; + return Ok(()); + } + + fn write(&mut self, _mmio_ac: &MMIOAccess) -> HvResult { + warn!("isr should not be write"); + return Ok(()); + } +} + +#[derive(Debug)] +pub struct VirtioNotifyCap { + // cap: VirtioPciCap, + queue_list: Vec<(usize, Arc>)>, + msix_table: Arc>, +} + +impl VirtioNotifyCap { + pub fn new(msix_table: Arc>) -> Self { + Self { + queue_list: Vec::new(), + msix_table, + } + } + + pub fn insert_queue( + &mut self, + qu: Arc>, + cap_notify_offset: u32, + multiplier: u32, + ) { + let queue_notify_off = qu.read().queue_notify_off as u32; + let offset = cap_notify_offset + queue_notify_off * multiplier; + self.queue_list.push((offset as usize, qu)); + // if let VirtioCfgType::NotifyCfg(multiplier) = self.cap.cfg_type { + // let offset = self.cap.offset + queue_notify_off * multiplier; + // self.queue_list.push((offset as usize, qu)); + // } else { + // error!("Notify cap has to have NotifyCfg type!"); + // } + } + + fn get_queues(&self, offset: usize) -> impl Iterator>> { + self.queue_list + .iter() + .filter(move |(x, _)| *x == offset) + .map(|(_, res)| res) + } +} + +impl AreaInBar for VirtioNotifyCap { + fn read(&mut self, _mmio_ac: &mut MMIOAccess) -> HvResult { + warn!("Notify read has not been implemented yet"); + Ok(()) + } + + fn write(&mut self, mmio_ac: &MMIOAccess) -> HvResult { + let offset = mmio_ac.address; + for i in self.get_queues(offset) { + let info = i.read().get_data_info(); + self.msix_table + .write() + .add_pending_msix(info.get_msix_vector_idx() as usize); + if let Err(err) = VIRTIO_PCI_BRIDGE.lock().push_data_req(info) { + error!("virtio pci data enqueue failed: {:?}", err); + return Err(err); + } + send_event(0, SGI_IPI_ID as usize, IPI_EVENT_VIRTIO_PCI_DATA); + fence(core::sync::atomic::Ordering::SeqCst); + } + Ok(()) + } +} diff --git a/src/pci/vpci_dev/virtio_queue.rs b/src/pci/vpci_dev/virtio_queue.rs new file mode 100644 index 000000000..0e8de7f67 --- /dev/null +++ b/src/pci/vpci_dev/virtio_queue.rs @@ -0,0 +1,103 @@ +// Copyright (c) 2025 Syswonder +// hvisor is licensed under Mulan PSL v2. +// You can use this software according to the terms and conditions of the Mulan PSL v2. +// You may obtain a copy of Mulan PSL v2 at: +// http://license.coscl.org.cn/MulanPSL2 +// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR +// FIT FOR A PARTICULAR PURPOSE. +// See the Mulan PSL v2 for more details. +// +// Syswonder Website: +// https://www.syswonder.org +// +// Authors: +// + +use core::mem::size_of; + +use crate::pci::vpci_dev::tools::{GuestMemory, GuestSlice}; + +#[repr(C)] +#[derive(Clone, Copy, Debug)] +pub struct VirtqDesc { + pub addr: u64, + pub len: u32, + pub flags: u16, + pub next: u16, +} + +pub type DescriptorTable = GuestSlice; + +#[repr(C)] +#[derive(Clone, Copy, Debug)] +pub struct AvailRing { + mem: GuestMemory, + // base: u64, + queue_size: u16, +} + +impl AvailRing { + pub fn new(base: usize, queue_size: u16) -> Self { + let memory_size = 4 + queue_size as usize * 2; + let mem = GuestMemory::new(base, memory_size); + Self { mem, queue_size } + } + + pub fn set_ptr(&mut self, ptr: usize) { + self.mem.set_ptr(ptr); + } + + pub fn get_idx(&self) -> u16 { + self.mem.read_obj::(2) + } + + pub fn get_ring_content(&self, idx: usize) -> u16 { + let offset = 4 + idx * 2; + self.mem.read_obj::(offset as u64) + } +} + +#[repr(C)] +#[derive(Clone, Copy)] +pub struct VirtqUsedElem { + pub id: u32, + pub len: u32, +} + +impl VirtqUsedElem { + pub fn new(id: u32, len: u32) -> Self { + Self { id, len } + } +} + +#[derive(Clone, Copy, Debug)] +pub struct VirtqUsed { + mem: GuestMemory, + queue_size: u16, +} + +impl VirtqUsed { + pub fn new(base: usize, queue_size: u16) -> Self { + let memory_size = 4 + (queue_size as usize) * size_of::(); + let mem = GuestMemory::new(base, memory_size); + Self { mem, queue_size } + } + + pub fn set_ptr(&mut self, ptr: usize) { + self.mem.set_ptr(ptr); + } + + pub fn write_ring(&self, idx: usize, val: VirtqUsedElem) { + let offset = 4 + idx * size_of::(); + self.mem.write_obj(offset as u64, val); + } + + pub fn get_idx(&self) -> u16 { + self.mem.read_obj::(2) + } + + pub fn set_idx(&self, val: u16) { + self.mem.write_obj::(2, val); + } +} diff --git a/src/platform/mod.rs b/src/platform/mod.rs index d9dd18a65..64605c31c 100644 --- a/src/platform/mod.rs +++ b/src/platform/mod.rs @@ -72,7 +72,7 @@ pub fn platform_root_zone_config() -> HvZoneConfig { let mut _num_pci_devs: u64 = 0; let mut _num_pci_bus: u64 = 0; - #[cfg(feature = "pci")] + #[cfg(pci)] { check!(ROOT_PCI_DEVS.len(), CONFIG_MAX_PCI_DEV, "ROOT_PCI_DEVS"); pci_devs[..ROOT_PCI_DEVS.len()].copy_from_slice(&ROOT_PCI_DEVS); diff --git a/src/zone.rs b/src/zone.rs index 158d8c677..cc8145717 100644 --- a/src/zone.rs +++ b/src/zone.rs @@ -16,27 +16,34 @@ use alloc::sync::Arc; use alloc::vec::Vec; // use psci::error::INVALID_ADDRESS; -use crate::consts::{INVALID_ADDRESS, MAX_CPU_NUM}; +use crate::consts::{INVALID_ADDRESS, MAX_CPU_NUM, MAX_ZONE_NUM}; use crate::pci::pci_struct::VirtualRootComplex; -use spin::{RwLock, RwLockReadGuard, RwLockWriteGuard}; +use spin::{Mutex, RwLock, RwLockReadGuard, RwLockWriteGuard}; -#[cfg(feature = "dwc_pcie")] +#[cfg(dwc_pcie)] use crate::pci::{config_accessors::dwc_atu::AtuConfig, PciConfigAddress}; -#[cfg(feature = "dwc_pcie")] +#[cfg(dwc_pcie)] use alloc::collections::btree_map::BTreeMap; use crate::arch::mm::new_s2_memory_set; use crate::arch::s2pt::Stage2PageTable; -use crate::config::{HvZoneConfig, CONFIG_NAME_MAXLEN}; +use crate::config::{HvZoneBootMode, HvZoneConfig, CONFIG_NAME_MAXLEN}; use crate::cpu_data::{get_cpu_data, this_zone, CpuSet}; use crate::error::HvResult; use crate::memory::addr::GuestPhysAddr; -use crate::memory::{MMIOConfig, MMIOHandler, MMIORegion, MemorySet}; +use crate::memory::{MMIOConfig, MMIOHandler, MMIORegion, MemoryRegion, MemorySet}; use core::panic; use core::sync::atomic::{AtomicBool, Ordering}; -#[cfg(feature = "dwc_pcie")] +#[cfg(all(pci_init_delay, dwc_pcie))] +use crate::config::{HvPciConfig, HvPciDevConfig, CONFIG_MAX_PCI_DEV, CONFIG_PCI_BUS_MAXNUM}; +#[cfg(all(pci_init_delay, dwc_pcie))] +use crate::pci::pci_config::GLOBAL_PCIE_LIST; +#[cfg(all(pci_init_delay, dwc_pcie))] +use crate::pci::pci_struct::Bdf; + +#[cfg(dwc_pcie)] #[derive(Debug)] pub struct VirtualAtuConfigs { ecam_to_atu: BTreeMap, @@ -44,7 +51,7 @@ pub struct VirtualAtuConfigs { cfg_base_to_ecam: BTreeMap, } -#[cfg(feature = "dwc_pcie")] +#[cfg(dwc_pcie)] impl VirtualAtuConfigs { pub fn new() -> Self { Self { @@ -66,13 +73,6 @@ impl VirtualAtuConfigs { self.ecam_to_atu.insert(ecam_base, atu) } - pub fn get_or_insert_atu(&mut self, ecam_base: usize, f: F) -> &mut AtuConfig - where - F: FnOnce() -> AtuConfig, - { - self.ecam_to_atu.entry(ecam_base).or_insert_with(f) - } - pub fn get_atu_by_io_base(&self, io_base: PciConfigAddress) -> Option<&AtuConfig> { let ecam = self.io_base_to_ecam.get(&io_base); if let Some(ecam) = ecam { @@ -119,11 +119,15 @@ pub struct ZoneInner { mmio: Vec, cpu_num: usize, cpu_set: CpuSet, + // Guest-visible CPU ids are not guaranteed to be dense or equal to pCPU ids. + // Keep explicit maps here; CpuSet only records physical CPU ownership. + guest_to_phys_cpu: [Option; MAX_CPU_NUM], + phys_to_guest_cpu: [Option; MAX_CPU_NUM], irq_bitmap: [u32; 1024 / 32], gpm: MemorySet, iommu_pt: Option>, vpci_bus: VirtualRootComplex, - #[cfg(feature = "dwc_pcie")] + #[cfg(dwc_pcie)] atu_configs: VirtualAtuConfigs, } @@ -174,14 +178,16 @@ impl ZoneInner { mmio: Vec::new(), cpu_num: 0, cpu_set: CpuSet::new(MAX_CPU_NUM as usize, 0), + guest_to_phys_cpu: [None; MAX_CPU_NUM], + phys_to_guest_cpu: [None; MAX_CPU_NUM], irq_bitmap: [0; 1024 / 32], - iommu_pt: if cfg!(feature = "iommu") { + iommu_pt: if cfg!(iommu) { Some(new_s2_memory_set()) } else { None }, vpci_bus: VirtualRootComplex::new(), - #[cfg(feature = "dwc_pcie")] + #[cfg(dwc_pcie)] atu_configs: VirtualAtuConfigs::new(), } } @@ -215,6 +221,15 @@ impl ZoneInner { handler: MMIOHandler, arg: usize, ) { + // TODO: add error handling instead of just warning. + // See https://github.com/syswonder/hvisor/issues/385 + if self.gpm.is_range_overlap(start, size) { + warn!( + "MMIO handler region [{:#x}, {:#x}) overlaps with passthrough region", + start, + start + size + ); + } if let Some(mmio) = self.mmio.iter_mut().find(|mmio| mmio.region.start == start) { warn!("duplicated mmio region {:#x?}", mmio); if mmio.region.size != size { @@ -253,6 +268,29 @@ impl ZoneInner { .find(|cfg| cfg.region.contains_region(addr, size)) .map(|cfg| (cfg.region, cfg.handler, cfg.arg)) } + /// Check whether `[start, start+size)` overlaps with any registered MMIO handler region. + pub fn is_mmio_handler_overlap(&self, start: GuestPhysAddr, size: usize) -> bool { + let region = MMIORegion { start, size }; + self.mmio + .iter() + .any(|cfg| cfg.region.is_overlap_with(®ion)) + } + /// Insert a passthrough region, warning if it overlaps an MMIO handler region. + pub fn insert_passthrough_region_quiet( + &mut self, + region: MemoryRegion, + ) -> HvResult { + // TODO: add error handling instead of just warning. + // See https://github.com/syswonder/hvisor/issues/385 + if self.is_mmio_handler_overlap(region.start, region.size) { + warn!( + "passthrough region [{:#x}, {:#x}) overlaps with MMIO handler region", + region.start, + region.start + region.size + ); + } + self.gpm.try_insert_quiet(region) + } /// If irq_id belongs to this zone pub fn irq_in_zone(&self, irq_id: u32) -> bool { let idx = (irq_id / 32) as usize; @@ -276,6 +314,36 @@ impl ZoneInner { &mut self.cpu_set } + pub fn map_cpu(&mut self, guest_cpu: usize, phys_cpu: usize) { + if guest_cpu >= MAX_CPU_NUM || phys_cpu >= MAX_CPU_NUM { + warn!( + "ignore invalid CPU map guest_cpu={}, phys_cpu={}", + guest_cpu, phys_cpu + ); + return; + } + if let Some(old_phys_cpu) = self.guest_to_phys_cpu[guest_cpu] { + if self.phys_to_guest_cpu[old_phys_cpu] == Some(guest_cpu) { + self.phys_to_guest_cpu[old_phys_cpu] = None; + } + } + if let Some(old_guest_cpu) = self.phys_to_guest_cpu[phys_cpu] { + if self.guest_to_phys_cpu[old_guest_cpu] == Some(phys_cpu) { + self.guest_to_phys_cpu[old_guest_cpu] = None; + } + } + self.guest_to_phys_cpu[guest_cpu] = Some(phys_cpu); + self.phys_to_guest_cpu[phys_cpu] = Some(guest_cpu); + } + + pub fn guest_to_phys_cpu(&self, guest_cpu: usize) -> Option { + self.guest_to_phys_cpu.get(guest_cpu).copied().flatten() + } + + pub fn phys_to_guest_cpu(&self, phys_cpu: usize) -> Option { + self.phys_to_guest_cpu.get(phys_cpu).copied().flatten() + } + pub fn irq_bitmap(&self) -> &[u32; 1024 / 32] { &self.irq_bitmap } @@ -308,18 +376,476 @@ impl ZoneInner { &mut self.vpci_bus } - #[cfg(feature = "dwc_pcie")] + #[cfg(dwc_pcie)] pub fn atu_configs(&self) -> &VirtualAtuConfigs { &self.atu_configs } - #[cfg(feature = "dwc_pcie")] + #[cfg(dwc_pcie)] pub fn atu_configs_mut(&mut self) -> &mut VirtualAtuConfigs { &mut self.atu_configs } + + #[cfg(all(pci_init_delay, dwc_pcie))] + pub fn guest_pci_init_delay( + &mut self, + _zone_id: usize, + alloc_pci_devs: &[HvPciDevConfig; CONFIG_MAX_PCI_DEV], + num_pci_devs: u64, + pci_config: &[HvPciConfig], + _num_pci_config: usize, + domain_id: u8, + ) -> HvResult { + let guard = GLOBAL_PCIE_LIST.lock(); + for target_pci_config in pci_config { + // Skip empty config + if target_pci_config.ecam_base == 0 || target_pci_config.domain != domain_id { + continue; + } + + #[allow(unused_variables)] + let ecam_base = target_pci_config.ecam_base; + let target_domain = target_pci_config.domain; + let bus_range_begin = target_pci_config.bus_range_begin as u8; + + // Create accessor for VirtualRootComplex, similar to RootComplex + #[cfg(dwc_pcie)] + { + use crate::pci::config_accessors::dwc::DwcConfigAccessor; + use crate::platform; + use alloc::sync::Arc; + + let atu_config = platform::ROOT_DWC_ATU_CONFIG + .iter() + .find(|atu_cfg| atu_cfg.ecam_base == ecam_base); + + match atu_config { + Some(cfg) => { + let root_bus = bus_range_begin; + let accessor = Arc::new(DwcConfigAccessor::new(cfg, root_bus)); + self.vpci_bus_mut().set_accessor(accessor); + } + None => { + warn!("No ATU config found for ecam_base 0x{:x}", ecam_base); + continue; + } + } + } + + #[cfg(loongarch64_pcie)] + { + use crate::pci::config_accessors::loongarch64::LoongArchConfigAccessor; + use alloc::sync::Arc; + + let root_bus = bus_range_begin; + let accessor = Arc::new(LoongArchConfigAccessor::new( + ecam_base, + target_pci_config.ecam_size, + root_bus, + )); + self.vpci_bus_mut().set_accessor(accessor); + } + + #[cfg(ecam_pcie)] + { + use crate::pci::config_accessors::ecam::EcamConfigAccessor; + use alloc::sync::Arc; + + let accessor = Arc::new(EcamConfigAccessor::new(ecam_base)); + self.vpci_bus_mut().set_accessor(accessor); + } + + let mut filtered_devices: alloc::vec::Vec = alloc::vec::Vec::new(); + for i in 0..num_pci_devs { + let dev_config = alloc_pci_devs[i as usize]; + if dev_config.domain == target_domain { + filtered_devices.push(dev_config); + } + } + + // Skip if no devices for this domain + if filtered_devices.is_empty() { + continue; + } + + filtered_devices.sort_by(|a, b| { + a.bus + .cmp(&b.bus) + .then_with(|| a.device.cmp(&b.device)) + .then_with(|| a.function.cmp(&b.function)) + }); + + let mut domain_msi_count: u32 = 0; + + for dev_config in &filtered_devices { + let bdf = Bdf::new_from_config(*dev_config); + let vbdf = Bdf::new( + bdf.domain(), + dev_config.v_bus, + dev_config.v_device, + dev_config.v_function, + ); + + info!("set bdf {:#?} to vbdf {:#?}", bdf, vbdf); + + #[cfg(any( + all(iommu, target_arch = "aarch64"), + all(iommu, target_arch = "riscv64"), + target_arch = "x86_64" + ))] + { + let iommu_pt_addr = if self.iommu_pt().is_some() { + self.iommu_pt().unwrap().root_paddr() + } else { + 0 + }; + let device_id = (dev_config.bus as usize) << 8 + | (dev_config.device as usize) << 3 + | dev_config.function as usize; + #[cfg(share_s2pt)] + crate::device::iommu::iommu_add_device_with_root_pt_addr( + _zone_id, + device_id as _, + self.gpm().root_paddr(), + ); + #[cfg(not(share_s2pt))] + crate::device::iommu::iommu_add_device_with_root_pt_addr( + _zone_id, + device_id as _, + iommu_pt_addr, + ); + } + + // Insert device into vpci_bus with calculated vbdf + if let Some(dev) = guard.get(&bdf) { + if bdf.is_host_bridge(dev.read().get_host_bdf().bus()) + || dev.with_config_value(|config_value| -> bool { + config_value.get_class().0 == 0x6 + }) + { + let mut vdev = dev.read().config_space.clone(); + vdev.set_vbdf_with_bus_map( + vbdf, + target_pci_config.bus_range_end as u8, + &filtered_devices, + ); + let msi_count = vdev.get_msi_count(); + domain_msi_count += msi_count; + self.vpci_bus_mut().insert(vbdf, vdev); + } else { + // Allow allocation if zone_id is None (unassigned), or if zone_id is + // Some(0) and the device is a SRIOV VF (initially assigned to root zone + // during enumeration, can be reassigned to a guest zone). + let is_sriov_vf_from_root = dev.get_zone_id() == Some(0) + && dev.read().get_sriov_vf_info().is_some(); + let is_pf = dev.read().get_sriov_info().is_some(); + if dev.get_zone_id().is_none() || is_sriov_vf_from_root { + if is_pf && _zone_id != 0 { + warn!( + "The SR-IOV PF {:#x?} can only be assigned to the root VM", + bdf + ); + } else { + dev.set_zone_id(Some(_zone_id as u32)); + let mut vdev_inner = dev.read().config_space.clone(); + vdev_inner.set_vbdf_with_bus_map( + vbdf, + target_pci_config.bus_range_end as u8, + &filtered_devices, + ); + let msi_count = vdev_inner.get_msi_count(); + domain_msi_count += msi_count; + self.vpci_bus_mut().insert(vbdf, vdev_inner); + } + } else { + warn!( + "Device {:#?} is already allocated to zone {:?}", + bdf, + dev.get_zone_id() + ); + } + } + } else { + warn!("can not find dev {:#?} in GLOBAL_PCIE_LIST (not detected during enumeration)", bdf); + #[cfg(ecam_pcie)] + { + use crate::pci::pci_struct::VirtualPciConfigSpace; + use crate::pci::vpci_dev::{get_handler, VpciDevType}; + + let dev_type = dev_config.dev_type; + match dev_type { + VpciDevType::Physical => { + warn!("can not find dev {:#?}", bdf); + } + _ => { + if let Some(_handler) = get_handler(dev_type) { + let base = ecam_base + + ((bdf.bus() as u64) << 20) + + ((bdf.device() as u64) << 15) + + ((bdf.function() as u64) << 12); + let dev = VirtualPciConfigSpace::virt_dev(bdf, base, dev_type); + self.vpci_bus_mut().insert(vbdf, dev); + } else { + warn!("can not find dev {:#?}, unknown device type", bdf); + } + } + } + } + } + } + + // After processing all devices for this domain, allocate hardware MSI bits + if domain_msi_count > 0 { + #[cfg(all(dwc_msi, dwc_pcie))] + { + // Get the DW MSI domain allocator and allocate hwbit + if let Some(mut domain_lock) = + crate::pci::dwc_msi::get_dwc_msi_domain_mut(target_domain) + { + if let Some(domain_msi) = domain_lock.get_mut(&target_domain) { + let zone_cpu_set = self.cpu_set(); + let target_cpu = zone_cpu_set.first_cpu().unwrap_or(0); + match domain_msi.allocate_for_cpu(target_cpu, domain_msi_count) { + Ok(hwirq_bit) => { + // Register the MSI info for this domain + self.vpci_bus_mut().add_msi_count_for_domain( + target_domain, + domain_msi_count, + hwirq_bit, + ); + } + Err(e) => { + warn!( + "Failed to allocate MSI for domain {}: {:?}", + target_domain, e + ); + } + } + } + } + } + + #[cfg(not(dwc_msi))] + { + // Without dwc_msi feature, just register without hardware bit allocation + self.vpci_bus_mut().add_msi_count_for_domain( + target_domain, + domain_msi_count, + 0, // hwirq_bit is 0 when not using dwc_msi + ); + } + } + } + info!("vpci bus init done\n {:#x?}", self.vpci_bus()); + Ok(()) + } + + #[cfg(all(pci_init_delay, dwc_pcie))] + pub fn virtual_pci_dbi_pref_init( + &mut self, + pci_rootcomplex_config: &[HvPciConfig; CONFIG_PCI_BUS_MAXNUM], + _num_pci_config: usize, + ) { + use crate::memory::mmio_generic_handler; + use crate::pci::pci_handler::mmio_vpci_handler_dbi; + use crate::platform; + + for rootcomplex_config in pci_rootcomplex_config { + if rootcomplex_config.ecam_base == 0 { + continue; + } + + let encoded_arg = + rootcomplex_config.ecam_base as usize + (rootcomplex_config.domain as usize); + self.mmio_region_register( + rootcomplex_config.ecam_base as usize, + rootcomplex_config.ecam_size as usize, + mmio_vpci_handler_dbi, + encoded_arg, + ); + + let extend_config = platform::ROOT_DWC_ATU_CONFIG + .iter() + .find(|cfg| cfg.ecam_base == rootcomplex_config.ecam_base); + if let Some(extend_config) = extend_config { + if extend_config.apb_base != 0 && extend_config.apb_size != 0 { + self.mmio_region_register( + extend_config.apb_base as usize, + extend_config.apb_size as usize, + mmio_generic_handler, + extend_config.apb_base as usize, + ); + } + } + } + } + + #[cfg(all(pci_init_delay, dwc_pcie))] + pub fn virtual_pci_mmio_init_delay( + &mut self, + pci_rootcomplex_config: &[HvPciConfig; CONFIG_PCI_BUS_MAXNUM], + _num_pci_config: usize, + domain_id: u8, + ) { + #[cfg(loongarch64_pcie)] + let mut emergency_map_regions: alloc::vec::Vec<(usize, usize)> = alloc::vec::Vec::new(); + + for rootcomplex_config in pci_rootcomplex_config { + if rootcomplex_config.ecam_base == 0 || rootcomplex_config.domain != domain_id { + continue; + } + #[cfg(ecam_pcie)] + { + use crate::pci::pci_handler::mmio_vpci_handler; + + self.mmio_region_register( + rootcomplex_config.ecam_base as usize, + rootcomplex_config.ecam_size as usize, + mmio_vpci_handler, + rootcomplex_config.ecam_base as usize, + ); + } + #[cfg(dwc_pcie)] + { + use crate::memory::mmio_generic_handler; + use crate::pci::config_accessors::dwc_atu::AtuConfig; + use crate::pci::config_accessors::{dwc::DwcConfigRegionBackend, PciRegionMmio}; + use crate::pci::pci_handler::{ + mmio_dwc_cfg_handler, mmio_dwc_io_handler, mmio_vpci_handler_dbi, + }; + use crate::platform; + + let encoded_arg = + rootcomplex_config.ecam_base as usize + (rootcomplex_config.domain as usize); + self.mmio_region_register( + rootcomplex_config.ecam_base as usize, + rootcomplex_config.ecam_size as usize, + mmio_vpci_handler_dbi, + encoded_arg, + ); + + let extend_config = platform::ROOT_DWC_ATU_CONFIG + .iter() + .find(|extend_cfg| extend_cfg.ecam_base == rootcomplex_config.ecam_base); + + if let Some(extend_config) = extend_config { + if extend_config.apb_base != 0 && extend_config.apb_size != 0 { + self.mmio_region_register( + extend_config.apb_base as usize, + extend_config.apb_size as usize, + mmio_generic_handler, + extend_config.apb_base as usize, + ); + } + + let cfg_size_half = extend_config.cfg_size / 2; + let cfg0_base = extend_config.cfg_base; + if cfg0_base != 0 && cfg_size_half != 0 { + self.mmio_region_register( + cfg0_base as usize, + cfg_size_half as usize, + mmio_dwc_cfg_handler, + cfg0_base as usize, + ); + } + + let cfg1_base = extend_config.cfg_base + cfg_size_half; + if cfg1_base != 0 && cfg_size_half != 0 { + self.mmio_region_register( + cfg1_base as usize, + cfg_size_half as usize, + mmio_dwc_cfg_handler, + cfg1_base as usize, + ); + } + + if extend_config.io_cfg_atu_shared != 0 { + self.mmio_region_register( + rootcomplex_config.io_base as usize, + rootcomplex_config.io_size as usize, + mmio_dwc_io_handler, + rootcomplex_config.io_base as usize, + ); + } + + let mut atu = AtuConfig::default(); + + let dbi_base = extend_config.dbi_base as crate::pci::PciConfigAddress; + let dbi_size = extend_config.dbi_size; + let dbi_region = PciRegionMmio::new(dbi_base, dbi_size); + let dbi_backend = DwcConfigRegionBackend::new(dbi_region); + if let Err(e) = atu.init_limit_hw_value(&dbi_backend) { + warn!("Failed to initialize ATU0 limit defaults: {:?}", e); + } + + self.atu_configs_mut() + .insert_atu(rootcomplex_config.ecam_base as usize, atu); + self.atu_configs_mut().insert_cfg_base_mapping( + extend_config.cfg_base as crate::pci::PciConfigAddress, + rootcomplex_config.ecam_base as usize, + ); + self.atu_configs_mut().insert_cfg_base_mapping( + cfg1_base as crate::pci::PciConfigAddress, + rootcomplex_config.ecam_base as usize, + ); + self.atu_configs_mut().insert_io_base_mapping( + rootcomplex_config.io_base as crate::pci::PciConfigAddress, + rootcomplex_config.ecam_base as usize, + ); + } + } + #[cfg(loongarch64_pcie)] + { + use crate::pci::pci_handler::mmio_vpci_direct_handler; + + self.mmio_region_register( + rootcomplex_config.ecam_base as usize, + rootcomplex_config.ecam_size as usize, + mmio_vpci_direct_handler, + rootcomplex_config.ecam_base as usize, + ); + emergency_map_regions.push(( + rootcomplex_config.ecam_base as usize, + rootcomplex_config.ecam_size as usize, + )); + } + #[cfg(not(any(ecam_pcie, dwc_pcie, loongarch64_pcie)))] + { + warn!( + "No extend config found for base 0x{:x}", + rootcomplex_config.ecam_base + ); + } + } + + // Note: emergency_map_regions requires access to self (for Zone), so this must be handled at Zone level + } } static ZONE_LIST: RwLock>> = RwLock::new(vec![]); +static ZONE_BOOT_MODES: Mutex<[Option; MAX_ZONE_NUM]> = + Mutex::new([None; MAX_ZONE_NUM]); + +pub fn set_zone_boot_mode(zone_id: usize, mode: HvZoneBootMode) { + if let Some(slot) = ZONE_BOOT_MODES.lock().get_mut(zone_id) { + *slot = Some(mode); + } +} + +pub fn zone_boot_mode(zone_id: usize) -> HvZoneBootMode { + ZONE_BOOT_MODES + .lock() + .get(zone_id) + .copied() + .flatten() + .unwrap_or_default() +} + +pub fn clear_zone_boot_mode(zone_id: usize) { + if let Some(slot) = ZONE_BOOT_MODES.lock().get_mut(zone_id) { + *slot = None; + } +} pub fn root_zone() -> Arc { ZONE_LIST.read().get(0).cloned().unwrap() @@ -388,31 +914,8 @@ pub fn zone_create(config: &HvZoneConfig) -> HvResult> { zone.pt_init(config.memory_regions())?; zone.mmio_init(&config.arch_config); - #[cfg(feature = "pci")] - { - let _ = zone.virtual_pci_mmio_init(&config.pci_config, config.num_pci_bus as usize); - let _ = zone.guest_pci_init( - zone_id, - &config.alloc_pci_devs, - config.num_pci_devs, - &config.pci_config, - config.num_pci_bus as usize, - ); - } - - // #[cfg(target_arch = "aarch64")] - // zone.ivc_init(config.ivc_config()); - - /* loongarch page table emergency */ - /* Kai: Maybe unnecessary but i can't boot vms on my 3A6000 PC without this function. */ - // #[cfg(target_arch = "loongarch64")] - // zone.page_table_emergency( - // config.pci_config[0].ecam_base as _, - // config.pci_config[0].ecam_size as _, - // )?; - let mut cpu_num = 0; - for cpu_id in config.cpus().iter() { + for (guest_cpu, cpu_id) in config.cpus().iter().enumerate() { if let Some(existing_zone) = get_cpu_data(*cpu_id as _).zone.clone() { return hv_result_err!( EBUSY, @@ -423,10 +926,71 @@ pub fn zone_create(config: &HvZoneConfig) -> HvResult> { ) ); } - zone.write().cpu_set_mut().set_bit(*cpu_id as _); + let cpu_id = *cpu_id as usize; + let mut zone_inner = zone.write(); + zone_inner.cpu_set_mut().set_bit(cpu_id); + // The config lists physical CPUs, while guests use dense CPU ids from + // zero. Preserve that distinction for non-root SMP zones. + zone_inner.map_cpu(guest_cpu, cpu_id); cpu_num += 1; } zone.write().set_cpu_num(cpu_num); + + #[cfg(pci)] + { + #[cfg(pci_init_delay)] + { + #[cfg(dwc_pcie)] + { + let num_pci_bus = config.num_pci_bus as usize; + if zone_id == 0 { + let mut inner = zone.write(); + inner.virtual_pci_dbi_pref_init(&config.pci_config, num_pci_bus); + } else { + let _ = zone.virtual_pci_mmio_init(&config.pci_config, num_pci_bus); + let _ = zone.guest_pci_init( + zone_id, + &config.alloc_pci_devs, + config.num_pci_devs, + &config.pci_config, + num_pci_bus, + ); + } + } + } + + #[cfg(not(pci_init_delay))] + { + let _ = zone.virtual_pci_mmio_init(&config.pci_config, config.num_pci_bus as usize); + let _ = zone.guest_pci_init( + zone_id, + &config.alloc_pci_devs, + config.num_pci_devs, + &config.pci_config, + config.num_pci_bus as usize, + ); + } + } + + #[cfg(viommu)] + { + use crate::platform::{IOMMU_SYS_BASE, IOMMU_SYS_SIZE}; + // Create viommu instance and register mmio handler for target zone. + crate::device::iommu::viommu_init(zone_id); + crate::device::iommu::viommu_mmio_handler_register(&zone, IOMMU_SYS_BASE, IOMMU_SYS_SIZE); + } + + // #[cfg(target_arch = "aarch64")] + // zone.ivc_init(config.ivc_config()); + + /* loongarch page table emergency */ + /* Kai: Maybe unnecessary but i can't boot vms on my 3A6000 PC without this function. */ + // #[cfg(target_arch = "loongarch64")] + // zone.page_table_emergency( + // config.pci_config[0].ecam_base as _, + // config.pci_config[0].ecam_size as _, + // )?; + let cpu_set = zone.read().cpu_set(); info!("zone cpu_set: {:#b}", cpu_set.bitmap); @@ -434,7 +998,7 @@ pub fn zone_create(config: &HvZoneConfig) -> HvResult> { // #[cfg(target_arch = "aarch64")] // zone.ivc_init(config.ivc_config()); - #[cfg(all(feature = "iommu", target_arch = "aarch64"))] + #[cfg(all(iommu, target_arch = "aarch64"))] zone.iommu_pt_init(config.memory_regions(), &config.arch_config)?; /* loongarch page table emergency */ diff --git a/tools/check_hv_mem_overlap.py b/tools/check_hv_mem_overlap.py new file mode 100644 index 000000000..078183807 --- /dev/null +++ b/tools/check_hv_mem_overlap.py @@ -0,0 +1,196 @@ +#!/usr/bin/env python3 +""" +Post-link overlap check for hvisor. + +Verifies that no MEM_TYPE_RAM region in ROOT_ZONE_MEMORY_REGIONS overlaps +with hvisor's own physical memory range [skernel, __hv_end). + +Without this check, the root zone's Linux may allocate and write to physical +pages that hvisor uses for its page tables and heap (memory stomping), +causing "unhandled MMIO fault" panics when those corrupted page tables +are traversed. + +Usage: + python3 tools/check_hv_mem_overlap.py + +Returns exit code 0 if no overlap, 1 if overlap detected or error. +""" + +import re +import subprocess +import sys +from typing import Optional + + +def get_symbol_value(elf_path: str, symbol: str) -> Optional[int]: + """Read a symbol value from the ELF using rust-nm.""" + result = subprocess.run( + ["rust-nm", elf_path], + capture_output=True, + text=True, + ) + for line in result.stdout.splitlines(): + parts = line.split() + if len(parts) >= 3 and parts[2] == symbol: + return int(parts[0], 16) + return None + + +def strip_rust_comments(text: str) -> str: + """Strip Rust line comments (//) and block comments (/* ... */) from text.""" + # Strip block comments first (non-greedy) + text = re.sub(r"/\*.*?\*/", "", text, flags=re.DOTALL) + # Strip line comments + text = re.sub(r"//[^\n]*", "", text) + return text + + +def parse_root_zone_memory_regions(board_rs_path: str) -> list: + """Parse ROOT_ZONE_MEMORY_REGIONS from board.rs. + + Returns list of (mem_type, physical_start, size) tuples. + """ + with open(board_rs_path) as f: + content = f.read() + + # Strip comments before parsing + content = strip_rust_comments(content) + + # Find the ROOT_ZONE_MEMORY_REGIONS array + match = re.search( + r"pub\s+const\s+ROOT_ZONE_MEMORY_REGIONS\s*:\s*&\[HvConfigMemoryRegion\]\s*=\s*&\[(.*?)\];", + content, + re.DOTALL, + ) + if not match: + print(f"WARN: ROOT_ZONE_MEMORY_REGIONS not found in {board_rs_path}, skipping check", + file=sys.stderr) + return [] + + regions_str = match.group(1) + + regions = [] + # Match each HvConfigMemoryRegion block + for block_match in re.finditer( + r"HvConfigMemoryRegion\s*\{(.*?)\}", regions_str, re.DOTALL + ): + block = block_match.group(1) + + mem_type_m = re.search(r"mem_type\s*:\s*(MEM_TYPE_\w+)", block) + pstart_m = re.search(r"physical_start\s*:\s*(0x[0-9a-fA-F]+)", block) + size_m = re.search(r"size\s*:\s*(0x[0-9a-fA-F]+)", block) + + if mem_type_m and pstart_m and size_m: + regions.append(( + mem_type_m.group(1), + int(pstart_m.group(1), 16), + int(size_m.group(1), 16), + )) + + return regions + + +def do_regions_overlap(start_a: int, end_a: int, start_b: int, end_b: int) -> bool: + """Check if [start_a, end_a) overlaps with [start_b, end_b).""" + return start_a < end_b and start_b < end_a + + +def term_bold(text: str) -> str: + """Wrap text in ANSI bold escape codes.""" + return f"\033[1m{text}\033[22m" + + +def term_red(text: str) -> str: + """Wrap text in ANSI red escape codes.""" + return f"\033[31m{text}\033[39m" + + +def term_bold_red(text: str) -> str: + """Wrap text in ANSI bold+red escape codes.""" + return f"\033[1;31m{text}\033[0m" + + +def main() -> int: + if len(sys.argv) < 3: + print(f"Usage: {sys.argv[0]} ", file=sys.stderr) + return 1 + + elf_path = sys.argv[1] + board_rs_path = sys.argv[2] + + # Read hvisor memory range from ELF + skernel = get_symbol_value(elf_path, "skernel") + hv_end = get_symbol_value(elf_path, "__hv_end") + + if skernel is None: + print(f"WARN: symbol 'skernel' not found in {elf_path}, skipping check", + file=sys.stderr) + return 0 + if hv_end is None: + print(f"WARN: symbol '__hv_end' not found in {elf_path}, skipping check", + file=sys.stderr) + return 0 + + # Parse root zone memory regions + regions = parse_root_zone_memory_regions(board_rs_path) + if not regions: + return 0 + + # Check each MEM_TYPE_RAM region for overlap + found_overlap = False + for mem_type, pstart, size in regions: + pend = pstart + size + if mem_type != "MEM_TYPE_RAM": + continue + if do_regions_overlap(pstart, pend, skernel, hv_end): + overlap_start = max(pstart, skernel) + overlap_end = min(pend, hv_end) + overlap_bytes = overlap_end - overlap_start + + # --- bold/red error header --- + print() + print(term_bold_red("╔══════════════════════════════════════════════════════════════╗")) + print(term_bold_red("║ HVISOR MEMORY REGION OVERLAP! ║")) + print(term_bold_red("╚══════════════════════════════════════════════════════════════╝")) + print() + + # --- what happened --- + print(f" hvisor physical memory: {term_bold(f'[{skernel:#x}, {hv_end:#x})')}") + print(f" overlaps ROOT_ZONE_MEMORY_REGIONS RAM range: " + f"{term_bold(f'[{pstart:#x}, {pend:#x})')}") + print(f" overlap: {term_bold_red(f'{overlap_bytes} bytes')} " + f"({term_bold(f'[{overlap_start:#x}, {overlap_end:#x})')})") + print() + + # --- danger description --- + print(f" {term_bold_red('DANGER')}: Linux in the root zone treats hvisor's") + print(f" physical pages as free memory. The kernel page allocator will") + print(f" hand them out to kernel or user code and write to them,") + print(f" {term_bold_red('corrupting hvisor page tables')} and causing unrecoverable panics.") + print() + + # --- fix instructions --- + print(f" {term_bold('Fix')}:") + print() + print(f" 1. Edit ROOT_ZONE_MEMORY_REGIONS in {term_bold(board_rs_path)}") + print(f" to exclude the hvisor range [{skernel:#x}, {hv_end:#x})") + print(f" from the overlapping MEM_TYPE_RAM region.") + print() + print(f" 2. Reduce hvisor's memory footprint to avoid overlap:") + print(f" - Ensure MODE=release (shrinks binary size)") + print(f" - Reduce HV_MEM_POOL_SIZE (src/consts.rs, currently 64MB)") + print(f" - Adjust BASE_ADDRESS in the linker script") + print() + + found_overlap = True + + if found_overlap: + return 1 + + print(f"OK: hvisor [{term_bold(f'{skernel:#x}')}, {term_bold(f'{hv_end:#x}')}) " + f"does not overlap any ROOT_ZONE_MEMORY_REGIONS RAM region") + return 0 + + +if __name__ == "__main__": + sys.exit(main()) diff --git a/tools/gen_cargo_config.sh b/tools/gen_cargo_config.sh deleted file mode 100755 index 3bb6832ab..000000000 --- a/tools/gen_cargo_config.sh +++ /dev/null @@ -1,60 +0,0 @@ -#!/bin/bash - -set -e - -CONFIG_TOML=".cargo/config.toml" -echo "" > $CONFIG_TOML - -function find_hvisor_src { - # find in ./CHANGELOG.md ../CHANGELOG.md - ret=$(find . -name CHANGELOG.md -exec grep -l "hvisor" {} \;) - if [ -z "$ret" ]; then - ret=$(find .. -name CHANGELOG.md -exec grep -l "hvisor" {} \;) - fi - if [ -z "$ret" ]; then - echo "." - fi - echo $(dirname $ret) -} - -CONFIG_TOML_TEMPLATE="platform/$ARCH/$BOARD/cargo/config.template.toml" -CONFIG_TOML_TEMPLATE=$(realpath $CONFIG_TOML_TEMPLATE) -TEMPLATE=$(cat $CONFIG_TOML_TEMPLATE) -LD_SCRIPT="platform/$ARCH/$BOARD/linker.ld" -LD_SCRIPT=$(realpath $LD_SCRIPT) -HVISOR_SRC=$(realpath $(find_hvisor_src)) -HOST_ARCH=$(uname -m) -OS=$(uname -s) -OS_VERSION=$(uname -r) -DISTRO=unknown -if [ -f /etc/os-release ]; then - DISTRO=$(grep '^ID=' /etc/os-release | cut -d= -f2) -fi - -echo "# Generated by gen_cargo_config.sh at $(date) ($(whoami)@$(hostname))" >> $CONFIG_TOML -echo "# BASH_VERSION = $BASH_VERSION" >> $CONFIG_TOML -echo "# HOST_ARCH = $HOST_ARCH" >> $CONFIG_TOML -echo "# OS_INFO = $OS $OS_VERSION $DISTRO" >> $CONFIG_TOML -echo "# ARCH = $ARCH" >> $CONFIG_TOML -echo "# BOARD = $BOARD" >> $CONFIG_TOML -echo "# FEATURES = $FEATURES" >> $CONFIG_TOML -echo "# HVISOR_SRC = $HVISOR_SRC" >> $CONFIG_TOML -echo "# LD_SCRIPT = $LD_SCRIPT" >> $CONFIG_TOML -echo "# TEMPLATE = $CONFIG_TOML_TEMPLATE" >> $CONFIG_TOML -echo "" >> $CONFIG_TOML - -# place holders: __XXX__ -> XXX -TEMPLATE=$(echo "$TEMPLATE" | sed -e 's/__ARCH__/'"$ARCH"'/g') -TEMPLATE=$(echo "$TEMPLATE" | sed -e 's/__BOARD__/'"$BOARD"'/g') - -echo "$TEMPLATE" >> $CONFIG_TOML - -# also generate a .config file in the HVISOR_SRC directory -CONFIG_FILE="$HVISOR_SRC/.config" -echo "ARCH=$ARCH" > $CONFIG_FILE -echo "BOARD=$BOARD" >> $CONFIG_FILE -echo "BID=$ARCH/$BOARD" >> $CONFIG_FILE -echo "FEATURES=$FEATURES" >> $CONFIG_FILE -echo "HVISOR_SRC=$HVISOR_SRC" >> $CONFIG_FILE -echo "LD_SCRIPT=$LD_SCRIPT" >> $CONFIG_FILE -echo "TEMPLATE=$CONFIG_TOML_TEMPLATE" >> $CONFIG_FILE \ No newline at end of file diff --git a/tools/gen_vscode_settings.sh b/tools/gen_vscode_settings.sh deleted file mode 100755 index 2d911faa0..000000000 --- a/tools/gen_vscode_settings.sh +++ /dev/null @@ -1,62 +0,0 @@ -#!/bin/bash -set -e - -function find_hvisor_src { - ret=$(find . -name CHANGELOG.md -exec grep -l "hvisor" {} \;) - if [ -z "$ret" ]; then - ret=$(find .. -name CHANGELOG.md -exec grep -l "hvisor" {} \;) - fi - if [ -z "$ret" ]; then - echo "ERROR: Could not locate hvisor source root (CHANGELOG.md with 'hvisor')" >&2 - exit 1 - fi - echo "$(dirname "$ret")" -} - -HVISOR_SRC=$(realpath $(find_hvisor_src)) -cd "$HVISOR_SRC" - -if [ -n "$BID" ]; then - ARCH=$(echo "$BID" | cut -d'/' -f1) - BOARD=$(echo "$BID" | cut -d'/' -f2) -fi - -if [ -z "$ARCH" ] || [ -z "$BOARD" ]; then - echo "ERROR: ARCH/BOARD not set, please use BID=arch/board or ARCH=... BOARD=..." - exit 1 -fi - -if [ -z "$FEATURES" ]; then - FEATURES=$(./tools/read_features.sh "$ARCH" "$BOARD") -fi - -FEATURES=$(echo "$FEATURES" | tr '\n' ' ' | tr -s ' ' | sed 's/^ *//;s/ *$//') - -case "$ARCH" in - aarch64) TARGET="aarch64-unknown-none" ;; - riscv64) TARGET="riscv64gc-unknown-none-elf" ;; - loongarch64) TARGET="loongarch64-unknown-none" ;; - x86_64) TARGET="x86_64-unknown-none" ;; - *) - echo "ERROR: Unsupported ARCH value: $ARCH" - exit 1 - ;; -esac - -mkdir -p .vscode - -cat > .vscode/settings.json <&2 + exit 1 +fi + +if [[ -x "${VENV}/bin/python" ]] && "${VENV}/bin/python" -c 'import kconfiglib, sys; __import__("tomllib" if sys.version_info >= (3, 11) else "tomli")' 2>/dev/null; then + exit 0 +fi + +if [[ ! -x "${VENV}/bin/pip" ]]; then + python3 -m venv "${VENV}" +fi +"${VENV}/bin/pip" install -q -r "${REQ}" diff --git a/tools/kconfig/host_config.sh b/tools/kconfig/host_config.sh new file mode 100755 index 000000000..fa40c950d --- /dev/null +++ b/tools/kconfig/host_config.sh @@ -0,0 +1,121 @@ +#!/usr/bin/env bash +# Host-side helpers that consume repo-root .config (Kconfig + metadata from kconfig_cli.py). +# Usage (from repo root, or any cwd — script cds to root): +# ./tools/kconfig/host_config.sh cargo # write .cargo/config.toml +# ./tools/kconfig/host_config.sh vscode # refresh .config + write .vscode/settings.json +set -euo pipefail + +SCRIPT_DIR="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)" +ROOT="$(cd "$SCRIPT_DIR/../.." && pwd)" +cd "$ROOT" + +KPY="$ROOT/tools/kconfig/.venv/bin/python" +CLI="$ROOT/tools/kconfig/kconfig_cli.py" + +cmd_gen_cargo() { + local CONFIG_TOML=".cargo/config.toml" + echo "" >"$CONFIG_TOML" + + if [ ! -f .config ]; then + echo "error: missing .config (run: make defconfig)" >&2 + exit 1 + fi + local ARCH BOARD HVISOR_SRC LD_SCRIPT CONFIG_TOML_TEMPLATE + ARCH=$(grep '^# ARCH=' .config 2>/dev/null | head -1 | sed 's/^# ARCH=//') + [ -n "$ARCH" ] || ARCH=$(grep '^ARCH=' .config | head -1 | cut -d= -f2-) + BOARD=$(grep '^# BOARD=' .config 2>/dev/null | head -1 | sed 's/^# BOARD=//') + [ -n "$BOARD" ] || BOARD=$(grep '^BOARD=' .config | head -1 | cut -d= -f2-) + HVISOR_SRC=$(grep '^# HVISOR_SRC=' .config 2>/dev/null | head -1 | sed 's/^# HVISOR_SRC=//') + [ -n "$HVISOR_SRC" ] || HVISOR_SRC=$(grep '^HVISOR_SRC=' .config | head -1 | cut -d= -f2-) + LD_SCRIPT=$(grep '^# LD_SCRIPT=' .config 2>/dev/null | head -1 | sed 's/^# LD_SCRIPT=//') + [ -n "$LD_SCRIPT" ] || LD_SCRIPT=$(grep '^LD_SCRIPT=' .config | head -1 | cut -d= -f2-) + CONFIG_TOML_TEMPLATE=$(grep '^# TEMPLATE=' .config 2>/dev/null | head -1 | sed 's/^# TEMPLATE=//') + [ -n "$CONFIG_TOML_TEMPLATE" ] || CONFIG_TOML_TEMPLATE=$(grep '^TEMPLATE=' .config | head -1 | cut -d= -f2-) + if [ -z "$ARCH" ] || [ -z "$BOARD" ] || [ -z "$HVISOR_SRC" ] || [ -z "$LD_SCRIPT" ] || [ -z "$CONFIG_TOML_TEMPLATE" ]; then + echo "error: .config missing ARCH/BOARD/HVISOR_SRC/LD_SCRIPT/TEMPLATE lines (run: make defconfig)" >&2 + exit 1 + fi + local TEMPLATE + TEMPLATE=$(cat "$CONFIG_TOML_TEMPLATE") + local HOST_ARCH OS OS_VERSION DISTRO + HOST_ARCH=$(uname -m) + OS=$(uname -s) + OS_VERSION=$(uname -r) + DISTRO=unknown + if [ -f /etc/os-release ]; then + DISTRO=$(grep '^ID=' /etc/os-release | cut -d= -f2) + fi + + { + echo "# Generated by tools/kconfig/host_config.sh cargo at $(date) ($(whoami)@$(hostname))" + echo "# BASH_VERSION = $BASH_VERSION" + echo "# HOST_ARCH = $HOST_ARCH" + echo "# OS_INFO = $OS $OS_VERSION $DISTRO" + echo "# ARCH = $ARCH" + echo "# BOARD = $BOARD" + echo "# (platform toggles come from .config CONFIG_* via build.rs)" + echo "# HVISOR_SRC = $HVISOR_SRC" + echo "# LD_SCRIPT = $LD_SCRIPT" + echo "# TEMPLATE = $CONFIG_TOML_TEMPLATE" + echo "" + } >>"$CONFIG_TOML" + + TEMPLATE=$(echo "$TEMPLATE" | sed -e 's/__ARCH__/'"$ARCH"'/g') + TEMPLATE=$(echo "$TEMPLATE" | sed -e 's/__BOARD__/'"$BOARD"'/g') + echo "$TEMPLATE" >>"$CONFIG_TOML" +} + +cmd_vscode() { + local ARCH="${ARCH:-}" BOARD="${BOARD:-}" + if [ -n "${BID:-}" ]; then + ARCH=$(echo "$BID" | cut -d'/' -f1) + BOARD=$(echo "$BID" | cut -d'/' -f2) + fi + if [ -z "$ARCH" ] || [ -z "$BOARD" ]; then + echo "ERROR: ARCH/BOARD not set, use BID=arch/board or ARCH=... BOARD=..." >&2 + exit 1 + fi + if [ ! -x "$KPY" ]; then + echo "ERROR: tools/kconfig/.venv missing. Run: ./tools/kconfig/bootstrap_venv.sh" >&2 + exit 1 + fi + ARCH="$ARCH" BOARD="$BOARD" "$KPY" "$CLI" defconfig + + local CFG_JSON + CFG_JSON=$("$KPY" "$CLI" vscode-cfgs .config kconfig/cfg_map.toml) + + local TARGET + case "$ARCH" in + aarch64) TARGET="aarch64-unknown-none" ;; + riscv64) TARGET="riscv64gc-unknown-none-elf" ;; + loongarch64) TARGET="loongarch64-unknown-none" ;; + x86_64) TARGET="x86_64-unknown-none" ;; + *) + echo "ERROR: Unsupported ARCH value: $ARCH" >&2 + exit 1 + ;; + esac + + mkdir -p .vscode + cat >.vscode/settings.json <&2 + exit 2 + ;; +esac diff --git a/tools/kconfig/kconfig_cli.py b/tools/kconfig/kconfig_cli.py new file mode 100644 index 000000000..c2fb208e6 --- /dev/null +++ b/tools/kconfig/kconfig_cli.py @@ -0,0 +1,168 @@ +#!/usr/bin/env python3 +"""Kconfig entrypoints: defconfig, menuconfig, vscode-cfgs.""" +from __future__ import annotations + +import argparse +import json +import os +import re +import sys +from pathlib import Path + +try: + import tomllib +except ModuleNotFoundError: # Python < 3.11 + import tomli as tomllib + +_KCONF_ARCH_TO_DIR: dict[str, str] = { + "ARCH_AARCH64": "aarch64", + "ARCH_RISCV64": "riscv64", + "ARCH_LOONGARCH64": "loongarch64", + "ARCH_X86_64": "x86_64", +} + + +def arch_from_kconf(kconf) -> str | None: + for sym_name, arch in _KCONF_ARCH_TO_DIR.items(): + sym = kconf.syms.get(sym_name) + if sym is not None and sym.str_value == "y": + return arch + return None + + +def write_root_dot_config(root: Path, arch: str, board: str, kconf) -> None: + """Write repo-root `.config`: comment metadata (Kconfig-safe) then kconfiglib body.""" + cfg = root / ".config" + derived = arch_from_kconf(kconf) + if derived is None: + raise SystemExit( + "Kconfig: no architecture selected; enable exactly one of " + "ARCH_AARCH64 / ARCH_RISCV64 / ARCH_LOONGARCH64 / ARCH_X86_64 in defconfig." + ) + if derived != arch: + raise SystemExit( + f"Kconfig architecture ({derived}) does not match " + f"platform path arch ({arch}) for board {board!r}. " + "Fix kconfig/defconfig or pick the correct ARCH/BOARD." + ) + arch_out = derived + ld = (root / "platform" / arch_out / board / "linker.ld").resolve() + tmpl = (root / "platform" / arch_out / board / "cargo" / "config.template.toml").resolve() + hvisor_src = str(root.resolve()) + bid = f"{arch_out}/{board}" + kconf.write_config(str(cfg)) + body = cfg.read_text() + meta = ( + f"# ARCH={arch_out}\n" + f"# BOARD={board}\n" + f"# BID={bid}\n" + f"# HVISOR_SRC={hvisor_src}\n" + f"# LD_SCRIPT={ld}\n" + f"# TEMPLATE={tmpl}\n" + "\n" + ) + cfg.write_text(meta + body) + + +def _repo_root() -> Path: + return Path(__file__).resolve().parents[2] + + +def cmd_defconfig() -> None: + arch = os.environ.get("ARCH", "") + board = os.environ.get("BOARD", "") + if not arch or not board: + print("error: set ARCH and BOARD", file=sys.stderr) + sys.exit(2) + root = _repo_root() + os.chdir(root) + try: + from kconfiglib import Kconfig + except ImportError: + print("error: pip install kconfiglib (see tools/kconfig/requirements.txt)", file=sys.stderr) + sys.exit(1) + kconf = Kconfig(str(root / "kconfig" / "Kconfig")) + defcfg = root / "platform" / arch / board / "kconfig" / "defconfig" + if not defcfg.is_file(): + print(f"error: missing {defcfg}", file=sys.stderr) + sys.exit(1) + kconf.load_config(str(defcfg)) + write_root_dot_config(root, arch, board, kconf) + print(f"wrote .config for {arch}/{board}") + + +def cmd_menuconfig() -> None: + arch = os.environ.get("ARCH", "") + board = os.environ.get("BOARD", "") + if not arch or not board: + print("error: set ARCH and BOARD", file=sys.stderr) + sys.exit(2) + root = _repo_root() + os.chdir(root) + try: + from kconfiglib import Kconfig + except ImportError as e: + print(f"error: kconfiglib is not installed: {e}", file=sys.stderr) + print("hint: tools/kconfig/.venv/bin/pip install -r tools/kconfig/requirements.txt", file=sys.stderr) + sys.exit(1) + try: + import menuconfig as kc_menu + except ImportError as e: + print(f"error: kconfiglib TUI (menuconfig) could not load: {e}", file=sys.stderr) + print( + "hint: the UI needs Python stdlib curses. " + "Debian/Ubuntu: apt install python3-curses; Fedora: dnf install python3-curses; " + "Windows: pip install windows-curses", + file=sys.stderr, + ) + sys.exit(1) + kconf = Kconfig(str(root / "kconfig" / "Kconfig")) + cfg = root / ".config" + defcfg = root / "platform" / arch / board / "kconfig" / "defconfig" + if cfg.is_file(): + kconf.load_config(str(cfg)) + elif defcfg.is_file(): + kconf.load_config(str(defcfg)) + kc_menu.menuconfig(kconf) + write_root_dot_config(root, arch, board, kconf) + + +def cmd_vscode_cfgs(cfg_path: Path, map_path: Path) -> None: + sym = tomllib.loads(map_path.read_text(encoding="utf-8"))["symbols"] + enabled: set[str] = set() + for line in cfg_path.read_text().splitlines(): + line = line.strip() + m = re.match(r"^(CONFIG_[A-Z0-9_]+)=(y|m)$", line) + if not m: + continue + k = m.group(1) + if k in sym: + enabled.add(sym[k]) + print(json.dumps(sorted(enabled))) + + +def main() -> int: + p = argparse.ArgumentParser(description="hvisor Kconfig helpers") + sub = p.add_subparsers(dest="cmd", required=True) + + sub.add_parser("defconfig", help="merge board defconfig + Kconfig into repo-root .config (env ARCH, BOARD)") + sub.add_parser( + "menuconfig", + help="interactive Kconfig UI (env ARCH, BOARD); do not name this file menuconfig.py", + ) + p_vc = sub.add_parser("vscode-cfgs", help="emit JSON array of rustc cfg names for rust-analyzer") + p_vc.add_argument("config", type=Path, help="path to repo-root .config") + p_vc.add_argument("map", type=Path, help="path to kconfig/cfg_map.toml") + + args = p.parse_args() + if args.cmd == "defconfig": + cmd_defconfig() + elif args.cmd == "menuconfig": + cmd_menuconfig() + elif args.cmd == "vscode-cfgs": + cmd_vscode_cfgs(args.config, args.map) + return 0 + + +if __name__ == "__main__": + raise SystemExit(main()) diff --git a/tools/kconfig/requirements.txt b/tools/kconfig/requirements.txt new file mode 100644 index 000000000..1e0d7bc4a --- /dev/null +++ b/tools/kconfig/requirements.txt @@ -0,0 +1,3 @@ +PySocks>=1.7.1 +kconfiglib>=14.1.0 +tomli>=2.0.1; python_version < "3.11" diff --git a/tools/kconfig/save_defconfig.sh b/tools/kconfig/save_defconfig.sh new file mode 100755 index 000000000..f474d5d3a --- /dev/null +++ b/tools/kconfig/save_defconfig.sh @@ -0,0 +1,17 @@ +#!/usr/bin/env bash +# Write CONFIG_* lines from repo-root .config to the board defconfig (sorted). +set -euo pipefail +ARCH="${1:?arch}" +BOARD="${2:?board}" +SCRIPT_DIR="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)" +ROOT="$(cd "$SCRIPT_DIR/../.." && pwd)" +cd "$ROOT" + +OUT="platform/${ARCH}/${BOARD}/kconfig/defconfig" +mkdir -p "$(dirname "$OUT")" +if [[ ! -f .config ]]; then + echo "error: no .config in repo root" >&2 + exit 1 +fi +grep '^CONFIG_' .config | LC_ALL=C sort >"$OUT" +echo "wrote $OUT" diff --git a/tools/license_checker.sh b/tools/license_checker.sh index 5a4fdb5d4..e9f004887 100755 --- a/tools/license_checker.sh +++ b/tools/license_checker.sh @@ -12,7 +12,8 @@ while read -r file; do fi done < <(find . -type f -name "*.rs" \ -not \( -path "./vendor/*" -prune \) \ - -not \( -path "./target/*" -prune \)) + -not \( -path "./target/*" -prune \) \ + -not \( -path "./hvisor-tool/*" -prune \)) echo $ec exit $ec \ No newline at end of file diff --git a/tools/read_features.sh b/tools/read_features.sh deleted file mode 100755 index 81b0b4841..000000000 --- a/tools/read_features.sh +++ /dev/null @@ -1,12 +0,0 @@ -#!/bin/bash - -set -e - -ARCH=$1 -BOARD=$2 - -FEATURES="platform/$ARCH/$BOARD/cargo/features" -FEATURES=$(cat $FEATURES) -FEATURES=$(echo $FEATURES | tr '\n' ' ') -FEATURES=$(echo $FEATURES | tr -d '\r') -echo $FEATURES