From b546f772717584e5a8421ebd0d77fa954c68d919 Mon Sep 17 00:00:00 2001 From: "rust-mos-sync[bot]" Date: Fri, 16 Oct 2026 11:22:37 +0000 Subject: [PATCH 1/2] versions.toml: bump rust.stable to 1.99.1 --- versions.toml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/versions.toml b/versions.toml index b076255..33ef2ba 100644 --- a/versions.toml +++ b/versions.toml @@ -2,7 +2,7 @@ # Read and written only through scripts/lib.sh (ver_get / ver_set). [rust.stable] -tag = "1.99.0" +tag = "1.99.1" llvm_branch = "rustc/23.1-2026-07-22" llvm_commit = "1b9c0d5ff9bbe7634aead059efe6b11a7eeba145" @@ -31,4 +31,4 @@ sha256 = "4d6c9f1833666261a3178906cef11d9544b0f3a8c238f9c288073a8055ae9e61" commit = "0eaa8d9762d02631346bdd90ddd67bcc851ad75e" [release] -mos_revision = 2 +mos_revision = 1 From bd6e02281cfaffd44ad9a0006c9bbee02d45c98b Mon Sep 17 00:00:00 2001 From: "rust-mos-sync[bot]" Date: Fri, 16 Oct 2026 12:25:18 +0000 Subject: [PATCH 2/2] patches: regenerate after the stable sync --- .../0001-MOS-Add-the-llvm-mos-backend.patch | 28 +++++++++---------- ...dd-MOS-6502-targets-llvm-mos-backend.patch | 4 +-- 2 files changed, 16 insertions(+), 16 deletions(-) diff --git a/patches/llvm/23.1/0001-MOS-Add-the-llvm-mos-backend.patch b/patches/llvm/23.1/0001-MOS-Add-the-llvm-mos-backend.patch index 8d3193a..981f39f 100644 --- a/patches/llvm/23.1/0001-MOS-Add-the-llvm-mos-backend.patch +++ b/patches/llvm/23.1/0001-MOS-Add-the-llvm-mos-backend.patch @@ -2037,7 +2037,7 @@ index 6fdd603092fc6b32ab479d444944e013cb5ba274..a804e4d112bbb0cb8e689c9e92bc20ef /// The integer bit size to use for SjLj based exception handling. diff --git a/llvm/include/llvm/TargetParser/Triple.h b/llvm/include/llvm/TargetParser/Triple.h -index c5af232523c695764e369a29ec85e875e9ab1696..816dfa22447af1b43b8df14404170226fb99278c 100644 +index d819c4975b13e5190611b78c8e37cb95e5ebde19..c0b9e8de2c7c71dfc3f8b48fdecea834b46ae3c4 100644 --- a/llvm/include/llvm/TargetParser/Triple.h +++ b/llvm/include/llvm/TargetParser/Triple.h @@ -68,6 +68,7 @@ public: @@ -2048,7 +2048,7 @@ index c5af232523c695764e369a29ec85e875e9ab1696..816dfa22447af1b43b8df14404170226 msp430, // MSP430: msp430 ppc, // PPC: powerpc ppcle, // PPCLE: powerpc (little endian) -@@ -1237,6 +1238,11 @@ public: +@@ -1230,6 +1231,11 @@ public: return Env == Triple::GNUX32 || Env == Triple::MuslX32; } @@ -30537,10 +30537,10 @@ index bf91c53270067f85681d6119d083aeb60537fcfd..ced5562296ec28582028bc66b27595bc MRI = &MF.getRegInfo(); } diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp -index 8eb20927fb8a088627d48b81ddaf415ffa7da72c..5f682325af35739bf5bb653c16012c83b69c68f6 100644 +index bbd1738cd511719ffe260c23d3e6c938ec6b8d58..e98e31f831af20874d05beb988c767541d4ba35f 100644 --- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp -@@ -2634,6 +2634,8 @@ bool RISCVFrameLowering::isSupportedStackID(TargetStackID::Value ID) const { +@@ -2629,6 +2629,8 @@ bool RISCVFrameLowering::isSupportedStackID(TargetStackID::Value ID) const { case TargetStackID::SGPRSpill: case TargetStackID::WasmLocal: case TargetStackID::ScalablePredicateVector: @@ -30678,7 +30678,7 @@ index 18f0c13907e52db48fca08f65cf54f1f49b46a20..4457b7f163838cb2489f5d9064ffe86f return "e-m:e-p:16:16-i32:16-i64:16-f32:16-f64:16-a:8-n8:16-S16"; case Triple::ppc: diff --git a/llvm/lib/TargetParser/Triple.cpp b/llvm/lib/TargetParser/Triple.cpp -index 2e4fe7ce70887e38e54239a9f2c6f10bd1873efe..8e1129b1a102cd0f9f5497fe3ab4d011a7b54a4b 100644 +index 356782c1f6ad49fa75ea774c96865ea401cec0b8..d88fad94c036689766d328060c6eec4449d0ec76 100644 --- a/llvm/lib/TargetParser/Triple.cpp +++ b/llvm/lib/TargetParser/Triple.cpp @@ -92,6 +92,8 @@ StringRef Triple::getArchTypeName(ArchType Kind) { @@ -30690,7 +30690,7 @@ index 2e4fe7ce70887e38e54239a9f2c6f10bd1873efe..8e1129b1a102cd0f9f5497fe3ab4d011 case msp430: return "msp430"; case nvptx64: -@@ -412,6 +414,9 @@ StringRef Triple::getArchTypePrefix(ArchType Kind) { +@@ -410,6 +412,9 @@ StringRef Triple::getArchTypePrefix(ArchType Kind) { case loongarch64: return "loongarch"; @@ -30700,7 +30700,7 @@ index 2e4fe7ce70887e38e54239a9f2c6f10bd1873efe..8e1129b1a102cd0f9f5497fe3ab4d011 case dxil: return "dx"; -@@ -567,6 +572,7 @@ Triple::ArchType Triple::getArchTypeForLLVMName(StringRef Name) { +@@ -565,6 +570,7 @@ Triple::ArchType Triple::getArchTypeForLLVMName(StringRef Name) { .Case("csky", csky) .Case("loongarch32", loongarch32) .Case("loongarch64", loongarch64) @@ -30708,7 +30708,7 @@ index 2e4fe7ce70887e38e54239a9f2c6f10bd1873efe..8e1129b1a102cd0f9f5497fe3ab4d011 .Case("dxil", dxil) .Case("xtensa", xtensa) .Default(UnknownArch); -@@ -666,6 +672,7 @@ Triple::ArchType Triple::parseArch(StringRef ArchName) { +@@ -663,6 +669,7 @@ Triple::ArchType Triple::parseArch(StringRef ArchName) { .Case("thumbeb", Triple::thumbeb) .Case("avr", Triple::avr) .Case("m68k", Triple::m68k) @@ -30716,7 +30716,7 @@ index 2e4fe7ce70887e38e54239a9f2c6f10bd1873efe..8e1129b1a102cd0f9f5497fe3ab4d011 .Case("msp430", Triple::msp430) .Cases({"mips", "mipseb", "mipsallegrex", "mipsisa32r6", "mipsr6"}, Triple::mips) -@@ -1026,6 +1033,7 @@ static Triple::ObjectFormatType getDefaultFormat(const Triple &T) { +@@ -1021,6 +1028,7 @@ static Triple::ObjectFormatType getDefaultFormat(const Triple &T) { case Triple::mips64: case Triple::mips64el: case Triple::mips: @@ -30724,7 +30724,7 @@ index 2e4fe7ce70887e38e54239a9f2c6f10bd1873efe..8e1129b1a102cd0f9f5497fe3ab4d011 case Triple::msp430: case Triple::nvptx64: case Triple::nvptx: -@@ -1779,6 +1787,7 @@ unsigned Triple::getArchPointerBitWidth(llvm::Triple::ArchType Arch) { +@@ -1774,6 +1782,7 @@ unsigned Triple::getArchPointerBitWidth(llvm::Triple::ArchType Arch) { return 0; case llvm::Triple::avr: @@ -30732,7 +30732,7 @@ index 2e4fe7ce70887e38e54239a9f2c6f10bd1873efe..8e1129b1a102cd0f9f5497fe3ab4d011 case llvm::Triple::msp430: return 16; -@@ -1887,6 +1896,7 @@ Triple Triple::get32BitArchVariant() const { +@@ -1882,6 +1891,7 @@ Triple Triple::get32BitArchVariant() const { case Triple::avr: case Triple::bpfeb: case Triple::bpfel: @@ -30740,7 +30740,7 @@ index 2e4fe7ce70887e38e54239a9f2c6f10bd1873efe..8e1129b1a102cd0f9f5497fe3ab4d011 case Triple::msp430: case Triple::systemz: case Triple::ve: -@@ -2005,6 +2015,7 @@ Triple Triple::get64BitArchVariant() const { +@@ -2000,6 +2010,7 @@ Triple Triple::get64BitArchVariant() const { case Triple::kalimba: case Triple::lanai: case Triple::m68k: @@ -30748,7 +30748,7 @@ index 2e4fe7ce70887e38e54239a9f2c6f10bd1873efe..8e1129b1a102cd0f9f5497fe3ab4d011 case Triple::msp430: case Triple::r600: case Triple::shave: -@@ -2131,6 +2142,7 @@ Triple Triple::getBigEndianArchVariant() const { +@@ -2126,6 +2137,7 @@ Triple Triple::getBigEndianArchVariant() const { case Triple::kalimba: case Triple::loongarch32: case Triple::loongarch64: @@ -30756,7 +30756,7 @@ index 2e4fe7ce70887e38e54239a9f2c6f10bd1873efe..8e1129b1a102cd0f9f5497fe3ab4d011 case Triple::msp430: case Triple::nvptx64: case Triple::nvptx: -@@ -2271,6 +2283,7 @@ bool Triple::isLittleEndian() const { +@@ -2266,6 +2278,7 @@ bool Triple::isLittleEndian() const { case Triple::loongarch64: case Triple::mips64el: case Triple::mipsel: diff --git a/patches/rust/1.99/0001-Add-MOS-6502-targets-llvm-mos-backend.patch b/patches/rust/1.99/0001-Add-MOS-6502-targets-llvm-mos-backend.patch index 2e85366..2351764 100644 --- a/patches/rust/1.99/0001-Add-MOS-6502-targets-llvm-mos-backend.patch +++ b/patches/rust/1.99/0001-Add-MOS-6502-targets-llvm-mos-backend.patch @@ -102,7 +102,7 @@ index 8d99035fd0db40c13d6e43ce1332904217ffe317..89f438426d6a7748f258d4b31e71af6b } } diff --git a/compiler/rustc_target/src/callconv/mod.rs b/compiler/rustc_target/src/callconv/mod.rs -index a06a6a0a69e12b8a774f9990995b4ceecac85720..37e195f604ea71fec44ac7e38ae92e0f42d585c9 100644 +index 2a10921f99578df47c4aea6d5582c7c5b9f3bde4..f1026e96b53ebb09e2c7d04a1564fb9a20bb2089 100644 --- a/compiler/rustc_target/src/callconv/mod.rs +++ b/compiler/rustc_target/src/callconv/mod.rs @@ -19,6 +19,7 @@ @@ -113,7 +113,7 @@ index a06a6a0a69e12b8a774f9990995b4ceecac85720..37e195f604ea71fec44ac7e38ae92e0f mod mips; mod mips64; mod msp430; -@@ -702,6 +703,7 @@ pub fn adjust_for_foreign_abi(&mut self, cx: &C, abi: ExternAbi) +@@ -704,6 +705,7 @@ pub fn adjust_for_foreign_abi(&mut self, cx: &C, abi: ExternAbi) Arch::Avr => avr::compute_abi_info(cx, self), Arch::LoongArch32 | Arch::LoongArch64 => loongarch::compute_abi_info(cx, self), Arch::M68k => m68k::compute_abi_info(cx, self),