Context
PR #112 introduced rdtsc-based timestamps on x86_64. The rdtsc instruction reads the Time Stamp Counter, which is not guaranteed to be monotonic across cores on pre-Nehalem (pre-2008) x86_64 processors. The current implementation does not verify invariant TSC support via CPUID.
On modern hardware (Nehalem and later), the TSC is invariant and synchronized across cores, so this is near-theoretical. However, the limitation should be documented for completeness.
Proposed Change
Add a comment block in piano-runtime/src/tsc.rs documenting:
- The reliance on invariant TSC (available since Nehalem / CPUID leaf 0x80000007 bit 8)
- That on pre-Nehalem processors,
rdtsc may not be monotonic across cores, which could cause negative elapsed times if a thread migrates between cores between the enter and exit timestamps
- That this is not checked at runtime, and the practical impact is negligible on any hardware from the last ~15 years
Optionally, mention this in piano-runtime's crate-level documentation if there is a public-facing docs section.
Scope
Context
PR #112 introduced
rdtsc-based timestamps on x86_64. Therdtscinstruction reads the Time Stamp Counter, which is not guaranteed to be monotonic across cores on pre-Nehalem (pre-2008) x86_64 processors. The current implementation does not verify invariant TSC support via CPUID.On modern hardware (Nehalem and later), the TSC is invariant and synchronized across cores, so this is near-theoretical. However, the limitation should be documented for completeness.
Proposed Change
Add a comment block in
piano-runtime/src/tsc.rsdocumenting:rdtscmay not be monotonic across cores, which could cause negative elapsed times if a thread migrates between cores between the enter and exit timestampsOptionally, mention this in piano-runtime's crate-level documentation if there is a public-facing docs section.
Scope
piano-runtime/src/tsc.rs