From d99ddb491c651702768cbd601c923cba7ec81d43 Mon Sep 17 00:00:00 2001 From: Biancaa Ramesh Date: Mon, 1 Dec 2025 18:17:13 +0530 Subject: [PATCH] Minor fixes to spel --- firmware/fw_base.S | 2 +- platform/generic/include/thead/c9xx_encoding.h | 4 ++-- platform/generic/platform.c | 2 +- platform/nuclei/ux600/platform.c | 2 +- platform/template/objects.mk | 2 +- 5 files changed, 6 insertions(+), 6 deletions(-) diff --git a/firmware/fw_base.S b/firmware/fw_base.S index 5300ecf22e0..79ca2beb952 100644 --- a/firmware/fw_base.S +++ b/firmware/fw_base.S @@ -253,7 +253,7 @@ _scratch_init: blt t1, s7, _scratch_init /* - * Relocate Flatened Device Tree (FDT) + * Relocate Flattened Device Tree (FDT) * source FDT address = previous arg1 * destination FDT address = next arg1 * diff --git a/platform/generic/include/thead/c9xx_encoding.h b/platform/generic/include/thead/c9xx_encoding.h index a45b171e521..aacd3065b94 100644 --- a/platform/generic/include/thead/c9xx_encoding.h +++ b/platform/generic/include/thead/c9xx_encoding.h @@ -96,13 +96,13 @@ /* T-HEAD C9xx U mode CSR. */ #define THEAD_C9XX_CSR_FXCR 0x800 -/* T-HEAD C9xx MMU extentions. */ +/* T-HEAD C9xx MMU extensions. */ #define THEAD_C9XX_CSR_SMIR 0x9c0 #define THEAD_C9XX_CSR_SMEL 0x9c1 #define THEAD_C9XX_CSR_SMEH 0x9c2 #define THEAD_C9XX_CSR_SMCIR 0x9c3 -/* T-HEAD C9xx Security CSR(May be droped). */ +/* T-HEAD C9xx Security CSR(May be dropped). */ #define THEAD_C9XX_CSR_MEBR 0xbe0 #define THEAD_C9XX_CSR_NT_MSTATUS 0xbe1 #define THEAD_C9XX_CSR_NT_MIE 0xbe2 diff --git a/platform/generic/platform.c b/platform/generic/platform.c index e66f99fa8a8..0c2650c8f7f 100644 --- a/platform/generic/platform.c +++ b/platform/generic/platform.c @@ -312,7 +312,7 @@ uint64_t generic_pmu_xlate_to_mhpmevent(uint32_t event_idx, uint64_t data) /** * Generic platform follows the SBI specification recommendation * i.e. zero extended event_idx is used as mhpmevent value for - * hardware general/cache events if platform does't define one. + * hardware general/cache events if platform doesn't define one. */ evt_val = fdt_pmu_get_select_value(event_idx); if (!evt_val) diff --git a/platform/nuclei/ux600/platform.c b/platform/nuclei/ux600/platform.c index 14fbaeb6c07..d3da213f1a0 100644 --- a/platform/nuclei/ux600/platform.c +++ b/platform/nuclei/ux600/platform.c @@ -30,7 +30,7 @@ #define UX600_NUCLEI_TIMER_ADDR 0x2000000 #define UX600_NUCLEI_TIMER_MSFTRST_OFS 0xFF0 #define UX600_NUCLEI_TIMER_MSFTRST_KEY 0x80000A5F -/* The clint compatiable timer offset is 0x1000 against nuclei timer */ +/* The clint compatible timer offset is 0x1000 against nuclei timer */ #define UX600_CLINT_TIMER_ADDR (UX600_NUCLEI_TIMER_ADDR + 0x1000) #define UX600_ACLINT_MSWI_ADDR (UX600_CLINT_TIMER_ADDR + \ CLINT_MSWI_OFFSET) diff --git a/platform/template/objects.mk b/platform/template/objects.mk index f240a5576eb..a55a43bb1d8 100644 --- a/platform/template/objects.mk +++ b/platform/template/objects.mk @@ -23,7 +23,7 @@ platform-ldflags-y = # # Platform RISC-V XLEN, ABI, ISA and Code Model configuration. -# These are optional parameters but platforms can optionaly provide it. +# These are optional parameters but platforms can optionally provide it. # Some of these are guessed based on GCC compiler capabilities # # PLATFORM_RISCV_XLEN = 64