From c3b7ad6d294eeb83585def02d2cd203689fc1dfa Mon Sep 17 00:00:00 2001 From: Sean Dolbec Date: Sun, 1 Nov 2026 20:58:50 -0500 Subject: [PATCH 01/12] dt-bindings: apple: Add the T8132 compatibles the Mac mini boots with The M4 (T8132) Mac mini needs its NVMe controller, the SART, the SMC, the SPMI controllers, the PCIe controller and their DARTs and mailboxes before it can boot from its SSD and reach the network. Each block works with an existing generation's driver, so add the T8132 compatibles with the fallbacks T8122 and T8140 already use: - apple,t8132-dart (apple,t8110-dart) - apple,t8132-sart (apple,t6000-sart) - apple,t8132-asc-mailbox (apple,asc-mailbox-v4) - apple,t8132-smc (apple,t8103-smc) - apple,t8132-spmi (apple,t8103-spmi) - apple,t8132-pcie (apple,t6020-pcie), next to apple,t8122-pcie - apple,abbey-pmic (apple,spmi-nvmem), the T8132 main PMU A J773g runs today with these compatibles and fallbacks under GravityLinux's gravity-m4 kernel. The DART and mailbox lines are the same as in the open omacom/linux-aurora #200 (T8132 SEP); whichever change lands second drops them. Signed-off-by: Sean Dolbec Co-Authored-By: Claude Opus 5.5 --- Documentation/devicetree/bindings/iommu/apple,dart.yaml | 1 + Documentation/devicetree/bindings/iommu/apple,sart.yaml | 1 + Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml | 1 + Documentation/devicetree/bindings/mfd/apple,smc.yaml | 1 + Documentation/devicetree/bindings/nvmem/apple,spmi-nvmem.yaml | 1 + Documentation/devicetree/bindings/pci/apple,pcie.yaml | 4 +++- Documentation/devicetree/bindings/spmi/apple,spmi.yaml | 1 + 7 files changed, 9 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/iommu/apple,dart.yaml b/Documentation/devicetree/bindings/iommu/apple,dart.yaml index 44a0499ada2cbc..ad3f8e90338618 100644 --- a/Documentation/devicetree/bindings/iommu/apple,dart.yaml +++ b/Documentation/devicetree/bindings/iommu/apple,dart.yaml @@ -37,6 +37,7 @@ properties: - enum: - apple,t6020-dart - apple,t8122-dart + - apple,t8132-dart - apple,t8140-dart - apple,t8142-dart - const: apple,t8110-dart diff --git a/Documentation/devicetree/bindings/iommu/apple,sart.yaml b/Documentation/devicetree/bindings/iommu/apple,sart.yaml index 472454c3d24d67..e2e5da6504f11c 100644 --- a/Documentation/devicetree/bindings/iommu/apple,sart.yaml +++ b/Documentation/devicetree/bindings/iommu/apple,sart.yaml @@ -34,6 +34,7 @@ properties: - apple,t6020-sart - apple,t8112-sart - apple,t8122-sart + - apple,t8132-sart - apple,t8140-sart - const: apple,t6000-sart - enum: diff --git a/Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml b/Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml index 8d66dc77c0a54e..7e7644c1732e34 100644 --- a/Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml +++ b/Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml @@ -31,6 +31,7 @@ properties: - apple,t8103-asc-mailbox - apple,t8112-asc-mailbox - apple,t8122-asc-mailbox + - apple,t8132-asc-mailbox - apple,t8140-asc-mailbox - apple,t8142-asc-mailbox - apple,t6000-asc-mailbox diff --git a/Documentation/devicetree/bindings/mfd/apple,smc.yaml b/Documentation/devicetree/bindings/mfd/apple,smc.yaml index 31d1940f9d3dc0..ff42e94cf252d8 100644 --- a/Documentation/devicetree/bindings/mfd/apple,smc.yaml +++ b/Documentation/devicetree/bindings/mfd/apple,smc.yaml @@ -20,6 +20,7 @@ properties: - enum: - apple,t6020-smc - apple,t8122-smc + - apple,t8132-smc - apple,t8140-smc - apple,t8142-smc - const: apple,t8103-smc diff --git a/Documentation/devicetree/bindings/nvmem/apple,spmi-nvmem.yaml b/Documentation/devicetree/bindings/nvmem/apple,spmi-nvmem.yaml index 09cdd776f8d8bd..2eecc48c9b0616 100644 --- a/Documentation/devicetree/bindings/nvmem/apple,spmi-nvmem.yaml +++ b/Documentation/devicetree/bindings/nvmem/apple,spmi-nvmem.yaml @@ -18,6 +18,7 @@ properties: compatible: items: - enum: + - apple,abbey-pmic - apple,baku-pmic - apple,maverick-pmic - apple,sera-pmic diff --git a/Documentation/devicetree/bindings/pci/apple,pcie.yaml b/Documentation/devicetree/bindings/pci/apple,pcie.yaml index df7ef17ae8d2fb..3274a787e0f67b 100644 --- a/Documentation/devicetree/bindings/pci/apple,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/apple,pcie.yaml @@ -56,7 +56,9 @@ properties: - apple,t6000-pcie - const: apple,pcie - items: - - const: apple,t8122-pcie + - enum: + - apple,t8122-pcie + - apple,t8132-pcie - const: apple,t6020-pcie - const: apple,t6020-pcie - const: apple,t8140-pcie diff --git a/Documentation/devicetree/bindings/spmi/apple,spmi.yaml b/Documentation/devicetree/bindings/spmi/apple,spmi.yaml index f88e21c348667b..931d5c1d369387 100644 --- a/Documentation/devicetree/bindings/spmi/apple,spmi.yaml +++ b/Documentation/devicetree/bindings/spmi/apple,spmi.yaml @@ -25,6 +25,7 @@ properties: - apple,t8012-spmi - apple,t8015-spmi - apple,t8122-spmi + - apple,t8132-spmi - apple,t8140-spmi - const: apple,t8103-spmi - items: From 85e94e2768d22fff34340b49d77fae92560d0ab8 Mon Sep 17 00:00:00 2001 From: Yureka Lilian Date: Sat, 25 Jul 2026 16:48:30 +0200 Subject: [PATCH 02/12] arm64: dts: apple: t8132: Add the SMC and its mailbox Describe the T8132 System Management Controller and its ASC mailbox. The SMC's GPIO controller switches the power of the PCIe Wi-Fi port and the SMC handles power-off, reboot, the RTC and the power button, so every T8132 board needs it before it can run from its own storage and network. Both nodes stay disabled; a board enables them. [sdolbec: Ported from GravityLinux gravity-m4 commit be925f37d4ef ("t8132 smc"), a cherry-pick of Yureka's commit d7525ca925b6 ("t8132 smc"). Renamed mbox@ to mailbox@ and added status = "disabled", as t8140.dtsi does. The original commit carries no Signed-off-by; it is forwarded here under DCO clause (b), and Yureka's Signed-off-by should be added before this is merged. The J773g runs these nodes, unchanged apart from the status, under that kernel.] Signed-off-by: Sean Dolbec Co-Authored-By: Claude Opus 5.5 --- arch/arm64/boot/dts/apple/t8132.dtsi | 29 ++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8132.dtsi b/arch/arm64/boot/dts/apple/t8132.dtsi index afec92a0601562..72bb9d0e0646f8 100644 --- a/arch/arm64/boot/dts/apple/t8132.dtsi +++ b/arch/arm64/boot/dts/apple/t8132.dtsi @@ -451,6 +451,35 @@ status = "disabled"; }; + + smc_mbox: mailbox@38c608000 { + compatible = "apple,t8132-asc-mailbox", "apple,asc-mailbox-v4"; + reg = <0x3 0x8c608000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = , + , + , + ; + interrupt-names = "send-empty", "send-not-empty", + "recv-empty", "recv-not-empty"; + #mbox-cells = <0>; + status = "disabled"; + }; + + smc: smc@38c600000 { + compatible = "apple,t8132-smc", "apple,t8103-smc"; + reg = <0x3 0x8c600000 0x0 0x4000>, + <0x3 0x8de00000 0x0 0x100000>; + reg-names = "smc", "sram"; + mboxes = <&smc_mbox>; + status = "disabled"; + + smc_gpio: gpio { + compatible = "apple,smc-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + }; }; timer { From cbeeb00e88f5d55070979ed6eec69942e485a3af Mon Sep 17 00:00:00 2001 From: Yureka Lilian Date: Sat, 25 Jul 2026 23:15:24 +0200 Subject: [PATCH 03/12] arm64: dts: apple: t8132: Add NVMe nodes Describe the T8132 ANS2 NVMe controller, its SART and its mailbox. Signed-off-by: Yureka Lilian [sdolbec: Ported from GravityLinux gravity-m4 79b86cbb4473, a cherry-pick of Yureka's 9a864cea9329. Renamed mbox@ to mailbox@ and sart@ to iommu@ and added status = "disabled" to all three nodes, as t8140.dtsi does. Added the one-line description above.] Signed-off-by: Sean Dolbec Co-Authored-By: Claude Opus 5.5 --- arch/arm64/boot/dts/apple/t8132.dtsi | 43 ++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8132.dtsi b/arch/arm64/boot/dts/apple/t8132.dtsi index 72bb9d0e0646f8..c147568e732d2b 100644 --- a/arch/arm64/boot/dts/apple/t8132.dtsi +++ b/arch/arm64/boot/dts/apple/t8132.dtsi @@ -480,6 +480,49 @@ #gpio-cells = <2>; }; }; + + ans_mbox: mailbox@481608000 { + compatible = "apple,t8132-asc-mailbox", "apple,asc-mailbox-v4"; + reg = <0x4 0x81608000 0x0 0x4000>; + + interrupt-parent = <&aic>; + interrupts = , + , + , + ; + interrupt-names = "send-empty", "send-not-empty", + "recv-empty", "recv-not-empty"; + + #mbox-cells = <0>; + power-domains = <&ps_ans>; + status = "disabled"; + }; + + sart: iommu@485c50000 { + compatible = "apple,t8132-sart", "apple,t6000-sart"; + reg = <0x4 0x85c50000 0x0 0x10000>; + power-domains = <&ps_ans>; + status = "disabled"; + }; + + nvme: nvme@4c5cc0000 { + compatible = "apple,t8132-nvme-ans2"; + reg = <0x4 0xc5cc0000 0x0 0x60000>, + <0x4 0x81600000 0x0 0x4000>; + reg-names = "nvme", "ans"; + + interrupt-parent = <&aic>; + interrupts = ; + + mboxes = <&ans_mbox>; + + power-domains = <&ps_ans>, <&ps_apcie_sys_st>; + power-domain-names = "ans", "apcie0"; + resets = <&ps_ans>; + + apple,sart = <&sart>; + status = "disabled"; + }; }; timer { From b3d59b4a50c9011a973039ec724fcd9db4941cc2 Mon Sep 17 00:00:00 2001 From: Sean Dolbec Date: Sun, 1 Nov 2026 21:00:24 -0500 Subject: [PATCH 04/12] arm64: dts: apple: t8132: Describe the NVMe controller and NVMMU windows This tree's T8132 ANS2 support (apple_nvme_t8132_hw) maps the NVMMU from its own "nvmmu" resource and fails to probe without it. The T8132 ANS has two windows: the ADT's /arm-io/ans reg[9] is the NVMe controller and reg[3] is the NVMMU, the split m1n1 uses for every chip with nvme-secure-bar. On T8132 they are at 0x4c5cc0000 and 0x485cc0000, the same layout as T8140 (0x3cdcc0000 and 0x38dcc0000). Add the 0x60000 NVMMU window, which holds the TCB registers at +0x28100..+0x28120. Keep the controller window at 0x60000 rather than the 0x28000 the linear queue registers need: GravityLinux's driver reaches the NVMMU registers through this alias at the same offsets, and our J773g runs from its SSD that way today. Keeping the window lets one device tree boot both kernels, which matters while J773g owners move between them and as a fallback while this tree is tested. The window split follows KB2UKA's reading of the J713 ADT (Kb2uka/Omarchy-M4-Native, "fix(dts): t8132: split M4 NVMe and NVMMU windows"). This layout has not been booted with this tree's driver yet. Signed-off-by: Sean Dolbec Co-Authored-By: Claude Opus 5.5 --- arch/arm64/boot/dts/apple/t8132.dtsi | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/apple/t8132.dtsi b/arch/arm64/boot/dts/apple/t8132.dtsi index c147568e732d2b..d7f643d4952794 100644 --- a/arch/arm64/boot/dts/apple/t8132.dtsi +++ b/arch/arm64/boot/dts/apple/t8132.dtsi @@ -507,9 +507,15 @@ nvme: nvme@4c5cc0000 { compatible = "apple,t8132-nvme-ans2"; + /* + * ADT reg[9] is the controller window and reg[3] the + * NVMMU. The controller window also aliases the NVMMU + * registers, which older kernels use. + */ reg = <0x4 0xc5cc0000 0x0 0x60000>, - <0x4 0x81600000 0x0 0x4000>; - reg-names = "nvme", "ans"; + <0x4 0x81600000 0x0 0x4000>, + <0x4 0x85cc0000 0x0 0x60000>; + reg-names = "nvme", "ans", "nvmmu"; interrupt-parent = <&aic>; interrupts = ; From c2dd52c5d2868e71c233609e5ce469c80b96a462 Mon Sep 17 00:00:00 2001 From: Yureka Lilian Date: Sat, 25 Jul 2026 15:42:41 +0200 Subject: [PATCH 05/12] arm64: dts: apple: t8132: Add the PCIe controller and its DARTs Describe the T8132 internal PCIe controller, its three root ports and the DART of each port. On the M4 machines port 0 carries the Wi-Fi and Bluetooth module, and on the Mac mini port 2 carries the Ethernet controller. Give the SoC bus the same dma-ranges as T8112, T8122 and T6030 so that devices behind DARTs get DMA above 4 GiB, and include gpio.h for the PERST# lines. Everything stays disabled. A board enables the controller, the ports it wires and their DARTs, and maps their requester IDs (iommu-map), because the stream IDs differ between boards. [sdolbec: Ported from GravityLinux gravity-m4 commit 9edf52c13ea3 ("t8132 pcie") and commit bdafece9eddb ("t8132 wifi pwren"), cherry-picks of Yureka's commit 19103645439f ("t8132 pcie") and commit c59a7a826661 ("t8132 wifi pwren"). SoC part only; the board parts move to t8132-j773g.dts in a later commit. Changes: port labels pcie0_portN as in t8140.dtsi, status = "disabled" on the controller, its ports and DARTs, iommu-map left to the board, and the controller's power domain apcie_phy_sw instead of apcie_gp, which is what the J773g runs with today under gravity-m4 (changed there after these commits). The original commits carry no Signed-off-by; they are forwarded here under DCO clause (b), and Yureka's Signed-off-by should be added before this is merged.] Signed-off-by: Sean Dolbec Co-Authored-By: Claude Opus 5.5 --- arch/arm64/boot/dts/apple/t8132.dtsi | 142 +++++++++++++++++++++++++++ 1 file changed, 142 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8132.dtsi b/arch/arm64/boot/dts/apple/t8132.dtsi index d7f643d4952794..d211b40d19b2f8 100644 --- a/arch/arm64/boot/dts/apple/t8132.dtsi +++ b/arch/arm64/boot/dts/apple/t8132.dtsi @@ -5,6 +5,7 @@ * Copyright The Asahi Linux Contributors */ +#include #include #include #include @@ -196,6 +197,8 @@ ranges; nonposted-mmio; + /* Required to get >32-bit DMA via DARTs */ + dma-ranges = <0 0 0 0 0xffffffff 0xffffc000>; pmgr: power-management@380700000 { compatible = "apple,t8132-pmgr", "apple,t8103-pmgr", "syscon", "simple-mfd"; @@ -352,6 +355,13 @@ pinmux = , ; }; + + pcie_pins: pcie-pins { + /* CLKREQ# of ports 0-2 */ + pinmux = , + , + ; + }; }; i2c0: i2c@3ad010000 { @@ -529,6 +539,138 @@ apple,sart = <&sart>; status = "disabled"; }; + + pcie0_dart: iommu@490000000 { + compatible = "apple,t8132-dart", "apple,t8110-dart"; + reg = <0x4 0x90000000 0x0 0x4000>; + #iommu-cells = <1>; + interrupt-parent = <&aic>; + interrupts = ; + power-domains = <&ps_apcie_gp>; + status = "disabled"; + }; + + pcie1_dart: iommu@491000000 { + compatible = "apple,t8132-dart", "apple,t8110-dart"; + reg = <0x4 0x91000000 0x0 0x4000>; + #iommu-cells = <1>; + interrupt-parent = <&aic>; + interrupts = ; + power-domains = <&ps_apcie_gp>; + status = "disabled"; + }; + + pcie2_dart: iommu@492000000 { + compatible = "apple,t8132-dart", "apple,t8110-dart"; + reg = <0x4 0x92000000 0x0 0x4000>; + #iommu-cells = <1>; + interrupt-parent = <&aic>; + interrupts = ; + power-domains = <&ps_apcie_gp>; + status = "disabled"; + }; + + pcie0: pcie@1cb0000000 { + compatible = "apple,t8132-pcie", "apple,t6020-pcie"; + device_type = "pci"; + + reg = <0x1c 0xb0000000 0x0 0x1000000>, + <0x4 0x94000000 0x0 0x4000>, + <0x4 0x90028000 0x0 0x4000>, + <0x4 0x91028000 0x0 0x4000>, + <0x4 0x92028000 0x0 0x4000>, + <0x4 0x97020000 0x0 0x4000>, + <0x4 0x97024000 0x0 0x4000>, + <0x4 0x97028000 0x0 0x4000>; + reg-names = "config", "rc", "port0", "port1", "port2", + "phy0", "phy1", "phy2"; + + interrupt-parent = <&aic>; + interrupts = , + , + ; + + msi-controller; + msi-parent = <&pcie0>; + msi-ranges = <&aic AIC_IRQ 1506 IRQ_TYPE_EDGE_RISING 32>; + + /* Boards map the requester IDs of the ports they use. */ + iommu-map-mask = <0xff00>; + + bus-range = <0 3>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x43000000 0xb 0xc0000000 0xb 0xc0000000 0x0 0x20000000>, + <0x02000000 0x0 0x80000000 0xb 0x80000000 0x0 0x40000000>; + + power-domains = <&ps_apcie_phy_sw>; + pinctrl-0 = <&pcie_pins>; + pinctrl-names = "default"; + status = "disabled"; + + pcie0_port0: pci@0,0 { + compatible = "pciclass,0604"; + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + reset-gpios = <&pinctrl_ap 163 GPIO_ACTIVE_LOW>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie0_port0 0 0 0 0>, + <0 0 0 2 &pcie0_port0 0 0 0 1>, + <0 0 0 3 &pcie0_port0 0 0 0 2>, + <0 0 0 4 &pcie0_port0 0 0 0 3>; + status = "disabled"; + }; + + pcie0_port1: pci@1,0 { + compatible = "pciclass,0604"; + device_type = "pci"; + reg = <0x800 0x0 0x0 0x0 0x0>; + reset-gpios = <&pinctrl_ap 164 GPIO_ACTIVE_LOW>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie0_port1 0 0 0 0>, + <0 0 0 2 &pcie0_port1 0 0 0 1>, + <0 0 0 3 &pcie0_port1 0 0 0 2>, + <0 0 0 4 &pcie0_port1 0 0 0 3>; + status = "disabled"; + }; + + pcie0_port2: pci@2,0 { + compatible = "pciclass,0604"; + device_type = "pci"; + reg = <0x1000 0x0 0x0 0x0 0x0>; + reset-gpios = <&pinctrl_ap 165 GPIO_ACTIVE_LOW>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie0_port2 0 0 0 0>, + <0 0 0 2 &pcie0_port2 0 0 0 1>, + <0 0 0 3 &pcie0_port2 0 0 0 2>, + <0 0 0 4 &pcie0_port2 0 0 0 3>; + status = "disabled"; + }; + }; }; timer { From a0810e7a54ab1bd3ce60d5bc997727cd0eb8ff09 Mon Sep 17 00:00:00 2001 From: Sean Dolbec Date: Sun, 1 Nov 2026 21:02:02 -0500 Subject: [PATCH 06/12] arm64: dts: apple: t8132: Add the nub SPMI controller The main PMU of the T8132 machines sits on the nub SPMI bus at 0x388714000 (macOS: nub-spmi0). Its NVMEM holds the shutdown, boot-stage and RTC-offset cells that the SMC reboot and RTC drivers need: without the shutdown flag, the SMC's "off1" restarts the machine instead of powering it off. Add the controller, disabled, with its always-on nub_spmi0 power domain as t8140.dtsi does. Boards add the PMU and enable the bus. Signed-off-by: Sean Dolbec Co-Authored-By: Claude Opus 5.5 --- arch/arm64/boot/dts/apple/t8132.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8132.dtsi b/arch/arm64/boot/dts/apple/t8132.dtsi index d211b40d19b2f8..be0bec478b92e7 100644 --- a/arch/arm64/boot/dts/apple/t8132.dtsi +++ b/arch/arm64/boot/dts/apple/t8132.dtsi @@ -9,6 +9,7 @@ #include #include #include +#include / { compatible = "apple,t8132", "apple,arm-platform"; @@ -462,6 +463,15 @@ status = "disabled"; }; + nub_spmi: spmi@388714000 { + compatible = "apple,t8132-spmi", "apple,t8103-spmi"; + reg = <0x3 0x88714000 0x0 0x100>; + #address-cells = <2>; + #size-cells = <0>; + power-domains = <&ps_nub_spmi0>; + status = "disabled"; + }; + smc_mbox: mailbox@38c608000 { compatible = "apple,t8132-asc-mailbox", "apple,asc-mailbox-v4"; reg = <0x3 0x8c608000 0x0 0x4000>; From 1a45abe4d5a76ccc14d7b594b5409f89d228b90e Mon Sep 17 00:00:00 2001 From: Sean Dolbec Date: Sun, 1 Nov 2026 21:02:23 -0500 Subject: [PATCH 07/12] arm64: dts: apple: t8132-j773g: Enable the SMC, PMU cells, reboot and RTC Enable the SMC on the Mac mini and give it the reboot and RTC children, fed by the main PMU's (Abbey, SPMI 0xe) NVMEM cells. This gives the mini power-off, reboot, the RTC and the power button (macsmc-input), and the SMC GPIO that switches the Wi-Fi port's power. The cell offsets come from this mini's macOS IORegistry: pmu-main@E "pmu,abbey", info-leg_scrpad 0xf800, info-pm_setting 0x2001, info-clock_offset 0x2100 (6 bytes), info-fault_shadow 0x867b (0x10), info-scrpad_socd 0x8b00 (0x1800). The state cells sit at leg_scrpad + 1, + 2 and + 0xf, as on the other Apple families. These values are the same as on the M4 MacBook Air (J713). Tested on a J773g (2026-10-17) with the same nodes under GravityLinux's gravity-m4 7.1.13 kernel: the PMU cells appear, macsmc-reboot and macsmc-rtc bind, rtc0 keeps time across reboots and `systemctl poweroff` turns the mini off (power LED off). Without the shutdown flag it restarted instead. Signed-off-by: Sean Dolbec Co-Authored-By: Claude Opus 5.5 --- arch/arm64/boot/dts/apple/t8132-j773g.dts | 72 +++++++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8132-j773g.dts b/arch/arm64/boot/dts/apple/t8132-j773g.dts index 0583cb9d19f627..12ba8b854b02f9 100644 --- a/arch/arm64/boot/dts/apple/t8132-j773g.dts +++ b/arch/arm64/boot/dts/apple/t8132-j773g.dts @@ -23,3 +23,75 @@ &framebuffer0 { power-domains = <&ps_dispext0_fe>, <&ps_dptx_phy>; }; + +&smc_mbox { + status = "okay"; +}; + +&smc { + status = "okay"; + + smc_reboot: reboot { + compatible = "apple,smc-reboot"; + nvmem-cells = <&shutdown_flag>, <&boot_stage>, + <&boot_error_count>, <&panic_count>; + nvmem-cell-names = "shutdown_flag", "boot_stage", + "boot_error_count", "panic_count"; + }; + + smc_rtc: rtc { + compatible = "apple,smc-rtc"; + nvmem-cells = <&rtc_offset>; + nvmem-cell-names = "rtc_offset"; + }; +}; + +&nub_spmi { + status = "okay"; + + pmic1: pmic@e { + compatible = "apple,abbey-pmic", "apple,spmi-nvmem"; + reg = <0xe SPMI_USID>; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + pm_setting: pm-setting@2001 { + reg = <0x2001 0x1>; + }; + + rtc_offset: rtc-offset@2100 { + reg = <0x2100 0x6>; + }; + + fault_shadow: fault-shadow@867b { + reg = <0x867b 0x10>; + }; + + socd: socd@8b00 { + reg = <0x8b00 0x1800>; + }; + + boot_stage: boot-stage@f801 { + reg = <0xf801 0x1>; + }; + + boot_error_count: boot-error-count@f802,0 { + reg = <0xf802 0x1>; + bits = <0 4>; + }; + + panic_count: panic-count@f802,4 { + reg = <0xf802 0x1>; + bits = <4 4>; + }; + + shutdown_flag: shutdown-flag@f80f,3 { + reg = <0xf80f 0x1>; + bits = <3 1>; + }; + }; + }; +}; From 2eac1fd64f88a7c9baa91e9b1c1f429d8e2b80ef Mon Sep 17 00:00:00 2001 From: Sean Dolbec Date: Sun, 1 Nov 2026 21:03:05 -0500 Subject: [PATCH 08/12] arm64: dts: apple: t8132-j773g: Enable the SSD, Wi-Fi, Bluetooth and Ethernet Enable the internal NVMe SSD (ANS2, its SART and mailbox) and the internal PCIe controller on the M4 Mac mini, with the BCM4388 Wi-Fi and Bluetooth module on port 0 and the Ethernet controller on port 2. With this the mini boots from its own SSD and reaches the network, with the display on the boot framebuffer. - Port 0 is powered by SMC GPIO 19 (pwren-pcie0-port0). Its Wi-Fi and Bluetooth functions use the "apple,sakhalin" firmware. - Port 2 has its own DART. The requester IDs map to stream 1 of the port 0 and port 2 DARTs. - The ethernet0, wifi0 and bluetooth0 aliases let m1n1 fill in the MAC and Bluetooth addresses and the Wi-Fi calibration. The board wiring follows Yureka Lilian's J773g PCIe description ("t8132 pcie", picked into GravityLinux gravity-m4 as 9edf52c13ea3) and the board-type fix in gravity-m4's current J773g tree. The ATC (USB-C) ports, HDMI, audio, CPU frequency scaling and the GPU are not part of this change. A J773g runs these board nodes today under gravity-m4 7.1.13 (AQC113 on the atlantic driver, BCM4388 on brcmfmac and hci_bcm4377, NVMe root file system); this tree with this commit has not been booted yet. Signed-off-by: Sean Dolbec Co-Authored-By: Claude Opus 5.5 --- arch/arm64/boot/dts/apple/t8132-j773g.dts | 82 +++++++++++++++++++++++ 1 file changed, 82 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8132-j773g.dts b/arch/arm64/boot/dts/apple/t8132-j773g.dts index 12ba8b854b02f9..e8e05f8d9ac057 100644 --- a/arch/arm64/boot/dts/apple/t8132-j773g.dts +++ b/arch/arm64/boot/dts/apple/t8132-j773g.dts @@ -15,6 +15,19 @@ / { compatible = "apple,j773g", "apple,t8132", "apple,arm-platform"; model = "Apple Mac mini (M4, 2024)"; + + aliases { + bluetooth0 = &bluetooth0; + ethernet0 = ðernet0; + wifi0 = &wifi0; + }; + + vreg_pcie0_port0: regulator-pcie0-port0 { + compatible = "regulator-fixed"; + regulator-name = "pwren-pcie0-port0"; + gpio = <&smc_gpio 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; }; /* @@ -95,3 +108,72 @@ }; }; }; + +/* Internal SSD */ + +&ans_mbox { + status = "okay"; +}; + +&sart { + status = "okay"; +}; + +&nvme { + status = "okay"; +}; + +/* + * Internal PCIe: Wi-Fi and Bluetooth (BCM4388) on port 0 and Ethernet on + * port 2 (an AQC113 on the 10 Gb Ethernet model). Port 1 is not wired. + * Fixed bus numbers let the device nodes below carry the MAC and + * Bluetooth addresses and the calibration the loader fills in. + */ + +&pcie0 { + iommu-map = <0x100 &pcie0_dart 1 1>, + <0x200 &pcie2_dart 1 1>; + status = "okay"; +}; + +&pcie0_dart { + status = "okay"; +}; + +&pcie2_dart { + status = "okay"; +}; + +&pcie0_port0 { + power-supply = <&vreg_pcie0_port0>; + bus-range = <1 1>; + status = "okay"; + + wifi0: wifi@0,0 { + compatible = "pci14e4,4434"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + /* To be filled by the loader */ + local-mac-address = [00 00 00 00 00 00]; + apple,antenna-sku = "XX"; + brcm,board-type = "apple,sakhalin"; + }; + + bluetooth0: bluetooth@0,1 { + compatible = "pci14e4,5f72"; + reg = <0x10100 0x0 0x0 0x0 0x0>; + /* To be filled by the loader */ + local-bd-address = [00 00 00 00 00 00]; + brcm,board-type = "apple,sakhalin"; + }; +}; + +&pcie0_port2 { + bus-range = <2 2>; + status = "okay"; + + ethernet0: ethernet@0,0 { + reg = <0x20000 0x0 0x0 0x0 0x0>; + /* To be filled by the loader */ + local-mac-address = [00 10 18 00 00 00]; + }; +}; From 58e3998fd61c4ad57525c01b3326e631db0a9f83 Mon Sep 17 00:00:00 2001 From: Niklas Sheth Date: Tue, 18 Aug 2026 09:57:36 +0000 Subject: [PATCH 09/12] arm64: dts: apple: t8132-j773g: Reserve a ramoops region Give pstore a fixed 2 MiB RAM region on the Mac mini (J773g): 1 MiB for the kernel console, 256 KiB records and 256 KiB for pmsg. It is near the top of RAM and outside m1n1's kernel and initramfs load area. Without it a J773g boot that fails before the root filesystem leaves no trace: no journal and an empty pstore. That is what a first boot of this tree on a J773g did. With CONFIG_PSTORE_RAM and CONFIG_PSTORE_CONSOLE built in, the console of a crashed boot can be read from /sys/fs/pstore on the next one. Signed-off-by: Niklas Sheth [sdolbec: split out of GravityLinux gravity-m4 877c574dfa4f "drm/apple: bring up T8132 DCP hotplug" (the ramoops hunk only, unchanged values); the same region is in use on our J773g under GravityLinux 7.1.13] Signed-off-by: Sean Dolbec Co-Authored-By: Claude Opus 5.5 --- arch/arm64/boot/dts/apple/t8132-j773g.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8132-j773g.dts b/arch/arm64/boot/dts/apple/t8132-j773g.dts index e8e05f8d9ac057..8fb264efdd22af 100644 --- a/arch/arm64/boot/dts/apple/t8132-j773g.dts +++ b/arch/arm64/boot/dts/apple/t8132-j773g.dts @@ -30,6 +30,20 @@ }; }; +/* + * Persistent console capture for early T8132 bring-up failures. Keep this + * near the top of RAM, outside m1n1's kernel/initramfs load area. + */ +&{/reserved-memory} { + ramoops@103e0000000 { + compatible = "ramoops"; + reg = <0x103 0xe0000000 0x0 0x200000>; + record-size = <0x40000>; + console-size = <0x100000>; + pmsg-size = <0x40000>; + }; +}; + /* * Keep the power-domains used for the HDMI port on. */ From 8fe5d3299a8385c050c052ac556ae39bc9c4b2fe Mon Sep 17 00:00:00 2001 From: Sean Dolbec Date: Mon, 2 Nov 2026 19:50:16 -0500 Subject: [PATCH 10/12] dt-bindings: pci: apple,pcie: Describe the three T8132 root ports The T8132 (M4) controller has three root ports, each with its own PHY register window, like the T8140: config, rc, port0-2 and phy0-2. It uses the apple,t6020-pcie fallback, whose rule asks for four ports and four PHY windows (ten regions), so a T8132 node with its eight regions failed dtbs_check. Give T8132 the T8140 list and leave the other T6020-derived controllers unchanged. Signed-off-by: Sean Dolbec Co-Authored-By: Claude Opus 5.5 --- Documentation/devicetree/bindings/pci/apple,pcie.yaml | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/apple,pcie.yaml b/Documentation/devicetree/bindings/pci/apple,pcie.yaml index 3274a787e0f67b..b3234aa02009cd 100644 --- a/Documentation/devicetree/bindings/pci/apple,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/apple,pcie.yaml @@ -200,6 +200,9 @@ allOf: compatible: contains: const: apple,t6020-pcie + not: + contains: + const: apple,t8132-pcie then: properties: reg-names: @@ -252,7 +255,9 @@ allOf: properties: compatible: contains: - const: apple,t8140-pcie + enum: + - apple,t8132-pcie + - apple,t8140-pcie then: properties: reg: From 24f75ab2d9bddd14cac4628fac603a98041ed9fc Mon Sep 17 00:00:00 2001 From: Sean Dolbec Date: Mon, 2 Nov 2026 19:50:17 -0500 Subject: [PATCH 11/12] arm64: dts: apple: t8132: Power the PCIe ports with pwren-gpios Describe the Wi-Fi/Bluetooth port's power enable (SMC GPIO 19) as pwren-gpios on the root port, as the other Apple boards in this tree do. pcie-apple then drives it itself, with its power-on delay, before the link comes up. Before, the J773g used a fixed regulator through the generic PCI power-control driver, with "pciclass,0604" root-port compatibles. Both are outside apple,pcie.yaml, so dtbs_check refused the J773g tree. Drop the root-port compatibles and the regulator. The GPIO, polarity and port are unchanged. Signed-off-by: Sean Dolbec Co-Authored-By: Claude Opus 5.5 --- arch/arm64/boot/dts/apple/t8132-j773g.dts | 9 +-------- arch/arm64/boot/dts/apple/t8132.dtsi | 3 --- 2 files changed, 1 insertion(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/apple/t8132-j773g.dts b/arch/arm64/boot/dts/apple/t8132-j773g.dts index 8fb264efdd22af..8c09229f69f19e 100644 --- a/arch/arm64/boot/dts/apple/t8132-j773g.dts +++ b/arch/arm64/boot/dts/apple/t8132-j773g.dts @@ -21,13 +21,6 @@ ethernet0 = ðernet0; wifi0 = &wifi0; }; - - vreg_pcie0_port0: regulator-pcie0-port0 { - compatible = "regulator-fixed"; - regulator-name = "pwren-pcie0-port0"; - gpio = <&smc_gpio 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; }; /* @@ -159,7 +152,7 @@ }; &pcie0_port0 { - power-supply = <&vreg_pcie0_port0>; + pwren-gpios = <&smc_gpio 19 GPIO_ACTIVE_HIGH>; bus-range = <1 1>; status = "okay"; diff --git a/arch/arm64/boot/dts/apple/t8132.dtsi b/arch/arm64/boot/dts/apple/t8132.dtsi index be0bec478b92e7..1adafa4d442a6c 100644 --- a/arch/arm64/boot/dts/apple/t8132.dtsi +++ b/arch/arm64/boot/dts/apple/t8132.dtsi @@ -619,7 +619,6 @@ status = "disabled"; pcie0_port0: pci@0,0 { - compatible = "pciclass,0604"; device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; reset-gpios = <&pinctrl_ap 163 GPIO_ACTIVE_LOW>; @@ -640,7 +639,6 @@ }; pcie0_port1: pci@1,0 { - compatible = "pciclass,0604"; device_type = "pci"; reg = <0x800 0x0 0x0 0x0 0x0>; reset-gpios = <&pinctrl_ap 164 GPIO_ACTIVE_LOW>; @@ -661,7 +659,6 @@ }; pcie0_port2: pci@2,0 { - compatible = "pciclass,0604"; device_type = "pci"; reg = <0x1000 0x0 0x0 0x0 0x0>; reset-gpios = <&pinctrl_ap 165 GPIO_ACTIVE_LOW>; From c0f65cd71fd8196ce0ad284ad85e35768b9e56be Mon Sep 17 00:00:00 2001 From: Sean Dolbec Date: Wed, 4 Nov 2026 06:27:26 -0500 Subject: [PATCH 12/12] arm64: dts: apple: t8132: Map the full PCIe DART register windows The T8132 PCIe DARTs report version 2.2. Those keep the exception bitmap at 0x4000 and the per-stream exception records at 0x8000, and the driver reads both when it resets the DART at probe. A reg of 0x4000 leaves them unmapped, so the first exception read faults and the kernel dies in the device initcalls with no output; the bootloader watchdog resets the SoC about a minute later. Use 0xc000, as aurora-silicon's t8132.dtsi does. The ADT describes 0x20000 for dart-apcie0 and dart-apcie2. Tested on the Mac mini M4 (J773g): Aurora boots with 0xc000 windows on these DARTs and every other short DART, and never boots with 0x4000. Assisted-by: LLM Signed-off-by: Sean Dolbec --- arch/arm64/boot/dts/apple/t8132.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/apple/t8132.dtsi b/arch/arm64/boot/dts/apple/t8132.dtsi index 1adafa4d442a6c..8f37fe7d12a2de 100644 --- a/arch/arm64/boot/dts/apple/t8132.dtsi +++ b/arch/arm64/boot/dts/apple/t8132.dtsi @@ -552,7 +552,7 @@ pcie0_dart: iommu@490000000 { compatible = "apple,t8132-dart", "apple,t8110-dart"; - reg = <0x4 0x90000000 0x0 0x4000>; + reg = <0x4 0x90000000 0x0 0xc000>; #iommu-cells = <1>; interrupt-parent = <&aic>; interrupts = ; @@ -562,7 +562,7 @@ pcie1_dart: iommu@491000000 { compatible = "apple,t8132-dart", "apple,t8110-dart"; - reg = <0x4 0x91000000 0x0 0x4000>; + reg = <0x4 0x91000000 0x0 0xc000>; #iommu-cells = <1>; interrupt-parent = <&aic>; interrupts = ; @@ -572,7 +572,7 @@ pcie2_dart: iommu@492000000 { compatible = "apple,t8132-dart", "apple,t8110-dart"; - reg = <0x4 0x92000000 0x0 0x4000>; + reg = <0x4 0x92000000 0x0 0xc000>; #iommu-cells = <1>; interrupt-parent = <&aic>; interrupts = ;