From 57b2e4fab4cb9c7951e68b848c317acd8b237a0f Mon Sep 17 00:00:00 2001 From: Alice Ziuziakowska Date: Fri, 12 Jun 2026 14:01:32 +0100 Subject: [PATCH] sw: devicetree: fix PLIC context interrupt mapping Signed-off-by: Alice Ziuziakowska --- sw/device/devicetree/mocha.S | 4 ++-- sw/device/devicetree/mocha.dts | 7 ++++--- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/sw/device/devicetree/mocha.S b/sw/device/devicetree/mocha.S index fc40d3b10..eef017702 100644 --- a/sw/device/devicetree/mocha.S +++ b/sw/device/devicetree/mocha.S @@ -1437,7 +1437,7 @@ plic: .byte 0x00 .byte 0x00 .byte 0x00 - .byte 0x09 + .byte 0x0b .byte 0x00 .byte 0x00 .byte 0x00 @@ -1445,7 +1445,7 @@ plic: .byte 0x00 .byte 0x00 .byte 0x00 - .byte 0x0b + .byte 0x09 .balign 4, 0 /* FDT_PROP */ .byte 0x00 diff --git a/sw/device/devicetree/mocha.dts b/sw/device/devicetree/mocha.dts index 7325c4aea..415e8b39f 100644 --- a/sw/device/devicetree/mocha.dts +++ b/sw/device/devicetree/mocha.dts @@ -79,14 +79,15 @@ }; plic: interrupt-controller@48000000 { + // Compatible with the standard and SiFive PLIC memory layout compatible = "lowrisc,opentitan-plic", - "sifive,plic-1.0.0"; // Compatible with the SiFive PLIC memory layout + "sifive,plic-1.0.0"; interrupt-controller; #address-cells = <0>; #interrupt-cells = <1>; reg = <0x0 0x48000000 0x0 0x4000000>; - interrupts-extended = <&cpu0intc 9>, // S-mode external interrupt - <&cpu0intc 11>; // M-mode external interrupt + interrupts-extended = <&cpu0intc 11>, // Context 0: M-mode external interrupt + <&cpu0intc 9>; // Context 1: S-mode external interrupt riscv,ndev = <32>; };