I2C DV -- Device TX-RX test

[KinzaQamar]

Write a vseq that will act as a host to send write and read transfer. At the end, contains some self checking mechanism to compare the data written is equal to data received

[KinzaQamar]

A minimal SW test is written. Working towards writing the vseq. It is going to be a bit different OT. In OT, SW first write to TX FIFO and vseq reads that data then write the same data back to the target. SW after writing TX FIFO, send a message to DV and vseq after reading that message, starts the transfer. SW does the checking b/w read and write dat bytes

In Mocha, we don't have that logging functionality yet. So, vseq needs to have a checking mechanism and SW should stay idle while the transfer happens and read some status register fields to check if the transfer happened is succesfull

[KinzaQamar]

In Mocha, we don't have that logging functionality yet.

Logging is required and to make the SW and UVM in sync. Otherwise, when SW is in the middle of configuring the registers, UVM generates a start condiiton which doesn't become visible to the target FSM (as SW has not configured the I2C block as target) so it will stay IDLE. At the moment, I have made it work by adding a delay in UVM.

Depends on #600

[KinzaQamar]

Created a vseq that can act as a host and send read and write transfer. Write works debugging reads