Top (PT) IO pins cannot do differential input. Most likely would be best to move to a pair of pins in one of the DDR3 banks. Workaround for now is to use the 12MHz single ended clock, this seems fine for a PLL input.
Top (PT) IO pins cannot do differential input. Most likely would be best to move to a pair of pins in one of the DDR3 banks.
Workaround for now is to use the 12MHz single ended clock, this seems fine for a PLL input.