single-cycle-cpu/waves.vcd at main · eulere28/single-cycle-cpu · GitHub

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$date
  2023-08-29T12:53:58.731480
$end
$version
  ROHD v0.4.2
$end
$comment
  Generated by ROHD - www.github.com/intel/rohd
$end
$timescale 1ps $end
$scope module counter $end
  $var wire 1 s0 en $end
  $var wire 1 s1 reset $end
  $var wire 1 s2 clk $end
  $var wire 8 s3 val $end
  $var wire 8 s4 nextVal $end
  $scope module sequential $end
    $var wire 1 s5 _in0_reset $end
    $var wire 8 s6 _in1_const_0 $end
    $var wire 1 s7 _in2_en $end
    $var wire 8 s8 _in3_nextVal $end
    $var wire 1 s9 _clk0_clk $end
    $var wire 8 s10 _out4_val $end
  $upscope $end
$upscope $end
$enddefinitions $end
$dumpvars
zs0
zs1
0s2
bzzzzzzzz s3
bxxxxxxxx s4
zs5
b00000000 s6
zs7
bxxxxxxxx s8
0s9
bzzzzzzzz s10
$end
#0
0s0
0s7
1s1
1s5
#5
1s2
1s9
b00000001 s4
b00000001 s8
b00000000 s3
b00000000 s10
#10
0s2
0s9
#15
1s2
1s9
#20
0s2
0s9
#25
0s1
0s5
1s2
1s9
#30
0s2
0s9
#35
1s2
1s9
#40
0s2
0s9
#45
1s0
1s7
1s2
1s9
b00000010 s4
b00000010 s8
b00000001 s3
b00000001 s10
#50
0s2
0s9
#55
1s2
1s9
b00000011 s4
b00000011 s8
b00000010 s3
b00000010 s10
#60
0s2
0s9
#65
1s2
1s9
b00000100 s4
b00000100 s8
b00000011 s3
b00000011 s10
#70
0s2
0s9
#75
1s2
1s9
b00000101 s4
b00000101 s8
b00000100 s3
b00000100 s10
#80
0s2
0s9
#85
1s2
1s9
b00000110 s4
b00000110 s8
b00000101 s3
b00000101 s10
#90
0s2
0s9
#95
1s2
1s9
b00000111 s4
b00000111 s8
b00000110 s3
b00000110 s10
#100
0s2
0s9