Problem recognizing input in module

[RobyB]

Hi,
just observed that the extension does not recognize a module input in SystemVerilog if it is defined as:
input wire logic Clock;

An example follows.
This syntax is perfectly legit and has to be used, for module inputs, if the file contains the
`default_nettype none directive.

Here is a small example:

`default_nettype none

module Test(
input wire logic clock,
input wire logic Rst_b,
input wire logic [7:0] InData,
output wire. OutData);

always_ff @(posedge clock) begin
if (Rst_b == 1'b0) OutData <= 8'b0;
else OutData <= InData;
end

endmodule

`default_nettype wire